1# AArch64 A64 allowed instruction decoding 2# 3# Copyright (c) 2023 Linaro, Ltd 4# 5# This library is free software; you can redistribute it and/or 6# modify it under the terms of the GNU Lesser General Public 7# License as published by the Free Software Foundation; either 8# version 2.1 of the License, or (at your option) any later version. 9# 10# This library is distributed in the hope that it will be useful, 11# but WITHOUT ANY WARRANTY; without even the implied warranty of 12# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13# Lesser General Public License for more details. 14# 15# You should have received a copy of the GNU Lesser General Public 16# License along with this library; if not, see <http://www.gnu.org/licenses/>. 17 18# 19# This file is processed by scripts/decodetree.py 20# 21 22%rd 0:5 23%esz_sd 22:1 !function=plus_2 24%esz_hsd 22:2 !function=xor_2 25%hl 11:1 21:1 26%hlm 11:1 20:2 27 28&r rn 29&ri rd imm 30&rri_sf rd rn imm sf 31&i imm 32&rr_e rd rn esz 33&rrr_e rd rn rm esz 34&rrx_e rd rn rm idx esz 35&rrrr_e rd rn rm ra esz 36&qrr_e q rd rn esz 37&qrrr_e q rd rn rm esz 38&qrrx_e q rd rn rm idx esz 39&qrrrr_e q rd rn rm ra esz 40 41@rr_h ........ ... ..... ...... rn:5 rd:5 &rr_e esz=1 42@rr_d ........ ... ..... ...... rn:5 rd:5 &rr_e esz=3 43@rr_sd ........ ... ..... ...... rn:5 rd:5 &rr_e esz=%esz_sd 44 45@rrr_h ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=1 46@rrr_d ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=3 47@rrr_sd ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=%esz_sd 48@rrr_hsd ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=%esz_hsd 49@rrr_e ........ esz:2 . rm:5 ...... rn:5 rd:5 &rrr_e 50@r2r_e ........ esz:2 . ..... ...... rm:5 rd:5 &rrr_e rn=%rd 51 52@rrx_h ........ .. .. rm:4 .... . . rn:5 rd:5 &rrx_e esz=1 idx=%hlm 53@rrx_s ........ .. . rm:5 .... . . rn:5 rd:5 &rrx_e esz=2 idx=%hl 54@rrx_d ........ .. . rm:5 .... idx:1 . rn:5 rd:5 &rrx_e esz=3 55 56@rr_q1e0 ........ ........ ...... rn:5 rd:5 &qrr_e q=1 esz=0 57@r2r_q1e0 ........ ........ ...... rm:5 rd:5 &qrrr_e rn=%rd q=1 esz=0 58@rrr_q1e0 ........ ... rm:5 ...... rn:5 rd:5 &qrrr_e q=1 esz=0 59@rrr_q1e3 ........ ... rm:5 ...... rn:5 rd:5 &qrrr_e q=1 esz=3 60@rrrr_q1e3 ........ ... rm:5 . ra:5 rn:5 rd:5 &qrrrr_e q=1 esz=3 61 62@qrrr_b . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=0 63@qrrr_h . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=1 64@qrrr_s . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=2 65@qrrr_sd . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=%esz_sd 66@qrrr_e . q:1 ...... esz:2 . rm:5 ...... rn:5 rd:5 &qrrr_e 67@qr2r_e . q:1 ...... esz:2 . ..... ...... rm:5 rd:5 &qrrr_e rn=%rd 68 69@qrrx_h . q:1 .. .... .. .. rm:4 .... . . rn:5 rd:5 \ 70 &qrrx_e esz=1 idx=%hlm 71@qrrx_s . q:1 .. .... .. . rm:5 .... . . rn:5 rd:5 \ 72 &qrrx_e esz=2 idx=%hl 73@qrrx_d . q:1 .. .... .. . rm:5 .... idx:1 . rn:5 rd:5 \ 74 &qrrx_e esz=3 75 76### Data Processing - Immediate 77 78# PC-rel addressing 79 80%imm_pcrel 5:s19 29:2 81@pcrel . .. ..... ................... rd:5 &ri imm=%imm_pcrel 82 83ADR 0 .. 10000 ................... ..... @pcrel 84ADRP 1 .. 10000 ................... ..... @pcrel 85 86# Add/subtract (immediate) 87 88%imm12_sh12 10:12 !function=shl_12 89@addsub_imm sf:1 .. ...... . imm:12 rn:5 rd:5 90@addsub_imm12 sf:1 .. ...... . ............ rn:5 rd:5 imm=%imm12_sh12 91 92ADD_i . 00 100010 0 ............ ..... ..... @addsub_imm 93ADD_i . 00 100010 1 ............ ..... ..... @addsub_imm12 94ADDS_i . 01 100010 0 ............ ..... ..... @addsub_imm 95ADDS_i . 01 100010 1 ............ ..... ..... @addsub_imm12 96 97SUB_i . 10 100010 0 ............ ..... ..... @addsub_imm 98SUB_i . 10 100010 1 ............ ..... ..... @addsub_imm12 99SUBS_i . 11 100010 0 ............ ..... ..... @addsub_imm 100SUBS_i . 11 100010 1 ............ ..... ..... @addsub_imm12 101 102# Add/subtract (immediate with tags) 103 104&rri_tag rd rn uimm6 uimm4 105@addsub_imm_tag . .. ...... . uimm6:6 .. uimm4:4 rn:5 rd:5 &rri_tag 106 107ADDG_i 1 00 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag 108SUBG_i 1 10 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag 109 110# Logical (immediate) 111 112&rri_log rd rn sf dbm 113@logic_imm_64 1 .. ...... dbm:13 rn:5 rd:5 &rri_log sf=1 114@logic_imm_32 0 .. ...... 0 dbm:12 rn:5 rd:5 &rri_log sf=0 115 116AND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_64 117AND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_32 118ORR_i . 01 100100 . ...... ...... ..... ..... @logic_imm_64 119ORR_i . 01 100100 . ...... ...... ..... ..... @logic_imm_32 120EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_64 121EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_32 122ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_64 123ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_32 124 125# Move wide (immediate) 126 127&movw rd sf imm hw 128@movw_64 1 .. ...... hw:2 imm:16 rd:5 &movw sf=1 129@movw_32 0 .. ...... 0 hw:1 imm:16 rd:5 &movw sf=0 130 131MOVN . 00 100101 .. ................ ..... @movw_64 132MOVN . 00 100101 .. ................ ..... @movw_32 133MOVZ . 10 100101 .. ................ ..... @movw_64 134MOVZ . 10 100101 .. ................ ..... @movw_32 135MOVK . 11 100101 .. ................ ..... @movw_64 136MOVK . 11 100101 .. ................ ..... @movw_32 137 138# Bitfield 139 140&bitfield rd rn sf immr imms 141@bitfield_64 1 .. ...... 1 immr:6 imms:6 rn:5 rd:5 &bitfield sf=1 142@bitfield_32 0 .. ...... 0 0 immr:5 0 imms:5 rn:5 rd:5 &bitfield sf=0 143 144SBFM . 00 100110 . ...... ...... ..... ..... @bitfield_64 145SBFM . 00 100110 . ...... ...... ..... ..... @bitfield_32 146BFM . 01 100110 . ...... ...... ..... ..... @bitfield_64 147BFM . 01 100110 . ...... ...... ..... ..... @bitfield_32 148UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_64 149UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_32 150 151# Extract 152 153&extract rd rn rm imm sf 154 155EXTR 1 00 100111 1 0 rm:5 imm:6 rn:5 rd:5 &extract sf=1 156EXTR 0 00 100111 0 0 rm:5 0 imm:5 rn:5 rd:5 &extract sf=0 157 158# Branches 159 160%imm26 0:s26 !function=times_4 161@branch . ..... .......................... &i imm=%imm26 162 163B 0 00101 .......................... @branch 164BL 1 00101 .......................... @branch 165 166%imm19 5:s19 !function=times_4 167&cbz rt imm sf nz 168 169CBZ sf:1 011010 nz:1 ................... rt:5 &cbz imm=%imm19 170 171%imm14 5:s14 !function=times_4 172%imm31_19 31:1 19:5 173&tbz rt imm nz bitpos 174 175TBZ . 011011 nz:1 ..... .............. rt:5 &tbz imm=%imm14 bitpos=%imm31_19 176 177# B.cond and BC.cond 178B_cond 0101010 0 ................... c:1 cond:4 imm=%imm19 179 180BR 1101011 0000 11111 000000 rn:5 00000 &r 181BLR 1101011 0001 11111 000000 rn:5 00000 &r 182RET 1101011 0010 11111 000000 rn:5 00000 &r 183 184&braz rn m 185BRAZ 1101011 0000 11111 00001 m:1 rn:5 11111 &braz # BRAAZ, BRABZ 186BLRAZ 1101011 0001 11111 00001 m:1 rn:5 11111 &braz # BLRAAZ, BLRABZ 187 188&reta m 189RETA 1101011 0010 11111 00001 m:1 11111 11111 &reta # RETAA, RETAB 190 191&bra rn rm m 192BRA 1101011 1000 11111 00001 m:1 rn:5 rm:5 &bra # BRAA, BRAB 193BLRA 1101011 1001 11111 00001 m:1 rn:5 rm:5 &bra # BLRAA, BLRAB 194 195ERET 1101011 0100 11111 000000 11111 00000 196ERETA 1101011 0100 11111 00001 m:1 11111 11111 &reta # ERETAA, ERETAB 197 198# We don't need to decode DRPS because it always UNDEFs except when 199# the processor is in halting debug state (which we don't implement). 200# The pattern is listed here as documentation. 201# DRPS 1101011 0101 11111 000000 11111 00000 202 203# Hint instruction group 204{ 205 [ 206 YIELD 1101 0101 0000 0011 0010 0000 001 11111 207 WFE 1101 0101 0000 0011 0010 0000 010 11111 208 WFI 1101 0101 0000 0011 0010 0000 011 11111 209 # We implement WFE to never block, so our SEV/SEVL are NOPs 210 # SEV 1101 0101 0000 0011 0010 0000 100 11111 211 # SEVL 1101 0101 0000 0011 0010 0000 101 11111 212 # Our DGL is a NOP because we don't merge memory accesses anyway. 213 # DGL 1101 0101 0000 0011 0010 0000 110 11111 214 XPACLRI 1101 0101 0000 0011 0010 0000 111 11111 215 PACIA1716 1101 0101 0000 0011 0010 0001 000 11111 216 PACIB1716 1101 0101 0000 0011 0010 0001 010 11111 217 AUTIA1716 1101 0101 0000 0011 0010 0001 100 11111 218 AUTIB1716 1101 0101 0000 0011 0010 0001 110 11111 219 ESB 1101 0101 0000 0011 0010 0010 000 11111 220 PACIAZ 1101 0101 0000 0011 0010 0011 000 11111 221 PACIASP 1101 0101 0000 0011 0010 0011 001 11111 222 PACIBZ 1101 0101 0000 0011 0010 0011 010 11111 223 PACIBSP 1101 0101 0000 0011 0010 0011 011 11111 224 AUTIAZ 1101 0101 0000 0011 0010 0011 100 11111 225 AUTIASP 1101 0101 0000 0011 0010 0011 101 11111 226 AUTIBZ 1101 0101 0000 0011 0010 0011 110 11111 227 AUTIBSP 1101 0101 0000 0011 0010 0011 111 11111 228 ] 229 # The canonical NOP has CRm == op2 == 0, but all of the space 230 # that isn't specifically allocated to an instruction must NOP 231 NOP 1101 0101 0000 0011 0010 ---- --- 11111 232} 233 234# System instructions with register argument 235WFET 1101 0101 0000 0011 0001 0000 000 rd:5 236WFIT 1101 0101 0000 0011 0001 0000 001 rd:5 237 238# Barriers 239 240CLREX 1101 0101 0000 0011 0011 ---- 010 11111 241DSB_DMB 1101 0101 0000 0011 0011 domain:2 types:2 10- 11111 242ISB 1101 0101 0000 0011 0011 ---- 110 11111 243SB 1101 0101 0000 0011 0011 0000 111 11111 244 245# PSTATE 246 247CFINV 1101 0101 0000 0 000 0100 0000 000 11111 248XAFLAG 1101 0101 0000 0 000 0100 0000 001 11111 249AXFLAG 1101 0101 0000 0 000 0100 0000 010 11111 250 251# These are architecturally all "MSR (immediate)"; we decode the destination 252# register too because there is no commonality in our implementation. 253@msr_i .... .... .... . ... .... imm:4 ... ..... 254MSR_i_UAO 1101 0101 0000 0 000 0100 .... 011 11111 @msr_i 255MSR_i_PAN 1101 0101 0000 0 000 0100 .... 100 11111 @msr_i 256MSR_i_SPSEL 1101 0101 0000 0 000 0100 .... 101 11111 @msr_i 257MSR_i_SBSS 1101 0101 0000 0 011 0100 .... 001 11111 @msr_i 258MSR_i_DIT 1101 0101 0000 0 011 0100 .... 010 11111 @msr_i 259MSR_i_TCO 1101 0101 0000 0 011 0100 .... 100 11111 @msr_i 260MSR_i_DAIFSET 1101 0101 0000 0 011 0100 .... 110 11111 @msr_i 261MSR_i_DAIFCLEAR 1101 0101 0000 0 011 0100 .... 111 11111 @msr_i 262MSR_i_ALLINT 1101 0101 0000 0 001 0100 000 imm:1 000 11111 263MSR_i_SVCR 1101 0101 0000 0 011 0100 0 mask:2 imm:1 011 11111 264 265# MRS, MSR (register), SYS, SYSL. These are all essentially the 266# same instruction as far as QEMU is concerned. 267# NB: op0 is bits [20:19], but op0=0b00 is other insns, so we have 268# to hand-decode it. 269SYS 1101 0101 00 l:1 01 op1:3 crn:4 crm:4 op2:3 rt:5 op0=1 270SYS 1101 0101 00 l:1 10 op1:3 crn:4 crm:4 op2:3 rt:5 op0=2 271SYS 1101 0101 00 l:1 11 op1:3 crn:4 crm:4 op2:3 rt:5 op0=3 272 273# Exception generation 274 275@i16 .... .... ... imm:16 ... .. &i 276SVC 1101 0100 000 ................ 000 01 @i16 277HVC 1101 0100 000 ................ 000 10 @i16 278SMC 1101 0100 000 ................ 000 11 @i16 279BRK 1101 0100 001 ................ 000 00 @i16 280HLT 1101 0100 010 ................ 000 00 @i16 281# These insns always UNDEF unless in halting debug state, which 282# we don't implement. So we don't need to decode them. The patterns 283# are listed here as documentation. 284# DCPS1 1101 0100 101 ................ 000 01 @i16 285# DCPS2 1101 0100 101 ................ 000 10 @i16 286# DCPS3 1101 0100 101 ................ 000 11 @i16 287 288# Loads and stores 289 290&stxr rn rt rt2 rs sz lasr 291&stlr rn rt sz lasr 292@stxr sz:2 ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr 293@stlr sz:2 ...... ... ..... lasr:1 ..... rn:5 rt:5 &stlr 294%imm1_30_p2 30:1 !function=plus_2 295@stxp .. ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr sz=%imm1_30_p2 296STXR .. 001000 000 ..... . ..... ..... ..... @stxr # inc STLXR 297LDXR .. 001000 010 ..... . ..... ..... ..... @stxr # inc LDAXR 298STLR .. 001000 100 11111 . 11111 ..... ..... @stlr # inc STLLR 299LDAR .. 001000 110 11111 . 11111 ..... ..... @stlr # inc LDLAR 300 301STXP 1 . 001000 001 ..... . ..... ..... ..... @stxp # inc STLXP 302LDXP 1 . 001000 011 ..... . ..... ..... ..... @stxp # inc LDAXP 303 304# CASP, CASPA, CASPAL, CASPL (we don't decode the bits that determine 305# acquire/release semantics because QEMU's cmpxchg always has those) 306CASP 0 . 001000 0 - 1 rs:5 - 11111 rn:5 rt:5 sz=%imm1_30_p2 307# CAS, CASA, CASAL, CASL 308CAS sz:2 001000 1 - 1 rs:5 - 11111 rn:5 rt:5 309 310&ldlit rt imm sz sign 311@ldlit .. ... . .. ................... rt:5 &ldlit imm=%imm19 312 313LD_lit 00 011 0 00 ................... ..... @ldlit sz=2 sign=0 314LD_lit 01 011 0 00 ................... ..... @ldlit sz=3 sign=0 315LD_lit 10 011 0 00 ................... ..... @ldlit sz=2 sign=1 316LD_lit_v 00 011 1 00 ................... ..... @ldlit sz=2 sign=0 317LD_lit_v 01 011 1 00 ................... ..... @ldlit sz=3 sign=0 318LD_lit_v 10 011 1 00 ................... ..... @ldlit sz=4 sign=0 319 320# PRFM 321NOP 11 011 0 00 ------------------- ----- 322 323&ldstpair rt2 rt rn imm sz sign w p 324@ldstpair .. ... . ... . imm:s7 rt2:5 rn:5 rt:5 &ldstpair 325 326# STNP, LDNP: Signed offset, non-temporal hint. We don't emulate caches 327# so we ignore hints about data access patterns, and handle these like 328# plain signed offset. 329STP 00 101 0 000 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 330LDP 00 101 0 000 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 331STP 10 101 0 000 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 332LDP 10 101 0 000 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 333STP_v 00 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 334LDP_v 00 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 335STP_v 01 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 336LDP_v 01 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 337STP_v 10 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 338LDP_v 10 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 339 340# STP and LDP: post-indexed 341STP 00 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 342LDP 00 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 343LDP 01 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=1 w=1 344STP 10 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 345LDP 10 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 346STP_v 00 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 347LDP_v 00 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 348STP_v 01 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 349LDP_v 01 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 350STP_v 10 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=1 w=1 351LDP_v 10 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=1 w=1 352 353# STP and LDP: offset 354STP 00 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 355LDP 00 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 356LDP 01 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=0 w=0 357STP 10 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 358LDP 10 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 359STP_v 00 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 360LDP_v 00 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 361STP_v 01 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 362LDP_v 01 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 363STP_v 10 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 364LDP_v 10 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 365 366# STP and LDP: pre-indexed 367STP 00 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 368LDP 00 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 369LDP 01 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=0 w=1 370STP 10 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 371LDP 10 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 372STP_v 00 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 373LDP_v 00 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 374STP_v 01 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 375LDP_v 01 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 376STP_v 10 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=1 377LDP_v 10 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=1 378 379# STGP: store tag and pair 380STGP 01 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 381STGP 01 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 382STGP 01 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 383 384# Load/store register (unscaled immediate) 385&ldst_imm rt rn imm sz sign w p unpriv ext 386@ldst_imm .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=0 387@ldst_imm_pre .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=1 388@ldst_imm_post .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=1 w=1 389@ldst_imm_user .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=1 p=0 w=0 390 391STR_i sz:2 111 0 00 00 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 392LDR_i 00 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=0 393LDR_i 01 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=1 394LDR_i 10 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=2 395LDR_i 11 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=3 396LDR_i 00 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=0 397LDR_i 01 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=1 398LDR_i 10 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=2 399LDR_i 00 111 0 00 11 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=1 sz=0 400LDR_i 01 111 0 00 11 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=1 sz=1 401 402STR_i sz:2 111 0 00 00 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 403LDR_i 00 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=0 404LDR_i 01 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=1 405LDR_i 10 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=2 406LDR_i 11 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=3 407LDR_i 00 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=0 408LDR_i 01 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=1 409LDR_i 10 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=2 410LDR_i 00 111 0 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=1 sz=0 411LDR_i 01 111 0 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=1 sz=1 412 413STR_i sz:2 111 0 00 00 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=0 414LDR_i 00 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=0 415LDR_i 01 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=1 416LDR_i 10 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=2 417LDR_i 11 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=0 sz=3 418LDR_i 00 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=0 419LDR_i 01 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=1 420LDR_i 10 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=2 421LDR_i 00 111 0 00 11 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=1 sz=0 422LDR_i 01 111 0 00 11 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=1 sz=1 423 424STR_i sz:2 111 0 00 00 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 425LDR_i 00 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=0 426LDR_i 01 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=1 427LDR_i 10 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=2 428LDR_i 11 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=3 429LDR_i 00 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=0 430LDR_i 01 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=1 431LDR_i 10 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=2 432LDR_i 00 111 0 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=1 sz=0 433LDR_i 01 111 0 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=1 sz=1 434 435# PRFM : prefetch memory: a no-op for QEMU 436NOP 11 111 0 00 10 0 --------- 00 ----- ----- 437 438STR_v_i sz:2 111 1 00 00 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 439STR_v_i 00 111 1 00 10 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=4 440LDR_v_i sz:2 111 1 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 441LDR_v_i 00 111 1 00 11 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=4 442 443STR_v_i sz:2 111 1 00 00 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 444STR_v_i 00 111 1 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=4 445LDR_v_i sz:2 111 1 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 446LDR_v_i 00 111 1 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=4 447 448STR_v_i sz:2 111 1 00 00 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 449STR_v_i 00 111 1 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=4 450LDR_v_i sz:2 111 1 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 451LDR_v_i 00 111 1 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=4 452 453# Load/store with an unsigned 12 bit immediate, which is scaled by the 454# element size. The function gets the sz:imm and returns the scaled immediate. 455%uimm_scaled 10:12 sz:3 !function=uimm_scaled 456 457@ldst_uimm .. ... . .. .. ............ rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=0 imm=%uimm_scaled 458 459STR_i sz:2 111 0 01 00 ............ ..... ..... @ldst_uimm sign=0 ext=0 460LDR_i 00 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=0 461LDR_i 01 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=1 462LDR_i 10 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=2 463LDR_i 11 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=3 464LDR_i 00 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=0 465LDR_i 01 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=1 466LDR_i 10 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=2 467LDR_i 00 111 0 01 11 ............ ..... ..... @ldst_uimm sign=1 ext=1 sz=0 468LDR_i 01 111 0 01 11 ............ ..... ..... @ldst_uimm sign=1 ext=1 sz=1 469 470# PRFM 471NOP 11 111 0 01 10 ------------ ----- ----- 472 473STR_v_i sz:2 111 1 01 00 ............ ..... ..... @ldst_uimm sign=0 ext=0 474STR_v_i 00 111 1 01 10 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=4 475LDR_v_i sz:2 111 1 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=0 476LDR_v_i 00 111 1 01 11 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=4 477 478# Load/store with register offset 479&ldst rm rn rt sign ext sz opt s 480@ldst .. ... . .. .. . rm:5 opt:3 s:1 .. rn:5 rt:5 &ldst 481STR sz:2 111 0 00 00 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 482LDR 00 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=0 483LDR 01 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=1 484LDR 10 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=2 485LDR 11 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=3 486LDR 00 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=0 487LDR 01 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=1 488LDR 10 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=2 489LDR 00 111 0 00 11 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=1 sz=0 490LDR 01 111 0 00 11 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=1 sz=1 491 492# PRFM 493NOP 11 111 0 00 10 1 ----- -1- - 10 ----- ----- 494 495STR_v sz:2 111 1 00 00 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 496STR_v 00 111 1 00 10 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=4 497LDR_v sz:2 111 1 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 498LDR_v 00 111 1 00 11 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=4 499 500# Atomic memory operations 501&atomic rs rn rt a r sz 502@atomic sz:2 ... . .. a:1 r:1 . rs:5 . ... .. rn:5 rt:5 &atomic 503LDADD .. 111 0 00 . . 1 ..... 0000 00 ..... ..... @atomic 504LDCLR .. 111 0 00 . . 1 ..... 0001 00 ..... ..... @atomic 505LDEOR .. 111 0 00 . . 1 ..... 0010 00 ..... ..... @atomic 506LDSET .. 111 0 00 . . 1 ..... 0011 00 ..... ..... @atomic 507LDSMAX .. 111 0 00 . . 1 ..... 0100 00 ..... ..... @atomic 508LDSMIN .. 111 0 00 . . 1 ..... 0101 00 ..... ..... @atomic 509LDUMAX .. 111 0 00 . . 1 ..... 0110 00 ..... ..... @atomic 510LDUMIN .. 111 0 00 . . 1 ..... 0111 00 ..... ..... @atomic 511SWP .. 111 0 00 . . 1 ..... 1000 00 ..... ..... @atomic 512 513LDAPR sz:2 111 0 00 1 0 1 11111 1100 00 rn:5 rt:5 514 515# Load/store register (pointer authentication) 516 517# LDRA immediate is 10 bits signed and scaled, but the bits aren't all contiguous 518%ldra_imm 22:s1 12:9 !function=times_8 519 520LDRA 11 111 0 00 m:1 . 1 ......... w:1 1 rn:5 rt:5 imm=%ldra_imm 521 522&ldapr_stlr_i rn rt imm sz sign ext 523@ldapr_stlr_i .. ...... .. . imm:9 .. rn:5 rt:5 &ldapr_stlr_i 524STLR_i sz:2 011001 00 0 ......... 00 ..... ..... @ldapr_stlr_i sign=0 ext=0 525LDAPR_i sz:2 011001 01 0 ......... 00 ..... ..... @ldapr_stlr_i sign=0 ext=0 526LDAPR_i 00 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=0 527LDAPR_i 01 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=1 528LDAPR_i 10 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=2 529LDAPR_i 00 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=1 sz=0 530LDAPR_i 01 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=1 sz=1 531 532# Load/store multiple structures 533# The 4-bit opcode in [15:12] encodes repeat count and structure elements 534&ldst_mult rm rn rt sz q p rpt selem 535@ldst_mult . q:1 ...... p:1 . . rm:5 .... sz:2 rn:5 rt:5 &ldst_mult 536ST_mult 0 . 001100 . 0 0 ..... 0000 .. ..... ..... @ldst_mult rpt=1 selem=4 537ST_mult 0 . 001100 . 0 0 ..... 0010 .. ..... ..... @ldst_mult rpt=4 selem=1 538ST_mult 0 . 001100 . 0 0 ..... 0100 .. ..... ..... @ldst_mult rpt=1 selem=3 539ST_mult 0 . 001100 . 0 0 ..... 0110 .. ..... ..... @ldst_mult rpt=3 selem=1 540ST_mult 0 . 001100 . 0 0 ..... 0111 .. ..... ..... @ldst_mult rpt=1 selem=1 541ST_mult 0 . 001100 . 0 0 ..... 1000 .. ..... ..... @ldst_mult rpt=1 selem=2 542ST_mult 0 . 001100 . 0 0 ..... 1010 .. ..... ..... @ldst_mult rpt=2 selem=1 543 544LD_mult 0 . 001100 . 1 0 ..... 0000 .. ..... ..... @ldst_mult rpt=1 selem=4 545LD_mult 0 . 001100 . 1 0 ..... 0010 .. ..... ..... @ldst_mult rpt=4 selem=1 546LD_mult 0 . 001100 . 1 0 ..... 0100 .. ..... ..... @ldst_mult rpt=1 selem=3 547LD_mult 0 . 001100 . 1 0 ..... 0110 .. ..... ..... @ldst_mult rpt=3 selem=1 548LD_mult 0 . 001100 . 1 0 ..... 0111 .. ..... ..... @ldst_mult rpt=1 selem=1 549LD_mult 0 . 001100 . 1 0 ..... 1000 .. ..... ..... @ldst_mult rpt=1 selem=2 550LD_mult 0 . 001100 . 1 0 ..... 1010 .. ..... ..... @ldst_mult rpt=2 selem=1 551 552# Load/store single structure 553&ldst_single rm rn rt p selem index scale 554 555%ldst_single_selem 13:1 21:1 !function=plus_1 556 557%ldst_single_index_b 30:1 10:3 558%ldst_single_index_h 30:1 11:2 559%ldst_single_index_s 30:1 12:1 560 561@ldst_single_b .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \ 562 &ldst_single scale=0 selem=%ldst_single_selem \ 563 index=%ldst_single_index_b 564@ldst_single_h .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \ 565 &ldst_single scale=1 selem=%ldst_single_selem \ 566 index=%ldst_single_index_h 567@ldst_single_s .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \ 568 &ldst_single scale=2 selem=%ldst_single_selem \ 569 index=%ldst_single_index_s 570@ldst_single_d . index:1 ...... p:1 .. rm:5 ...... rn:5 rt:5 \ 571 &ldst_single scale=3 selem=%ldst_single_selem 572 573ST_single 0 . 001101 . 0 . ..... 00 . ... ..... ..... @ldst_single_b 574ST_single 0 . 001101 . 0 . ..... 01 . ..0 ..... ..... @ldst_single_h 575ST_single 0 . 001101 . 0 . ..... 10 . .00 ..... ..... @ldst_single_s 576ST_single 0 . 001101 . 0 . ..... 10 . 001 ..... ..... @ldst_single_d 577 578LD_single 0 . 001101 . 1 . ..... 00 . ... ..... ..... @ldst_single_b 579LD_single 0 . 001101 . 1 . ..... 01 . ..0 ..... ..... @ldst_single_h 580LD_single 0 . 001101 . 1 . ..... 10 . .00 ..... ..... @ldst_single_s 581LD_single 0 . 001101 . 1 . ..... 10 . 001 ..... ..... @ldst_single_d 582 583# Replicating load case 584LD_single_repl 0 q:1 001101 p:1 1 . rm:5 11 . 0 scale:2 rn:5 rt:5 selem=%ldst_single_selem 585 586%tag_offset 12:s9 !function=scale_by_log2_tag_granule 587&ldst_tag rn rt imm p w 588@ldst_tag ........ .. . ......... .. rn:5 rt:5 &ldst_tag imm=%tag_offset 589@ldst_tag_mult ........ .. . 000000000 .. rn:5 rt:5 &ldst_tag imm=0 590 591STZGM 11011001 00 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0 592STG 11011001 00 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 593STG 11011001 00 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 594STG 11011001 00 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 595 596LDG 11011001 01 1 ......... 00 ..... ..... @ldst_tag p=0 w=0 597STZG 11011001 01 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 598STZG 11011001 01 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 599STZG 11011001 01 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 600 601STGM 11011001 10 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0 602ST2G 11011001 10 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 603ST2G 11011001 10 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 604ST2G 11011001 10 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 605 606LDGM 11011001 11 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0 607STZ2G 11011001 11 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 608STZ2G 11011001 11 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 609STZ2G 11011001 11 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 610 611# Memory operations (memset, memcpy, memmove) 612# Each of these comes in a set of three, eg SETP (prologue), SETM (main), 613# SETE (epilogue), and each of those has different flavours to 614# indicate whether memory accesses should be unpriv or non-temporal. 615# We don't distinguish temporal and non-temporal accesses, but we 616# do need to report it in syndrome register values. 617 618# Memset 619&set rs rn rd unpriv nontemp 620# op2 bit 1 is nontemporal bit 621@set .. ......... rs:5 .. nontemp:1 unpriv:1 .. rn:5 rd:5 &set 622 623SETP 00 011001110 ..... 00 . . 01 ..... ..... @set 624SETM 00 011001110 ..... 01 . . 01 ..... ..... @set 625SETE 00 011001110 ..... 10 . . 01 ..... ..... @set 626 627# Like SET, but also setting MTE tags 628SETGP 00 011101110 ..... 00 . . 01 ..... ..... @set 629SETGM 00 011101110 ..... 01 . . 01 ..... ..... @set 630SETGE 00 011101110 ..... 10 . . 01 ..... ..... @set 631 632# Memmove/Memcopy: the CPY insns allow overlapping src/dest and 633# copy in the correct direction; the CPYF insns always copy forwards. 634# 635# options has the nontemporal and unpriv bits for src and dest 636&cpy rs rn rd options 637@cpy .. ... . ..... rs:5 options:4 .. rn:5 rd:5 &cpy 638 639CPYFP 00 011 0 01000 ..... .... 01 ..... ..... @cpy 640CPYFM 00 011 0 01010 ..... .... 01 ..... ..... @cpy 641CPYFE 00 011 0 01100 ..... .... 01 ..... ..... @cpy 642CPYP 00 011 1 01000 ..... .... 01 ..... ..... @cpy 643CPYM 00 011 1 01010 ..... .... 01 ..... ..... @cpy 644CPYE 00 011 1 01100 ..... .... 01 ..... ..... @cpy 645 646### Cryptographic AES 647 648AESE 01001110 00 10100 00100 10 ..... ..... @r2r_q1e0 649AESD 01001110 00 10100 00101 10 ..... ..... @r2r_q1e0 650AESMC 01001110 00 10100 00110 10 ..... ..... @rr_q1e0 651AESIMC 01001110 00 10100 00111 10 ..... ..... @rr_q1e0 652 653### Cryptographic three-register SHA 654 655SHA1C 0101 1110 000 ..... 000000 ..... ..... @rrr_q1e0 656SHA1P 0101 1110 000 ..... 000100 ..... ..... @rrr_q1e0 657SHA1M 0101 1110 000 ..... 001000 ..... ..... @rrr_q1e0 658SHA1SU0 0101 1110 000 ..... 001100 ..... ..... @rrr_q1e0 659SHA256H 0101 1110 000 ..... 010000 ..... ..... @rrr_q1e0 660SHA256H2 0101 1110 000 ..... 010100 ..... ..... @rrr_q1e0 661SHA256SU1 0101 1110 000 ..... 011000 ..... ..... @rrr_q1e0 662 663### Cryptographic two-register SHA 664 665SHA1H 0101 1110 0010 1000 0000 10 ..... ..... @rr_q1e0 666SHA1SU1 0101 1110 0010 1000 0001 10 ..... ..... @rr_q1e0 667SHA256SU0 0101 1110 0010 1000 0010 10 ..... ..... @rr_q1e0 668 669### Cryptographic three-register SHA512 670 671SHA512H 1100 1110 011 ..... 100000 ..... ..... @rrr_q1e0 672SHA512H2 1100 1110 011 ..... 100001 ..... ..... @rrr_q1e0 673SHA512SU1 1100 1110 011 ..... 100010 ..... ..... @rrr_q1e0 674RAX1 1100 1110 011 ..... 100011 ..... ..... @rrr_q1e3 675SM3PARTW1 1100 1110 011 ..... 110000 ..... ..... @rrr_q1e0 676SM3PARTW2 1100 1110 011 ..... 110001 ..... ..... @rrr_q1e0 677SM4EKEY 1100 1110 011 ..... 110010 ..... ..... @rrr_q1e0 678 679### Cryptographic two-register SHA512 680 681SHA512SU0 1100 1110 110 00000 100000 ..... ..... @rr_q1e0 682SM4E 1100 1110 110 00000 100001 ..... ..... @r2r_q1e0 683 684### Cryptographic four-register 685 686EOR3 1100 1110 000 ..... 0 ..... ..... ..... @rrrr_q1e3 687BCAX 1100 1110 001 ..... 0 ..... ..... ..... @rrrr_q1e3 688SM3SS1 1100 1110 010 ..... 0 ..... ..... ..... @rrrr_q1e3 689 690### Cryptographic three-register, imm2 691 692&crypto3i rd rn rm imm 693@crypto3i ........ ... rm:5 .. imm:2 .. rn:5 rd:5 &crypto3i 694 695SM3TT1A 11001110 010 ..... 10 .. 00 ..... ..... @crypto3i 696SM3TT1B 11001110 010 ..... 10 .. 01 ..... ..... @crypto3i 697SM3TT2A 11001110 010 ..... 10 .. 10 ..... ..... @crypto3i 698SM3TT2B 11001110 010 ..... 10 .. 11 ..... ..... @crypto3i 699 700### Cryptographic XAR 701 702XAR 1100 1110 100 rm:5 imm:6 rn:5 rd:5 703 704### Advanced SIMD scalar copy 705 706DUP_element_s 0101 1110 000 imm:5 0 0000 1 rn:5 rd:5 707 708### Advanced SIMD copy 709 710DUP_element_v 0 q:1 00 1110 000 imm:5 0 0000 1 rn:5 rd:5 711DUP_general 0 q:1 00 1110 000 imm:5 0 0001 1 rn:5 rd:5 712INS_general 0 1 00 1110 000 imm:5 0 0011 1 rn:5 rd:5 713SMOV 0 q:1 00 1110 000 imm:5 0 0101 1 rn:5 rd:5 714UMOV 0 q:1 00 1110 000 imm:5 0 0111 1 rn:5 rd:5 715INS_element 0 1 10 1110 000 di:5 0 si:4 1 rn:5 rd:5 716 717### Advanced SIMD scalar three same 718 719FADD_s 0001 1110 ..1 ..... 0010 10 ..... ..... @rrr_hsd 720FSUB_s 0001 1110 ..1 ..... 0011 10 ..... ..... @rrr_hsd 721FDIV_s 0001 1110 ..1 ..... 0001 10 ..... ..... @rrr_hsd 722FMUL_s 0001 1110 ..1 ..... 0000 10 ..... ..... @rrr_hsd 723FNMUL_s 0001 1110 ..1 ..... 1000 10 ..... ..... @rrr_hsd 724 725FMAX_s 0001 1110 ..1 ..... 0100 10 ..... ..... @rrr_hsd 726FMIN_s 0001 1110 ..1 ..... 0101 10 ..... ..... @rrr_hsd 727FMAXNM_s 0001 1110 ..1 ..... 0110 10 ..... ..... @rrr_hsd 728FMINNM_s 0001 1110 ..1 ..... 0111 10 ..... ..... @rrr_hsd 729 730FMULX_s 0101 1110 010 ..... 00011 1 ..... ..... @rrr_h 731FMULX_s 0101 1110 0.1 ..... 11011 1 ..... ..... @rrr_sd 732 733FCMEQ_s 0101 1110 010 ..... 00100 1 ..... ..... @rrr_h 734FCMEQ_s 0101 1110 0.1 ..... 11100 1 ..... ..... @rrr_sd 735 736FCMGE_s 0111 1110 010 ..... 00100 1 ..... ..... @rrr_h 737FCMGE_s 0111 1110 0.1 ..... 11100 1 ..... ..... @rrr_sd 738 739FCMGT_s 0111 1110 110 ..... 00100 1 ..... ..... @rrr_h 740FCMGT_s 0111 1110 1.1 ..... 11100 1 ..... ..... @rrr_sd 741 742FACGE_s 0111 1110 010 ..... 00101 1 ..... ..... @rrr_h 743FACGE_s 0111 1110 0.1 ..... 11101 1 ..... ..... @rrr_sd 744 745FACGT_s 0111 1110 110 ..... 00101 1 ..... ..... @rrr_h 746FACGT_s 0111 1110 1.1 ..... 11101 1 ..... ..... @rrr_sd 747 748FABD_s 0111 1110 110 ..... 00010 1 ..... ..... @rrr_h 749FABD_s 0111 1110 1.1 ..... 11010 1 ..... ..... @rrr_sd 750 751FRECPS_s 0101 1110 010 ..... 00111 1 ..... ..... @rrr_h 752FRECPS_s 0101 1110 0.1 ..... 11111 1 ..... ..... @rrr_sd 753 754FRSQRTS_s 0101 1110 110 ..... 00111 1 ..... ..... @rrr_h 755FRSQRTS_s 0101 1110 1.1 ..... 11111 1 ..... ..... @rrr_sd 756 757SQADD_s 0101 1110 ..1 ..... 00001 1 ..... ..... @rrr_e 758UQADD_s 0111 1110 ..1 ..... 00001 1 ..... ..... @rrr_e 759SQSUB_s 0101 1110 ..1 ..... 00101 1 ..... ..... @rrr_e 760UQSUB_s 0111 1110 ..1 ..... 00101 1 ..... ..... @rrr_e 761 762SUQADD_s 0101 1110 ..1 00000 00111 0 ..... ..... @r2r_e 763USQADD_s 0111 1110 ..1 00000 00111 0 ..... ..... @r2r_e 764 765SSHL_s 0101 1110 111 ..... 01000 1 ..... ..... @rrr_d 766USHL_s 0111 1110 111 ..... 01000 1 ..... ..... @rrr_d 767SRSHL_s 0101 1110 111 ..... 01010 1 ..... ..... @rrr_d 768URSHL_s 0111 1110 111 ..... 01010 1 ..... ..... @rrr_d 769SQSHL_s 0101 1110 ..1 ..... 01001 1 ..... ..... @rrr_e 770UQSHL_s 0111 1110 ..1 ..... 01001 1 ..... ..... @rrr_e 771SQRSHL_s 0101 1110 ..1 ..... 01011 1 ..... ..... @rrr_e 772UQRSHL_s 0111 1110 ..1 ..... 01011 1 ..... ..... @rrr_e 773 774ADD_s 0101 1110 111 ..... 10000 1 ..... ..... @rrr_d 775SUB_s 0111 1110 111 ..... 10000 1 ..... ..... @rrr_d 776CMGT_s 0101 1110 111 ..... 00110 1 ..... ..... @rrr_d 777CMHI_s 0111 1110 111 ..... 00110 1 ..... ..... @rrr_d 778CMGE_s 0101 1110 111 ..... 00111 1 ..... ..... @rrr_d 779CMHS_s 0111 1110 111 ..... 00111 1 ..... ..... @rrr_d 780CMTST_s 0101 1110 111 ..... 10001 1 ..... ..... @rrr_d 781CMEQ_s 0111 1110 111 ..... 10001 1 ..... ..... @rrr_d 782 783SQDMULH_s 0101 1110 ..1 ..... 10110 1 ..... ..... @rrr_e 784SQRDMULH_s 0111 1110 ..1 ..... 10110 1 ..... ..... @rrr_e 785SQRDMLAH_s 0111 1110 ..0 ..... 10000 1 ..... ..... @rrr_e 786SQRDMLSH_s 0111 1110 ..0 ..... 10001 1 ..... ..... @rrr_e 787 788### Advanced SIMD scalar pairwise 789 790FADDP_s 0101 1110 0011 0000 1101 10 ..... ..... @rr_h 791FADDP_s 0111 1110 0.11 0000 1101 10 ..... ..... @rr_sd 792 793FMAXP_s 0101 1110 0011 0000 1111 10 ..... ..... @rr_h 794FMAXP_s 0111 1110 0.11 0000 1111 10 ..... ..... @rr_sd 795 796FMINP_s 0101 1110 1011 0000 1111 10 ..... ..... @rr_h 797FMINP_s 0111 1110 1.11 0000 1111 10 ..... ..... @rr_sd 798 799FMAXNMP_s 0101 1110 0011 0000 1100 10 ..... ..... @rr_h 800FMAXNMP_s 0111 1110 0.11 0000 1100 10 ..... ..... @rr_sd 801 802FMINNMP_s 0101 1110 1011 0000 1100 10 ..... ..... @rr_h 803FMINNMP_s 0111 1110 1.11 0000 1100 10 ..... ..... @rr_sd 804 805ADDP_s 0101 1110 1111 0001 1011 10 ..... ..... @rr_d 806 807### Advanced SIMD three same 808 809FADD_v 0.00 1110 010 ..... 00010 1 ..... ..... @qrrr_h 810FADD_v 0.00 1110 0.1 ..... 11010 1 ..... ..... @qrrr_sd 811 812FSUB_v 0.00 1110 110 ..... 00010 1 ..... ..... @qrrr_h 813FSUB_v 0.00 1110 1.1 ..... 11010 1 ..... ..... @qrrr_sd 814 815FDIV_v 0.10 1110 010 ..... 00111 1 ..... ..... @qrrr_h 816FDIV_v 0.10 1110 0.1 ..... 11111 1 ..... ..... @qrrr_sd 817 818FMUL_v 0.10 1110 010 ..... 00011 1 ..... ..... @qrrr_h 819FMUL_v 0.10 1110 0.1 ..... 11011 1 ..... ..... @qrrr_sd 820 821FMAX_v 0.00 1110 010 ..... 00110 1 ..... ..... @qrrr_h 822FMAX_v 0.00 1110 0.1 ..... 11110 1 ..... ..... @qrrr_sd 823 824FMIN_v 0.00 1110 110 ..... 00110 1 ..... ..... @qrrr_h 825FMIN_v 0.00 1110 1.1 ..... 11110 1 ..... ..... @qrrr_sd 826 827FMAXNM_v 0.00 1110 010 ..... 00000 1 ..... ..... @qrrr_h 828FMAXNM_v 0.00 1110 0.1 ..... 11000 1 ..... ..... @qrrr_sd 829 830FMINNM_v 0.00 1110 110 ..... 00000 1 ..... ..... @qrrr_h 831FMINNM_v 0.00 1110 1.1 ..... 11000 1 ..... ..... @qrrr_sd 832 833FMULX_v 0.00 1110 010 ..... 00011 1 ..... ..... @qrrr_h 834FMULX_v 0.00 1110 0.1 ..... 11011 1 ..... ..... @qrrr_sd 835 836FMLA_v 0.00 1110 010 ..... 00001 1 ..... ..... @qrrr_h 837FMLA_v 0.00 1110 0.1 ..... 11001 1 ..... ..... @qrrr_sd 838 839FMLS_v 0.00 1110 110 ..... 00001 1 ..... ..... @qrrr_h 840FMLS_v 0.00 1110 1.1 ..... 11001 1 ..... ..... @qrrr_sd 841 842FMLAL_v 0.00 1110 001 ..... 11101 1 ..... ..... @qrrr_h 843FMLSL_v 0.00 1110 101 ..... 11101 1 ..... ..... @qrrr_h 844FMLAL2_v 0.10 1110 001 ..... 11001 1 ..... ..... @qrrr_h 845FMLSL2_v 0.10 1110 101 ..... 11001 1 ..... ..... @qrrr_h 846 847FCMEQ_v 0.00 1110 010 ..... 00100 1 ..... ..... @qrrr_h 848FCMEQ_v 0.00 1110 0.1 ..... 11100 1 ..... ..... @qrrr_sd 849 850FCMGE_v 0.10 1110 010 ..... 00100 1 ..... ..... @qrrr_h 851FCMGE_v 0.10 1110 0.1 ..... 11100 1 ..... ..... @qrrr_sd 852 853FCMGT_v 0.10 1110 110 ..... 00100 1 ..... ..... @qrrr_h 854FCMGT_v 0.10 1110 1.1 ..... 11100 1 ..... ..... @qrrr_sd 855 856FACGE_v 0.10 1110 010 ..... 00101 1 ..... ..... @qrrr_h 857FACGE_v 0.10 1110 0.1 ..... 11101 1 ..... ..... @qrrr_sd 858 859FACGT_v 0.10 1110 110 ..... 00101 1 ..... ..... @qrrr_h 860FACGT_v 0.10 1110 1.1 ..... 11101 1 ..... ..... @qrrr_sd 861 862FABD_v 0.10 1110 110 ..... 00010 1 ..... ..... @qrrr_h 863FABD_v 0.10 1110 1.1 ..... 11010 1 ..... ..... @qrrr_sd 864 865FRECPS_v 0.00 1110 010 ..... 00111 1 ..... ..... @qrrr_h 866FRECPS_v 0.00 1110 0.1 ..... 11111 1 ..... ..... @qrrr_sd 867 868FRSQRTS_v 0.00 1110 110 ..... 00111 1 ..... ..... @qrrr_h 869FRSQRTS_v 0.00 1110 1.1 ..... 11111 1 ..... ..... @qrrr_sd 870 871FADDP_v 0.10 1110 010 ..... 00010 1 ..... ..... @qrrr_h 872FADDP_v 0.10 1110 0.1 ..... 11010 1 ..... ..... @qrrr_sd 873 874FMAXP_v 0.10 1110 010 ..... 00110 1 ..... ..... @qrrr_h 875FMAXP_v 0.10 1110 0.1 ..... 11110 1 ..... ..... @qrrr_sd 876 877FMINP_v 0.10 1110 110 ..... 00110 1 ..... ..... @qrrr_h 878FMINP_v 0.10 1110 1.1 ..... 11110 1 ..... ..... @qrrr_sd 879 880FMAXNMP_v 0.10 1110 010 ..... 00000 1 ..... ..... @qrrr_h 881FMAXNMP_v 0.10 1110 0.1 ..... 11000 1 ..... ..... @qrrr_sd 882 883FMINNMP_v 0.10 1110 110 ..... 00000 1 ..... ..... @qrrr_h 884FMINNMP_v 0.10 1110 1.1 ..... 11000 1 ..... ..... @qrrr_sd 885 886ADDP_v 0.00 1110 ..1 ..... 10111 1 ..... ..... @qrrr_e 887SMAXP_v 0.00 1110 ..1 ..... 10100 1 ..... ..... @qrrr_e 888SMINP_v 0.00 1110 ..1 ..... 10101 1 ..... ..... @qrrr_e 889UMAXP_v 0.10 1110 ..1 ..... 10100 1 ..... ..... @qrrr_e 890UMINP_v 0.10 1110 ..1 ..... 10101 1 ..... ..... @qrrr_e 891 892AND_v 0.00 1110 001 ..... 00011 1 ..... ..... @qrrr_b 893BIC_v 0.00 1110 011 ..... 00011 1 ..... ..... @qrrr_b 894ORR_v 0.00 1110 101 ..... 00011 1 ..... ..... @qrrr_b 895ORN_v 0.00 1110 111 ..... 00011 1 ..... ..... @qrrr_b 896EOR_v 0.10 1110 001 ..... 00011 1 ..... ..... @qrrr_b 897BSL_v 0.10 1110 011 ..... 00011 1 ..... ..... @qrrr_b 898BIT_v 0.10 1110 101 ..... 00011 1 ..... ..... @qrrr_b 899BIF_v 0.10 1110 111 ..... 00011 1 ..... ..... @qrrr_b 900 901SQADD_v 0.00 1110 ..1 ..... 00001 1 ..... ..... @qrrr_e 902UQADD_v 0.10 1110 ..1 ..... 00001 1 ..... ..... @qrrr_e 903SQSUB_v 0.00 1110 ..1 ..... 00101 1 ..... ..... @qrrr_e 904UQSUB_v 0.10 1110 ..1 ..... 00101 1 ..... ..... @qrrr_e 905 906SUQADD_v 0.00 1110 ..1 00000 00111 0 ..... ..... @qr2r_e 907USQADD_v 0.10 1110 ..1 00000 00111 0 ..... ..... @qr2r_e 908 909SSHL_v 0.00 1110 ..1 ..... 01000 1 ..... ..... @qrrr_e 910USHL_v 0.10 1110 ..1 ..... 01000 1 ..... ..... @qrrr_e 911SRSHL_v 0.00 1110 ..1 ..... 01010 1 ..... ..... @qrrr_e 912URSHL_v 0.10 1110 ..1 ..... 01010 1 ..... ..... @qrrr_e 913SQSHL_v 0.00 1110 ..1 ..... 01001 1 ..... ..... @qrrr_e 914UQSHL_v 0.10 1110 ..1 ..... 01001 1 ..... ..... @qrrr_e 915SQRSHL_v 0.00 1110 ..1 ..... 01011 1 ..... ..... @qrrr_e 916UQRSHL_v 0.10 1110 ..1 ..... 01011 1 ..... ..... @qrrr_e 917 918ADD_v 0.00 1110 ..1 ..... 10000 1 ..... ..... @qrrr_e 919SUB_v 0.10 1110 ..1 ..... 10000 1 ..... ..... @qrrr_e 920CMGT_v 0.00 1110 ..1 ..... 00110 1 ..... ..... @qrrr_e 921CMHI_v 0.10 1110 ..1 ..... 00110 1 ..... ..... @qrrr_e 922CMGE_v 0.00 1110 ..1 ..... 00111 1 ..... ..... @qrrr_e 923CMHS_v 0.10 1110 ..1 ..... 00111 1 ..... ..... @qrrr_e 924CMTST_v 0.00 1110 ..1 ..... 10001 1 ..... ..... @qrrr_e 925CMEQ_v 0.10 1110 ..1 ..... 10001 1 ..... ..... @qrrr_e 926SHADD_v 0.00 1110 ..1 ..... 00000 1 ..... ..... @qrrr_e 927UHADD_v 0.10 1110 ..1 ..... 00000 1 ..... ..... @qrrr_e 928SHSUB_v 0.00 1110 ..1 ..... 00100 1 ..... ..... @qrrr_e 929UHSUB_v 0.10 1110 ..1 ..... 00100 1 ..... ..... @qrrr_e 930SRHADD_v 0.00 1110 ..1 ..... 00010 1 ..... ..... @qrrr_e 931URHADD_v 0.10 1110 ..1 ..... 00010 1 ..... ..... @qrrr_e 932SMAX_v 0.00 1110 ..1 ..... 01100 1 ..... ..... @qrrr_e 933UMAX_v 0.10 1110 ..1 ..... 01100 1 ..... ..... @qrrr_e 934SMIN_v 0.00 1110 ..1 ..... 01101 1 ..... ..... @qrrr_e 935UMIN_v 0.10 1110 ..1 ..... 01101 1 ..... ..... @qrrr_e 936SABD_v 0.00 1110 ..1 ..... 01110 1 ..... ..... @qrrr_e 937UABD_v 0.10 1110 ..1 ..... 01110 1 ..... ..... @qrrr_e 938SABA_v 0.00 1110 ..1 ..... 01111 1 ..... ..... @qrrr_e 939UABA_v 0.10 1110 ..1 ..... 01111 1 ..... ..... @qrrr_e 940MUL_v 0.00 1110 ..1 ..... 10011 1 ..... ..... @qrrr_e 941PMUL_v 0.10 1110 001 ..... 10011 1 ..... ..... @qrrr_b 942MLA_v 0.00 1110 ..1 ..... 10010 1 ..... ..... @qrrr_e 943MLS_v 0.10 1110 ..1 ..... 10010 1 ..... ..... @qrrr_e 944 945SQDMULH_v 0.00 1110 ..1 ..... 10110 1 ..... ..... @qrrr_e 946SQRDMULH_v 0.10 1110 ..1 ..... 10110 1 ..... ..... @qrrr_e 947SQRDMLAH_v 0.10 1110 ..0 ..... 10000 1 ..... ..... @qrrr_e 948SQRDMLSH_v 0.10 1110 ..0 ..... 10001 1 ..... ..... @qrrr_e 949 950SDOT_v 0.00 1110 100 ..... 10010 1 ..... ..... @qrrr_s 951UDOT_v 0.10 1110 100 ..... 10010 1 ..... ..... @qrrr_s 952USDOT_v 0.00 1110 100 ..... 10011 1 ..... ..... @qrrr_s 953BFDOT_v 0.10 1110 010 ..... 11111 1 ..... ..... @qrrr_s 954BFMLAL_v 0.10 1110 110 ..... 11111 1 ..... ..... @qrrr_h 955BFMMLA 0110 1110 010 ..... 11101 1 ..... ..... @rrr_q1e0 956SMMLA 0100 1110 100 ..... 10100 1 ..... ..... @rrr_q1e0 957UMMLA 0110 1110 100 ..... 10100 1 ..... ..... @rrr_q1e0 958USMMLA 0100 1110 100 ..... 10101 1 ..... ..... @rrr_q1e0 959 960FCADD_90 0.10 1110 ..0 ..... 11100 1 ..... ..... @qrrr_e 961FCADD_270 0.10 1110 ..0 ..... 11110 1 ..... ..... @qrrr_e 962 963FCMLA_v 0 q:1 10 1110 esz:2 0 rm:5 110 rot:2 1 rn:5 rd:5 964 965### Advanced SIMD scalar x indexed element 966 967FMUL_si 0101 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h 968FMUL_si 0101 1111 10 . ..... 1001 . 0 ..... ..... @rrx_s 969FMUL_si 0101 1111 11 0 ..... 1001 . 0 ..... ..... @rrx_d 970 971FMLA_si 0101 1111 00 .. .... 0001 . 0 ..... ..... @rrx_h 972FMLA_si 0101 1111 10 .. .... 0001 . 0 ..... ..... @rrx_s 973FMLA_si 0101 1111 11 0. .... 0001 . 0 ..... ..... @rrx_d 974 975FMLS_si 0101 1111 00 .. .... 0101 . 0 ..... ..... @rrx_h 976FMLS_si 0101 1111 10 .. .... 0101 . 0 ..... ..... @rrx_s 977FMLS_si 0101 1111 11 0. .... 0101 . 0 ..... ..... @rrx_d 978 979FMULX_si 0111 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h 980FMULX_si 0111 1111 10 . ..... 1001 . 0 ..... ..... @rrx_s 981FMULX_si 0111 1111 11 0 ..... 1001 . 0 ..... ..... @rrx_d 982 983SQDMULH_si 0101 1111 01 .. .... 1100 . 0 ..... ..... @rrx_h 984SQDMULH_si 0101 1111 10 .. .... 1100 . 0 ..... ..... @rrx_s 985 986SQRDMULH_si 0101 1111 01 .. .... 1101 . 0 ..... ..... @rrx_h 987SQRDMULH_si 0101 1111 10 . ..... 1101 . 0 ..... ..... @rrx_s 988 989SQRDMLAH_si 0111 1111 01 .. .... 1101 . 0 ..... ..... @rrx_h 990SQRDMLAH_si 0111 1111 10 .. .... 1101 . 0 ..... ..... @rrx_s 991 992SQRDMLSH_si 0111 1111 01 .. .... 1111 . 0 ..... ..... @rrx_h 993SQRDMLSH_si 0111 1111 10 .. .... 1111 . 0 ..... ..... @rrx_s 994 995### Advanced SIMD vector x indexed element 996 997FMUL_vi 0.00 1111 00 .. .... 1001 . 0 ..... ..... @qrrx_h 998FMUL_vi 0.00 1111 10 . ..... 1001 . 0 ..... ..... @qrrx_s 999FMUL_vi 0.00 1111 11 0 ..... 1001 . 0 ..... ..... @qrrx_d 1000 1001FMLA_vi 0.00 1111 00 .. .... 0001 . 0 ..... ..... @qrrx_h 1002FMLA_vi 0.00 1111 10 . ..... 0001 . 0 ..... ..... @qrrx_s 1003FMLA_vi 0.00 1111 11 0 ..... 0001 . 0 ..... ..... @qrrx_d 1004 1005FMLS_vi 0.00 1111 00 .. .... 0101 . 0 ..... ..... @qrrx_h 1006FMLS_vi 0.00 1111 10 . ..... 0101 . 0 ..... ..... @qrrx_s 1007FMLS_vi 0.00 1111 11 0 ..... 0101 . 0 ..... ..... @qrrx_d 1008 1009FMULX_vi 0.10 1111 00 .. .... 1001 . 0 ..... ..... @qrrx_h 1010FMULX_vi 0.10 1111 10 . ..... 1001 . 0 ..... ..... @qrrx_s 1011FMULX_vi 0.10 1111 11 0 ..... 1001 . 0 ..... ..... @qrrx_d 1012 1013FMLAL_vi 0.00 1111 10 .. .... 0000 . 0 ..... ..... @qrrx_h 1014FMLSL_vi 0.00 1111 10 .. .... 0100 . 0 ..... ..... @qrrx_h 1015FMLAL2_vi 0.10 1111 10 .. .... 1000 . 0 ..... ..... @qrrx_h 1016FMLSL2_vi 0.10 1111 10 .. .... 1100 . 0 ..... ..... @qrrx_h 1017 1018MUL_vi 0.00 1111 01 .. .... 1000 . 0 ..... ..... @qrrx_h 1019MUL_vi 0.00 1111 10 . ..... 1000 . 0 ..... ..... @qrrx_s 1020 1021MLA_vi 0.10 1111 01 .. .... 0000 . 0 ..... ..... @qrrx_h 1022MLA_vi 0.10 1111 10 . ..... 0000 . 0 ..... ..... @qrrx_s 1023 1024MLS_vi 0.10 1111 01 .. .... 0100 . 0 ..... ..... @qrrx_h 1025MLS_vi 0.10 1111 10 . ..... 0100 . 0 ..... ..... @qrrx_s 1026 1027SQDMULH_vi 0.00 1111 01 .. .... 1100 . 0 ..... ..... @qrrx_h 1028SQDMULH_vi 0.00 1111 10 . ..... 1100 . 0 ..... ..... @qrrx_s 1029 1030SQRDMULH_vi 0.00 1111 01 .. .... 1101 . 0 ..... ..... @qrrx_h 1031SQRDMULH_vi 0.00 1111 10 . ..... 1101 . 0 ..... ..... @qrrx_s 1032 1033SQRDMLAH_vi 0.10 1111 01 .. .... 1101 . 0 ..... ..... @qrrx_h 1034SQRDMLAH_vi 0.10 1111 10 .. .... 1101 . 0 ..... ..... @qrrx_s 1035 1036SQRDMLSH_vi 0.10 1111 01 .. .... 1111 . 0 ..... ..... @qrrx_h 1037SQRDMLSH_vi 0.10 1111 10 .. .... 1111 . 0 ..... ..... @qrrx_s 1038 1039SDOT_vi 0.00 1111 10 .. .... 1110 . 0 ..... ..... @qrrx_s 1040UDOT_vi 0.10 1111 10 .. .... 1110 . 0 ..... ..... @qrrx_s 1041SUDOT_vi 0.00 1111 00 .. .... 1111 . 0 ..... ..... @qrrx_s 1042USDOT_vi 0.00 1111 10 .. .... 1111 . 0 ..... ..... @qrrx_s 1043BFDOT_vi 0.00 1111 01 .. .... 1111 . 0 ..... ..... @qrrx_s 1044BFMLAL_vi 0.00 1111 11 .. .... 1111 . 0 ..... ..... @qrrx_h 1045 1046FCMLA_vi 0 0 10 1111 01 idx:1 rm:5 0 rot:2 1 0 0 rn:5 rd:5 esz=1 q=0 1047FCMLA_vi 0 1 10 1111 01 . rm:5 0 rot:2 1 . 0 rn:5 rd:5 esz=1 idx=%hl q=1 1048FCMLA_vi 0 1 10 1111 10 0 rm:5 0 rot:2 1 idx:1 0 rn:5 rd:5 esz=2 q=1 1049 1050# Floating-point conditional select 1051 1052FCSEL 0001 1110 .. 1 rm:5 cond:4 11 rn:5 rd:5 esz=%esz_hsd 1053 1054# Floating-point data-processing (3 source) 1055 1056@rrrr_hsd .... .... .. . rm:5 . ra:5 rn:5 rd:5 &rrrr_e esz=%esz_hsd 1057 1058FMADD 0001 1111 .. 0 ..... 0 ..... ..... ..... @rrrr_hsd 1059FMSUB 0001 1111 .. 0 ..... 1 ..... ..... ..... @rrrr_hsd 1060FNMADD 0001 1111 .. 1 ..... 0 ..... ..... ..... @rrrr_hsd 1061FNMSUB 0001 1111 .. 1 ..... 1 ..... ..... ..... @rrrr_hsd 1062