1# AArch64 A64 allowed instruction decoding 2# 3# Copyright (c) 2023 Linaro, Ltd 4# 5# This library is free software; you can redistribute it and/or 6# modify it under the terms of the GNU Lesser General Public 7# License as published by the Free Software Foundation; either 8# version 2.1 of the License, or (at your option) any later version. 9# 10# This library is distributed in the hope that it will be useful, 11# but WITHOUT ANY WARRANTY; without even the implied warranty of 12# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13# Lesser General Public License for more details. 14# 15# You should have received a copy of the GNU Lesser General Public 16# License along with this library; if not, see <http://www.gnu.org/licenses/>. 17 18# 19# This file is processed by scripts/decodetree.py 20# 21 22&r rn 23&ri rd imm 24&rri_sf rd rn imm sf 25&i imm 26 27 28### Data Processing - Immediate 29 30# PC-rel addressing 31 32%imm_pcrel 5:s19 29:2 33@pcrel . .. ..... ................... rd:5 &ri imm=%imm_pcrel 34 35ADR 0 .. 10000 ................... ..... @pcrel 36ADRP 1 .. 10000 ................... ..... @pcrel 37 38# Add/subtract (immediate) 39 40%imm12_sh12 10:12 !function=shl_12 41@addsub_imm sf:1 .. ...... . imm:12 rn:5 rd:5 42@addsub_imm12 sf:1 .. ...... . ............ rn:5 rd:5 imm=%imm12_sh12 43 44ADD_i . 00 100010 0 ............ ..... ..... @addsub_imm 45ADD_i . 00 100010 1 ............ ..... ..... @addsub_imm12 46ADDS_i . 01 100010 0 ............ ..... ..... @addsub_imm 47ADDS_i . 01 100010 1 ............ ..... ..... @addsub_imm12 48 49SUB_i . 10 100010 0 ............ ..... ..... @addsub_imm 50SUB_i . 10 100010 1 ............ ..... ..... @addsub_imm12 51SUBS_i . 11 100010 0 ............ ..... ..... @addsub_imm 52SUBS_i . 11 100010 1 ............ ..... ..... @addsub_imm12 53 54# Add/subtract (immediate with tags) 55 56&rri_tag rd rn uimm6 uimm4 57@addsub_imm_tag . .. ...... . uimm6:6 .. uimm4:4 rn:5 rd:5 &rri_tag 58 59ADDG_i 1 00 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag 60SUBG_i 1 10 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag 61 62# Logical (immediate) 63 64&rri_log rd rn sf dbm 65@logic_imm_64 1 .. ...... dbm:13 rn:5 rd:5 &rri_log sf=1 66@logic_imm_32 0 .. ...... 0 dbm:12 rn:5 rd:5 &rri_log sf=0 67 68AND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_64 69AND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_32 70ORR_i . 01 100100 . ...... ...... ..... ..... @logic_imm_64 71ORR_i . 01 100100 . ...... ...... ..... ..... @logic_imm_32 72EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_64 73EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_32 74ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_64 75ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_32 76 77# Move wide (immediate) 78 79&movw rd sf imm hw 80@movw_64 1 .. ...... hw:2 imm:16 rd:5 &movw sf=1 81@movw_32 0 .. ...... 0 hw:1 imm:16 rd:5 &movw sf=0 82 83MOVN . 00 100101 .. ................ ..... @movw_64 84MOVN . 00 100101 .. ................ ..... @movw_32 85MOVZ . 10 100101 .. ................ ..... @movw_64 86MOVZ . 10 100101 .. ................ ..... @movw_32 87MOVK . 11 100101 .. ................ ..... @movw_64 88MOVK . 11 100101 .. ................ ..... @movw_32 89 90# Bitfield 91 92&bitfield rd rn sf immr imms 93@bitfield_64 1 .. ...... 1 immr:6 imms:6 rn:5 rd:5 &bitfield sf=1 94@bitfield_32 0 .. ...... 0 0 immr:5 0 imms:5 rn:5 rd:5 &bitfield sf=0 95 96SBFM . 00 100110 . ...... ...... ..... ..... @bitfield_64 97SBFM . 00 100110 . ...... ...... ..... ..... @bitfield_32 98BFM . 01 100110 . ...... ...... ..... ..... @bitfield_64 99BFM . 01 100110 . ...... ...... ..... ..... @bitfield_32 100UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_64 101UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_32 102 103# Extract 104 105&extract rd rn rm imm sf 106 107EXTR 1 00 100111 1 0 rm:5 imm:6 rn:5 rd:5 &extract sf=1 108EXTR 0 00 100111 0 0 rm:5 0 imm:5 rn:5 rd:5 &extract sf=0 109 110# Branches 111 112%imm26 0:s26 !function=times_4 113@branch . ..... .......................... &i imm=%imm26 114 115B 0 00101 .......................... @branch 116BL 1 00101 .......................... @branch 117 118%imm19 5:s19 !function=times_4 119&cbz rt imm sf nz 120 121CBZ sf:1 011010 nz:1 ................... rt:5 &cbz imm=%imm19 122 123%imm14 5:s14 !function=times_4 124%imm31_19 31:1 19:5 125&tbz rt imm nz bitpos 126 127TBZ . 011011 nz:1 ..... .............. rt:5 &tbz imm=%imm14 bitpos=%imm31_19 128 129B_cond 0101010 0 ................... 0 cond:4 imm=%imm19 130 131BR 1101011 0000 11111 000000 rn:5 00000 &r 132BLR 1101011 0001 11111 000000 rn:5 00000 &r 133RET 1101011 0010 11111 000000 rn:5 00000 &r 134 135&braz rn m 136BRAZ 1101011 0000 11111 00001 m:1 rn:5 11111 &braz # BRAAZ, BRABZ 137BLRAZ 1101011 0001 11111 00001 m:1 rn:5 11111 &braz # BLRAAZ, BLRABZ 138 139&reta m 140RETA 1101011 0010 11111 00001 m:1 11111 11111 &reta # RETAA, RETAB 141 142&bra rn rm m 143BRA 1101011 1000 11111 00001 m:1 rn:5 rm:5 &bra # BRAA, BRAB 144BLRA 1101011 1001 11111 00001 m:1 rn:5 rm:5 &bra # BLRAA, BLRAB 145 146ERET 1101011 0100 11111 000000 11111 00000 147ERETA 1101011 0100 11111 00001 m:1 11111 11111 &reta # ERETAA, ERETAB 148 149# We don't need to decode DRPS because it always UNDEFs except when 150# the processor is in halting debug state (which we don't implement). 151# The pattern is listed here as documentation. 152# DRPS 1101011 0101 11111 000000 11111 00000 153 154# Hint instruction group 155{ 156 [ 157 YIELD 1101 0101 0000 0011 0010 0000 001 11111 158 WFE 1101 0101 0000 0011 0010 0000 010 11111 159 WFI 1101 0101 0000 0011 0010 0000 011 11111 160 # We implement WFE to never block, so our SEV/SEVL are NOPs 161 # SEV 1101 0101 0000 0011 0010 0000 100 11111 162 # SEVL 1101 0101 0000 0011 0010 0000 101 11111 163 # Our DGL is a NOP because we don't merge memory accesses anyway. 164 # DGL 1101 0101 0000 0011 0010 0000 110 11111 165 XPACLRI 1101 0101 0000 0011 0010 0000 111 11111 166 PACIA1716 1101 0101 0000 0011 0010 0001 000 11111 167 PACIB1716 1101 0101 0000 0011 0010 0001 010 11111 168 AUTIA1716 1101 0101 0000 0011 0010 0001 100 11111 169 AUTIB1716 1101 0101 0000 0011 0010 0001 110 11111 170 ESB 1101 0101 0000 0011 0010 0010 000 11111 171 PACIAZ 1101 0101 0000 0011 0010 0011 000 11111 172 PACIASP 1101 0101 0000 0011 0010 0011 001 11111 173 PACIBZ 1101 0101 0000 0011 0010 0011 010 11111 174 PACIBSP 1101 0101 0000 0011 0010 0011 011 11111 175 AUTIAZ 1101 0101 0000 0011 0010 0011 100 11111 176 AUTIASP 1101 0101 0000 0011 0010 0011 101 11111 177 AUTIBZ 1101 0101 0000 0011 0010 0011 110 11111 178 AUTIBSP 1101 0101 0000 0011 0010 0011 111 11111 179 ] 180 # The canonical NOP has CRm == op2 == 0, but all of the space 181 # that isn't specifically allocated to an instruction must NOP 182 NOP 1101 0101 0000 0011 0010 ---- --- 11111 183} 184 185# Barriers 186 187CLREX 1101 0101 0000 0011 0011 ---- 010 11111 188DSB_DMB 1101 0101 0000 0011 0011 domain:2 types:2 10- 11111 189ISB 1101 0101 0000 0011 0011 ---- 110 11111 190SB 1101 0101 0000 0011 0011 0000 111 11111 191 192# PSTATE 193 194CFINV 1101 0101 0000 0 000 0100 0000 000 11111 195XAFLAG 1101 0101 0000 0 000 0100 0000 001 11111 196AXFLAG 1101 0101 0000 0 000 0100 0000 010 11111 197 198# These are architecturally all "MSR (immediate)"; we decode the destination 199# register too because there is no commonality in our implementation. 200@msr_i .... .... .... . ... .... imm:4 ... ..... 201MSR_i_UAO 1101 0101 0000 0 000 0100 .... 011 11111 @msr_i 202MSR_i_PAN 1101 0101 0000 0 000 0100 .... 100 11111 @msr_i 203MSR_i_SPSEL 1101 0101 0000 0 000 0100 .... 101 11111 @msr_i 204MSR_i_SBSS 1101 0101 0000 0 011 0100 .... 001 11111 @msr_i 205MSR_i_DIT 1101 0101 0000 0 011 0100 .... 010 11111 @msr_i 206MSR_i_TCO 1101 0101 0000 0 011 0100 .... 100 11111 @msr_i 207MSR_i_DAIFSET 1101 0101 0000 0 011 0100 .... 110 11111 @msr_i 208MSR_i_DAIFCLEAR 1101 0101 0000 0 011 0100 .... 111 11111 @msr_i 209MSR_i_SVCR 1101 0101 0000 0 011 0100 0 mask:2 imm:1 011 11111 210 211# MRS, MSR (register), SYS, SYSL. These are all essentially the 212# same instruction as far as QEMU is concerned. 213# NB: op0 is bits [20:19], but op0=0b00 is other insns, so we have 214# to hand-decode it. 215SYS 1101 0101 00 l:1 01 op1:3 crn:4 crm:4 op2:3 rt:5 op0=1 216SYS 1101 0101 00 l:1 10 op1:3 crn:4 crm:4 op2:3 rt:5 op0=2 217SYS 1101 0101 00 l:1 11 op1:3 crn:4 crm:4 op2:3 rt:5 op0=3 218 219# Exception generation 220 221@i16 .... .... ... imm:16 ... .. &i 222SVC 1101 0100 000 ................ 000 01 @i16 223HVC 1101 0100 000 ................ 000 10 @i16 224SMC 1101 0100 000 ................ 000 11 @i16 225BRK 1101 0100 001 ................ 000 00 @i16 226HLT 1101 0100 010 ................ 000 00 @i16 227# These insns always UNDEF unless in halting debug state, which 228# we don't implement. So we don't need to decode them. The patterns 229# are listed here as documentation. 230# DCPS1 1101 0100 101 ................ 000 01 @i16 231# DCPS2 1101 0100 101 ................ 000 10 @i16 232# DCPS3 1101 0100 101 ................ 000 11 @i16 233 234# Loads and stores 235 236&stxr rn rt rt2 rs sz lasr 237&stlr rn rt sz lasr 238@stxr sz:2 ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr 239@stlr sz:2 ...... ... ..... lasr:1 ..... rn:5 rt:5 &stlr 240%imm1_30_p2 30:1 !function=plus_2 241@stxp .. ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr sz=%imm1_30_p2 242STXR .. 001000 000 ..... . ..... ..... ..... @stxr # inc STLXR 243LDXR .. 001000 010 ..... . ..... ..... ..... @stxr # inc LDAXR 244STLR .. 001000 100 11111 . 11111 ..... ..... @stlr # inc STLLR 245LDAR .. 001000 110 11111 . 11111 ..... ..... @stlr # inc LDLAR 246 247STXP 1 . 001000 001 ..... . ..... ..... ..... @stxp # inc STLXP 248LDXP 1 . 001000 011 ..... . ..... ..... ..... @stxp # inc LDAXP 249 250# CASP, CASPA, CASPAL, CASPL (we don't decode the bits that determine 251# acquire/release semantics because QEMU's cmpxchg always has those) 252CASP 0 . 001000 0 - 1 rs:5 - 11111 rn:5 rt:5 sz=%imm1_30_p2 253# CAS, CASA, CASAL, CASL 254CAS sz:2 001000 1 - 1 rs:5 - 11111 rn:5 rt:5 255 256&ldlit rt imm sz sign 257@ldlit .. ... . .. ................... rt:5 &ldlit imm=%imm19 258 259LD_lit 00 011 0 00 ................... ..... @ldlit sz=2 sign=0 260LD_lit 01 011 0 00 ................... ..... @ldlit sz=3 sign=0 261LD_lit 10 011 0 00 ................... ..... @ldlit sz=2 sign=1 262LD_lit_v 00 011 1 00 ................... ..... @ldlit sz=2 sign=0 263LD_lit_v 01 011 1 00 ................... ..... @ldlit sz=3 sign=0 264LD_lit_v 10 011 1 00 ................... ..... @ldlit sz=4 sign=0 265 266# PRFM 267NOP 11 011 0 00 ------------------- ----- 268 269&ldstpair rt2 rt rn imm sz sign w p 270@ldstpair .. ... . ... . imm:s7 rt2:5 rn:5 rt:5 &ldstpair 271 272# STNP, LDNP: Signed offset, non-temporal hint. We don't emulate caches 273# so we ignore hints about data access patterns, and handle these like 274# plain signed offset. 275STP 00 101 0 000 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 276LDP 00 101 0 000 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 277STP 10 101 0 000 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 278LDP 10 101 0 000 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 279STP_v 00 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 280LDP_v 00 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 281STP_v 01 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 282LDP_v 01 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 283STP_v 10 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 284LDP_v 10 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 285 286# STP and LDP: post-indexed 287STP 00 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 288LDP 00 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 289LDP 01 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=1 w=1 290STP 10 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 291LDP 10 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 292STP_v 00 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 293LDP_v 00 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 294STP_v 01 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 295LDP_v 01 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 296STP_v 10 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=1 w=1 297LDP_v 10 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=1 w=1 298 299# STP and LDP: offset 300STP 00 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 301LDP 00 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 302LDP 01 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=0 w=0 303STP 10 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 304LDP 10 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 305STP_v 00 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 306LDP_v 00 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 307STP_v 01 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 308LDP_v 01 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 309STP_v 10 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 310LDP_v 10 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 311 312# STP and LDP: pre-indexed 313STP 00 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 314LDP 00 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 315LDP 01 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=0 w=1 316STP 10 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 317LDP 10 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 318STP_v 00 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 319LDP_v 00 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 320STP_v 01 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 321LDP_v 01 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 322STP_v 10 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=1 323LDP_v 10 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=1 324 325# STGP: store tag and pair 326STGP 01 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 327STGP 01 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 328STGP 01 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 329 330# Load/store register (unscaled immediate) 331&ldst_imm rt rn imm sz sign w p unpriv ext 332@ldst_imm .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=0 333@ldst_imm_pre .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=1 334@ldst_imm_post .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=1 w=1 335@ldst_imm_user .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=1 p=0 w=0 336 337STR_i sz:2 111 0 00 00 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 338LDR_i 00 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=0 339LDR_i 01 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=1 340LDR_i 10 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=2 341LDR_i 11 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=3 342LDR_i 00 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=0 343LDR_i 01 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=1 344LDR_i 10 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=2 345LDR_i 00 111 0 00 11 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=1 sz=0 346LDR_i 01 111 0 00 11 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=1 sz=1 347 348STR_i sz:2 111 0 00 00 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 349LDR_i 00 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=0 350LDR_i 01 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=1 351LDR_i 10 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=2 352LDR_i 11 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=3 353LDR_i 00 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=0 354LDR_i 01 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=1 355LDR_i 10 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=2 356LDR_i 00 111 0 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=1 sz=0 357LDR_i 01 111 0 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=1 sz=1 358 359STR_i sz:2 111 0 00 00 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=0 360LDR_i 00 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=0 361LDR_i 01 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=1 362LDR_i 10 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=2 363LDR_i 11 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=0 sz=3 364LDR_i 00 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=0 365LDR_i 01 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=1 366LDR_i 10 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=2 367LDR_i 00 111 0 00 11 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=1 sz=0 368LDR_i 01 111 0 00 11 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=1 sz=1 369 370STR_i sz:2 111 0 00 00 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 371LDR_i 00 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=0 372LDR_i 01 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=1 373LDR_i 10 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=2 374LDR_i 11 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=3 375LDR_i 00 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=0 376LDR_i 01 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=1 377LDR_i 10 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=2 378LDR_i 00 111 0 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=1 sz=0 379LDR_i 01 111 0 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=1 sz=1 380 381# PRFM : prefetch memory: a no-op for QEMU 382NOP 11 111 0 00 10 0 --------- 00 ----- ----- 383 384STR_v_i sz:2 111 1 00 00 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 385STR_v_i 00 111 1 00 10 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=4 386LDR_v_i sz:2 111 1 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 387LDR_v_i 00 111 1 00 11 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=4 388 389STR_v_i sz:2 111 1 00 00 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 390STR_v_i 00 111 1 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=4 391LDR_v_i sz:2 111 1 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 392LDR_v_i 00 111 1 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=4 393 394STR_v_i sz:2 111 1 00 00 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 395STR_v_i 00 111 1 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=4 396LDR_v_i sz:2 111 1 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 397LDR_v_i 00 111 1 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=4 398 399# Load/store with an unsigned 12 bit immediate, which is scaled by the 400# element size. The function gets the sz:imm and returns the scaled immediate. 401%uimm_scaled 10:12 sz:3 !function=uimm_scaled 402 403@ldst_uimm .. ... . .. .. ............ rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=0 imm=%uimm_scaled 404 405STR_i sz:2 111 0 01 00 ............ ..... ..... @ldst_uimm sign=0 ext=0 406LDR_i 00 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=0 407LDR_i 01 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=1 408LDR_i 10 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=2 409LDR_i 11 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=3 410LDR_i 00 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=0 411LDR_i 01 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=1 412LDR_i 10 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=2 413LDR_i 00 111 0 01 11 ............ ..... ..... @ldst_uimm sign=1 ext=1 sz=0 414LDR_i 01 111 0 01 11 ............ ..... ..... @ldst_uimm sign=1 ext=1 sz=1 415 416# PRFM 417NOP 11 111 0 01 10 ------------ ----- ----- 418 419STR_v_i sz:2 111 1 01 00 ............ ..... ..... @ldst_uimm sign=0 ext=0 420STR_v_i 00 111 1 01 10 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=4 421LDR_v_i sz:2 111 1 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=0 422LDR_v_i 00 111 1 01 11 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=4 423 424# Load/store with register offset 425&ldst rm rn rt sign ext sz opt s 426@ldst .. ... . .. .. . rm:5 opt:3 s:1 .. rn:5 rt:5 &ldst 427STR sz:2 111 0 00 00 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 428LDR 00 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=0 429LDR 01 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=1 430LDR 10 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=2 431LDR 11 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=3 432LDR 00 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=0 433LDR 01 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=1 434LDR 10 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=2 435LDR 00 111 0 00 11 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=1 sz=0 436LDR 01 111 0 00 11 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=1 sz=1 437 438# PRFM 439NOP 11 111 0 00 10 1 ----- -1- - 10 ----- ----- 440 441STR_v sz:2 111 1 00 00 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 442STR_v 00 111 1 00 10 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=4 443LDR_v sz:2 111 1 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 444LDR_v 00 111 1 00 11 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=4 445 446# Atomic memory operations 447&atomic rs rn rt a r sz 448@atomic sz:2 ... . .. a:1 r:1 . rs:5 . ... .. rn:5 rt:5 &atomic 449LDADD .. 111 0 00 . . 1 ..... 0000 00 ..... ..... @atomic 450LDCLR .. 111 0 00 . . 1 ..... 0001 00 ..... ..... @atomic 451LDEOR .. 111 0 00 . . 1 ..... 0010 00 ..... ..... @atomic 452LDSET .. 111 0 00 . . 1 ..... 0011 00 ..... ..... @atomic 453LDSMAX .. 111 0 00 . . 1 ..... 0100 00 ..... ..... @atomic 454LDSMIN .. 111 0 00 . . 1 ..... 0101 00 ..... ..... @atomic 455LDUMAX .. 111 0 00 . . 1 ..... 0110 00 ..... ..... @atomic 456LDUMIN .. 111 0 00 . . 1 ..... 0111 00 ..... ..... @atomic 457SWP .. 111 0 00 . . 1 ..... 1000 00 ..... ..... @atomic 458 459LDAPR sz:2 111 0 00 1 0 1 11111 1100 00 rn:5 rt:5 460 461# Load/store register (pointer authentication) 462 463# LDRA immediate is 10 bits signed and scaled, but the bits aren't all contiguous 464%ldra_imm 22:s1 12:9 !function=times_2 465 466LDRA 11 111 0 00 m:1 . 1 ......... w:1 1 rn:5 rt:5 imm=%ldra_imm 467 468&ldapr_stlr_i rn rt imm sz sign ext 469@ldapr_stlr_i .. ...... .. . imm:9 .. rn:5 rt:5 &ldapr_stlr_i 470STLR_i sz:2 011001 00 0 ......... 00 ..... ..... @ldapr_stlr_i sign=0 ext=0 471LDAPR_i sz:2 011001 01 0 ......... 00 ..... ..... @ldapr_stlr_i sign=0 ext=0 472LDAPR_i 00 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=0 473LDAPR_i 01 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=1 474LDAPR_i 10 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=2 475LDAPR_i 00 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=1 sz=0 476LDAPR_i 01 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=1 sz=1 477 478# Load/store multiple structures 479# The 4-bit opcode in [15:12] encodes repeat count and structure elements 480&ldst_mult rm rn rt sz q p rpt selem 481@ldst_mult . q:1 ...... p:1 . . rm:5 .... sz:2 rn:5 rt:5 &ldst_mult 482ST_mult 0 . 001100 . 0 0 ..... 0000 .. ..... ..... @ldst_mult rpt=1 selem=4 483ST_mult 0 . 001100 . 0 0 ..... 0010 .. ..... ..... @ldst_mult rpt=4 selem=1 484ST_mult 0 . 001100 . 0 0 ..... 0100 .. ..... ..... @ldst_mult rpt=1 selem=3 485ST_mult 0 . 001100 . 0 0 ..... 0110 .. ..... ..... @ldst_mult rpt=3 selem=1 486ST_mult 0 . 001100 . 0 0 ..... 0111 .. ..... ..... @ldst_mult rpt=1 selem=1 487ST_mult 0 . 001100 . 0 0 ..... 1000 .. ..... ..... @ldst_mult rpt=1 selem=2 488ST_mult 0 . 001100 . 0 0 ..... 1010 .. ..... ..... @ldst_mult rpt=2 selem=1 489 490LD_mult 0 . 001100 . 1 0 ..... 0000 .. ..... ..... @ldst_mult rpt=1 selem=4 491LD_mult 0 . 001100 . 1 0 ..... 0010 .. ..... ..... @ldst_mult rpt=4 selem=1 492LD_mult 0 . 001100 . 1 0 ..... 0100 .. ..... ..... @ldst_mult rpt=1 selem=3 493LD_mult 0 . 001100 . 1 0 ..... 0110 .. ..... ..... @ldst_mult rpt=3 selem=1 494LD_mult 0 . 001100 . 1 0 ..... 0111 .. ..... ..... @ldst_mult rpt=1 selem=1 495LD_mult 0 . 001100 . 1 0 ..... 1000 .. ..... ..... @ldst_mult rpt=1 selem=2 496LD_mult 0 . 001100 . 1 0 ..... 1010 .. ..... ..... @ldst_mult rpt=2 selem=1 497 498# Load/store single structure 499&ldst_single rm rn rt p selem index scale 500 501%ldst_single_selem 13:1 21:1 !function=plus_1 502 503%ldst_single_index_b 30:1 10:3 504%ldst_single_index_h 30:1 11:2 505%ldst_single_index_s 30:1 12:1 506 507@ldst_single_b .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \ 508 &ldst_single scale=0 selem=%ldst_single_selem \ 509 index=%ldst_single_index_b 510@ldst_single_h .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \ 511 &ldst_single scale=1 selem=%ldst_single_selem \ 512 index=%ldst_single_index_h 513@ldst_single_s .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \ 514 &ldst_single scale=2 selem=%ldst_single_selem \ 515 index=%ldst_single_index_s 516@ldst_single_d . index:1 ...... p:1 .. rm:5 ...... rn:5 rt:5 \ 517 &ldst_single scale=3 selem=%ldst_single_selem 518 519ST_single 0 . 001101 . 0 . ..... 00 . ... ..... ..... @ldst_single_b 520ST_single 0 . 001101 . 0 . ..... 01 . ..0 ..... ..... @ldst_single_h 521ST_single 0 . 001101 . 0 . ..... 10 . .00 ..... ..... @ldst_single_s 522ST_single 0 . 001101 . 0 . ..... 10 . 001 ..... ..... @ldst_single_d 523 524LD_single 0 . 001101 . 1 . ..... 00 . ... ..... ..... @ldst_single_b 525LD_single 0 . 001101 . 1 . ..... 01 . ..0 ..... ..... @ldst_single_h 526LD_single 0 . 001101 . 1 . ..... 10 . .00 ..... ..... @ldst_single_s 527LD_single 0 . 001101 . 1 . ..... 10 . 001 ..... ..... @ldst_single_d 528 529# Replicating load case 530LD_single_repl 0 q:1 001101 p:1 1 . rm:5 11 . 0 scale:2 rn:5 rt:5 selem=%ldst_single_selem 531 532%tag_offset 12:s9 !function=scale_by_log2_tag_granule 533&ldst_tag rn rt imm p w 534@ldst_tag ........ .. . ......... .. rn:5 rt:5 &ldst_tag imm=%tag_offset 535@ldst_tag_mult ........ .. . 000000000 .. rn:5 rt:5 &ldst_tag imm=0 536 537STZGM 11011001 00 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0 538STG 11011001 00 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 539STG 11011001 00 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 540STG 11011001 00 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 541 542LDG 11011001 01 1 ......... 00 ..... ..... @ldst_tag p=0 w=0 543STZG 11011001 01 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 544STZG 11011001 01 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 545STZG 11011001 01 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 546 547STGM 11011001 10 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0 548ST2G 11011001 10 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 549ST2G 11011001 10 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 550ST2G 11011001 10 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 551 552LDGM 11011001 11 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0 553STZ2G 11011001 11 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 554STZ2G 11011001 11 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 555STZ2G 11011001 11 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 556