1# AArch64 A64 allowed instruction decoding 2# 3# Copyright (c) 2023 Linaro, Ltd 4# 5# This library is free software; you can redistribute it and/or 6# modify it under the terms of the GNU Lesser General Public 7# License as published by the Free Software Foundation; either 8# version 2.1 of the License, or (at your option) any later version. 9# 10# This library is distributed in the hope that it will be useful, 11# but WITHOUT ANY WARRANTY; without even the implied warranty of 12# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13# Lesser General Public License for more details. 14# 15# You should have received a copy of the GNU Lesser General Public 16# License along with this library; if not, see <http://www.gnu.org/licenses/>. 17 18# 19# This file is processed by scripts/decodetree.py 20# 21 22&r rn 23&ri rd imm 24&rri_sf rd rn imm sf 25&i imm 26 27 28### Data Processing - Immediate 29 30# PC-rel addressing 31 32%imm_pcrel 5:s19 29:2 33@pcrel . .. ..... ................... rd:5 &ri imm=%imm_pcrel 34 35ADR 0 .. 10000 ................... ..... @pcrel 36ADRP 1 .. 10000 ................... ..... @pcrel 37 38# Add/subtract (immediate) 39 40%imm12_sh12 10:12 !function=shl_12 41@addsub_imm sf:1 .. ...... . imm:12 rn:5 rd:5 42@addsub_imm12 sf:1 .. ...... . ............ rn:5 rd:5 imm=%imm12_sh12 43 44ADD_i . 00 100010 0 ............ ..... ..... @addsub_imm 45ADD_i . 00 100010 1 ............ ..... ..... @addsub_imm12 46ADDS_i . 01 100010 0 ............ ..... ..... @addsub_imm 47ADDS_i . 01 100010 1 ............ ..... ..... @addsub_imm12 48 49SUB_i . 10 100010 0 ............ ..... ..... @addsub_imm 50SUB_i . 10 100010 1 ............ ..... ..... @addsub_imm12 51SUBS_i . 11 100010 0 ............ ..... ..... @addsub_imm 52SUBS_i . 11 100010 1 ............ ..... ..... @addsub_imm12 53 54# Add/subtract (immediate with tags) 55 56&rri_tag rd rn uimm6 uimm4 57@addsub_imm_tag . .. ...... . uimm6:6 .. uimm4:4 rn:5 rd:5 &rri_tag 58 59ADDG_i 1 00 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag 60SUBG_i 1 10 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag 61 62# Logical (immediate) 63 64&rri_log rd rn sf dbm 65@logic_imm_64 1 .. ...... dbm:13 rn:5 rd:5 &rri_log sf=1 66@logic_imm_32 0 .. ...... 0 dbm:12 rn:5 rd:5 &rri_log sf=0 67 68AND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_64 69AND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_32 70ORR_i . 01 100100 . ...... ...... ..... ..... @logic_imm_64 71ORR_i . 01 100100 . ...... ...... ..... ..... @logic_imm_32 72EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_64 73EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_32 74ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_64 75ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_32 76 77# Move wide (immediate) 78 79&movw rd sf imm hw 80@movw_64 1 .. ...... hw:2 imm:16 rd:5 &movw sf=1 81@movw_32 0 .. ...... 0 hw:1 imm:16 rd:5 &movw sf=0 82 83MOVN . 00 100101 .. ................ ..... @movw_64 84MOVN . 00 100101 .. ................ ..... @movw_32 85MOVZ . 10 100101 .. ................ ..... @movw_64 86MOVZ . 10 100101 .. ................ ..... @movw_32 87MOVK . 11 100101 .. ................ ..... @movw_64 88MOVK . 11 100101 .. ................ ..... @movw_32 89 90# Bitfield 91 92&bitfield rd rn sf immr imms 93@bitfield_64 1 .. ...... 1 immr:6 imms:6 rn:5 rd:5 &bitfield sf=1 94@bitfield_32 0 .. ...... 0 0 immr:5 0 imms:5 rn:5 rd:5 &bitfield sf=0 95 96SBFM . 00 100110 . ...... ...... ..... ..... @bitfield_64 97SBFM . 00 100110 . ...... ...... ..... ..... @bitfield_32 98BFM . 01 100110 . ...... ...... ..... ..... @bitfield_64 99BFM . 01 100110 . ...... ...... ..... ..... @bitfield_32 100UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_64 101UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_32 102 103# Extract 104 105&extract rd rn rm imm sf 106 107EXTR 1 00 100111 1 0 rm:5 imm:6 rn:5 rd:5 &extract sf=1 108EXTR 0 00 100111 0 0 rm:5 0 imm:5 rn:5 rd:5 &extract sf=0 109 110# Branches 111 112%imm26 0:s26 !function=times_4 113@branch . ..... .......................... &i imm=%imm26 114 115B 0 00101 .......................... @branch 116BL 1 00101 .......................... @branch 117 118%imm19 5:s19 !function=times_4 119&cbz rt imm sf nz 120 121CBZ sf:1 011010 nz:1 ................... rt:5 &cbz imm=%imm19 122 123%imm14 5:s14 !function=times_4 124%imm31_19 31:1 19:5 125&tbz rt imm nz bitpos 126 127TBZ . 011011 nz:1 ..... .............. rt:5 &tbz imm=%imm14 bitpos=%imm31_19 128 129B_cond 0101010 0 ................... 0 cond:4 imm=%imm19 130 131BR 1101011 0000 11111 000000 rn:5 00000 &r 132BLR 1101011 0001 11111 000000 rn:5 00000 &r 133RET 1101011 0010 11111 000000 rn:5 00000 &r 134 135&braz rn m 136BRAZ 1101011 0000 11111 00001 m:1 rn:5 11111 &braz # BRAAZ, BRABZ 137BLRAZ 1101011 0001 11111 00001 m:1 rn:5 11111 &braz # BLRAAZ, BLRABZ 138 139&reta m 140RETA 1101011 0010 11111 00001 m:1 11111 11111 &reta # RETAA, RETAB 141 142&bra rn rm m 143BRA 1101011 1000 11111 00001 m:1 rn:5 rm:5 &bra # BRAA, BRAB 144BLRA 1101011 1001 11111 00001 m:1 rn:5 rm:5 &bra # BLRAA, BLRAB 145 146ERET 1101011 0100 11111 000000 11111 00000 147ERETA 1101011 0100 11111 00001 m:1 11111 11111 &reta # ERETAA, ERETAB 148 149# We don't need to decode DRPS because it always UNDEFs except when 150# the processor is in halting debug state (which we don't implement). 151# The pattern is listed here as documentation. 152# DRPS 1101011 0101 11111 000000 11111 00000 153