1# AArch64 A64 allowed instruction decoding 2# 3# Copyright (c) 2023 Linaro, Ltd 4# 5# This library is free software; you can redistribute it and/or 6# modify it under the terms of the GNU Lesser General Public 7# License as published by the Free Software Foundation; either 8# version 2.1 of the License, or (at your option) any later version. 9# 10# This library is distributed in the hope that it will be useful, 11# but WITHOUT ANY WARRANTY; without even the implied warranty of 12# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13# Lesser General Public License for more details. 14# 15# You should have received a copy of the GNU Lesser General Public 16# License along with this library; if not, see <http://www.gnu.org/licenses/>. 17 18# 19# This file is processed by scripts/decodetree.py 20# 21 22%rd 0:5 23%esz_sd 22:1 !function=plus_2 24%esz_hsd 22:2 !function=xor_2 25%hl 11:1 21:1 26%hlm 11:1 20:2 27 28&r rn 29&ri rd imm 30&rri_sf rd rn imm sf 31&i imm 32&rr_e rd rn esz 33&rrr_e rd rn rm esz 34&rrx_e rd rn rm idx esz 35&qrr_e q rd rn esz 36&qrrr_e q rd rn rm esz 37&qrrx_e q rd rn rm idx esz 38&qrrrr_e q rd rn rm ra esz 39 40@rr_h ........ ... ..... ...... rn:5 rd:5 &rr_e esz=1 41@rr_d ........ ... ..... ...... rn:5 rd:5 &rr_e esz=3 42@rr_sd ........ ... ..... ...... rn:5 rd:5 &rr_e esz=%esz_sd 43 44@rrr_h ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=1 45@rrr_sd ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=%esz_sd 46@rrr_hsd ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=%esz_hsd 47 48@rrx_h ........ .. .. rm:4 .... . . rn:5 rd:5 &rrx_e esz=1 idx=%hlm 49@rrx_s ........ .. . rm:5 .... . . rn:5 rd:5 &rrx_e esz=2 idx=%hl 50@rrx_d ........ .. . rm:5 .... idx:1 . rn:5 rd:5 &rrx_e esz=3 51 52@rr_q1e0 ........ ........ ...... rn:5 rd:5 &qrr_e q=1 esz=0 53@r2r_q1e0 ........ ........ ...... rm:5 rd:5 &qrrr_e rn=%rd q=1 esz=0 54@rrr_q1e0 ........ ... rm:5 ...... rn:5 rd:5 &qrrr_e q=1 esz=0 55@rrr_q1e3 ........ ... rm:5 ...... rn:5 rd:5 &qrrr_e q=1 esz=3 56@rrrr_q1e3 ........ ... rm:5 . ra:5 rn:5 rd:5 &qrrrr_e q=1 esz=3 57 58@qrrr_h . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=1 59@qrrr_sd . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=%esz_sd 60@qrrr_e . q:1 ...... esz:2 . rm:5 ...... rn:5 rd:5 &qrrr_e 61 62@qrrx_h . q:1 .. .... .. .. rm:4 .... . . rn:5 rd:5 \ 63 &qrrx_e esz=1 idx=%hlm 64@qrrx_s . q:1 .. .... .. . rm:5 .... . . rn:5 rd:5 \ 65 &qrrx_e esz=2 idx=%hl 66@qrrx_d . q:1 .. .... .. . rm:5 .... idx:1 . rn:5 rd:5 \ 67 &qrrx_e esz=3 68 69### Data Processing - Immediate 70 71# PC-rel addressing 72 73%imm_pcrel 5:s19 29:2 74@pcrel . .. ..... ................... rd:5 &ri imm=%imm_pcrel 75 76ADR 0 .. 10000 ................... ..... @pcrel 77ADRP 1 .. 10000 ................... ..... @pcrel 78 79# Add/subtract (immediate) 80 81%imm12_sh12 10:12 !function=shl_12 82@addsub_imm sf:1 .. ...... . imm:12 rn:5 rd:5 83@addsub_imm12 sf:1 .. ...... . ............ rn:5 rd:5 imm=%imm12_sh12 84 85ADD_i . 00 100010 0 ............ ..... ..... @addsub_imm 86ADD_i . 00 100010 1 ............ ..... ..... @addsub_imm12 87ADDS_i . 01 100010 0 ............ ..... ..... @addsub_imm 88ADDS_i . 01 100010 1 ............ ..... ..... @addsub_imm12 89 90SUB_i . 10 100010 0 ............ ..... ..... @addsub_imm 91SUB_i . 10 100010 1 ............ ..... ..... @addsub_imm12 92SUBS_i . 11 100010 0 ............ ..... ..... @addsub_imm 93SUBS_i . 11 100010 1 ............ ..... ..... @addsub_imm12 94 95# Add/subtract (immediate with tags) 96 97&rri_tag rd rn uimm6 uimm4 98@addsub_imm_tag . .. ...... . uimm6:6 .. uimm4:4 rn:5 rd:5 &rri_tag 99 100ADDG_i 1 00 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag 101SUBG_i 1 10 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag 102 103# Logical (immediate) 104 105&rri_log rd rn sf dbm 106@logic_imm_64 1 .. ...... dbm:13 rn:5 rd:5 &rri_log sf=1 107@logic_imm_32 0 .. ...... 0 dbm:12 rn:5 rd:5 &rri_log sf=0 108 109AND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_64 110AND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_32 111ORR_i . 01 100100 . ...... ...... ..... ..... @logic_imm_64 112ORR_i . 01 100100 . ...... ...... ..... ..... @logic_imm_32 113EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_64 114EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_32 115ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_64 116ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_32 117 118# Move wide (immediate) 119 120&movw rd sf imm hw 121@movw_64 1 .. ...... hw:2 imm:16 rd:5 &movw sf=1 122@movw_32 0 .. ...... 0 hw:1 imm:16 rd:5 &movw sf=0 123 124MOVN . 00 100101 .. ................ ..... @movw_64 125MOVN . 00 100101 .. ................ ..... @movw_32 126MOVZ . 10 100101 .. ................ ..... @movw_64 127MOVZ . 10 100101 .. ................ ..... @movw_32 128MOVK . 11 100101 .. ................ ..... @movw_64 129MOVK . 11 100101 .. ................ ..... @movw_32 130 131# Bitfield 132 133&bitfield rd rn sf immr imms 134@bitfield_64 1 .. ...... 1 immr:6 imms:6 rn:5 rd:5 &bitfield sf=1 135@bitfield_32 0 .. ...... 0 0 immr:5 0 imms:5 rn:5 rd:5 &bitfield sf=0 136 137SBFM . 00 100110 . ...... ...... ..... ..... @bitfield_64 138SBFM . 00 100110 . ...... ...... ..... ..... @bitfield_32 139BFM . 01 100110 . ...... ...... ..... ..... @bitfield_64 140BFM . 01 100110 . ...... ...... ..... ..... @bitfield_32 141UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_64 142UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_32 143 144# Extract 145 146&extract rd rn rm imm sf 147 148EXTR 1 00 100111 1 0 rm:5 imm:6 rn:5 rd:5 &extract sf=1 149EXTR 0 00 100111 0 0 rm:5 0 imm:5 rn:5 rd:5 &extract sf=0 150 151# Branches 152 153%imm26 0:s26 !function=times_4 154@branch . ..... .......................... &i imm=%imm26 155 156B 0 00101 .......................... @branch 157BL 1 00101 .......................... @branch 158 159%imm19 5:s19 !function=times_4 160&cbz rt imm sf nz 161 162CBZ sf:1 011010 nz:1 ................... rt:5 &cbz imm=%imm19 163 164%imm14 5:s14 !function=times_4 165%imm31_19 31:1 19:5 166&tbz rt imm nz bitpos 167 168TBZ . 011011 nz:1 ..... .............. rt:5 &tbz imm=%imm14 bitpos=%imm31_19 169 170# B.cond and BC.cond 171B_cond 0101010 0 ................... c:1 cond:4 imm=%imm19 172 173BR 1101011 0000 11111 000000 rn:5 00000 &r 174BLR 1101011 0001 11111 000000 rn:5 00000 &r 175RET 1101011 0010 11111 000000 rn:5 00000 &r 176 177&braz rn m 178BRAZ 1101011 0000 11111 00001 m:1 rn:5 11111 &braz # BRAAZ, BRABZ 179BLRAZ 1101011 0001 11111 00001 m:1 rn:5 11111 &braz # BLRAAZ, BLRABZ 180 181&reta m 182RETA 1101011 0010 11111 00001 m:1 11111 11111 &reta # RETAA, RETAB 183 184&bra rn rm m 185BRA 1101011 1000 11111 00001 m:1 rn:5 rm:5 &bra # BRAA, BRAB 186BLRA 1101011 1001 11111 00001 m:1 rn:5 rm:5 &bra # BLRAA, BLRAB 187 188ERET 1101011 0100 11111 000000 11111 00000 189ERETA 1101011 0100 11111 00001 m:1 11111 11111 &reta # ERETAA, ERETAB 190 191# We don't need to decode DRPS because it always UNDEFs except when 192# the processor is in halting debug state (which we don't implement). 193# The pattern is listed here as documentation. 194# DRPS 1101011 0101 11111 000000 11111 00000 195 196# Hint instruction group 197{ 198 [ 199 YIELD 1101 0101 0000 0011 0010 0000 001 11111 200 WFE 1101 0101 0000 0011 0010 0000 010 11111 201 WFI 1101 0101 0000 0011 0010 0000 011 11111 202 # We implement WFE to never block, so our SEV/SEVL are NOPs 203 # SEV 1101 0101 0000 0011 0010 0000 100 11111 204 # SEVL 1101 0101 0000 0011 0010 0000 101 11111 205 # Our DGL is a NOP because we don't merge memory accesses anyway. 206 # DGL 1101 0101 0000 0011 0010 0000 110 11111 207 XPACLRI 1101 0101 0000 0011 0010 0000 111 11111 208 PACIA1716 1101 0101 0000 0011 0010 0001 000 11111 209 PACIB1716 1101 0101 0000 0011 0010 0001 010 11111 210 AUTIA1716 1101 0101 0000 0011 0010 0001 100 11111 211 AUTIB1716 1101 0101 0000 0011 0010 0001 110 11111 212 ESB 1101 0101 0000 0011 0010 0010 000 11111 213 PACIAZ 1101 0101 0000 0011 0010 0011 000 11111 214 PACIASP 1101 0101 0000 0011 0010 0011 001 11111 215 PACIBZ 1101 0101 0000 0011 0010 0011 010 11111 216 PACIBSP 1101 0101 0000 0011 0010 0011 011 11111 217 AUTIAZ 1101 0101 0000 0011 0010 0011 100 11111 218 AUTIASP 1101 0101 0000 0011 0010 0011 101 11111 219 AUTIBZ 1101 0101 0000 0011 0010 0011 110 11111 220 AUTIBSP 1101 0101 0000 0011 0010 0011 111 11111 221 ] 222 # The canonical NOP has CRm == op2 == 0, but all of the space 223 # that isn't specifically allocated to an instruction must NOP 224 NOP 1101 0101 0000 0011 0010 ---- --- 11111 225} 226 227# Barriers 228 229CLREX 1101 0101 0000 0011 0011 ---- 010 11111 230DSB_DMB 1101 0101 0000 0011 0011 domain:2 types:2 10- 11111 231ISB 1101 0101 0000 0011 0011 ---- 110 11111 232SB 1101 0101 0000 0011 0011 0000 111 11111 233 234# PSTATE 235 236CFINV 1101 0101 0000 0 000 0100 0000 000 11111 237XAFLAG 1101 0101 0000 0 000 0100 0000 001 11111 238AXFLAG 1101 0101 0000 0 000 0100 0000 010 11111 239 240# These are architecturally all "MSR (immediate)"; we decode the destination 241# register too because there is no commonality in our implementation. 242@msr_i .... .... .... . ... .... imm:4 ... ..... 243MSR_i_UAO 1101 0101 0000 0 000 0100 .... 011 11111 @msr_i 244MSR_i_PAN 1101 0101 0000 0 000 0100 .... 100 11111 @msr_i 245MSR_i_SPSEL 1101 0101 0000 0 000 0100 .... 101 11111 @msr_i 246MSR_i_SBSS 1101 0101 0000 0 011 0100 .... 001 11111 @msr_i 247MSR_i_DIT 1101 0101 0000 0 011 0100 .... 010 11111 @msr_i 248MSR_i_TCO 1101 0101 0000 0 011 0100 .... 100 11111 @msr_i 249MSR_i_DAIFSET 1101 0101 0000 0 011 0100 .... 110 11111 @msr_i 250MSR_i_DAIFCLEAR 1101 0101 0000 0 011 0100 .... 111 11111 @msr_i 251MSR_i_ALLINT 1101 0101 0000 0 001 0100 000 imm:1 000 11111 252MSR_i_SVCR 1101 0101 0000 0 011 0100 0 mask:2 imm:1 011 11111 253 254# MRS, MSR (register), SYS, SYSL. These are all essentially the 255# same instruction as far as QEMU is concerned. 256# NB: op0 is bits [20:19], but op0=0b00 is other insns, so we have 257# to hand-decode it. 258SYS 1101 0101 00 l:1 01 op1:3 crn:4 crm:4 op2:3 rt:5 op0=1 259SYS 1101 0101 00 l:1 10 op1:3 crn:4 crm:4 op2:3 rt:5 op0=2 260SYS 1101 0101 00 l:1 11 op1:3 crn:4 crm:4 op2:3 rt:5 op0=3 261 262# Exception generation 263 264@i16 .... .... ... imm:16 ... .. &i 265SVC 1101 0100 000 ................ 000 01 @i16 266HVC 1101 0100 000 ................ 000 10 @i16 267SMC 1101 0100 000 ................ 000 11 @i16 268BRK 1101 0100 001 ................ 000 00 @i16 269HLT 1101 0100 010 ................ 000 00 @i16 270# These insns always UNDEF unless in halting debug state, which 271# we don't implement. So we don't need to decode them. The patterns 272# are listed here as documentation. 273# DCPS1 1101 0100 101 ................ 000 01 @i16 274# DCPS2 1101 0100 101 ................ 000 10 @i16 275# DCPS3 1101 0100 101 ................ 000 11 @i16 276 277# Loads and stores 278 279&stxr rn rt rt2 rs sz lasr 280&stlr rn rt sz lasr 281@stxr sz:2 ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr 282@stlr sz:2 ...... ... ..... lasr:1 ..... rn:5 rt:5 &stlr 283%imm1_30_p2 30:1 !function=plus_2 284@stxp .. ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr sz=%imm1_30_p2 285STXR .. 001000 000 ..... . ..... ..... ..... @stxr # inc STLXR 286LDXR .. 001000 010 ..... . ..... ..... ..... @stxr # inc LDAXR 287STLR .. 001000 100 11111 . 11111 ..... ..... @stlr # inc STLLR 288LDAR .. 001000 110 11111 . 11111 ..... ..... @stlr # inc LDLAR 289 290STXP 1 . 001000 001 ..... . ..... ..... ..... @stxp # inc STLXP 291LDXP 1 . 001000 011 ..... . ..... ..... ..... @stxp # inc LDAXP 292 293# CASP, CASPA, CASPAL, CASPL (we don't decode the bits that determine 294# acquire/release semantics because QEMU's cmpxchg always has those) 295CASP 0 . 001000 0 - 1 rs:5 - 11111 rn:5 rt:5 sz=%imm1_30_p2 296# CAS, CASA, CASAL, CASL 297CAS sz:2 001000 1 - 1 rs:5 - 11111 rn:5 rt:5 298 299&ldlit rt imm sz sign 300@ldlit .. ... . .. ................... rt:5 &ldlit imm=%imm19 301 302LD_lit 00 011 0 00 ................... ..... @ldlit sz=2 sign=0 303LD_lit 01 011 0 00 ................... ..... @ldlit sz=3 sign=0 304LD_lit 10 011 0 00 ................... ..... @ldlit sz=2 sign=1 305LD_lit_v 00 011 1 00 ................... ..... @ldlit sz=2 sign=0 306LD_lit_v 01 011 1 00 ................... ..... @ldlit sz=3 sign=0 307LD_lit_v 10 011 1 00 ................... ..... @ldlit sz=4 sign=0 308 309# PRFM 310NOP 11 011 0 00 ------------------- ----- 311 312&ldstpair rt2 rt rn imm sz sign w p 313@ldstpair .. ... . ... . imm:s7 rt2:5 rn:5 rt:5 &ldstpair 314 315# STNP, LDNP: Signed offset, non-temporal hint. We don't emulate caches 316# so we ignore hints about data access patterns, and handle these like 317# plain signed offset. 318STP 00 101 0 000 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 319LDP 00 101 0 000 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 320STP 10 101 0 000 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 321LDP 10 101 0 000 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 322STP_v 00 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 323LDP_v 00 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 324STP_v 01 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 325LDP_v 01 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 326STP_v 10 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 327LDP_v 10 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 328 329# STP and LDP: post-indexed 330STP 00 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 331LDP 00 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 332LDP 01 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=1 w=1 333STP 10 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 334LDP 10 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 335STP_v 00 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 336LDP_v 00 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 337STP_v 01 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 338LDP_v 01 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 339STP_v 10 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=1 w=1 340LDP_v 10 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=1 w=1 341 342# STP and LDP: offset 343STP 00 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 344LDP 00 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 345LDP 01 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=0 w=0 346STP 10 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 347LDP 10 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 348STP_v 00 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 349LDP_v 00 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 350STP_v 01 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 351LDP_v 01 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 352STP_v 10 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 353LDP_v 10 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 354 355# STP and LDP: pre-indexed 356STP 00 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 357LDP 00 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 358LDP 01 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=0 w=1 359STP 10 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 360LDP 10 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 361STP_v 00 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 362LDP_v 00 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 363STP_v 01 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 364LDP_v 01 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 365STP_v 10 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=1 366LDP_v 10 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=1 367 368# STGP: store tag and pair 369STGP 01 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 370STGP 01 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 371STGP 01 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 372 373# Load/store register (unscaled immediate) 374&ldst_imm rt rn imm sz sign w p unpriv ext 375@ldst_imm .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=0 376@ldst_imm_pre .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=1 377@ldst_imm_post .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=1 w=1 378@ldst_imm_user .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=1 p=0 w=0 379 380STR_i sz:2 111 0 00 00 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 381LDR_i 00 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=0 382LDR_i 01 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=1 383LDR_i 10 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=2 384LDR_i 11 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=3 385LDR_i 00 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=0 386LDR_i 01 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=1 387LDR_i 10 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=2 388LDR_i 00 111 0 00 11 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=1 sz=0 389LDR_i 01 111 0 00 11 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=1 sz=1 390 391STR_i sz:2 111 0 00 00 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 392LDR_i 00 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=0 393LDR_i 01 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=1 394LDR_i 10 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=2 395LDR_i 11 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=3 396LDR_i 00 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=0 397LDR_i 01 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=1 398LDR_i 10 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=2 399LDR_i 00 111 0 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=1 sz=0 400LDR_i 01 111 0 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=1 sz=1 401 402STR_i sz:2 111 0 00 00 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=0 403LDR_i 00 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=0 404LDR_i 01 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=1 405LDR_i 10 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=2 406LDR_i 11 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=0 sz=3 407LDR_i 00 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=0 408LDR_i 01 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=1 409LDR_i 10 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=2 410LDR_i 00 111 0 00 11 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=1 sz=0 411LDR_i 01 111 0 00 11 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=1 sz=1 412 413STR_i sz:2 111 0 00 00 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 414LDR_i 00 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=0 415LDR_i 01 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=1 416LDR_i 10 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=2 417LDR_i 11 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=3 418LDR_i 00 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=0 419LDR_i 01 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=1 420LDR_i 10 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=2 421LDR_i 00 111 0 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=1 sz=0 422LDR_i 01 111 0 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=1 sz=1 423 424# PRFM : prefetch memory: a no-op for QEMU 425NOP 11 111 0 00 10 0 --------- 00 ----- ----- 426 427STR_v_i sz:2 111 1 00 00 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 428STR_v_i 00 111 1 00 10 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=4 429LDR_v_i sz:2 111 1 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 430LDR_v_i 00 111 1 00 11 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=4 431 432STR_v_i sz:2 111 1 00 00 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 433STR_v_i 00 111 1 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=4 434LDR_v_i sz:2 111 1 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 435LDR_v_i 00 111 1 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=4 436 437STR_v_i sz:2 111 1 00 00 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 438STR_v_i 00 111 1 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=4 439LDR_v_i sz:2 111 1 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 440LDR_v_i 00 111 1 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=4 441 442# Load/store with an unsigned 12 bit immediate, which is scaled by the 443# element size. The function gets the sz:imm and returns the scaled immediate. 444%uimm_scaled 10:12 sz:3 !function=uimm_scaled 445 446@ldst_uimm .. ... . .. .. ............ rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=0 imm=%uimm_scaled 447 448STR_i sz:2 111 0 01 00 ............ ..... ..... @ldst_uimm sign=0 ext=0 449LDR_i 00 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=0 450LDR_i 01 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=1 451LDR_i 10 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=2 452LDR_i 11 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=3 453LDR_i 00 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=0 454LDR_i 01 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=1 455LDR_i 10 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=2 456LDR_i 00 111 0 01 11 ............ ..... ..... @ldst_uimm sign=1 ext=1 sz=0 457LDR_i 01 111 0 01 11 ............ ..... ..... @ldst_uimm sign=1 ext=1 sz=1 458 459# PRFM 460NOP 11 111 0 01 10 ------------ ----- ----- 461 462STR_v_i sz:2 111 1 01 00 ............ ..... ..... @ldst_uimm sign=0 ext=0 463STR_v_i 00 111 1 01 10 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=4 464LDR_v_i sz:2 111 1 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=0 465LDR_v_i 00 111 1 01 11 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=4 466 467# Load/store with register offset 468&ldst rm rn rt sign ext sz opt s 469@ldst .. ... . .. .. . rm:5 opt:3 s:1 .. rn:5 rt:5 &ldst 470STR sz:2 111 0 00 00 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 471LDR 00 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=0 472LDR 01 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=1 473LDR 10 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=2 474LDR 11 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=3 475LDR 00 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=0 476LDR 01 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=1 477LDR 10 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=2 478LDR 00 111 0 00 11 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=1 sz=0 479LDR 01 111 0 00 11 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=1 sz=1 480 481# PRFM 482NOP 11 111 0 00 10 1 ----- -1- - 10 ----- ----- 483 484STR_v sz:2 111 1 00 00 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 485STR_v 00 111 1 00 10 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=4 486LDR_v sz:2 111 1 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 487LDR_v 00 111 1 00 11 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=4 488 489# Atomic memory operations 490&atomic rs rn rt a r sz 491@atomic sz:2 ... . .. a:1 r:1 . rs:5 . ... .. rn:5 rt:5 &atomic 492LDADD .. 111 0 00 . . 1 ..... 0000 00 ..... ..... @atomic 493LDCLR .. 111 0 00 . . 1 ..... 0001 00 ..... ..... @atomic 494LDEOR .. 111 0 00 . . 1 ..... 0010 00 ..... ..... @atomic 495LDSET .. 111 0 00 . . 1 ..... 0011 00 ..... ..... @atomic 496LDSMAX .. 111 0 00 . . 1 ..... 0100 00 ..... ..... @atomic 497LDSMIN .. 111 0 00 . . 1 ..... 0101 00 ..... ..... @atomic 498LDUMAX .. 111 0 00 . . 1 ..... 0110 00 ..... ..... @atomic 499LDUMIN .. 111 0 00 . . 1 ..... 0111 00 ..... ..... @atomic 500SWP .. 111 0 00 . . 1 ..... 1000 00 ..... ..... @atomic 501 502LDAPR sz:2 111 0 00 1 0 1 11111 1100 00 rn:5 rt:5 503 504# Load/store register (pointer authentication) 505 506# LDRA immediate is 10 bits signed and scaled, but the bits aren't all contiguous 507%ldra_imm 22:s1 12:9 !function=times_8 508 509LDRA 11 111 0 00 m:1 . 1 ......... w:1 1 rn:5 rt:5 imm=%ldra_imm 510 511&ldapr_stlr_i rn rt imm sz sign ext 512@ldapr_stlr_i .. ...... .. . imm:9 .. rn:5 rt:5 &ldapr_stlr_i 513STLR_i sz:2 011001 00 0 ......... 00 ..... ..... @ldapr_stlr_i sign=0 ext=0 514LDAPR_i sz:2 011001 01 0 ......... 00 ..... ..... @ldapr_stlr_i sign=0 ext=0 515LDAPR_i 00 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=0 516LDAPR_i 01 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=1 517LDAPR_i 10 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=2 518LDAPR_i 00 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=1 sz=0 519LDAPR_i 01 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=1 sz=1 520 521# Load/store multiple structures 522# The 4-bit opcode in [15:12] encodes repeat count and structure elements 523&ldst_mult rm rn rt sz q p rpt selem 524@ldst_mult . q:1 ...... p:1 . . rm:5 .... sz:2 rn:5 rt:5 &ldst_mult 525ST_mult 0 . 001100 . 0 0 ..... 0000 .. ..... ..... @ldst_mult rpt=1 selem=4 526ST_mult 0 . 001100 . 0 0 ..... 0010 .. ..... ..... @ldst_mult rpt=4 selem=1 527ST_mult 0 . 001100 . 0 0 ..... 0100 .. ..... ..... @ldst_mult rpt=1 selem=3 528ST_mult 0 . 001100 . 0 0 ..... 0110 .. ..... ..... @ldst_mult rpt=3 selem=1 529ST_mult 0 . 001100 . 0 0 ..... 0111 .. ..... ..... @ldst_mult rpt=1 selem=1 530ST_mult 0 . 001100 . 0 0 ..... 1000 .. ..... ..... @ldst_mult rpt=1 selem=2 531ST_mult 0 . 001100 . 0 0 ..... 1010 .. ..... ..... @ldst_mult rpt=2 selem=1 532 533LD_mult 0 . 001100 . 1 0 ..... 0000 .. ..... ..... @ldst_mult rpt=1 selem=4 534LD_mult 0 . 001100 . 1 0 ..... 0010 .. ..... ..... @ldst_mult rpt=4 selem=1 535LD_mult 0 . 001100 . 1 0 ..... 0100 .. ..... ..... @ldst_mult rpt=1 selem=3 536LD_mult 0 . 001100 . 1 0 ..... 0110 .. ..... ..... @ldst_mult rpt=3 selem=1 537LD_mult 0 . 001100 . 1 0 ..... 0111 .. ..... ..... @ldst_mult rpt=1 selem=1 538LD_mult 0 . 001100 . 1 0 ..... 1000 .. ..... ..... @ldst_mult rpt=1 selem=2 539LD_mult 0 . 001100 . 1 0 ..... 1010 .. ..... ..... @ldst_mult rpt=2 selem=1 540 541# Load/store single structure 542&ldst_single rm rn rt p selem index scale 543 544%ldst_single_selem 13:1 21:1 !function=plus_1 545 546%ldst_single_index_b 30:1 10:3 547%ldst_single_index_h 30:1 11:2 548%ldst_single_index_s 30:1 12:1 549 550@ldst_single_b .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \ 551 &ldst_single scale=0 selem=%ldst_single_selem \ 552 index=%ldst_single_index_b 553@ldst_single_h .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \ 554 &ldst_single scale=1 selem=%ldst_single_selem \ 555 index=%ldst_single_index_h 556@ldst_single_s .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \ 557 &ldst_single scale=2 selem=%ldst_single_selem \ 558 index=%ldst_single_index_s 559@ldst_single_d . index:1 ...... p:1 .. rm:5 ...... rn:5 rt:5 \ 560 &ldst_single scale=3 selem=%ldst_single_selem 561 562ST_single 0 . 001101 . 0 . ..... 00 . ... ..... ..... @ldst_single_b 563ST_single 0 . 001101 . 0 . ..... 01 . ..0 ..... ..... @ldst_single_h 564ST_single 0 . 001101 . 0 . ..... 10 . .00 ..... ..... @ldst_single_s 565ST_single 0 . 001101 . 0 . ..... 10 . 001 ..... ..... @ldst_single_d 566 567LD_single 0 . 001101 . 1 . ..... 00 . ... ..... ..... @ldst_single_b 568LD_single 0 . 001101 . 1 . ..... 01 . ..0 ..... ..... @ldst_single_h 569LD_single 0 . 001101 . 1 . ..... 10 . .00 ..... ..... @ldst_single_s 570LD_single 0 . 001101 . 1 . ..... 10 . 001 ..... ..... @ldst_single_d 571 572# Replicating load case 573LD_single_repl 0 q:1 001101 p:1 1 . rm:5 11 . 0 scale:2 rn:5 rt:5 selem=%ldst_single_selem 574 575%tag_offset 12:s9 !function=scale_by_log2_tag_granule 576&ldst_tag rn rt imm p w 577@ldst_tag ........ .. . ......... .. rn:5 rt:5 &ldst_tag imm=%tag_offset 578@ldst_tag_mult ........ .. . 000000000 .. rn:5 rt:5 &ldst_tag imm=0 579 580STZGM 11011001 00 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0 581STG 11011001 00 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 582STG 11011001 00 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 583STG 11011001 00 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 584 585LDG 11011001 01 1 ......... 00 ..... ..... @ldst_tag p=0 w=0 586STZG 11011001 01 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 587STZG 11011001 01 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 588STZG 11011001 01 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 589 590STGM 11011001 10 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0 591ST2G 11011001 10 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 592ST2G 11011001 10 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 593ST2G 11011001 10 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 594 595LDGM 11011001 11 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0 596STZ2G 11011001 11 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 597STZ2G 11011001 11 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 598STZ2G 11011001 11 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 599 600# Memory operations (memset, memcpy, memmove) 601# Each of these comes in a set of three, eg SETP (prologue), SETM (main), 602# SETE (epilogue), and each of those has different flavours to 603# indicate whether memory accesses should be unpriv or non-temporal. 604# We don't distinguish temporal and non-temporal accesses, but we 605# do need to report it in syndrome register values. 606 607# Memset 608&set rs rn rd unpriv nontemp 609# op2 bit 1 is nontemporal bit 610@set .. ......... rs:5 .. nontemp:1 unpriv:1 .. rn:5 rd:5 &set 611 612SETP 00 011001110 ..... 00 . . 01 ..... ..... @set 613SETM 00 011001110 ..... 01 . . 01 ..... ..... @set 614SETE 00 011001110 ..... 10 . . 01 ..... ..... @set 615 616# Like SET, but also setting MTE tags 617SETGP 00 011101110 ..... 00 . . 01 ..... ..... @set 618SETGM 00 011101110 ..... 01 . . 01 ..... ..... @set 619SETGE 00 011101110 ..... 10 . . 01 ..... ..... @set 620 621# Memmove/Memcopy: the CPY insns allow overlapping src/dest and 622# copy in the correct direction; the CPYF insns always copy forwards. 623# 624# options has the nontemporal and unpriv bits for src and dest 625&cpy rs rn rd options 626@cpy .. ... . ..... rs:5 options:4 .. rn:5 rd:5 &cpy 627 628CPYFP 00 011 0 01000 ..... .... 01 ..... ..... @cpy 629CPYFM 00 011 0 01010 ..... .... 01 ..... ..... @cpy 630CPYFE 00 011 0 01100 ..... .... 01 ..... ..... @cpy 631CPYP 00 011 1 01000 ..... .... 01 ..... ..... @cpy 632CPYM 00 011 1 01010 ..... .... 01 ..... ..... @cpy 633CPYE 00 011 1 01100 ..... .... 01 ..... ..... @cpy 634 635### Cryptographic AES 636 637AESE 01001110 00 10100 00100 10 ..... ..... @r2r_q1e0 638AESD 01001110 00 10100 00101 10 ..... ..... @r2r_q1e0 639AESMC 01001110 00 10100 00110 10 ..... ..... @rr_q1e0 640AESIMC 01001110 00 10100 00111 10 ..... ..... @rr_q1e0 641 642### Cryptographic three-register SHA 643 644SHA1C 0101 1110 000 ..... 000000 ..... ..... @rrr_q1e0 645SHA1P 0101 1110 000 ..... 000100 ..... ..... @rrr_q1e0 646SHA1M 0101 1110 000 ..... 001000 ..... ..... @rrr_q1e0 647SHA1SU0 0101 1110 000 ..... 001100 ..... ..... @rrr_q1e0 648SHA256H 0101 1110 000 ..... 010000 ..... ..... @rrr_q1e0 649SHA256H2 0101 1110 000 ..... 010100 ..... ..... @rrr_q1e0 650SHA256SU1 0101 1110 000 ..... 011000 ..... ..... @rrr_q1e0 651 652### Cryptographic two-register SHA 653 654SHA1H 0101 1110 0010 1000 0000 10 ..... ..... @rr_q1e0 655SHA1SU1 0101 1110 0010 1000 0001 10 ..... ..... @rr_q1e0 656SHA256SU0 0101 1110 0010 1000 0010 10 ..... ..... @rr_q1e0 657 658### Cryptographic three-register SHA512 659 660SHA512H 1100 1110 011 ..... 100000 ..... ..... @rrr_q1e0 661SHA512H2 1100 1110 011 ..... 100001 ..... ..... @rrr_q1e0 662SHA512SU1 1100 1110 011 ..... 100010 ..... ..... @rrr_q1e0 663RAX1 1100 1110 011 ..... 100011 ..... ..... @rrr_q1e3 664SM3PARTW1 1100 1110 011 ..... 110000 ..... ..... @rrr_q1e0 665SM3PARTW2 1100 1110 011 ..... 110001 ..... ..... @rrr_q1e0 666SM4EKEY 1100 1110 011 ..... 110010 ..... ..... @rrr_q1e0 667 668### Cryptographic two-register SHA512 669 670SHA512SU0 1100 1110 110 00000 100000 ..... ..... @rr_q1e0 671SM4E 1100 1110 110 00000 100001 ..... ..... @r2r_q1e0 672 673### Cryptographic four-register 674 675EOR3 1100 1110 000 ..... 0 ..... ..... ..... @rrrr_q1e3 676BCAX 1100 1110 001 ..... 0 ..... ..... ..... @rrrr_q1e3 677SM3SS1 1100 1110 010 ..... 0 ..... ..... ..... @rrrr_q1e3 678 679### Cryptographic three-register, imm2 680 681&crypto3i rd rn rm imm 682@crypto3i ........ ... rm:5 .. imm:2 .. rn:5 rd:5 &crypto3i 683 684SM3TT1A 11001110 010 ..... 10 .. 00 ..... ..... @crypto3i 685SM3TT1B 11001110 010 ..... 10 .. 01 ..... ..... @crypto3i 686SM3TT2A 11001110 010 ..... 10 .. 10 ..... ..... @crypto3i 687SM3TT2B 11001110 010 ..... 10 .. 11 ..... ..... @crypto3i 688 689### Cryptographic XAR 690 691XAR 1100 1110 100 rm:5 imm:6 rn:5 rd:5 692 693### Advanced SIMD scalar copy 694 695DUP_element_s 0101 1110 000 imm:5 0 0000 1 rn:5 rd:5 696 697### Advanced SIMD copy 698 699DUP_element_v 0 q:1 00 1110 000 imm:5 0 0000 1 rn:5 rd:5 700DUP_general 0 q:1 00 1110 000 imm:5 0 0001 1 rn:5 rd:5 701INS_general 0 1 00 1110 000 imm:5 0 0011 1 rn:5 rd:5 702SMOV 0 q:1 00 1110 000 imm:5 0 0101 1 rn:5 rd:5 703UMOV 0 q:1 00 1110 000 imm:5 0 0111 1 rn:5 rd:5 704INS_element 0 1 10 1110 000 di:5 0 si:4 1 rn:5 rd:5 705 706### Advanced SIMD scalar three same 707 708FADD_s 0001 1110 ..1 ..... 0010 10 ..... ..... @rrr_hsd 709FSUB_s 0001 1110 ..1 ..... 0011 10 ..... ..... @rrr_hsd 710FDIV_s 0001 1110 ..1 ..... 0001 10 ..... ..... @rrr_hsd 711FMUL_s 0001 1110 ..1 ..... 0000 10 ..... ..... @rrr_hsd 712FNMUL_s 0001 1110 ..1 ..... 1000 10 ..... ..... @rrr_hsd 713 714FMAX_s 0001 1110 ..1 ..... 0100 10 ..... ..... @rrr_hsd 715FMIN_s 0001 1110 ..1 ..... 0101 10 ..... ..... @rrr_hsd 716FMAXNM_s 0001 1110 ..1 ..... 0110 10 ..... ..... @rrr_hsd 717FMINNM_s 0001 1110 ..1 ..... 0111 10 ..... ..... @rrr_hsd 718 719FMULX_s 0101 1110 010 ..... 00011 1 ..... ..... @rrr_h 720FMULX_s 0101 1110 0.1 ..... 11011 1 ..... ..... @rrr_sd 721 722FCMEQ_s 0101 1110 010 ..... 00100 1 ..... ..... @rrr_h 723FCMEQ_s 0101 1110 0.1 ..... 11100 1 ..... ..... @rrr_sd 724 725FCMGE_s 0111 1110 010 ..... 00100 1 ..... ..... @rrr_h 726FCMGE_s 0111 1110 0.1 ..... 11100 1 ..... ..... @rrr_sd 727 728FCMGT_s 0111 1110 110 ..... 00100 1 ..... ..... @rrr_h 729FCMGT_s 0111 1110 1.1 ..... 11100 1 ..... ..... @rrr_sd 730 731FACGE_s 0111 1110 010 ..... 00101 1 ..... ..... @rrr_h 732FACGE_s 0111 1110 0.1 ..... 11101 1 ..... ..... @rrr_sd 733 734FACGT_s 0111 1110 110 ..... 00101 1 ..... ..... @rrr_h 735FACGT_s 0111 1110 1.1 ..... 11101 1 ..... ..... @rrr_sd 736 737FABD_s 0111 1110 110 ..... 00010 1 ..... ..... @rrr_h 738FABD_s 0111 1110 1.1 ..... 11010 1 ..... ..... @rrr_sd 739 740FRECPS_s 0101 1110 010 ..... 00111 1 ..... ..... @rrr_h 741FRECPS_s 0101 1110 0.1 ..... 11111 1 ..... ..... @rrr_sd 742 743FRSQRTS_s 0101 1110 110 ..... 00111 1 ..... ..... @rrr_h 744FRSQRTS_s 0101 1110 1.1 ..... 11111 1 ..... ..... @rrr_sd 745 746### Advanced SIMD scalar pairwise 747 748FADDP_s 0101 1110 0011 0000 1101 10 ..... ..... @rr_h 749FADDP_s 0111 1110 0.11 0000 1101 10 ..... ..... @rr_sd 750 751FMAXP_s 0101 1110 0011 0000 1111 10 ..... ..... @rr_h 752FMAXP_s 0111 1110 0.11 0000 1111 10 ..... ..... @rr_sd 753 754FMINP_s 0101 1110 1011 0000 1111 10 ..... ..... @rr_h 755FMINP_s 0111 1110 1.11 0000 1111 10 ..... ..... @rr_sd 756 757FMAXNMP_s 0101 1110 0011 0000 1100 10 ..... ..... @rr_h 758FMAXNMP_s 0111 1110 0.11 0000 1100 10 ..... ..... @rr_sd 759 760FMINNMP_s 0101 1110 1011 0000 1100 10 ..... ..... @rr_h 761FMINNMP_s 0111 1110 1.11 0000 1100 10 ..... ..... @rr_sd 762 763ADDP_s 0101 1110 1111 0001 1011 10 ..... ..... @rr_d 764 765### Advanced SIMD three same 766 767FADD_v 0.00 1110 010 ..... 00010 1 ..... ..... @qrrr_h 768FADD_v 0.00 1110 0.1 ..... 11010 1 ..... ..... @qrrr_sd 769 770FSUB_v 0.00 1110 110 ..... 00010 1 ..... ..... @qrrr_h 771FSUB_v 0.00 1110 1.1 ..... 11010 1 ..... ..... @qrrr_sd 772 773FDIV_v 0.10 1110 010 ..... 00111 1 ..... ..... @qrrr_h 774FDIV_v 0.10 1110 0.1 ..... 11111 1 ..... ..... @qrrr_sd 775 776FMUL_v 0.10 1110 010 ..... 00011 1 ..... ..... @qrrr_h 777FMUL_v 0.10 1110 0.1 ..... 11011 1 ..... ..... @qrrr_sd 778 779FMAX_v 0.00 1110 010 ..... 00110 1 ..... ..... @qrrr_h 780FMAX_v 0.00 1110 0.1 ..... 11110 1 ..... ..... @qrrr_sd 781 782FMIN_v 0.00 1110 110 ..... 00110 1 ..... ..... @qrrr_h 783FMIN_v 0.00 1110 1.1 ..... 11110 1 ..... ..... @qrrr_sd 784 785FMAXNM_v 0.00 1110 010 ..... 00000 1 ..... ..... @qrrr_h 786FMAXNM_v 0.00 1110 0.1 ..... 11000 1 ..... ..... @qrrr_sd 787 788FMINNM_v 0.00 1110 110 ..... 00000 1 ..... ..... @qrrr_h 789FMINNM_v 0.00 1110 1.1 ..... 11000 1 ..... ..... @qrrr_sd 790 791FMULX_v 0.00 1110 010 ..... 00011 1 ..... ..... @qrrr_h 792FMULX_v 0.00 1110 0.1 ..... 11011 1 ..... ..... @qrrr_sd 793 794FMLA_v 0.00 1110 010 ..... 00001 1 ..... ..... @qrrr_h 795FMLA_v 0.00 1110 0.1 ..... 11001 1 ..... ..... @qrrr_sd 796 797FMLS_v 0.00 1110 110 ..... 00001 1 ..... ..... @qrrr_h 798FMLS_v 0.00 1110 1.1 ..... 11001 1 ..... ..... @qrrr_sd 799 800FMLAL_v 0.00 1110 001 ..... 11101 1 ..... ..... @qrrr_h 801FMLSL_v 0.00 1110 101 ..... 11101 1 ..... ..... @qrrr_h 802FMLAL2_v 0.10 1110 001 ..... 11001 1 ..... ..... @qrrr_h 803FMLSL2_v 0.10 1110 101 ..... 11001 1 ..... ..... @qrrr_h 804 805FCMEQ_v 0.00 1110 010 ..... 00100 1 ..... ..... @qrrr_h 806FCMEQ_v 0.00 1110 0.1 ..... 11100 1 ..... ..... @qrrr_sd 807 808FCMGE_v 0.10 1110 010 ..... 00100 1 ..... ..... @qrrr_h 809FCMGE_v 0.10 1110 0.1 ..... 11100 1 ..... ..... @qrrr_sd 810 811FCMGT_v 0.10 1110 110 ..... 00100 1 ..... ..... @qrrr_h 812FCMGT_v 0.10 1110 1.1 ..... 11100 1 ..... ..... @qrrr_sd 813 814FACGE_v 0.10 1110 010 ..... 00101 1 ..... ..... @qrrr_h 815FACGE_v 0.10 1110 0.1 ..... 11101 1 ..... ..... @qrrr_sd 816 817FACGT_v 0.10 1110 110 ..... 00101 1 ..... ..... @qrrr_h 818FACGT_v 0.10 1110 1.1 ..... 11101 1 ..... ..... @qrrr_sd 819 820FABD_v 0.10 1110 110 ..... 00010 1 ..... ..... @qrrr_h 821FABD_v 0.10 1110 1.1 ..... 11010 1 ..... ..... @qrrr_sd 822 823FRECPS_v 0.00 1110 010 ..... 00111 1 ..... ..... @qrrr_h 824FRECPS_v 0.00 1110 0.1 ..... 11111 1 ..... ..... @qrrr_sd 825 826FRSQRTS_v 0.00 1110 110 ..... 00111 1 ..... ..... @qrrr_h 827FRSQRTS_v 0.00 1110 1.1 ..... 11111 1 ..... ..... @qrrr_sd 828 829FADDP_v 0.10 1110 010 ..... 00010 1 ..... ..... @qrrr_h 830FADDP_v 0.10 1110 0.1 ..... 11010 1 ..... ..... @qrrr_sd 831 832FMAXP_v 0.10 1110 010 ..... 00110 1 ..... ..... @qrrr_h 833FMAXP_v 0.10 1110 0.1 ..... 11110 1 ..... ..... @qrrr_sd 834 835FMINP_v 0.10 1110 110 ..... 00110 1 ..... ..... @qrrr_h 836FMINP_v 0.10 1110 1.1 ..... 11110 1 ..... ..... @qrrr_sd 837 838FMAXNMP_v 0.10 1110 010 ..... 00000 1 ..... ..... @qrrr_h 839FMAXNMP_v 0.10 1110 0.1 ..... 11000 1 ..... ..... @qrrr_sd 840 841FMINNMP_v 0.10 1110 110 ..... 00000 1 ..... ..... @qrrr_h 842FMINNMP_v 0.10 1110 1.1 ..... 11000 1 ..... ..... @qrrr_sd 843 844ADDP_v 0.00 1110 ..1 ..... 10111 1 ..... ..... @qrrr_e 845SMAXP_v 0.00 1110 ..1 ..... 10100 1 ..... ..... @qrrr_e 846SMINP_v 0.00 1110 ..1 ..... 10101 1 ..... ..... @qrrr_e 847UMAXP_v 0.10 1110 ..1 ..... 10100 1 ..... ..... @qrrr_e 848UMINP_v 0.10 1110 ..1 ..... 10101 1 ..... ..... @qrrr_e 849 850### Advanced SIMD scalar x indexed element 851 852FMUL_si 0101 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h 853FMUL_si 0101 1111 10 . ..... 1001 . 0 ..... ..... @rrx_s 854FMUL_si 0101 1111 11 0 ..... 1001 . 0 ..... ..... @rrx_d 855 856FMLA_si 0101 1111 00 .. .... 0001 . 0 ..... ..... @rrx_h 857FMLA_si 0101 1111 10 .. .... 0001 . 0 ..... ..... @rrx_s 858FMLA_si 0101 1111 11 0. .... 0001 . 0 ..... ..... @rrx_d 859 860FMLS_si 0101 1111 00 .. .... 0101 . 0 ..... ..... @rrx_h 861FMLS_si 0101 1111 10 .. .... 0101 . 0 ..... ..... @rrx_s 862FMLS_si 0101 1111 11 0. .... 0101 . 0 ..... ..... @rrx_d 863 864FMULX_si 0111 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h 865FMULX_si 0111 1111 10 . ..... 1001 . 0 ..... ..... @rrx_s 866FMULX_si 0111 1111 11 0 ..... 1001 . 0 ..... ..... @rrx_d 867 868### Advanced SIMD vector x indexed element 869 870FMUL_vi 0.00 1111 00 .. .... 1001 . 0 ..... ..... @qrrx_h 871FMUL_vi 0.00 1111 10 . ..... 1001 . 0 ..... ..... @qrrx_s 872FMUL_vi 0.00 1111 11 0 ..... 1001 . 0 ..... ..... @qrrx_d 873 874FMLA_vi 0.00 1111 00 .. .... 0001 . 0 ..... ..... @qrrx_h 875FMLA_vi 0.00 1111 10 . ..... 0001 . 0 ..... ..... @qrrx_s 876FMLA_vi 0.00 1111 11 0 ..... 0001 . 0 ..... ..... @qrrx_d 877 878FMLS_vi 0.00 1111 00 .. .... 0101 . 0 ..... ..... @qrrx_h 879FMLS_vi 0.00 1111 10 . ..... 0101 . 0 ..... ..... @qrrx_s 880FMLS_vi 0.00 1111 11 0 ..... 0101 . 0 ..... ..... @qrrx_d 881 882FMULX_vi 0.10 1111 00 .. .... 1001 . 0 ..... ..... @qrrx_h 883FMULX_vi 0.10 1111 10 . ..... 1001 . 0 ..... ..... @qrrx_s 884FMULX_vi 0.10 1111 11 0 ..... 1001 . 0 ..... ..... @qrrx_d 885 886FMLAL_vi 0.00 1111 10 .. .... 0000 . 0 ..... ..... @qrrx_h 887FMLSL_vi 0.00 1111 10 .. .... 0100 . 0 ..... ..... @qrrx_h 888FMLAL2_vi 0.10 1111 10 .. .... 1000 . 0 ..... ..... @qrrx_h 889FMLSL2_vi 0.10 1111 10 .. .... 1100 . 0 ..... ..... @qrrx_h 890