1# AArch64 A64 allowed instruction decoding 2# 3# Copyright (c) 2023 Linaro, Ltd 4# 5# This library is free software; you can redistribute it and/or 6# modify it under the terms of the GNU Lesser General Public 7# License as published by the Free Software Foundation; either 8# version 2.1 of the License, or (at your option) any later version. 9# 10# This library is distributed in the hope that it will be useful, 11# but WITHOUT ANY WARRANTY; without even the implied warranty of 12# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13# Lesser General Public License for more details. 14# 15# You should have received a copy of the GNU Lesser General Public 16# License along with this library; if not, see <http://www.gnu.org/licenses/>. 17 18# 19# This file is processed by scripts/decodetree.py 20# 21 22%rd 0:5 23%esz_sd 22:1 !function=plus_2 24%esz_hsd 22:2 !function=xor_2 25%hl 11:1 21:1 26%hlm 11:1 20:2 27 28&r rn 29&ri rd imm 30&rri_sf rd rn imm sf 31&i imm 32&rr_e rd rn esz 33&rrr_e rd rn rm esz 34&rrx_e rd rn rm idx esz 35&qrr_e q rd rn esz 36&qrrr_e q rd rn rm esz 37&qrrx_e q rd rn rm idx esz 38&qrrrr_e q rd rn rm ra esz 39 40@rr_h ........ ... ..... ...... rn:5 rd:5 &rr_e esz=1 41@rr_sd ........ ... ..... ...... rn:5 rd:5 &rr_e esz=%esz_sd 42 43@rrr_h ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=1 44@rrr_sd ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=%esz_sd 45@rrr_hsd ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=%esz_hsd 46 47@rrx_h ........ .. .. rm:4 .... . . rn:5 rd:5 &rrx_e esz=1 idx=%hlm 48@rrx_s ........ .. . rm:5 .... . . rn:5 rd:5 &rrx_e esz=2 idx=%hl 49@rrx_d ........ .. . rm:5 .... idx:1 . rn:5 rd:5 &rrx_e esz=3 50 51@rr_q1e0 ........ ........ ...... rn:5 rd:5 &qrr_e q=1 esz=0 52@r2r_q1e0 ........ ........ ...... rm:5 rd:5 &qrrr_e rn=%rd q=1 esz=0 53@rrr_q1e0 ........ ... rm:5 ...... rn:5 rd:5 &qrrr_e q=1 esz=0 54@rrr_q1e3 ........ ... rm:5 ...... rn:5 rd:5 &qrrr_e q=1 esz=3 55@rrrr_q1e3 ........ ... rm:5 . ra:5 rn:5 rd:5 &qrrrr_e q=1 esz=3 56 57@qrrr_h . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=1 58@qrrr_sd . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=%esz_sd 59 60@qrrx_h . q:1 .. .... .. .. rm:4 .... . . rn:5 rd:5 \ 61 &qrrx_e esz=1 idx=%hlm 62@qrrx_s . q:1 .. .... .. . rm:5 .... . . rn:5 rd:5 \ 63 &qrrx_e esz=2 idx=%hl 64@qrrx_d . q:1 .. .... .. . rm:5 .... idx:1 . rn:5 rd:5 \ 65 &qrrx_e esz=3 66 67### Data Processing - Immediate 68 69# PC-rel addressing 70 71%imm_pcrel 5:s19 29:2 72@pcrel . .. ..... ................... rd:5 &ri imm=%imm_pcrel 73 74ADR 0 .. 10000 ................... ..... @pcrel 75ADRP 1 .. 10000 ................... ..... @pcrel 76 77# Add/subtract (immediate) 78 79%imm12_sh12 10:12 !function=shl_12 80@addsub_imm sf:1 .. ...... . imm:12 rn:5 rd:5 81@addsub_imm12 sf:1 .. ...... . ............ rn:5 rd:5 imm=%imm12_sh12 82 83ADD_i . 00 100010 0 ............ ..... ..... @addsub_imm 84ADD_i . 00 100010 1 ............ ..... ..... @addsub_imm12 85ADDS_i . 01 100010 0 ............ ..... ..... @addsub_imm 86ADDS_i . 01 100010 1 ............ ..... ..... @addsub_imm12 87 88SUB_i . 10 100010 0 ............ ..... ..... @addsub_imm 89SUB_i . 10 100010 1 ............ ..... ..... @addsub_imm12 90SUBS_i . 11 100010 0 ............ ..... ..... @addsub_imm 91SUBS_i . 11 100010 1 ............ ..... ..... @addsub_imm12 92 93# Add/subtract (immediate with tags) 94 95&rri_tag rd rn uimm6 uimm4 96@addsub_imm_tag . .. ...... . uimm6:6 .. uimm4:4 rn:5 rd:5 &rri_tag 97 98ADDG_i 1 00 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag 99SUBG_i 1 10 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag 100 101# Logical (immediate) 102 103&rri_log rd rn sf dbm 104@logic_imm_64 1 .. ...... dbm:13 rn:5 rd:5 &rri_log sf=1 105@logic_imm_32 0 .. ...... 0 dbm:12 rn:5 rd:5 &rri_log sf=0 106 107AND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_64 108AND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_32 109ORR_i . 01 100100 . ...... ...... ..... ..... @logic_imm_64 110ORR_i . 01 100100 . ...... ...... ..... ..... @logic_imm_32 111EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_64 112EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_32 113ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_64 114ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_32 115 116# Move wide (immediate) 117 118&movw rd sf imm hw 119@movw_64 1 .. ...... hw:2 imm:16 rd:5 &movw sf=1 120@movw_32 0 .. ...... 0 hw:1 imm:16 rd:5 &movw sf=0 121 122MOVN . 00 100101 .. ................ ..... @movw_64 123MOVN . 00 100101 .. ................ ..... @movw_32 124MOVZ . 10 100101 .. ................ ..... @movw_64 125MOVZ . 10 100101 .. ................ ..... @movw_32 126MOVK . 11 100101 .. ................ ..... @movw_64 127MOVK . 11 100101 .. ................ ..... @movw_32 128 129# Bitfield 130 131&bitfield rd rn sf immr imms 132@bitfield_64 1 .. ...... 1 immr:6 imms:6 rn:5 rd:5 &bitfield sf=1 133@bitfield_32 0 .. ...... 0 0 immr:5 0 imms:5 rn:5 rd:5 &bitfield sf=0 134 135SBFM . 00 100110 . ...... ...... ..... ..... @bitfield_64 136SBFM . 00 100110 . ...... ...... ..... ..... @bitfield_32 137BFM . 01 100110 . ...... ...... ..... ..... @bitfield_64 138BFM . 01 100110 . ...... ...... ..... ..... @bitfield_32 139UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_64 140UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_32 141 142# Extract 143 144&extract rd rn rm imm sf 145 146EXTR 1 00 100111 1 0 rm:5 imm:6 rn:5 rd:5 &extract sf=1 147EXTR 0 00 100111 0 0 rm:5 0 imm:5 rn:5 rd:5 &extract sf=0 148 149# Branches 150 151%imm26 0:s26 !function=times_4 152@branch . ..... .......................... &i imm=%imm26 153 154B 0 00101 .......................... @branch 155BL 1 00101 .......................... @branch 156 157%imm19 5:s19 !function=times_4 158&cbz rt imm sf nz 159 160CBZ sf:1 011010 nz:1 ................... rt:5 &cbz imm=%imm19 161 162%imm14 5:s14 !function=times_4 163%imm31_19 31:1 19:5 164&tbz rt imm nz bitpos 165 166TBZ . 011011 nz:1 ..... .............. rt:5 &tbz imm=%imm14 bitpos=%imm31_19 167 168# B.cond and BC.cond 169B_cond 0101010 0 ................... c:1 cond:4 imm=%imm19 170 171BR 1101011 0000 11111 000000 rn:5 00000 &r 172BLR 1101011 0001 11111 000000 rn:5 00000 &r 173RET 1101011 0010 11111 000000 rn:5 00000 &r 174 175&braz rn m 176BRAZ 1101011 0000 11111 00001 m:1 rn:5 11111 &braz # BRAAZ, BRABZ 177BLRAZ 1101011 0001 11111 00001 m:1 rn:5 11111 &braz # BLRAAZ, BLRABZ 178 179&reta m 180RETA 1101011 0010 11111 00001 m:1 11111 11111 &reta # RETAA, RETAB 181 182&bra rn rm m 183BRA 1101011 1000 11111 00001 m:1 rn:5 rm:5 &bra # BRAA, BRAB 184BLRA 1101011 1001 11111 00001 m:1 rn:5 rm:5 &bra # BLRAA, BLRAB 185 186ERET 1101011 0100 11111 000000 11111 00000 187ERETA 1101011 0100 11111 00001 m:1 11111 11111 &reta # ERETAA, ERETAB 188 189# We don't need to decode DRPS because it always UNDEFs except when 190# the processor is in halting debug state (which we don't implement). 191# The pattern is listed here as documentation. 192# DRPS 1101011 0101 11111 000000 11111 00000 193 194# Hint instruction group 195{ 196 [ 197 YIELD 1101 0101 0000 0011 0010 0000 001 11111 198 WFE 1101 0101 0000 0011 0010 0000 010 11111 199 WFI 1101 0101 0000 0011 0010 0000 011 11111 200 # We implement WFE to never block, so our SEV/SEVL are NOPs 201 # SEV 1101 0101 0000 0011 0010 0000 100 11111 202 # SEVL 1101 0101 0000 0011 0010 0000 101 11111 203 # Our DGL is a NOP because we don't merge memory accesses anyway. 204 # DGL 1101 0101 0000 0011 0010 0000 110 11111 205 XPACLRI 1101 0101 0000 0011 0010 0000 111 11111 206 PACIA1716 1101 0101 0000 0011 0010 0001 000 11111 207 PACIB1716 1101 0101 0000 0011 0010 0001 010 11111 208 AUTIA1716 1101 0101 0000 0011 0010 0001 100 11111 209 AUTIB1716 1101 0101 0000 0011 0010 0001 110 11111 210 ESB 1101 0101 0000 0011 0010 0010 000 11111 211 PACIAZ 1101 0101 0000 0011 0010 0011 000 11111 212 PACIASP 1101 0101 0000 0011 0010 0011 001 11111 213 PACIBZ 1101 0101 0000 0011 0010 0011 010 11111 214 PACIBSP 1101 0101 0000 0011 0010 0011 011 11111 215 AUTIAZ 1101 0101 0000 0011 0010 0011 100 11111 216 AUTIASP 1101 0101 0000 0011 0010 0011 101 11111 217 AUTIBZ 1101 0101 0000 0011 0010 0011 110 11111 218 AUTIBSP 1101 0101 0000 0011 0010 0011 111 11111 219 ] 220 # The canonical NOP has CRm == op2 == 0, but all of the space 221 # that isn't specifically allocated to an instruction must NOP 222 NOP 1101 0101 0000 0011 0010 ---- --- 11111 223} 224 225# Barriers 226 227CLREX 1101 0101 0000 0011 0011 ---- 010 11111 228DSB_DMB 1101 0101 0000 0011 0011 domain:2 types:2 10- 11111 229ISB 1101 0101 0000 0011 0011 ---- 110 11111 230SB 1101 0101 0000 0011 0011 0000 111 11111 231 232# PSTATE 233 234CFINV 1101 0101 0000 0 000 0100 0000 000 11111 235XAFLAG 1101 0101 0000 0 000 0100 0000 001 11111 236AXFLAG 1101 0101 0000 0 000 0100 0000 010 11111 237 238# These are architecturally all "MSR (immediate)"; we decode the destination 239# register too because there is no commonality in our implementation. 240@msr_i .... .... .... . ... .... imm:4 ... ..... 241MSR_i_UAO 1101 0101 0000 0 000 0100 .... 011 11111 @msr_i 242MSR_i_PAN 1101 0101 0000 0 000 0100 .... 100 11111 @msr_i 243MSR_i_SPSEL 1101 0101 0000 0 000 0100 .... 101 11111 @msr_i 244MSR_i_SBSS 1101 0101 0000 0 011 0100 .... 001 11111 @msr_i 245MSR_i_DIT 1101 0101 0000 0 011 0100 .... 010 11111 @msr_i 246MSR_i_TCO 1101 0101 0000 0 011 0100 .... 100 11111 @msr_i 247MSR_i_DAIFSET 1101 0101 0000 0 011 0100 .... 110 11111 @msr_i 248MSR_i_DAIFCLEAR 1101 0101 0000 0 011 0100 .... 111 11111 @msr_i 249MSR_i_ALLINT 1101 0101 0000 0 001 0100 000 imm:1 000 11111 250MSR_i_SVCR 1101 0101 0000 0 011 0100 0 mask:2 imm:1 011 11111 251 252# MRS, MSR (register), SYS, SYSL. These are all essentially the 253# same instruction as far as QEMU is concerned. 254# NB: op0 is bits [20:19], but op0=0b00 is other insns, so we have 255# to hand-decode it. 256SYS 1101 0101 00 l:1 01 op1:3 crn:4 crm:4 op2:3 rt:5 op0=1 257SYS 1101 0101 00 l:1 10 op1:3 crn:4 crm:4 op2:3 rt:5 op0=2 258SYS 1101 0101 00 l:1 11 op1:3 crn:4 crm:4 op2:3 rt:5 op0=3 259 260# Exception generation 261 262@i16 .... .... ... imm:16 ... .. &i 263SVC 1101 0100 000 ................ 000 01 @i16 264HVC 1101 0100 000 ................ 000 10 @i16 265SMC 1101 0100 000 ................ 000 11 @i16 266BRK 1101 0100 001 ................ 000 00 @i16 267HLT 1101 0100 010 ................ 000 00 @i16 268# These insns always UNDEF unless in halting debug state, which 269# we don't implement. So we don't need to decode them. The patterns 270# are listed here as documentation. 271# DCPS1 1101 0100 101 ................ 000 01 @i16 272# DCPS2 1101 0100 101 ................ 000 10 @i16 273# DCPS3 1101 0100 101 ................ 000 11 @i16 274 275# Loads and stores 276 277&stxr rn rt rt2 rs sz lasr 278&stlr rn rt sz lasr 279@stxr sz:2 ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr 280@stlr sz:2 ...... ... ..... lasr:1 ..... rn:5 rt:5 &stlr 281%imm1_30_p2 30:1 !function=plus_2 282@stxp .. ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr sz=%imm1_30_p2 283STXR .. 001000 000 ..... . ..... ..... ..... @stxr # inc STLXR 284LDXR .. 001000 010 ..... . ..... ..... ..... @stxr # inc LDAXR 285STLR .. 001000 100 11111 . 11111 ..... ..... @stlr # inc STLLR 286LDAR .. 001000 110 11111 . 11111 ..... ..... @stlr # inc LDLAR 287 288STXP 1 . 001000 001 ..... . ..... ..... ..... @stxp # inc STLXP 289LDXP 1 . 001000 011 ..... . ..... ..... ..... @stxp # inc LDAXP 290 291# CASP, CASPA, CASPAL, CASPL (we don't decode the bits that determine 292# acquire/release semantics because QEMU's cmpxchg always has those) 293CASP 0 . 001000 0 - 1 rs:5 - 11111 rn:5 rt:5 sz=%imm1_30_p2 294# CAS, CASA, CASAL, CASL 295CAS sz:2 001000 1 - 1 rs:5 - 11111 rn:5 rt:5 296 297&ldlit rt imm sz sign 298@ldlit .. ... . .. ................... rt:5 &ldlit imm=%imm19 299 300LD_lit 00 011 0 00 ................... ..... @ldlit sz=2 sign=0 301LD_lit 01 011 0 00 ................... ..... @ldlit sz=3 sign=0 302LD_lit 10 011 0 00 ................... ..... @ldlit sz=2 sign=1 303LD_lit_v 00 011 1 00 ................... ..... @ldlit sz=2 sign=0 304LD_lit_v 01 011 1 00 ................... ..... @ldlit sz=3 sign=0 305LD_lit_v 10 011 1 00 ................... ..... @ldlit sz=4 sign=0 306 307# PRFM 308NOP 11 011 0 00 ------------------- ----- 309 310&ldstpair rt2 rt rn imm sz sign w p 311@ldstpair .. ... . ... . imm:s7 rt2:5 rn:5 rt:5 &ldstpair 312 313# STNP, LDNP: Signed offset, non-temporal hint. We don't emulate caches 314# so we ignore hints about data access patterns, and handle these like 315# plain signed offset. 316STP 00 101 0 000 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 317LDP 00 101 0 000 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 318STP 10 101 0 000 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 319LDP 10 101 0 000 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 320STP_v 00 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 321LDP_v 00 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 322STP_v 01 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 323LDP_v 01 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 324STP_v 10 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 325LDP_v 10 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 326 327# STP and LDP: post-indexed 328STP 00 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 329LDP 00 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 330LDP 01 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=1 w=1 331STP 10 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 332LDP 10 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 333STP_v 00 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 334LDP_v 00 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 335STP_v 01 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 336LDP_v 01 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 337STP_v 10 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=1 w=1 338LDP_v 10 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=1 w=1 339 340# STP and LDP: offset 341STP 00 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 342LDP 00 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 343LDP 01 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=0 w=0 344STP 10 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 345LDP 10 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 346STP_v 00 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 347LDP_v 00 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 348STP_v 01 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 349LDP_v 01 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 350STP_v 10 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 351LDP_v 10 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 352 353# STP and LDP: pre-indexed 354STP 00 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 355LDP 00 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 356LDP 01 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=0 w=1 357STP 10 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 358LDP 10 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 359STP_v 00 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 360LDP_v 00 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 361STP_v 01 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 362LDP_v 01 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 363STP_v 10 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=1 364LDP_v 10 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=1 365 366# STGP: store tag and pair 367STGP 01 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 368STGP 01 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 369STGP 01 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 370 371# Load/store register (unscaled immediate) 372&ldst_imm rt rn imm sz sign w p unpriv ext 373@ldst_imm .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=0 374@ldst_imm_pre .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=1 375@ldst_imm_post .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=1 w=1 376@ldst_imm_user .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=1 p=0 w=0 377 378STR_i sz:2 111 0 00 00 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 379LDR_i 00 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=0 380LDR_i 01 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=1 381LDR_i 10 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=2 382LDR_i 11 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=3 383LDR_i 00 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=0 384LDR_i 01 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=1 385LDR_i 10 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=2 386LDR_i 00 111 0 00 11 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=1 sz=0 387LDR_i 01 111 0 00 11 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=1 sz=1 388 389STR_i sz:2 111 0 00 00 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 390LDR_i 00 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=0 391LDR_i 01 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=1 392LDR_i 10 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=2 393LDR_i 11 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=3 394LDR_i 00 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=0 395LDR_i 01 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=1 396LDR_i 10 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=2 397LDR_i 00 111 0 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=1 sz=0 398LDR_i 01 111 0 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=1 sz=1 399 400STR_i sz:2 111 0 00 00 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=0 401LDR_i 00 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=0 402LDR_i 01 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=1 403LDR_i 10 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=2 404LDR_i 11 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=0 sz=3 405LDR_i 00 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=0 406LDR_i 01 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=1 407LDR_i 10 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=2 408LDR_i 00 111 0 00 11 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=1 sz=0 409LDR_i 01 111 0 00 11 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=1 sz=1 410 411STR_i sz:2 111 0 00 00 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 412LDR_i 00 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=0 413LDR_i 01 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=1 414LDR_i 10 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=2 415LDR_i 11 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=3 416LDR_i 00 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=0 417LDR_i 01 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=1 418LDR_i 10 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=2 419LDR_i 00 111 0 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=1 sz=0 420LDR_i 01 111 0 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=1 sz=1 421 422# PRFM : prefetch memory: a no-op for QEMU 423NOP 11 111 0 00 10 0 --------- 00 ----- ----- 424 425STR_v_i sz:2 111 1 00 00 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 426STR_v_i 00 111 1 00 10 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=4 427LDR_v_i sz:2 111 1 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 428LDR_v_i 00 111 1 00 11 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=4 429 430STR_v_i sz:2 111 1 00 00 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 431STR_v_i 00 111 1 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=4 432LDR_v_i sz:2 111 1 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 433LDR_v_i 00 111 1 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=4 434 435STR_v_i sz:2 111 1 00 00 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 436STR_v_i 00 111 1 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=4 437LDR_v_i sz:2 111 1 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 438LDR_v_i 00 111 1 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=4 439 440# Load/store with an unsigned 12 bit immediate, which is scaled by the 441# element size. The function gets the sz:imm and returns the scaled immediate. 442%uimm_scaled 10:12 sz:3 !function=uimm_scaled 443 444@ldst_uimm .. ... . .. .. ............ rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=0 imm=%uimm_scaled 445 446STR_i sz:2 111 0 01 00 ............ ..... ..... @ldst_uimm sign=0 ext=0 447LDR_i 00 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=0 448LDR_i 01 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=1 449LDR_i 10 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=2 450LDR_i 11 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=3 451LDR_i 00 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=0 452LDR_i 01 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=1 453LDR_i 10 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=2 454LDR_i 00 111 0 01 11 ............ ..... ..... @ldst_uimm sign=1 ext=1 sz=0 455LDR_i 01 111 0 01 11 ............ ..... ..... @ldst_uimm sign=1 ext=1 sz=1 456 457# PRFM 458NOP 11 111 0 01 10 ------------ ----- ----- 459 460STR_v_i sz:2 111 1 01 00 ............ ..... ..... @ldst_uimm sign=0 ext=0 461STR_v_i 00 111 1 01 10 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=4 462LDR_v_i sz:2 111 1 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=0 463LDR_v_i 00 111 1 01 11 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=4 464 465# Load/store with register offset 466&ldst rm rn rt sign ext sz opt s 467@ldst .. ... . .. .. . rm:5 opt:3 s:1 .. rn:5 rt:5 &ldst 468STR sz:2 111 0 00 00 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 469LDR 00 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=0 470LDR 01 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=1 471LDR 10 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=2 472LDR 11 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=3 473LDR 00 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=0 474LDR 01 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=1 475LDR 10 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=2 476LDR 00 111 0 00 11 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=1 sz=0 477LDR 01 111 0 00 11 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=1 sz=1 478 479# PRFM 480NOP 11 111 0 00 10 1 ----- -1- - 10 ----- ----- 481 482STR_v sz:2 111 1 00 00 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 483STR_v 00 111 1 00 10 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=4 484LDR_v sz:2 111 1 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 485LDR_v 00 111 1 00 11 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=4 486 487# Atomic memory operations 488&atomic rs rn rt a r sz 489@atomic sz:2 ... . .. a:1 r:1 . rs:5 . ... .. rn:5 rt:5 &atomic 490LDADD .. 111 0 00 . . 1 ..... 0000 00 ..... ..... @atomic 491LDCLR .. 111 0 00 . . 1 ..... 0001 00 ..... ..... @atomic 492LDEOR .. 111 0 00 . . 1 ..... 0010 00 ..... ..... @atomic 493LDSET .. 111 0 00 . . 1 ..... 0011 00 ..... ..... @atomic 494LDSMAX .. 111 0 00 . . 1 ..... 0100 00 ..... ..... @atomic 495LDSMIN .. 111 0 00 . . 1 ..... 0101 00 ..... ..... @atomic 496LDUMAX .. 111 0 00 . . 1 ..... 0110 00 ..... ..... @atomic 497LDUMIN .. 111 0 00 . . 1 ..... 0111 00 ..... ..... @atomic 498SWP .. 111 0 00 . . 1 ..... 1000 00 ..... ..... @atomic 499 500LDAPR sz:2 111 0 00 1 0 1 11111 1100 00 rn:5 rt:5 501 502# Load/store register (pointer authentication) 503 504# LDRA immediate is 10 bits signed and scaled, but the bits aren't all contiguous 505%ldra_imm 22:s1 12:9 !function=times_8 506 507LDRA 11 111 0 00 m:1 . 1 ......... w:1 1 rn:5 rt:5 imm=%ldra_imm 508 509&ldapr_stlr_i rn rt imm sz sign ext 510@ldapr_stlr_i .. ...... .. . imm:9 .. rn:5 rt:5 &ldapr_stlr_i 511STLR_i sz:2 011001 00 0 ......... 00 ..... ..... @ldapr_stlr_i sign=0 ext=0 512LDAPR_i sz:2 011001 01 0 ......... 00 ..... ..... @ldapr_stlr_i sign=0 ext=0 513LDAPR_i 00 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=0 514LDAPR_i 01 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=1 515LDAPR_i 10 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=2 516LDAPR_i 00 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=1 sz=0 517LDAPR_i 01 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=1 sz=1 518 519# Load/store multiple structures 520# The 4-bit opcode in [15:12] encodes repeat count and structure elements 521&ldst_mult rm rn rt sz q p rpt selem 522@ldst_mult . q:1 ...... p:1 . . rm:5 .... sz:2 rn:5 rt:5 &ldst_mult 523ST_mult 0 . 001100 . 0 0 ..... 0000 .. ..... ..... @ldst_mult rpt=1 selem=4 524ST_mult 0 . 001100 . 0 0 ..... 0010 .. ..... ..... @ldst_mult rpt=4 selem=1 525ST_mult 0 . 001100 . 0 0 ..... 0100 .. ..... ..... @ldst_mult rpt=1 selem=3 526ST_mult 0 . 001100 . 0 0 ..... 0110 .. ..... ..... @ldst_mult rpt=3 selem=1 527ST_mult 0 . 001100 . 0 0 ..... 0111 .. ..... ..... @ldst_mult rpt=1 selem=1 528ST_mult 0 . 001100 . 0 0 ..... 1000 .. ..... ..... @ldst_mult rpt=1 selem=2 529ST_mult 0 . 001100 . 0 0 ..... 1010 .. ..... ..... @ldst_mult rpt=2 selem=1 530 531LD_mult 0 . 001100 . 1 0 ..... 0000 .. ..... ..... @ldst_mult rpt=1 selem=4 532LD_mult 0 . 001100 . 1 0 ..... 0010 .. ..... ..... @ldst_mult rpt=4 selem=1 533LD_mult 0 . 001100 . 1 0 ..... 0100 .. ..... ..... @ldst_mult rpt=1 selem=3 534LD_mult 0 . 001100 . 1 0 ..... 0110 .. ..... ..... @ldst_mult rpt=3 selem=1 535LD_mult 0 . 001100 . 1 0 ..... 0111 .. ..... ..... @ldst_mult rpt=1 selem=1 536LD_mult 0 . 001100 . 1 0 ..... 1000 .. ..... ..... @ldst_mult rpt=1 selem=2 537LD_mult 0 . 001100 . 1 0 ..... 1010 .. ..... ..... @ldst_mult rpt=2 selem=1 538 539# Load/store single structure 540&ldst_single rm rn rt p selem index scale 541 542%ldst_single_selem 13:1 21:1 !function=plus_1 543 544%ldst_single_index_b 30:1 10:3 545%ldst_single_index_h 30:1 11:2 546%ldst_single_index_s 30:1 12:1 547 548@ldst_single_b .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \ 549 &ldst_single scale=0 selem=%ldst_single_selem \ 550 index=%ldst_single_index_b 551@ldst_single_h .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \ 552 &ldst_single scale=1 selem=%ldst_single_selem \ 553 index=%ldst_single_index_h 554@ldst_single_s .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \ 555 &ldst_single scale=2 selem=%ldst_single_selem \ 556 index=%ldst_single_index_s 557@ldst_single_d . index:1 ...... p:1 .. rm:5 ...... rn:5 rt:5 \ 558 &ldst_single scale=3 selem=%ldst_single_selem 559 560ST_single 0 . 001101 . 0 . ..... 00 . ... ..... ..... @ldst_single_b 561ST_single 0 . 001101 . 0 . ..... 01 . ..0 ..... ..... @ldst_single_h 562ST_single 0 . 001101 . 0 . ..... 10 . .00 ..... ..... @ldst_single_s 563ST_single 0 . 001101 . 0 . ..... 10 . 001 ..... ..... @ldst_single_d 564 565LD_single 0 . 001101 . 1 . ..... 00 . ... ..... ..... @ldst_single_b 566LD_single 0 . 001101 . 1 . ..... 01 . ..0 ..... ..... @ldst_single_h 567LD_single 0 . 001101 . 1 . ..... 10 . .00 ..... ..... @ldst_single_s 568LD_single 0 . 001101 . 1 . ..... 10 . 001 ..... ..... @ldst_single_d 569 570# Replicating load case 571LD_single_repl 0 q:1 001101 p:1 1 . rm:5 11 . 0 scale:2 rn:5 rt:5 selem=%ldst_single_selem 572 573%tag_offset 12:s9 !function=scale_by_log2_tag_granule 574&ldst_tag rn rt imm p w 575@ldst_tag ........ .. . ......... .. rn:5 rt:5 &ldst_tag imm=%tag_offset 576@ldst_tag_mult ........ .. . 000000000 .. rn:5 rt:5 &ldst_tag imm=0 577 578STZGM 11011001 00 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0 579STG 11011001 00 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 580STG 11011001 00 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 581STG 11011001 00 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 582 583LDG 11011001 01 1 ......... 00 ..... ..... @ldst_tag p=0 w=0 584STZG 11011001 01 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 585STZG 11011001 01 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 586STZG 11011001 01 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 587 588STGM 11011001 10 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0 589ST2G 11011001 10 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 590ST2G 11011001 10 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 591ST2G 11011001 10 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 592 593LDGM 11011001 11 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0 594STZ2G 11011001 11 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 595STZ2G 11011001 11 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 596STZ2G 11011001 11 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 597 598# Memory operations (memset, memcpy, memmove) 599# Each of these comes in a set of three, eg SETP (prologue), SETM (main), 600# SETE (epilogue), and each of those has different flavours to 601# indicate whether memory accesses should be unpriv or non-temporal. 602# We don't distinguish temporal and non-temporal accesses, but we 603# do need to report it in syndrome register values. 604 605# Memset 606&set rs rn rd unpriv nontemp 607# op2 bit 1 is nontemporal bit 608@set .. ......... rs:5 .. nontemp:1 unpriv:1 .. rn:5 rd:5 &set 609 610SETP 00 011001110 ..... 00 . . 01 ..... ..... @set 611SETM 00 011001110 ..... 01 . . 01 ..... ..... @set 612SETE 00 011001110 ..... 10 . . 01 ..... ..... @set 613 614# Like SET, but also setting MTE tags 615SETGP 00 011101110 ..... 00 . . 01 ..... ..... @set 616SETGM 00 011101110 ..... 01 . . 01 ..... ..... @set 617SETGE 00 011101110 ..... 10 . . 01 ..... ..... @set 618 619# Memmove/Memcopy: the CPY insns allow overlapping src/dest and 620# copy in the correct direction; the CPYF insns always copy forwards. 621# 622# options has the nontemporal and unpriv bits for src and dest 623&cpy rs rn rd options 624@cpy .. ... . ..... rs:5 options:4 .. rn:5 rd:5 &cpy 625 626CPYFP 00 011 0 01000 ..... .... 01 ..... ..... @cpy 627CPYFM 00 011 0 01010 ..... .... 01 ..... ..... @cpy 628CPYFE 00 011 0 01100 ..... .... 01 ..... ..... @cpy 629CPYP 00 011 1 01000 ..... .... 01 ..... ..... @cpy 630CPYM 00 011 1 01010 ..... .... 01 ..... ..... @cpy 631CPYE 00 011 1 01100 ..... .... 01 ..... ..... @cpy 632 633### Cryptographic AES 634 635AESE 01001110 00 10100 00100 10 ..... ..... @r2r_q1e0 636AESD 01001110 00 10100 00101 10 ..... ..... @r2r_q1e0 637AESMC 01001110 00 10100 00110 10 ..... ..... @rr_q1e0 638AESIMC 01001110 00 10100 00111 10 ..... ..... @rr_q1e0 639 640### Cryptographic three-register SHA 641 642SHA1C 0101 1110 000 ..... 000000 ..... ..... @rrr_q1e0 643SHA1P 0101 1110 000 ..... 000100 ..... ..... @rrr_q1e0 644SHA1M 0101 1110 000 ..... 001000 ..... ..... @rrr_q1e0 645SHA1SU0 0101 1110 000 ..... 001100 ..... ..... @rrr_q1e0 646SHA256H 0101 1110 000 ..... 010000 ..... ..... @rrr_q1e0 647SHA256H2 0101 1110 000 ..... 010100 ..... ..... @rrr_q1e0 648SHA256SU1 0101 1110 000 ..... 011000 ..... ..... @rrr_q1e0 649 650### Cryptographic two-register SHA 651 652SHA1H 0101 1110 0010 1000 0000 10 ..... ..... @rr_q1e0 653SHA1SU1 0101 1110 0010 1000 0001 10 ..... ..... @rr_q1e0 654SHA256SU0 0101 1110 0010 1000 0010 10 ..... ..... @rr_q1e0 655 656### Cryptographic three-register SHA512 657 658SHA512H 1100 1110 011 ..... 100000 ..... ..... @rrr_q1e0 659SHA512H2 1100 1110 011 ..... 100001 ..... ..... @rrr_q1e0 660SHA512SU1 1100 1110 011 ..... 100010 ..... ..... @rrr_q1e0 661RAX1 1100 1110 011 ..... 100011 ..... ..... @rrr_q1e3 662SM3PARTW1 1100 1110 011 ..... 110000 ..... ..... @rrr_q1e0 663SM3PARTW2 1100 1110 011 ..... 110001 ..... ..... @rrr_q1e0 664SM4EKEY 1100 1110 011 ..... 110010 ..... ..... @rrr_q1e0 665 666### Cryptographic two-register SHA512 667 668SHA512SU0 1100 1110 110 00000 100000 ..... ..... @rr_q1e0 669SM4E 1100 1110 110 00000 100001 ..... ..... @r2r_q1e0 670 671### Cryptographic four-register 672 673EOR3 1100 1110 000 ..... 0 ..... ..... ..... @rrrr_q1e3 674BCAX 1100 1110 001 ..... 0 ..... ..... ..... @rrrr_q1e3 675SM3SS1 1100 1110 010 ..... 0 ..... ..... ..... @rrrr_q1e3 676 677### Cryptographic three-register, imm2 678 679&crypto3i rd rn rm imm 680@crypto3i ........ ... rm:5 .. imm:2 .. rn:5 rd:5 &crypto3i 681 682SM3TT1A 11001110 010 ..... 10 .. 00 ..... ..... @crypto3i 683SM3TT1B 11001110 010 ..... 10 .. 01 ..... ..... @crypto3i 684SM3TT2A 11001110 010 ..... 10 .. 10 ..... ..... @crypto3i 685SM3TT2B 11001110 010 ..... 10 .. 11 ..... ..... @crypto3i 686 687### Cryptographic XAR 688 689XAR 1100 1110 100 rm:5 imm:6 rn:5 rd:5 690 691### Advanced SIMD scalar copy 692 693DUP_element_s 0101 1110 000 imm:5 0 0000 1 rn:5 rd:5 694 695### Advanced SIMD copy 696 697DUP_element_v 0 q:1 00 1110 000 imm:5 0 0000 1 rn:5 rd:5 698DUP_general 0 q:1 00 1110 000 imm:5 0 0001 1 rn:5 rd:5 699INS_general 0 1 00 1110 000 imm:5 0 0011 1 rn:5 rd:5 700SMOV 0 q:1 00 1110 000 imm:5 0 0101 1 rn:5 rd:5 701UMOV 0 q:1 00 1110 000 imm:5 0 0111 1 rn:5 rd:5 702INS_element 0 1 10 1110 000 di:5 0 si:4 1 rn:5 rd:5 703 704### Advanced SIMD scalar three same 705 706FADD_s 0001 1110 ..1 ..... 0010 10 ..... ..... @rrr_hsd 707FSUB_s 0001 1110 ..1 ..... 0011 10 ..... ..... @rrr_hsd 708FDIV_s 0001 1110 ..1 ..... 0001 10 ..... ..... @rrr_hsd 709FMUL_s 0001 1110 ..1 ..... 0000 10 ..... ..... @rrr_hsd 710FNMUL_s 0001 1110 ..1 ..... 1000 10 ..... ..... @rrr_hsd 711 712FMAX_s 0001 1110 ..1 ..... 0100 10 ..... ..... @rrr_hsd 713FMIN_s 0001 1110 ..1 ..... 0101 10 ..... ..... @rrr_hsd 714FMAXNM_s 0001 1110 ..1 ..... 0110 10 ..... ..... @rrr_hsd 715FMINNM_s 0001 1110 ..1 ..... 0111 10 ..... ..... @rrr_hsd 716 717FMULX_s 0101 1110 010 ..... 00011 1 ..... ..... @rrr_h 718FMULX_s 0101 1110 0.1 ..... 11011 1 ..... ..... @rrr_sd 719 720FCMEQ_s 0101 1110 010 ..... 00100 1 ..... ..... @rrr_h 721FCMEQ_s 0101 1110 0.1 ..... 11100 1 ..... ..... @rrr_sd 722 723FCMGE_s 0111 1110 010 ..... 00100 1 ..... ..... @rrr_h 724FCMGE_s 0111 1110 0.1 ..... 11100 1 ..... ..... @rrr_sd 725 726FCMGT_s 0111 1110 110 ..... 00100 1 ..... ..... @rrr_h 727FCMGT_s 0111 1110 1.1 ..... 11100 1 ..... ..... @rrr_sd 728 729FACGE_s 0111 1110 010 ..... 00101 1 ..... ..... @rrr_h 730FACGE_s 0111 1110 0.1 ..... 11101 1 ..... ..... @rrr_sd 731 732FACGT_s 0111 1110 110 ..... 00101 1 ..... ..... @rrr_h 733FACGT_s 0111 1110 1.1 ..... 11101 1 ..... ..... @rrr_sd 734 735FABD_s 0111 1110 110 ..... 00010 1 ..... ..... @rrr_h 736FABD_s 0111 1110 1.1 ..... 11010 1 ..... ..... @rrr_sd 737 738FRECPS_s 0101 1110 010 ..... 00111 1 ..... ..... @rrr_h 739FRECPS_s 0101 1110 0.1 ..... 11111 1 ..... ..... @rrr_sd 740 741FRSQRTS_s 0101 1110 110 ..... 00111 1 ..... ..... @rrr_h 742FRSQRTS_s 0101 1110 1.1 ..... 11111 1 ..... ..... @rrr_sd 743 744### Advanced SIMD scalar pairwise 745 746FADDP_s 0101 1110 0011 0000 1101 10 ..... ..... @rr_h 747FADDP_s 0111 1110 0.11 0000 1101 10 ..... ..... @rr_sd 748 749### Advanced SIMD three same 750 751FADD_v 0.00 1110 010 ..... 00010 1 ..... ..... @qrrr_h 752FADD_v 0.00 1110 0.1 ..... 11010 1 ..... ..... @qrrr_sd 753 754FSUB_v 0.00 1110 110 ..... 00010 1 ..... ..... @qrrr_h 755FSUB_v 0.00 1110 1.1 ..... 11010 1 ..... ..... @qrrr_sd 756 757FDIV_v 0.10 1110 010 ..... 00111 1 ..... ..... @qrrr_h 758FDIV_v 0.10 1110 0.1 ..... 11111 1 ..... ..... @qrrr_sd 759 760FMUL_v 0.10 1110 010 ..... 00011 1 ..... ..... @qrrr_h 761FMUL_v 0.10 1110 0.1 ..... 11011 1 ..... ..... @qrrr_sd 762 763FMAX_v 0.00 1110 010 ..... 00110 1 ..... ..... @qrrr_h 764FMAX_v 0.00 1110 0.1 ..... 11110 1 ..... ..... @qrrr_sd 765 766FMIN_v 0.00 1110 110 ..... 00110 1 ..... ..... @qrrr_h 767FMIN_v 0.00 1110 1.1 ..... 11110 1 ..... ..... @qrrr_sd 768 769FMAXNM_v 0.00 1110 010 ..... 00000 1 ..... ..... @qrrr_h 770FMAXNM_v 0.00 1110 0.1 ..... 11000 1 ..... ..... @qrrr_sd 771 772FMINNM_v 0.00 1110 110 ..... 00000 1 ..... ..... @qrrr_h 773FMINNM_v 0.00 1110 1.1 ..... 11000 1 ..... ..... @qrrr_sd 774 775FMULX_v 0.00 1110 010 ..... 00011 1 ..... ..... @qrrr_h 776FMULX_v 0.00 1110 0.1 ..... 11011 1 ..... ..... @qrrr_sd 777 778FMLA_v 0.00 1110 010 ..... 00001 1 ..... ..... @qrrr_h 779FMLA_v 0.00 1110 0.1 ..... 11001 1 ..... ..... @qrrr_sd 780 781FMLS_v 0.00 1110 110 ..... 00001 1 ..... ..... @qrrr_h 782FMLS_v 0.00 1110 1.1 ..... 11001 1 ..... ..... @qrrr_sd 783 784FCMEQ_v 0.00 1110 010 ..... 00100 1 ..... ..... @qrrr_h 785FCMEQ_v 0.00 1110 0.1 ..... 11100 1 ..... ..... @qrrr_sd 786 787FCMGE_v 0.10 1110 010 ..... 00100 1 ..... ..... @qrrr_h 788FCMGE_v 0.10 1110 0.1 ..... 11100 1 ..... ..... @qrrr_sd 789 790FCMGT_v 0.10 1110 110 ..... 00100 1 ..... ..... @qrrr_h 791FCMGT_v 0.10 1110 1.1 ..... 11100 1 ..... ..... @qrrr_sd 792 793FACGE_v 0.10 1110 010 ..... 00101 1 ..... ..... @qrrr_h 794FACGE_v 0.10 1110 0.1 ..... 11101 1 ..... ..... @qrrr_sd 795 796FACGT_v 0.10 1110 110 ..... 00101 1 ..... ..... @qrrr_h 797FACGT_v 0.10 1110 1.1 ..... 11101 1 ..... ..... @qrrr_sd 798 799FABD_v 0.10 1110 110 ..... 00010 1 ..... ..... @qrrr_h 800FABD_v 0.10 1110 1.1 ..... 11010 1 ..... ..... @qrrr_sd 801 802FRECPS_v 0.00 1110 010 ..... 00111 1 ..... ..... @qrrr_h 803FRECPS_v 0.00 1110 0.1 ..... 11111 1 ..... ..... @qrrr_sd 804 805FRSQRTS_v 0.00 1110 110 ..... 00111 1 ..... ..... @qrrr_h 806FRSQRTS_v 0.00 1110 1.1 ..... 11111 1 ..... ..... @qrrr_sd 807 808FADDP_v 0.10 1110 010 ..... 00010 1 ..... ..... @qrrr_h 809FADDP_v 0.10 1110 0.1 ..... 11010 1 ..... ..... @qrrr_sd 810 811### Advanced SIMD scalar x indexed element 812 813FMUL_si 0101 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h 814FMUL_si 0101 1111 10 . ..... 1001 . 0 ..... ..... @rrx_s 815FMUL_si 0101 1111 11 0 ..... 1001 . 0 ..... ..... @rrx_d 816 817FMLA_si 0101 1111 00 .. .... 0001 . 0 ..... ..... @rrx_h 818FMLA_si 0101 1111 10 .. .... 0001 . 0 ..... ..... @rrx_s 819FMLA_si 0101 1111 11 0. .... 0001 . 0 ..... ..... @rrx_d 820 821FMLS_si 0101 1111 00 .. .... 0101 . 0 ..... ..... @rrx_h 822FMLS_si 0101 1111 10 .. .... 0101 . 0 ..... ..... @rrx_s 823FMLS_si 0101 1111 11 0. .... 0101 . 0 ..... ..... @rrx_d 824 825FMULX_si 0111 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h 826FMULX_si 0111 1111 10 . ..... 1001 . 0 ..... ..... @rrx_s 827FMULX_si 0111 1111 11 0 ..... 1001 . 0 ..... ..... @rrx_d 828 829### Advanced SIMD vector x indexed element 830 831FMUL_vi 0.00 1111 00 .. .... 1001 . 0 ..... ..... @qrrx_h 832FMUL_vi 0.00 1111 10 . ..... 1001 . 0 ..... ..... @qrrx_s 833FMUL_vi 0.00 1111 11 0 ..... 1001 . 0 ..... ..... @qrrx_d 834 835FMLA_vi 0.00 1111 00 .. .... 0001 . 0 ..... ..... @qrrx_h 836FMLA_vi 0.00 1111 10 . ..... 0001 . 0 ..... ..... @qrrx_s 837FMLA_vi 0.00 1111 11 0 ..... 0001 . 0 ..... ..... @qrrx_d 838 839FMLS_vi 0.00 1111 00 .. .... 0101 . 0 ..... ..... @qrrx_h 840FMLS_vi 0.00 1111 10 . ..... 0101 . 0 ..... ..... @qrrx_s 841FMLS_vi 0.00 1111 11 0 ..... 0101 . 0 ..... ..... @qrrx_d 842 843FMULX_vi 0.10 1111 00 .. .... 1001 . 0 ..... ..... @qrrx_h 844FMULX_vi 0.10 1111 10 . ..... 1001 . 0 ..... ..... @qrrx_s 845FMULX_vi 0.10 1111 11 0 ..... 1001 . 0 ..... ..... @qrrx_d 846