1# AArch64 A64 allowed instruction decoding 2# 3# Copyright (c) 2023 Linaro, Ltd 4# 5# This library is free software; you can redistribute it and/or 6# modify it under the terms of the GNU Lesser General Public 7# License as published by the Free Software Foundation; either 8# version 2.1 of the License, or (at your option) any later version. 9# 10# This library is distributed in the hope that it will be useful, 11# but WITHOUT ANY WARRANTY; without even the implied warranty of 12# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13# Lesser General Public License for more details. 14# 15# You should have received a copy of the GNU Lesser General Public 16# License along with this library; if not, see <http://www.gnu.org/licenses/>. 17 18# 19# This file is processed by scripts/decodetree.py 20# 21 22%rd 0:5 23%esz_sd 22:1 !function=plus_2 24%esz_hsd 22:2 !function=xor_2 25%hl 11:1 21:1 26%hlm 11:1 20:2 27 28&r rn 29&ri rd imm 30&rri_sf rd rn imm sf 31&i imm 32&rr_e rd rn esz 33&rrr_e rd rn rm esz 34&rrx_e rd rn rm idx esz 35&rrrr_e rd rn rm ra esz 36&qrr_e q rd rn esz 37&qrrr_e q rd rn rm esz 38&qrrx_e q rd rn rm idx esz 39&qrrrr_e q rd rn rm ra esz 40 41@rr_h ........ ... ..... ...... rn:5 rd:5 &rr_e esz=1 42@rr_d ........ ... ..... ...... rn:5 rd:5 &rr_e esz=3 43@rr_sd ........ ... ..... ...... rn:5 rd:5 &rr_e esz=%esz_sd 44 45@rrr_h ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=1 46@rrr_d ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=3 47@rrr_sd ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=%esz_sd 48@rrr_hsd ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=%esz_hsd 49@rrr_e ........ esz:2 . rm:5 ...... rn:5 rd:5 &rrr_e 50@r2r_e ........ esz:2 . ..... ...... rm:5 rd:5 &rrr_e rn=%rd 51 52@rrx_h ........ .. .. rm:4 .... . . rn:5 rd:5 &rrx_e esz=1 idx=%hlm 53@rrx_s ........ .. . rm:5 .... . . rn:5 rd:5 &rrx_e esz=2 idx=%hl 54@rrx_d ........ .. . rm:5 .... idx:1 . rn:5 rd:5 &rrx_e esz=3 55 56@rr_q1e0 ........ ........ ...... rn:5 rd:5 &qrr_e q=1 esz=0 57@r2r_q1e0 ........ ........ ...... rm:5 rd:5 &qrrr_e rn=%rd q=1 esz=0 58@rrr_q1e0 ........ ... rm:5 ...... rn:5 rd:5 &qrrr_e q=1 esz=0 59@rrr_q1e3 ........ ... rm:5 ...... rn:5 rd:5 &qrrr_e q=1 esz=3 60@rrrr_q1e3 ........ ... rm:5 . ra:5 rn:5 rd:5 &qrrrr_e q=1 esz=3 61 62@qrrr_b . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=0 63@qrrr_h . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=1 64@qrrr_sd . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=%esz_sd 65@qrrr_e . q:1 ...... esz:2 . rm:5 ...... rn:5 rd:5 &qrrr_e 66@qr2r_e . q:1 ...... esz:2 . ..... ...... rm:5 rd:5 &qrrr_e rn=%rd 67 68@qrrx_h . q:1 .. .... .. .. rm:4 .... . . rn:5 rd:5 \ 69 &qrrx_e esz=1 idx=%hlm 70@qrrx_s . q:1 .. .... .. . rm:5 .... . . rn:5 rd:5 \ 71 &qrrx_e esz=2 idx=%hl 72@qrrx_d . q:1 .. .... .. . rm:5 .... idx:1 . rn:5 rd:5 \ 73 &qrrx_e esz=3 74 75### Data Processing - Immediate 76 77# PC-rel addressing 78 79%imm_pcrel 5:s19 29:2 80@pcrel . .. ..... ................... rd:5 &ri imm=%imm_pcrel 81 82ADR 0 .. 10000 ................... ..... @pcrel 83ADRP 1 .. 10000 ................... ..... @pcrel 84 85# Add/subtract (immediate) 86 87%imm12_sh12 10:12 !function=shl_12 88@addsub_imm sf:1 .. ...... . imm:12 rn:5 rd:5 89@addsub_imm12 sf:1 .. ...... . ............ rn:5 rd:5 imm=%imm12_sh12 90 91ADD_i . 00 100010 0 ............ ..... ..... @addsub_imm 92ADD_i . 00 100010 1 ............ ..... ..... @addsub_imm12 93ADDS_i . 01 100010 0 ............ ..... ..... @addsub_imm 94ADDS_i . 01 100010 1 ............ ..... ..... @addsub_imm12 95 96SUB_i . 10 100010 0 ............ ..... ..... @addsub_imm 97SUB_i . 10 100010 1 ............ ..... ..... @addsub_imm12 98SUBS_i . 11 100010 0 ............ ..... ..... @addsub_imm 99SUBS_i . 11 100010 1 ............ ..... ..... @addsub_imm12 100 101# Add/subtract (immediate with tags) 102 103&rri_tag rd rn uimm6 uimm4 104@addsub_imm_tag . .. ...... . uimm6:6 .. uimm4:4 rn:5 rd:5 &rri_tag 105 106ADDG_i 1 00 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag 107SUBG_i 1 10 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag 108 109# Logical (immediate) 110 111&rri_log rd rn sf dbm 112@logic_imm_64 1 .. ...... dbm:13 rn:5 rd:5 &rri_log sf=1 113@logic_imm_32 0 .. ...... 0 dbm:12 rn:5 rd:5 &rri_log sf=0 114 115AND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_64 116AND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_32 117ORR_i . 01 100100 . ...... ...... ..... ..... @logic_imm_64 118ORR_i . 01 100100 . ...... ...... ..... ..... @logic_imm_32 119EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_64 120EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_32 121ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_64 122ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_32 123 124# Move wide (immediate) 125 126&movw rd sf imm hw 127@movw_64 1 .. ...... hw:2 imm:16 rd:5 &movw sf=1 128@movw_32 0 .. ...... 0 hw:1 imm:16 rd:5 &movw sf=0 129 130MOVN . 00 100101 .. ................ ..... @movw_64 131MOVN . 00 100101 .. ................ ..... @movw_32 132MOVZ . 10 100101 .. ................ ..... @movw_64 133MOVZ . 10 100101 .. ................ ..... @movw_32 134MOVK . 11 100101 .. ................ ..... @movw_64 135MOVK . 11 100101 .. ................ ..... @movw_32 136 137# Bitfield 138 139&bitfield rd rn sf immr imms 140@bitfield_64 1 .. ...... 1 immr:6 imms:6 rn:5 rd:5 &bitfield sf=1 141@bitfield_32 0 .. ...... 0 0 immr:5 0 imms:5 rn:5 rd:5 &bitfield sf=0 142 143SBFM . 00 100110 . ...... ...... ..... ..... @bitfield_64 144SBFM . 00 100110 . ...... ...... ..... ..... @bitfield_32 145BFM . 01 100110 . ...... ...... ..... ..... @bitfield_64 146BFM . 01 100110 . ...... ...... ..... ..... @bitfield_32 147UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_64 148UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_32 149 150# Extract 151 152&extract rd rn rm imm sf 153 154EXTR 1 00 100111 1 0 rm:5 imm:6 rn:5 rd:5 &extract sf=1 155EXTR 0 00 100111 0 0 rm:5 0 imm:5 rn:5 rd:5 &extract sf=0 156 157# Branches 158 159%imm26 0:s26 !function=times_4 160@branch . ..... .......................... &i imm=%imm26 161 162B 0 00101 .......................... @branch 163BL 1 00101 .......................... @branch 164 165%imm19 5:s19 !function=times_4 166&cbz rt imm sf nz 167 168CBZ sf:1 011010 nz:1 ................... rt:5 &cbz imm=%imm19 169 170%imm14 5:s14 !function=times_4 171%imm31_19 31:1 19:5 172&tbz rt imm nz bitpos 173 174TBZ . 011011 nz:1 ..... .............. rt:5 &tbz imm=%imm14 bitpos=%imm31_19 175 176# B.cond and BC.cond 177B_cond 0101010 0 ................... c:1 cond:4 imm=%imm19 178 179BR 1101011 0000 11111 000000 rn:5 00000 &r 180BLR 1101011 0001 11111 000000 rn:5 00000 &r 181RET 1101011 0010 11111 000000 rn:5 00000 &r 182 183&braz rn m 184BRAZ 1101011 0000 11111 00001 m:1 rn:5 11111 &braz # BRAAZ, BRABZ 185BLRAZ 1101011 0001 11111 00001 m:1 rn:5 11111 &braz # BLRAAZ, BLRABZ 186 187&reta m 188RETA 1101011 0010 11111 00001 m:1 11111 11111 &reta # RETAA, RETAB 189 190&bra rn rm m 191BRA 1101011 1000 11111 00001 m:1 rn:5 rm:5 &bra # BRAA, BRAB 192BLRA 1101011 1001 11111 00001 m:1 rn:5 rm:5 &bra # BLRAA, BLRAB 193 194ERET 1101011 0100 11111 000000 11111 00000 195ERETA 1101011 0100 11111 00001 m:1 11111 11111 &reta # ERETAA, ERETAB 196 197# We don't need to decode DRPS because it always UNDEFs except when 198# the processor is in halting debug state (which we don't implement). 199# The pattern is listed here as documentation. 200# DRPS 1101011 0101 11111 000000 11111 00000 201 202# Hint instruction group 203{ 204 [ 205 YIELD 1101 0101 0000 0011 0010 0000 001 11111 206 WFE 1101 0101 0000 0011 0010 0000 010 11111 207 WFI 1101 0101 0000 0011 0010 0000 011 11111 208 # We implement WFE to never block, so our SEV/SEVL are NOPs 209 # SEV 1101 0101 0000 0011 0010 0000 100 11111 210 # SEVL 1101 0101 0000 0011 0010 0000 101 11111 211 # Our DGL is a NOP because we don't merge memory accesses anyway. 212 # DGL 1101 0101 0000 0011 0010 0000 110 11111 213 XPACLRI 1101 0101 0000 0011 0010 0000 111 11111 214 PACIA1716 1101 0101 0000 0011 0010 0001 000 11111 215 PACIB1716 1101 0101 0000 0011 0010 0001 010 11111 216 AUTIA1716 1101 0101 0000 0011 0010 0001 100 11111 217 AUTIB1716 1101 0101 0000 0011 0010 0001 110 11111 218 ESB 1101 0101 0000 0011 0010 0010 000 11111 219 PACIAZ 1101 0101 0000 0011 0010 0011 000 11111 220 PACIASP 1101 0101 0000 0011 0010 0011 001 11111 221 PACIBZ 1101 0101 0000 0011 0010 0011 010 11111 222 PACIBSP 1101 0101 0000 0011 0010 0011 011 11111 223 AUTIAZ 1101 0101 0000 0011 0010 0011 100 11111 224 AUTIASP 1101 0101 0000 0011 0010 0011 101 11111 225 AUTIBZ 1101 0101 0000 0011 0010 0011 110 11111 226 AUTIBSP 1101 0101 0000 0011 0010 0011 111 11111 227 ] 228 # The canonical NOP has CRm == op2 == 0, but all of the space 229 # that isn't specifically allocated to an instruction must NOP 230 NOP 1101 0101 0000 0011 0010 ---- --- 11111 231} 232 233# System instructions with register argument 234WFET 1101 0101 0000 0011 0001 0000 000 rd:5 235WFIT 1101 0101 0000 0011 0001 0000 001 rd:5 236 237# Barriers 238 239CLREX 1101 0101 0000 0011 0011 ---- 010 11111 240DSB_DMB 1101 0101 0000 0011 0011 domain:2 types:2 10- 11111 241ISB 1101 0101 0000 0011 0011 ---- 110 11111 242SB 1101 0101 0000 0011 0011 0000 111 11111 243 244# PSTATE 245 246CFINV 1101 0101 0000 0 000 0100 0000 000 11111 247XAFLAG 1101 0101 0000 0 000 0100 0000 001 11111 248AXFLAG 1101 0101 0000 0 000 0100 0000 010 11111 249 250# These are architecturally all "MSR (immediate)"; we decode the destination 251# register too because there is no commonality in our implementation. 252@msr_i .... .... .... . ... .... imm:4 ... ..... 253MSR_i_UAO 1101 0101 0000 0 000 0100 .... 011 11111 @msr_i 254MSR_i_PAN 1101 0101 0000 0 000 0100 .... 100 11111 @msr_i 255MSR_i_SPSEL 1101 0101 0000 0 000 0100 .... 101 11111 @msr_i 256MSR_i_SBSS 1101 0101 0000 0 011 0100 .... 001 11111 @msr_i 257MSR_i_DIT 1101 0101 0000 0 011 0100 .... 010 11111 @msr_i 258MSR_i_TCO 1101 0101 0000 0 011 0100 .... 100 11111 @msr_i 259MSR_i_DAIFSET 1101 0101 0000 0 011 0100 .... 110 11111 @msr_i 260MSR_i_DAIFCLEAR 1101 0101 0000 0 011 0100 .... 111 11111 @msr_i 261MSR_i_ALLINT 1101 0101 0000 0 001 0100 000 imm:1 000 11111 262MSR_i_SVCR 1101 0101 0000 0 011 0100 0 mask:2 imm:1 011 11111 263 264# MRS, MSR (register), SYS, SYSL. These are all essentially the 265# same instruction as far as QEMU is concerned. 266# NB: op0 is bits [20:19], but op0=0b00 is other insns, so we have 267# to hand-decode it. 268SYS 1101 0101 00 l:1 01 op1:3 crn:4 crm:4 op2:3 rt:5 op0=1 269SYS 1101 0101 00 l:1 10 op1:3 crn:4 crm:4 op2:3 rt:5 op0=2 270SYS 1101 0101 00 l:1 11 op1:3 crn:4 crm:4 op2:3 rt:5 op0=3 271 272# Exception generation 273 274@i16 .... .... ... imm:16 ... .. &i 275SVC 1101 0100 000 ................ 000 01 @i16 276HVC 1101 0100 000 ................ 000 10 @i16 277SMC 1101 0100 000 ................ 000 11 @i16 278BRK 1101 0100 001 ................ 000 00 @i16 279HLT 1101 0100 010 ................ 000 00 @i16 280# These insns always UNDEF unless in halting debug state, which 281# we don't implement. So we don't need to decode them. The patterns 282# are listed here as documentation. 283# DCPS1 1101 0100 101 ................ 000 01 @i16 284# DCPS2 1101 0100 101 ................ 000 10 @i16 285# DCPS3 1101 0100 101 ................ 000 11 @i16 286 287# Loads and stores 288 289&stxr rn rt rt2 rs sz lasr 290&stlr rn rt sz lasr 291@stxr sz:2 ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr 292@stlr sz:2 ...... ... ..... lasr:1 ..... rn:5 rt:5 &stlr 293%imm1_30_p2 30:1 !function=plus_2 294@stxp .. ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr sz=%imm1_30_p2 295STXR .. 001000 000 ..... . ..... ..... ..... @stxr # inc STLXR 296LDXR .. 001000 010 ..... . ..... ..... ..... @stxr # inc LDAXR 297STLR .. 001000 100 11111 . 11111 ..... ..... @stlr # inc STLLR 298LDAR .. 001000 110 11111 . 11111 ..... ..... @stlr # inc LDLAR 299 300STXP 1 . 001000 001 ..... . ..... ..... ..... @stxp # inc STLXP 301LDXP 1 . 001000 011 ..... . ..... ..... ..... @stxp # inc LDAXP 302 303# CASP, CASPA, CASPAL, CASPL (we don't decode the bits that determine 304# acquire/release semantics because QEMU's cmpxchg always has those) 305CASP 0 . 001000 0 - 1 rs:5 - 11111 rn:5 rt:5 sz=%imm1_30_p2 306# CAS, CASA, CASAL, CASL 307CAS sz:2 001000 1 - 1 rs:5 - 11111 rn:5 rt:5 308 309&ldlit rt imm sz sign 310@ldlit .. ... . .. ................... rt:5 &ldlit imm=%imm19 311 312LD_lit 00 011 0 00 ................... ..... @ldlit sz=2 sign=0 313LD_lit 01 011 0 00 ................... ..... @ldlit sz=3 sign=0 314LD_lit 10 011 0 00 ................... ..... @ldlit sz=2 sign=1 315LD_lit_v 00 011 1 00 ................... ..... @ldlit sz=2 sign=0 316LD_lit_v 01 011 1 00 ................... ..... @ldlit sz=3 sign=0 317LD_lit_v 10 011 1 00 ................... ..... @ldlit sz=4 sign=0 318 319# PRFM 320NOP 11 011 0 00 ------------------- ----- 321 322&ldstpair rt2 rt rn imm sz sign w p 323@ldstpair .. ... . ... . imm:s7 rt2:5 rn:5 rt:5 &ldstpair 324 325# STNP, LDNP: Signed offset, non-temporal hint. We don't emulate caches 326# so we ignore hints about data access patterns, and handle these like 327# plain signed offset. 328STP 00 101 0 000 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 329LDP 00 101 0 000 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 330STP 10 101 0 000 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 331LDP 10 101 0 000 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 332STP_v 00 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 333LDP_v 00 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 334STP_v 01 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 335LDP_v 01 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 336STP_v 10 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 337LDP_v 10 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 338 339# STP and LDP: post-indexed 340STP 00 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 341LDP 00 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 342LDP 01 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=1 w=1 343STP 10 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 344LDP 10 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 345STP_v 00 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 346LDP_v 00 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 347STP_v 01 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 348LDP_v 01 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 349STP_v 10 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=1 w=1 350LDP_v 10 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=1 w=1 351 352# STP and LDP: offset 353STP 00 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 354LDP 00 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 355LDP 01 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=0 w=0 356STP 10 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 357LDP 10 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 358STP_v 00 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 359LDP_v 00 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 360STP_v 01 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 361LDP_v 01 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 362STP_v 10 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 363LDP_v 10 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 364 365# STP and LDP: pre-indexed 366STP 00 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 367LDP 00 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 368LDP 01 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=0 w=1 369STP 10 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 370LDP 10 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 371STP_v 00 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 372LDP_v 00 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 373STP_v 01 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 374LDP_v 01 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 375STP_v 10 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=1 376LDP_v 10 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=1 377 378# STGP: store tag and pair 379STGP 01 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 380STGP 01 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 381STGP 01 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 382 383# Load/store register (unscaled immediate) 384&ldst_imm rt rn imm sz sign w p unpriv ext 385@ldst_imm .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=0 386@ldst_imm_pre .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=1 387@ldst_imm_post .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=1 w=1 388@ldst_imm_user .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=1 p=0 w=0 389 390STR_i sz:2 111 0 00 00 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 391LDR_i 00 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=0 392LDR_i 01 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=1 393LDR_i 10 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=2 394LDR_i 11 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=3 395LDR_i 00 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=0 396LDR_i 01 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=1 397LDR_i 10 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=2 398LDR_i 00 111 0 00 11 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=1 sz=0 399LDR_i 01 111 0 00 11 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=1 sz=1 400 401STR_i sz:2 111 0 00 00 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 402LDR_i 00 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=0 403LDR_i 01 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=1 404LDR_i 10 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=2 405LDR_i 11 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=3 406LDR_i 00 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=0 407LDR_i 01 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=1 408LDR_i 10 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=2 409LDR_i 00 111 0 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=1 sz=0 410LDR_i 01 111 0 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=1 sz=1 411 412STR_i sz:2 111 0 00 00 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=0 413LDR_i 00 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=0 414LDR_i 01 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=1 415LDR_i 10 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=2 416LDR_i 11 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=0 sz=3 417LDR_i 00 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=0 418LDR_i 01 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=1 419LDR_i 10 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=2 420LDR_i 00 111 0 00 11 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=1 sz=0 421LDR_i 01 111 0 00 11 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=1 sz=1 422 423STR_i sz:2 111 0 00 00 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 424LDR_i 00 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=0 425LDR_i 01 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=1 426LDR_i 10 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=2 427LDR_i 11 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=3 428LDR_i 00 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=0 429LDR_i 01 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=1 430LDR_i 10 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=2 431LDR_i 00 111 0 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=1 sz=0 432LDR_i 01 111 0 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=1 sz=1 433 434# PRFM : prefetch memory: a no-op for QEMU 435NOP 11 111 0 00 10 0 --------- 00 ----- ----- 436 437STR_v_i sz:2 111 1 00 00 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 438STR_v_i 00 111 1 00 10 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=4 439LDR_v_i sz:2 111 1 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 440LDR_v_i 00 111 1 00 11 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=4 441 442STR_v_i sz:2 111 1 00 00 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 443STR_v_i 00 111 1 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=4 444LDR_v_i sz:2 111 1 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 445LDR_v_i 00 111 1 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=4 446 447STR_v_i sz:2 111 1 00 00 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 448STR_v_i 00 111 1 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=4 449LDR_v_i sz:2 111 1 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 450LDR_v_i 00 111 1 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=4 451 452# Load/store with an unsigned 12 bit immediate, which is scaled by the 453# element size. The function gets the sz:imm and returns the scaled immediate. 454%uimm_scaled 10:12 sz:3 !function=uimm_scaled 455 456@ldst_uimm .. ... . .. .. ............ rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=0 imm=%uimm_scaled 457 458STR_i sz:2 111 0 01 00 ............ ..... ..... @ldst_uimm sign=0 ext=0 459LDR_i 00 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=0 460LDR_i 01 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=1 461LDR_i 10 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=2 462LDR_i 11 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=3 463LDR_i 00 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=0 464LDR_i 01 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=1 465LDR_i 10 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=2 466LDR_i 00 111 0 01 11 ............ ..... ..... @ldst_uimm sign=1 ext=1 sz=0 467LDR_i 01 111 0 01 11 ............ ..... ..... @ldst_uimm sign=1 ext=1 sz=1 468 469# PRFM 470NOP 11 111 0 01 10 ------------ ----- ----- 471 472STR_v_i sz:2 111 1 01 00 ............ ..... ..... @ldst_uimm sign=0 ext=0 473STR_v_i 00 111 1 01 10 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=4 474LDR_v_i sz:2 111 1 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=0 475LDR_v_i 00 111 1 01 11 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=4 476 477# Load/store with register offset 478&ldst rm rn rt sign ext sz opt s 479@ldst .. ... . .. .. . rm:5 opt:3 s:1 .. rn:5 rt:5 &ldst 480STR sz:2 111 0 00 00 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 481LDR 00 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=0 482LDR 01 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=1 483LDR 10 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=2 484LDR 11 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=3 485LDR 00 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=0 486LDR 01 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=1 487LDR 10 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=2 488LDR 00 111 0 00 11 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=1 sz=0 489LDR 01 111 0 00 11 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=1 sz=1 490 491# PRFM 492NOP 11 111 0 00 10 1 ----- -1- - 10 ----- ----- 493 494STR_v sz:2 111 1 00 00 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 495STR_v 00 111 1 00 10 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=4 496LDR_v sz:2 111 1 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 497LDR_v 00 111 1 00 11 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=4 498 499# Atomic memory operations 500&atomic rs rn rt a r sz 501@atomic sz:2 ... . .. a:1 r:1 . rs:5 . ... .. rn:5 rt:5 &atomic 502LDADD .. 111 0 00 . . 1 ..... 0000 00 ..... ..... @atomic 503LDCLR .. 111 0 00 . . 1 ..... 0001 00 ..... ..... @atomic 504LDEOR .. 111 0 00 . . 1 ..... 0010 00 ..... ..... @atomic 505LDSET .. 111 0 00 . . 1 ..... 0011 00 ..... ..... @atomic 506LDSMAX .. 111 0 00 . . 1 ..... 0100 00 ..... ..... @atomic 507LDSMIN .. 111 0 00 . . 1 ..... 0101 00 ..... ..... @atomic 508LDUMAX .. 111 0 00 . . 1 ..... 0110 00 ..... ..... @atomic 509LDUMIN .. 111 0 00 . . 1 ..... 0111 00 ..... ..... @atomic 510SWP .. 111 0 00 . . 1 ..... 1000 00 ..... ..... @atomic 511 512LDAPR sz:2 111 0 00 1 0 1 11111 1100 00 rn:5 rt:5 513 514# Load/store register (pointer authentication) 515 516# LDRA immediate is 10 bits signed and scaled, but the bits aren't all contiguous 517%ldra_imm 22:s1 12:9 !function=times_8 518 519LDRA 11 111 0 00 m:1 . 1 ......... w:1 1 rn:5 rt:5 imm=%ldra_imm 520 521&ldapr_stlr_i rn rt imm sz sign ext 522@ldapr_stlr_i .. ...... .. . imm:9 .. rn:5 rt:5 &ldapr_stlr_i 523STLR_i sz:2 011001 00 0 ......... 00 ..... ..... @ldapr_stlr_i sign=0 ext=0 524LDAPR_i sz:2 011001 01 0 ......... 00 ..... ..... @ldapr_stlr_i sign=0 ext=0 525LDAPR_i 00 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=0 526LDAPR_i 01 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=1 527LDAPR_i 10 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=2 528LDAPR_i 00 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=1 sz=0 529LDAPR_i 01 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=1 sz=1 530 531# Load/store multiple structures 532# The 4-bit opcode in [15:12] encodes repeat count and structure elements 533&ldst_mult rm rn rt sz q p rpt selem 534@ldst_mult . q:1 ...... p:1 . . rm:5 .... sz:2 rn:5 rt:5 &ldst_mult 535ST_mult 0 . 001100 . 0 0 ..... 0000 .. ..... ..... @ldst_mult rpt=1 selem=4 536ST_mult 0 . 001100 . 0 0 ..... 0010 .. ..... ..... @ldst_mult rpt=4 selem=1 537ST_mult 0 . 001100 . 0 0 ..... 0100 .. ..... ..... @ldst_mult rpt=1 selem=3 538ST_mult 0 . 001100 . 0 0 ..... 0110 .. ..... ..... @ldst_mult rpt=3 selem=1 539ST_mult 0 . 001100 . 0 0 ..... 0111 .. ..... ..... @ldst_mult rpt=1 selem=1 540ST_mult 0 . 001100 . 0 0 ..... 1000 .. ..... ..... @ldst_mult rpt=1 selem=2 541ST_mult 0 . 001100 . 0 0 ..... 1010 .. ..... ..... @ldst_mult rpt=2 selem=1 542 543LD_mult 0 . 001100 . 1 0 ..... 0000 .. ..... ..... @ldst_mult rpt=1 selem=4 544LD_mult 0 . 001100 . 1 0 ..... 0010 .. ..... ..... @ldst_mult rpt=4 selem=1 545LD_mult 0 . 001100 . 1 0 ..... 0100 .. ..... ..... @ldst_mult rpt=1 selem=3 546LD_mult 0 . 001100 . 1 0 ..... 0110 .. ..... ..... @ldst_mult rpt=3 selem=1 547LD_mult 0 . 001100 . 1 0 ..... 0111 .. ..... ..... @ldst_mult rpt=1 selem=1 548LD_mult 0 . 001100 . 1 0 ..... 1000 .. ..... ..... @ldst_mult rpt=1 selem=2 549LD_mult 0 . 001100 . 1 0 ..... 1010 .. ..... ..... @ldst_mult rpt=2 selem=1 550 551# Load/store single structure 552&ldst_single rm rn rt p selem index scale 553 554%ldst_single_selem 13:1 21:1 !function=plus_1 555 556%ldst_single_index_b 30:1 10:3 557%ldst_single_index_h 30:1 11:2 558%ldst_single_index_s 30:1 12:1 559 560@ldst_single_b .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \ 561 &ldst_single scale=0 selem=%ldst_single_selem \ 562 index=%ldst_single_index_b 563@ldst_single_h .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \ 564 &ldst_single scale=1 selem=%ldst_single_selem \ 565 index=%ldst_single_index_h 566@ldst_single_s .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \ 567 &ldst_single scale=2 selem=%ldst_single_selem \ 568 index=%ldst_single_index_s 569@ldst_single_d . index:1 ...... p:1 .. rm:5 ...... rn:5 rt:5 \ 570 &ldst_single scale=3 selem=%ldst_single_selem 571 572ST_single 0 . 001101 . 0 . ..... 00 . ... ..... ..... @ldst_single_b 573ST_single 0 . 001101 . 0 . ..... 01 . ..0 ..... ..... @ldst_single_h 574ST_single 0 . 001101 . 0 . ..... 10 . .00 ..... ..... @ldst_single_s 575ST_single 0 . 001101 . 0 . ..... 10 . 001 ..... ..... @ldst_single_d 576 577LD_single 0 . 001101 . 1 . ..... 00 . ... ..... ..... @ldst_single_b 578LD_single 0 . 001101 . 1 . ..... 01 . ..0 ..... ..... @ldst_single_h 579LD_single 0 . 001101 . 1 . ..... 10 . .00 ..... ..... @ldst_single_s 580LD_single 0 . 001101 . 1 . ..... 10 . 001 ..... ..... @ldst_single_d 581 582# Replicating load case 583LD_single_repl 0 q:1 001101 p:1 1 . rm:5 11 . 0 scale:2 rn:5 rt:5 selem=%ldst_single_selem 584 585%tag_offset 12:s9 !function=scale_by_log2_tag_granule 586&ldst_tag rn rt imm p w 587@ldst_tag ........ .. . ......... .. rn:5 rt:5 &ldst_tag imm=%tag_offset 588@ldst_tag_mult ........ .. . 000000000 .. rn:5 rt:5 &ldst_tag imm=0 589 590STZGM 11011001 00 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0 591STG 11011001 00 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 592STG 11011001 00 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 593STG 11011001 00 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 594 595LDG 11011001 01 1 ......... 00 ..... ..... @ldst_tag p=0 w=0 596STZG 11011001 01 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 597STZG 11011001 01 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 598STZG 11011001 01 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 599 600STGM 11011001 10 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0 601ST2G 11011001 10 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 602ST2G 11011001 10 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 603ST2G 11011001 10 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 604 605LDGM 11011001 11 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0 606STZ2G 11011001 11 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 607STZ2G 11011001 11 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 608STZ2G 11011001 11 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 609 610# Memory operations (memset, memcpy, memmove) 611# Each of these comes in a set of three, eg SETP (prologue), SETM (main), 612# SETE (epilogue), and each of those has different flavours to 613# indicate whether memory accesses should be unpriv or non-temporal. 614# We don't distinguish temporal and non-temporal accesses, but we 615# do need to report it in syndrome register values. 616 617# Memset 618&set rs rn rd unpriv nontemp 619# op2 bit 1 is nontemporal bit 620@set .. ......... rs:5 .. nontemp:1 unpriv:1 .. rn:5 rd:5 &set 621 622SETP 00 011001110 ..... 00 . . 01 ..... ..... @set 623SETM 00 011001110 ..... 01 . . 01 ..... ..... @set 624SETE 00 011001110 ..... 10 . . 01 ..... ..... @set 625 626# Like SET, but also setting MTE tags 627SETGP 00 011101110 ..... 00 . . 01 ..... ..... @set 628SETGM 00 011101110 ..... 01 . . 01 ..... ..... @set 629SETGE 00 011101110 ..... 10 . . 01 ..... ..... @set 630 631# Memmove/Memcopy: the CPY insns allow overlapping src/dest and 632# copy in the correct direction; the CPYF insns always copy forwards. 633# 634# options has the nontemporal and unpriv bits for src and dest 635&cpy rs rn rd options 636@cpy .. ... . ..... rs:5 options:4 .. rn:5 rd:5 &cpy 637 638CPYFP 00 011 0 01000 ..... .... 01 ..... ..... @cpy 639CPYFM 00 011 0 01010 ..... .... 01 ..... ..... @cpy 640CPYFE 00 011 0 01100 ..... .... 01 ..... ..... @cpy 641CPYP 00 011 1 01000 ..... .... 01 ..... ..... @cpy 642CPYM 00 011 1 01010 ..... .... 01 ..... ..... @cpy 643CPYE 00 011 1 01100 ..... .... 01 ..... ..... @cpy 644 645### Cryptographic AES 646 647AESE 01001110 00 10100 00100 10 ..... ..... @r2r_q1e0 648AESD 01001110 00 10100 00101 10 ..... ..... @r2r_q1e0 649AESMC 01001110 00 10100 00110 10 ..... ..... @rr_q1e0 650AESIMC 01001110 00 10100 00111 10 ..... ..... @rr_q1e0 651 652### Cryptographic three-register SHA 653 654SHA1C 0101 1110 000 ..... 000000 ..... ..... @rrr_q1e0 655SHA1P 0101 1110 000 ..... 000100 ..... ..... @rrr_q1e0 656SHA1M 0101 1110 000 ..... 001000 ..... ..... @rrr_q1e0 657SHA1SU0 0101 1110 000 ..... 001100 ..... ..... @rrr_q1e0 658SHA256H 0101 1110 000 ..... 010000 ..... ..... @rrr_q1e0 659SHA256H2 0101 1110 000 ..... 010100 ..... ..... @rrr_q1e0 660SHA256SU1 0101 1110 000 ..... 011000 ..... ..... @rrr_q1e0 661 662### Cryptographic two-register SHA 663 664SHA1H 0101 1110 0010 1000 0000 10 ..... ..... @rr_q1e0 665SHA1SU1 0101 1110 0010 1000 0001 10 ..... ..... @rr_q1e0 666SHA256SU0 0101 1110 0010 1000 0010 10 ..... ..... @rr_q1e0 667 668### Cryptographic three-register SHA512 669 670SHA512H 1100 1110 011 ..... 100000 ..... ..... @rrr_q1e0 671SHA512H2 1100 1110 011 ..... 100001 ..... ..... @rrr_q1e0 672SHA512SU1 1100 1110 011 ..... 100010 ..... ..... @rrr_q1e0 673RAX1 1100 1110 011 ..... 100011 ..... ..... @rrr_q1e3 674SM3PARTW1 1100 1110 011 ..... 110000 ..... ..... @rrr_q1e0 675SM3PARTW2 1100 1110 011 ..... 110001 ..... ..... @rrr_q1e0 676SM4EKEY 1100 1110 011 ..... 110010 ..... ..... @rrr_q1e0 677 678### Cryptographic two-register SHA512 679 680SHA512SU0 1100 1110 110 00000 100000 ..... ..... @rr_q1e0 681SM4E 1100 1110 110 00000 100001 ..... ..... @r2r_q1e0 682 683### Cryptographic four-register 684 685EOR3 1100 1110 000 ..... 0 ..... ..... ..... @rrrr_q1e3 686BCAX 1100 1110 001 ..... 0 ..... ..... ..... @rrrr_q1e3 687SM3SS1 1100 1110 010 ..... 0 ..... ..... ..... @rrrr_q1e3 688 689### Cryptographic three-register, imm2 690 691&crypto3i rd rn rm imm 692@crypto3i ........ ... rm:5 .. imm:2 .. rn:5 rd:5 &crypto3i 693 694SM3TT1A 11001110 010 ..... 10 .. 00 ..... ..... @crypto3i 695SM3TT1B 11001110 010 ..... 10 .. 01 ..... ..... @crypto3i 696SM3TT2A 11001110 010 ..... 10 .. 10 ..... ..... @crypto3i 697SM3TT2B 11001110 010 ..... 10 .. 11 ..... ..... @crypto3i 698 699### Cryptographic XAR 700 701XAR 1100 1110 100 rm:5 imm:6 rn:5 rd:5 702 703### Advanced SIMD scalar copy 704 705DUP_element_s 0101 1110 000 imm:5 0 0000 1 rn:5 rd:5 706 707### Advanced SIMD copy 708 709DUP_element_v 0 q:1 00 1110 000 imm:5 0 0000 1 rn:5 rd:5 710DUP_general 0 q:1 00 1110 000 imm:5 0 0001 1 rn:5 rd:5 711INS_general 0 1 00 1110 000 imm:5 0 0011 1 rn:5 rd:5 712SMOV 0 q:1 00 1110 000 imm:5 0 0101 1 rn:5 rd:5 713UMOV 0 q:1 00 1110 000 imm:5 0 0111 1 rn:5 rd:5 714INS_element 0 1 10 1110 000 di:5 0 si:4 1 rn:5 rd:5 715 716### Advanced SIMD scalar three same 717 718FADD_s 0001 1110 ..1 ..... 0010 10 ..... ..... @rrr_hsd 719FSUB_s 0001 1110 ..1 ..... 0011 10 ..... ..... @rrr_hsd 720FDIV_s 0001 1110 ..1 ..... 0001 10 ..... ..... @rrr_hsd 721FMUL_s 0001 1110 ..1 ..... 0000 10 ..... ..... @rrr_hsd 722FNMUL_s 0001 1110 ..1 ..... 1000 10 ..... ..... @rrr_hsd 723 724FMAX_s 0001 1110 ..1 ..... 0100 10 ..... ..... @rrr_hsd 725FMIN_s 0001 1110 ..1 ..... 0101 10 ..... ..... @rrr_hsd 726FMAXNM_s 0001 1110 ..1 ..... 0110 10 ..... ..... @rrr_hsd 727FMINNM_s 0001 1110 ..1 ..... 0111 10 ..... ..... @rrr_hsd 728 729FMULX_s 0101 1110 010 ..... 00011 1 ..... ..... @rrr_h 730FMULX_s 0101 1110 0.1 ..... 11011 1 ..... ..... @rrr_sd 731 732FCMEQ_s 0101 1110 010 ..... 00100 1 ..... ..... @rrr_h 733FCMEQ_s 0101 1110 0.1 ..... 11100 1 ..... ..... @rrr_sd 734 735FCMGE_s 0111 1110 010 ..... 00100 1 ..... ..... @rrr_h 736FCMGE_s 0111 1110 0.1 ..... 11100 1 ..... ..... @rrr_sd 737 738FCMGT_s 0111 1110 110 ..... 00100 1 ..... ..... @rrr_h 739FCMGT_s 0111 1110 1.1 ..... 11100 1 ..... ..... @rrr_sd 740 741FACGE_s 0111 1110 010 ..... 00101 1 ..... ..... @rrr_h 742FACGE_s 0111 1110 0.1 ..... 11101 1 ..... ..... @rrr_sd 743 744FACGT_s 0111 1110 110 ..... 00101 1 ..... ..... @rrr_h 745FACGT_s 0111 1110 1.1 ..... 11101 1 ..... ..... @rrr_sd 746 747FABD_s 0111 1110 110 ..... 00010 1 ..... ..... @rrr_h 748FABD_s 0111 1110 1.1 ..... 11010 1 ..... ..... @rrr_sd 749 750FRECPS_s 0101 1110 010 ..... 00111 1 ..... ..... @rrr_h 751FRECPS_s 0101 1110 0.1 ..... 11111 1 ..... ..... @rrr_sd 752 753FRSQRTS_s 0101 1110 110 ..... 00111 1 ..... ..... @rrr_h 754FRSQRTS_s 0101 1110 1.1 ..... 11111 1 ..... ..... @rrr_sd 755 756SQADD_s 0101 1110 ..1 ..... 00001 1 ..... ..... @rrr_e 757UQADD_s 0111 1110 ..1 ..... 00001 1 ..... ..... @rrr_e 758SQSUB_s 0101 1110 ..1 ..... 00101 1 ..... ..... @rrr_e 759UQSUB_s 0111 1110 ..1 ..... 00101 1 ..... ..... @rrr_e 760 761SUQADD_s 0101 1110 ..1 00000 00111 0 ..... ..... @r2r_e 762USQADD_s 0111 1110 ..1 00000 00111 0 ..... ..... @r2r_e 763 764SSHL_s 0101 1110 111 ..... 01000 1 ..... ..... @rrr_d 765USHL_s 0111 1110 111 ..... 01000 1 ..... ..... @rrr_d 766SRSHL_s 0101 1110 111 ..... 01010 1 ..... ..... @rrr_d 767URSHL_s 0111 1110 111 ..... 01010 1 ..... ..... @rrr_d 768SQSHL_s 0101 1110 ..1 ..... 01001 1 ..... ..... @rrr_e 769UQSHL_s 0111 1110 ..1 ..... 01001 1 ..... ..... @rrr_e 770SQRSHL_s 0101 1110 ..1 ..... 01011 1 ..... ..... @rrr_e 771UQRSHL_s 0111 1110 ..1 ..... 01011 1 ..... ..... @rrr_e 772 773ADD_s 0101 1110 111 ..... 10000 1 ..... ..... @rrr_d 774SUB_s 0111 1110 111 ..... 10000 1 ..... ..... @rrr_d 775CMGT_s 0101 1110 111 ..... 00110 1 ..... ..... @rrr_d 776CMHI_s 0111 1110 111 ..... 00110 1 ..... ..... @rrr_d 777CMGE_s 0101 1110 111 ..... 00111 1 ..... ..... @rrr_d 778CMHS_s 0111 1110 111 ..... 00111 1 ..... ..... @rrr_d 779CMTST_s 0101 1110 111 ..... 10001 1 ..... ..... @rrr_d 780CMEQ_s 0111 1110 111 ..... 10001 1 ..... ..... @rrr_d 781 782SQDMULH_s 0101 1110 ..1 ..... 10110 1 ..... ..... @rrr_e 783SQRDMULH_s 0111 1110 ..1 ..... 10110 1 ..... ..... @rrr_e 784 785### Advanced SIMD scalar pairwise 786 787FADDP_s 0101 1110 0011 0000 1101 10 ..... ..... @rr_h 788FADDP_s 0111 1110 0.11 0000 1101 10 ..... ..... @rr_sd 789 790FMAXP_s 0101 1110 0011 0000 1111 10 ..... ..... @rr_h 791FMAXP_s 0111 1110 0.11 0000 1111 10 ..... ..... @rr_sd 792 793FMINP_s 0101 1110 1011 0000 1111 10 ..... ..... @rr_h 794FMINP_s 0111 1110 1.11 0000 1111 10 ..... ..... @rr_sd 795 796FMAXNMP_s 0101 1110 0011 0000 1100 10 ..... ..... @rr_h 797FMAXNMP_s 0111 1110 0.11 0000 1100 10 ..... ..... @rr_sd 798 799FMINNMP_s 0101 1110 1011 0000 1100 10 ..... ..... @rr_h 800FMINNMP_s 0111 1110 1.11 0000 1100 10 ..... ..... @rr_sd 801 802ADDP_s 0101 1110 1111 0001 1011 10 ..... ..... @rr_d 803 804### Advanced SIMD three same 805 806FADD_v 0.00 1110 010 ..... 00010 1 ..... ..... @qrrr_h 807FADD_v 0.00 1110 0.1 ..... 11010 1 ..... ..... @qrrr_sd 808 809FSUB_v 0.00 1110 110 ..... 00010 1 ..... ..... @qrrr_h 810FSUB_v 0.00 1110 1.1 ..... 11010 1 ..... ..... @qrrr_sd 811 812FDIV_v 0.10 1110 010 ..... 00111 1 ..... ..... @qrrr_h 813FDIV_v 0.10 1110 0.1 ..... 11111 1 ..... ..... @qrrr_sd 814 815FMUL_v 0.10 1110 010 ..... 00011 1 ..... ..... @qrrr_h 816FMUL_v 0.10 1110 0.1 ..... 11011 1 ..... ..... @qrrr_sd 817 818FMAX_v 0.00 1110 010 ..... 00110 1 ..... ..... @qrrr_h 819FMAX_v 0.00 1110 0.1 ..... 11110 1 ..... ..... @qrrr_sd 820 821FMIN_v 0.00 1110 110 ..... 00110 1 ..... ..... @qrrr_h 822FMIN_v 0.00 1110 1.1 ..... 11110 1 ..... ..... @qrrr_sd 823 824FMAXNM_v 0.00 1110 010 ..... 00000 1 ..... ..... @qrrr_h 825FMAXNM_v 0.00 1110 0.1 ..... 11000 1 ..... ..... @qrrr_sd 826 827FMINNM_v 0.00 1110 110 ..... 00000 1 ..... ..... @qrrr_h 828FMINNM_v 0.00 1110 1.1 ..... 11000 1 ..... ..... @qrrr_sd 829 830FMULX_v 0.00 1110 010 ..... 00011 1 ..... ..... @qrrr_h 831FMULX_v 0.00 1110 0.1 ..... 11011 1 ..... ..... @qrrr_sd 832 833FMLA_v 0.00 1110 010 ..... 00001 1 ..... ..... @qrrr_h 834FMLA_v 0.00 1110 0.1 ..... 11001 1 ..... ..... @qrrr_sd 835 836FMLS_v 0.00 1110 110 ..... 00001 1 ..... ..... @qrrr_h 837FMLS_v 0.00 1110 1.1 ..... 11001 1 ..... ..... @qrrr_sd 838 839FMLAL_v 0.00 1110 001 ..... 11101 1 ..... ..... @qrrr_h 840FMLSL_v 0.00 1110 101 ..... 11101 1 ..... ..... @qrrr_h 841FMLAL2_v 0.10 1110 001 ..... 11001 1 ..... ..... @qrrr_h 842FMLSL2_v 0.10 1110 101 ..... 11001 1 ..... ..... @qrrr_h 843 844FCMEQ_v 0.00 1110 010 ..... 00100 1 ..... ..... @qrrr_h 845FCMEQ_v 0.00 1110 0.1 ..... 11100 1 ..... ..... @qrrr_sd 846 847FCMGE_v 0.10 1110 010 ..... 00100 1 ..... ..... @qrrr_h 848FCMGE_v 0.10 1110 0.1 ..... 11100 1 ..... ..... @qrrr_sd 849 850FCMGT_v 0.10 1110 110 ..... 00100 1 ..... ..... @qrrr_h 851FCMGT_v 0.10 1110 1.1 ..... 11100 1 ..... ..... @qrrr_sd 852 853FACGE_v 0.10 1110 010 ..... 00101 1 ..... ..... @qrrr_h 854FACGE_v 0.10 1110 0.1 ..... 11101 1 ..... ..... @qrrr_sd 855 856FACGT_v 0.10 1110 110 ..... 00101 1 ..... ..... @qrrr_h 857FACGT_v 0.10 1110 1.1 ..... 11101 1 ..... ..... @qrrr_sd 858 859FABD_v 0.10 1110 110 ..... 00010 1 ..... ..... @qrrr_h 860FABD_v 0.10 1110 1.1 ..... 11010 1 ..... ..... @qrrr_sd 861 862FRECPS_v 0.00 1110 010 ..... 00111 1 ..... ..... @qrrr_h 863FRECPS_v 0.00 1110 0.1 ..... 11111 1 ..... ..... @qrrr_sd 864 865FRSQRTS_v 0.00 1110 110 ..... 00111 1 ..... ..... @qrrr_h 866FRSQRTS_v 0.00 1110 1.1 ..... 11111 1 ..... ..... @qrrr_sd 867 868FADDP_v 0.10 1110 010 ..... 00010 1 ..... ..... @qrrr_h 869FADDP_v 0.10 1110 0.1 ..... 11010 1 ..... ..... @qrrr_sd 870 871FMAXP_v 0.10 1110 010 ..... 00110 1 ..... ..... @qrrr_h 872FMAXP_v 0.10 1110 0.1 ..... 11110 1 ..... ..... @qrrr_sd 873 874FMINP_v 0.10 1110 110 ..... 00110 1 ..... ..... @qrrr_h 875FMINP_v 0.10 1110 1.1 ..... 11110 1 ..... ..... @qrrr_sd 876 877FMAXNMP_v 0.10 1110 010 ..... 00000 1 ..... ..... @qrrr_h 878FMAXNMP_v 0.10 1110 0.1 ..... 11000 1 ..... ..... @qrrr_sd 879 880FMINNMP_v 0.10 1110 110 ..... 00000 1 ..... ..... @qrrr_h 881FMINNMP_v 0.10 1110 1.1 ..... 11000 1 ..... ..... @qrrr_sd 882 883ADDP_v 0.00 1110 ..1 ..... 10111 1 ..... ..... @qrrr_e 884SMAXP_v 0.00 1110 ..1 ..... 10100 1 ..... ..... @qrrr_e 885SMINP_v 0.00 1110 ..1 ..... 10101 1 ..... ..... @qrrr_e 886UMAXP_v 0.10 1110 ..1 ..... 10100 1 ..... ..... @qrrr_e 887UMINP_v 0.10 1110 ..1 ..... 10101 1 ..... ..... @qrrr_e 888 889AND_v 0.00 1110 001 ..... 00011 1 ..... ..... @qrrr_b 890BIC_v 0.00 1110 011 ..... 00011 1 ..... ..... @qrrr_b 891ORR_v 0.00 1110 101 ..... 00011 1 ..... ..... @qrrr_b 892ORN_v 0.00 1110 111 ..... 00011 1 ..... ..... @qrrr_b 893EOR_v 0.10 1110 001 ..... 00011 1 ..... ..... @qrrr_b 894BSL_v 0.10 1110 011 ..... 00011 1 ..... ..... @qrrr_b 895BIT_v 0.10 1110 101 ..... 00011 1 ..... ..... @qrrr_b 896BIF_v 0.10 1110 111 ..... 00011 1 ..... ..... @qrrr_b 897 898SQADD_v 0.00 1110 ..1 ..... 00001 1 ..... ..... @qrrr_e 899UQADD_v 0.10 1110 ..1 ..... 00001 1 ..... ..... @qrrr_e 900SQSUB_v 0.00 1110 ..1 ..... 00101 1 ..... ..... @qrrr_e 901UQSUB_v 0.10 1110 ..1 ..... 00101 1 ..... ..... @qrrr_e 902 903SUQADD_v 0.00 1110 ..1 00000 00111 0 ..... ..... @qr2r_e 904USQADD_v 0.10 1110 ..1 00000 00111 0 ..... ..... @qr2r_e 905 906SSHL_v 0.00 1110 ..1 ..... 01000 1 ..... ..... @qrrr_e 907USHL_v 0.10 1110 ..1 ..... 01000 1 ..... ..... @qrrr_e 908SRSHL_v 0.00 1110 ..1 ..... 01010 1 ..... ..... @qrrr_e 909URSHL_v 0.10 1110 ..1 ..... 01010 1 ..... ..... @qrrr_e 910SQSHL_v 0.00 1110 ..1 ..... 01001 1 ..... ..... @qrrr_e 911UQSHL_v 0.10 1110 ..1 ..... 01001 1 ..... ..... @qrrr_e 912SQRSHL_v 0.00 1110 ..1 ..... 01011 1 ..... ..... @qrrr_e 913UQRSHL_v 0.10 1110 ..1 ..... 01011 1 ..... ..... @qrrr_e 914 915ADD_v 0.00 1110 ..1 ..... 10000 1 ..... ..... @qrrr_e 916SUB_v 0.10 1110 ..1 ..... 10000 1 ..... ..... @qrrr_e 917CMGT_v 0.00 1110 ..1 ..... 00110 1 ..... ..... @qrrr_e 918CMHI_v 0.10 1110 ..1 ..... 00110 1 ..... ..... @qrrr_e 919CMGE_v 0.00 1110 ..1 ..... 00111 1 ..... ..... @qrrr_e 920CMHS_v 0.10 1110 ..1 ..... 00111 1 ..... ..... @qrrr_e 921CMTST_v 0.00 1110 ..1 ..... 10001 1 ..... ..... @qrrr_e 922CMEQ_v 0.10 1110 ..1 ..... 10001 1 ..... ..... @qrrr_e 923SHADD_v 0.00 1110 ..1 ..... 00000 1 ..... ..... @qrrr_e 924UHADD_v 0.10 1110 ..1 ..... 00000 1 ..... ..... @qrrr_e 925SHSUB_v 0.00 1110 ..1 ..... 00100 1 ..... ..... @qrrr_e 926UHSUB_v 0.10 1110 ..1 ..... 00100 1 ..... ..... @qrrr_e 927SRHADD_v 0.00 1110 ..1 ..... 00010 1 ..... ..... @qrrr_e 928URHADD_v 0.10 1110 ..1 ..... 00010 1 ..... ..... @qrrr_e 929SMAX_v 0.00 1110 ..1 ..... 01100 1 ..... ..... @qrrr_e 930UMAX_v 0.10 1110 ..1 ..... 01100 1 ..... ..... @qrrr_e 931SMIN_v 0.00 1110 ..1 ..... 01101 1 ..... ..... @qrrr_e 932UMIN_v 0.10 1110 ..1 ..... 01101 1 ..... ..... @qrrr_e 933SABD_v 0.00 1110 ..1 ..... 01110 1 ..... ..... @qrrr_e 934UABD_v 0.10 1110 ..1 ..... 01110 1 ..... ..... @qrrr_e 935SABA_v 0.00 1110 ..1 ..... 01111 1 ..... ..... @qrrr_e 936UABA_v 0.10 1110 ..1 ..... 01111 1 ..... ..... @qrrr_e 937MUL_v 0.00 1110 ..1 ..... 10011 1 ..... ..... @qrrr_e 938PMUL_v 0.10 1110 001 ..... 10011 1 ..... ..... @qrrr_b 939MLA_v 0.00 1110 ..1 ..... 10010 1 ..... ..... @qrrr_e 940MLS_v 0.10 1110 ..1 ..... 10010 1 ..... ..... @qrrr_e 941 942SQDMULH_v 0.00 1110 ..1 ..... 10110 1 ..... ..... @qrrr_e 943SQRDMULH_v 0.10 1110 ..1 ..... 10110 1 ..... ..... @qrrr_e 944 945### Advanced SIMD scalar x indexed element 946 947FMUL_si 0101 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h 948FMUL_si 0101 1111 10 . ..... 1001 . 0 ..... ..... @rrx_s 949FMUL_si 0101 1111 11 0 ..... 1001 . 0 ..... ..... @rrx_d 950 951FMLA_si 0101 1111 00 .. .... 0001 . 0 ..... ..... @rrx_h 952FMLA_si 0101 1111 10 .. .... 0001 . 0 ..... ..... @rrx_s 953FMLA_si 0101 1111 11 0. .... 0001 . 0 ..... ..... @rrx_d 954 955FMLS_si 0101 1111 00 .. .... 0101 . 0 ..... ..... @rrx_h 956FMLS_si 0101 1111 10 .. .... 0101 . 0 ..... ..... @rrx_s 957FMLS_si 0101 1111 11 0. .... 0101 . 0 ..... ..... @rrx_d 958 959FMULX_si 0111 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h 960FMULX_si 0111 1111 10 . ..... 1001 . 0 ..... ..... @rrx_s 961FMULX_si 0111 1111 11 0 ..... 1001 . 0 ..... ..... @rrx_d 962 963SQDMULH_si 0101 1111 01 .. .... 1100 . 0 ..... ..... @rrx_h 964SQDMULH_si 0101 1111 10 .. .... 1100 . 0 ..... ..... @rrx_s 965 966SQRDMULH_si 0101 1111 01 .. .... 1101 . 0 ..... ..... @rrx_h 967SQRDMULH_si 0101 1111 10 . ..... 1101 . 0 ..... ..... @rrx_s 968 969### Advanced SIMD vector x indexed element 970 971FMUL_vi 0.00 1111 00 .. .... 1001 . 0 ..... ..... @qrrx_h 972FMUL_vi 0.00 1111 10 . ..... 1001 . 0 ..... ..... @qrrx_s 973FMUL_vi 0.00 1111 11 0 ..... 1001 . 0 ..... ..... @qrrx_d 974 975FMLA_vi 0.00 1111 00 .. .... 0001 . 0 ..... ..... @qrrx_h 976FMLA_vi 0.00 1111 10 . ..... 0001 . 0 ..... ..... @qrrx_s 977FMLA_vi 0.00 1111 11 0 ..... 0001 . 0 ..... ..... @qrrx_d 978 979FMLS_vi 0.00 1111 00 .. .... 0101 . 0 ..... ..... @qrrx_h 980FMLS_vi 0.00 1111 10 . ..... 0101 . 0 ..... ..... @qrrx_s 981FMLS_vi 0.00 1111 11 0 ..... 0101 . 0 ..... ..... @qrrx_d 982 983FMULX_vi 0.10 1111 00 .. .... 1001 . 0 ..... ..... @qrrx_h 984FMULX_vi 0.10 1111 10 . ..... 1001 . 0 ..... ..... @qrrx_s 985FMULX_vi 0.10 1111 11 0 ..... 1001 . 0 ..... ..... @qrrx_d 986 987FMLAL_vi 0.00 1111 10 .. .... 0000 . 0 ..... ..... @qrrx_h 988FMLSL_vi 0.00 1111 10 .. .... 0100 . 0 ..... ..... @qrrx_h 989FMLAL2_vi 0.10 1111 10 .. .... 1000 . 0 ..... ..... @qrrx_h 990FMLSL2_vi 0.10 1111 10 .. .... 1100 . 0 ..... ..... @qrrx_h 991 992MUL_vi 0.00 1111 01 .. .... 1000 . 0 ..... ..... @qrrx_h 993MUL_vi 0.00 1111 10 . ..... 1000 . 0 ..... ..... @qrrx_s 994 995MLA_vi 0.10 1111 01 .. .... 0000 . 0 ..... ..... @qrrx_h 996MLA_vi 0.10 1111 10 . ..... 0000 . 0 ..... ..... @qrrx_s 997 998MLS_vi 0.10 1111 01 .. .... 0100 . 0 ..... ..... @qrrx_h 999MLS_vi 0.10 1111 10 . ..... 0100 . 0 ..... ..... @qrrx_s 1000 1001SQDMULH_vi 0.00 1111 01 .. .... 1100 . 0 ..... ..... @qrrx_h 1002SQDMULH_vi 0.00 1111 10 . ..... 1100 . 0 ..... ..... @qrrx_s 1003 1004SQRDMULH_vi 0.00 1111 01 .. .... 1101 . 0 ..... ..... @qrrx_h 1005SQRDMULH_vi 0.00 1111 10 . ..... 1101 . 0 ..... ..... @qrrx_s 1006 1007# Floating-point conditional select 1008 1009FCSEL 0001 1110 .. 1 rm:5 cond:4 11 rn:5 rd:5 esz=%esz_hsd 1010 1011# Floating-point data-processing (3 source) 1012 1013@rrrr_hsd .... .... .. . rm:5 . ra:5 rn:5 rd:5 &rrrr_e esz=%esz_hsd 1014 1015FMADD 0001 1111 .. 0 ..... 0 ..... ..... ..... @rrrr_hsd 1016FMSUB 0001 1111 .. 0 ..... 1 ..... ..... ..... @rrrr_hsd 1017FNMADD 0001 1111 .. 1 ..... 0 ..... ..... ..... @rrrr_hsd 1018FNMSUB 0001 1111 .. 1 ..... 1 ..... ..... ..... @rrrr_hsd 1019