1# AArch64 A64 allowed instruction decoding 2# 3# Copyright (c) 2023 Linaro, Ltd 4# 5# This library is free software; you can redistribute it and/or 6# modify it under the terms of the GNU Lesser General Public 7# License as published by the Free Software Foundation; either 8# version 2.1 of the License, or (at your option) any later version. 9# 10# This library is distributed in the hope that it will be useful, 11# but WITHOUT ANY WARRANTY; without even the implied warranty of 12# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13# Lesser General Public License for more details. 14# 15# You should have received a copy of the GNU Lesser General Public 16# License along with this library; if not, see <http://www.gnu.org/licenses/>. 17 18# 19# This file is processed by scripts/decodetree.py 20# 21 22%rd 0:5 23%esz_sd 22:1 !function=plus_2 24%esz_hsd 22:2 !function=xor_2 25%hl 11:1 21:1 26%hlm 11:1 20:2 27 28&r rn 29&ri rd imm 30&rri_sf rd rn imm sf 31&i imm 32&rrr_e rd rn rm esz 33&rrx_e rd rn rm idx esz 34&qrr_e q rd rn esz 35&qrrr_e q rd rn rm esz 36&qrrx_e q rd rn rm idx esz 37&qrrrr_e q rd rn rm ra esz 38 39@rrr_h ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=1 40@rrr_sd ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=%esz_sd 41@rrr_hsd ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=%esz_hsd 42 43@rrx_h ........ .. .. rm:4 .... . . rn:5 rd:5 &rrx_e esz=1 idx=%hlm 44@rrx_s ........ .. . rm:5 .... . . rn:5 rd:5 &rrx_e esz=2 idx=%hl 45@rrx_d ........ .. . rm:5 .... idx:1 . rn:5 rd:5 &rrx_e esz=3 46 47@rr_q1e0 ........ ........ ...... rn:5 rd:5 &qrr_e q=1 esz=0 48@r2r_q1e0 ........ ........ ...... rm:5 rd:5 &qrrr_e rn=%rd q=1 esz=0 49@rrr_q1e0 ........ ... rm:5 ...... rn:5 rd:5 &qrrr_e q=1 esz=0 50@rrr_q1e3 ........ ... rm:5 ...... rn:5 rd:5 &qrrr_e q=1 esz=3 51@rrrr_q1e3 ........ ... rm:5 . ra:5 rn:5 rd:5 &qrrrr_e q=1 esz=3 52 53@qrrr_h . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=1 54@qrrr_sd . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=%esz_sd 55 56@qrrx_h . q:1 .. .... .. .. rm:4 .... . . rn:5 rd:5 \ 57 &qrrx_e esz=1 idx=%hlm 58@qrrx_s . q:1 .. .... .. . rm:5 .... . . rn:5 rd:5 \ 59 &qrrx_e esz=2 idx=%hl 60@qrrx_d . q:1 .. .... .. . rm:5 .... idx:1 . rn:5 rd:5 \ 61 &qrrx_e esz=3 62 63### Data Processing - Immediate 64 65# PC-rel addressing 66 67%imm_pcrel 5:s19 29:2 68@pcrel . .. ..... ................... rd:5 &ri imm=%imm_pcrel 69 70ADR 0 .. 10000 ................... ..... @pcrel 71ADRP 1 .. 10000 ................... ..... @pcrel 72 73# Add/subtract (immediate) 74 75%imm12_sh12 10:12 !function=shl_12 76@addsub_imm sf:1 .. ...... . imm:12 rn:5 rd:5 77@addsub_imm12 sf:1 .. ...... . ............ rn:5 rd:5 imm=%imm12_sh12 78 79ADD_i . 00 100010 0 ............ ..... ..... @addsub_imm 80ADD_i . 00 100010 1 ............ ..... ..... @addsub_imm12 81ADDS_i . 01 100010 0 ............ ..... ..... @addsub_imm 82ADDS_i . 01 100010 1 ............ ..... ..... @addsub_imm12 83 84SUB_i . 10 100010 0 ............ ..... ..... @addsub_imm 85SUB_i . 10 100010 1 ............ ..... ..... @addsub_imm12 86SUBS_i . 11 100010 0 ............ ..... ..... @addsub_imm 87SUBS_i . 11 100010 1 ............ ..... ..... @addsub_imm12 88 89# Add/subtract (immediate with tags) 90 91&rri_tag rd rn uimm6 uimm4 92@addsub_imm_tag . .. ...... . uimm6:6 .. uimm4:4 rn:5 rd:5 &rri_tag 93 94ADDG_i 1 00 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag 95SUBG_i 1 10 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag 96 97# Logical (immediate) 98 99&rri_log rd rn sf dbm 100@logic_imm_64 1 .. ...... dbm:13 rn:5 rd:5 &rri_log sf=1 101@logic_imm_32 0 .. ...... 0 dbm:12 rn:5 rd:5 &rri_log sf=0 102 103AND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_64 104AND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_32 105ORR_i . 01 100100 . ...... ...... ..... ..... @logic_imm_64 106ORR_i . 01 100100 . ...... ...... ..... ..... @logic_imm_32 107EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_64 108EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_32 109ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_64 110ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_32 111 112# Move wide (immediate) 113 114&movw rd sf imm hw 115@movw_64 1 .. ...... hw:2 imm:16 rd:5 &movw sf=1 116@movw_32 0 .. ...... 0 hw:1 imm:16 rd:5 &movw sf=0 117 118MOVN . 00 100101 .. ................ ..... @movw_64 119MOVN . 00 100101 .. ................ ..... @movw_32 120MOVZ . 10 100101 .. ................ ..... @movw_64 121MOVZ . 10 100101 .. ................ ..... @movw_32 122MOVK . 11 100101 .. ................ ..... @movw_64 123MOVK . 11 100101 .. ................ ..... @movw_32 124 125# Bitfield 126 127&bitfield rd rn sf immr imms 128@bitfield_64 1 .. ...... 1 immr:6 imms:6 rn:5 rd:5 &bitfield sf=1 129@bitfield_32 0 .. ...... 0 0 immr:5 0 imms:5 rn:5 rd:5 &bitfield sf=0 130 131SBFM . 00 100110 . ...... ...... ..... ..... @bitfield_64 132SBFM . 00 100110 . ...... ...... ..... ..... @bitfield_32 133BFM . 01 100110 . ...... ...... ..... ..... @bitfield_64 134BFM . 01 100110 . ...... ...... ..... ..... @bitfield_32 135UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_64 136UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_32 137 138# Extract 139 140&extract rd rn rm imm sf 141 142EXTR 1 00 100111 1 0 rm:5 imm:6 rn:5 rd:5 &extract sf=1 143EXTR 0 00 100111 0 0 rm:5 0 imm:5 rn:5 rd:5 &extract sf=0 144 145# Branches 146 147%imm26 0:s26 !function=times_4 148@branch . ..... .......................... &i imm=%imm26 149 150B 0 00101 .......................... @branch 151BL 1 00101 .......................... @branch 152 153%imm19 5:s19 !function=times_4 154&cbz rt imm sf nz 155 156CBZ sf:1 011010 nz:1 ................... rt:5 &cbz imm=%imm19 157 158%imm14 5:s14 !function=times_4 159%imm31_19 31:1 19:5 160&tbz rt imm nz bitpos 161 162TBZ . 011011 nz:1 ..... .............. rt:5 &tbz imm=%imm14 bitpos=%imm31_19 163 164# B.cond and BC.cond 165B_cond 0101010 0 ................... c:1 cond:4 imm=%imm19 166 167BR 1101011 0000 11111 000000 rn:5 00000 &r 168BLR 1101011 0001 11111 000000 rn:5 00000 &r 169RET 1101011 0010 11111 000000 rn:5 00000 &r 170 171&braz rn m 172BRAZ 1101011 0000 11111 00001 m:1 rn:5 11111 &braz # BRAAZ, BRABZ 173BLRAZ 1101011 0001 11111 00001 m:1 rn:5 11111 &braz # BLRAAZ, BLRABZ 174 175&reta m 176RETA 1101011 0010 11111 00001 m:1 11111 11111 &reta # RETAA, RETAB 177 178&bra rn rm m 179BRA 1101011 1000 11111 00001 m:1 rn:5 rm:5 &bra # BRAA, BRAB 180BLRA 1101011 1001 11111 00001 m:1 rn:5 rm:5 &bra # BLRAA, BLRAB 181 182ERET 1101011 0100 11111 000000 11111 00000 183ERETA 1101011 0100 11111 00001 m:1 11111 11111 &reta # ERETAA, ERETAB 184 185# We don't need to decode DRPS because it always UNDEFs except when 186# the processor is in halting debug state (which we don't implement). 187# The pattern is listed here as documentation. 188# DRPS 1101011 0101 11111 000000 11111 00000 189 190# Hint instruction group 191{ 192 [ 193 YIELD 1101 0101 0000 0011 0010 0000 001 11111 194 WFE 1101 0101 0000 0011 0010 0000 010 11111 195 WFI 1101 0101 0000 0011 0010 0000 011 11111 196 # We implement WFE to never block, so our SEV/SEVL are NOPs 197 # SEV 1101 0101 0000 0011 0010 0000 100 11111 198 # SEVL 1101 0101 0000 0011 0010 0000 101 11111 199 # Our DGL is a NOP because we don't merge memory accesses anyway. 200 # DGL 1101 0101 0000 0011 0010 0000 110 11111 201 XPACLRI 1101 0101 0000 0011 0010 0000 111 11111 202 PACIA1716 1101 0101 0000 0011 0010 0001 000 11111 203 PACIB1716 1101 0101 0000 0011 0010 0001 010 11111 204 AUTIA1716 1101 0101 0000 0011 0010 0001 100 11111 205 AUTIB1716 1101 0101 0000 0011 0010 0001 110 11111 206 ESB 1101 0101 0000 0011 0010 0010 000 11111 207 PACIAZ 1101 0101 0000 0011 0010 0011 000 11111 208 PACIASP 1101 0101 0000 0011 0010 0011 001 11111 209 PACIBZ 1101 0101 0000 0011 0010 0011 010 11111 210 PACIBSP 1101 0101 0000 0011 0010 0011 011 11111 211 AUTIAZ 1101 0101 0000 0011 0010 0011 100 11111 212 AUTIASP 1101 0101 0000 0011 0010 0011 101 11111 213 AUTIBZ 1101 0101 0000 0011 0010 0011 110 11111 214 AUTIBSP 1101 0101 0000 0011 0010 0011 111 11111 215 ] 216 # The canonical NOP has CRm == op2 == 0, but all of the space 217 # that isn't specifically allocated to an instruction must NOP 218 NOP 1101 0101 0000 0011 0010 ---- --- 11111 219} 220 221# Barriers 222 223CLREX 1101 0101 0000 0011 0011 ---- 010 11111 224DSB_DMB 1101 0101 0000 0011 0011 domain:2 types:2 10- 11111 225ISB 1101 0101 0000 0011 0011 ---- 110 11111 226SB 1101 0101 0000 0011 0011 0000 111 11111 227 228# PSTATE 229 230CFINV 1101 0101 0000 0 000 0100 0000 000 11111 231XAFLAG 1101 0101 0000 0 000 0100 0000 001 11111 232AXFLAG 1101 0101 0000 0 000 0100 0000 010 11111 233 234# These are architecturally all "MSR (immediate)"; we decode the destination 235# register too because there is no commonality in our implementation. 236@msr_i .... .... .... . ... .... imm:4 ... ..... 237MSR_i_UAO 1101 0101 0000 0 000 0100 .... 011 11111 @msr_i 238MSR_i_PAN 1101 0101 0000 0 000 0100 .... 100 11111 @msr_i 239MSR_i_SPSEL 1101 0101 0000 0 000 0100 .... 101 11111 @msr_i 240MSR_i_SBSS 1101 0101 0000 0 011 0100 .... 001 11111 @msr_i 241MSR_i_DIT 1101 0101 0000 0 011 0100 .... 010 11111 @msr_i 242MSR_i_TCO 1101 0101 0000 0 011 0100 .... 100 11111 @msr_i 243MSR_i_DAIFSET 1101 0101 0000 0 011 0100 .... 110 11111 @msr_i 244MSR_i_DAIFCLEAR 1101 0101 0000 0 011 0100 .... 111 11111 @msr_i 245MSR_i_ALLINT 1101 0101 0000 0 001 0100 000 imm:1 000 11111 246MSR_i_SVCR 1101 0101 0000 0 011 0100 0 mask:2 imm:1 011 11111 247 248# MRS, MSR (register), SYS, SYSL. These are all essentially the 249# same instruction as far as QEMU is concerned. 250# NB: op0 is bits [20:19], but op0=0b00 is other insns, so we have 251# to hand-decode it. 252SYS 1101 0101 00 l:1 01 op1:3 crn:4 crm:4 op2:3 rt:5 op0=1 253SYS 1101 0101 00 l:1 10 op1:3 crn:4 crm:4 op2:3 rt:5 op0=2 254SYS 1101 0101 00 l:1 11 op1:3 crn:4 crm:4 op2:3 rt:5 op0=3 255 256# Exception generation 257 258@i16 .... .... ... imm:16 ... .. &i 259SVC 1101 0100 000 ................ 000 01 @i16 260HVC 1101 0100 000 ................ 000 10 @i16 261SMC 1101 0100 000 ................ 000 11 @i16 262BRK 1101 0100 001 ................ 000 00 @i16 263HLT 1101 0100 010 ................ 000 00 @i16 264# These insns always UNDEF unless in halting debug state, which 265# we don't implement. So we don't need to decode them. The patterns 266# are listed here as documentation. 267# DCPS1 1101 0100 101 ................ 000 01 @i16 268# DCPS2 1101 0100 101 ................ 000 10 @i16 269# DCPS3 1101 0100 101 ................ 000 11 @i16 270 271# Loads and stores 272 273&stxr rn rt rt2 rs sz lasr 274&stlr rn rt sz lasr 275@stxr sz:2 ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr 276@stlr sz:2 ...... ... ..... lasr:1 ..... rn:5 rt:5 &stlr 277%imm1_30_p2 30:1 !function=plus_2 278@stxp .. ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr sz=%imm1_30_p2 279STXR .. 001000 000 ..... . ..... ..... ..... @stxr # inc STLXR 280LDXR .. 001000 010 ..... . ..... ..... ..... @stxr # inc LDAXR 281STLR .. 001000 100 11111 . 11111 ..... ..... @stlr # inc STLLR 282LDAR .. 001000 110 11111 . 11111 ..... ..... @stlr # inc LDLAR 283 284STXP 1 . 001000 001 ..... . ..... ..... ..... @stxp # inc STLXP 285LDXP 1 . 001000 011 ..... . ..... ..... ..... @stxp # inc LDAXP 286 287# CASP, CASPA, CASPAL, CASPL (we don't decode the bits that determine 288# acquire/release semantics because QEMU's cmpxchg always has those) 289CASP 0 . 001000 0 - 1 rs:5 - 11111 rn:5 rt:5 sz=%imm1_30_p2 290# CAS, CASA, CASAL, CASL 291CAS sz:2 001000 1 - 1 rs:5 - 11111 rn:5 rt:5 292 293&ldlit rt imm sz sign 294@ldlit .. ... . .. ................... rt:5 &ldlit imm=%imm19 295 296LD_lit 00 011 0 00 ................... ..... @ldlit sz=2 sign=0 297LD_lit 01 011 0 00 ................... ..... @ldlit sz=3 sign=0 298LD_lit 10 011 0 00 ................... ..... @ldlit sz=2 sign=1 299LD_lit_v 00 011 1 00 ................... ..... @ldlit sz=2 sign=0 300LD_lit_v 01 011 1 00 ................... ..... @ldlit sz=3 sign=0 301LD_lit_v 10 011 1 00 ................... ..... @ldlit sz=4 sign=0 302 303# PRFM 304NOP 11 011 0 00 ------------------- ----- 305 306&ldstpair rt2 rt rn imm sz sign w p 307@ldstpair .. ... . ... . imm:s7 rt2:5 rn:5 rt:5 &ldstpair 308 309# STNP, LDNP: Signed offset, non-temporal hint. We don't emulate caches 310# so we ignore hints about data access patterns, and handle these like 311# plain signed offset. 312STP 00 101 0 000 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 313LDP 00 101 0 000 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 314STP 10 101 0 000 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 315LDP 10 101 0 000 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 316STP_v 00 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 317LDP_v 00 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 318STP_v 01 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 319LDP_v 01 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 320STP_v 10 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 321LDP_v 10 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 322 323# STP and LDP: post-indexed 324STP 00 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 325LDP 00 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 326LDP 01 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=1 w=1 327STP 10 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 328LDP 10 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 329STP_v 00 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 330LDP_v 00 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 331STP_v 01 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 332LDP_v 01 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 333STP_v 10 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=1 w=1 334LDP_v 10 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=1 w=1 335 336# STP and LDP: offset 337STP 00 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 338LDP 00 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 339LDP 01 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=0 w=0 340STP 10 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 341LDP 10 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 342STP_v 00 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 343LDP_v 00 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 344STP_v 01 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 345LDP_v 01 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 346STP_v 10 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 347LDP_v 10 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 348 349# STP and LDP: pre-indexed 350STP 00 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 351LDP 00 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 352LDP 01 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=0 w=1 353STP 10 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 354LDP 10 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 355STP_v 00 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 356LDP_v 00 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 357STP_v 01 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 358LDP_v 01 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 359STP_v 10 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=1 360LDP_v 10 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=1 361 362# STGP: store tag and pair 363STGP 01 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 364STGP 01 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 365STGP 01 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 366 367# Load/store register (unscaled immediate) 368&ldst_imm rt rn imm sz sign w p unpriv ext 369@ldst_imm .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=0 370@ldst_imm_pre .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=1 371@ldst_imm_post .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=1 w=1 372@ldst_imm_user .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=1 p=0 w=0 373 374STR_i sz:2 111 0 00 00 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 375LDR_i 00 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=0 376LDR_i 01 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=1 377LDR_i 10 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=2 378LDR_i 11 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=3 379LDR_i 00 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=0 380LDR_i 01 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=1 381LDR_i 10 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=2 382LDR_i 00 111 0 00 11 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=1 sz=0 383LDR_i 01 111 0 00 11 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=1 sz=1 384 385STR_i sz:2 111 0 00 00 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 386LDR_i 00 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=0 387LDR_i 01 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=1 388LDR_i 10 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=2 389LDR_i 11 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=3 390LDR_i 00 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=0 391LDR_i 01 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=1 392LDR_i 10 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=2 393LDR_i 00 111 0 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=1 sz=0 394LDR_i 01 111 0 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=1 sz=1 395 396STR_i sz:2 111 0 00 00 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=0 397LDR_i 00 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=0 398LDR_i 01 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=1 399LDR_i 10 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=2 400LDR_i 11 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=0 sz=3 401LDR_i 00 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=0 402LDR_i 01 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=1 403LDR_i 10 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=2 404LDR_i 00 111 0 00 11 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=1 sz=0 405LDR_i 01 111 0 00 11 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=1 sz=1 406 407STR_i sz:2 111 0 00 00 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 408LDR_i 00 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=0 409LDR_i 01 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=1 410LDR_i 10 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=2 411LDR_i 11 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=3 412LDR_i 00 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=0 413LDR_i 01 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=1 414LDR_i 10 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=2 415LDR_i 00 111 0 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=1 sz=0 416LDR_i 01 111 0 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=1 sz=1 417 418# PRFM : prefetch memory: a no-op for QEMU 419NOP 11 111 0 00 10 0 --------- 00 ----- ----- 420 421STR_v_i sz:2 111 1 00 00 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 422STR_v_i 00 111 1 00 10 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=4 423LDR_v_i sz:2 111 1 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 424LDR_v_i 00 111 1 00 11 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=4 425 426STR_v_i sz:2 111 1 00 00 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 427STR_v_i 00 111 1 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=4 428LDR_v_i sz:2 111 1 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 429LDR_v_i 00 111 1 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=4 430 431STR_v_i sz:2 111 1 00 00 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 432STR_v_i 00 111 1 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=4 433LDR_v_i sz:2 111 1 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 434LDR_v_i 00 111 1 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=4 435 436# Load/store with an unsigned 12 bit immediate, which is scaled by the 437# element size. The function gets the sz:imm and returns the scaled immediate. 438%uimm_scaled 10:12 sz:3 !function=uimm_scaled 439 440@ldst_uimm .. ... . .. .. ............ rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=0 imm=%uimm_scaled 441 442STR_i sz:2 111 0 01 00 ............ ..... ..... @ldst_uimm sign=0 ext=0 443LDR_i 00 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=0 444LDR_i 01 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=1 445LDR_i 10 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=2 446LDR_i 11 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=3 447LDR_i 00 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=0 448LDR_i 01 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=1 449LDR_i 10 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=2 450LDR_i 00 111 0 01 11 ............ ..... ..... @ldst_uimm sign=1 ext=1 sz=0 451LDR_i 01 111 0 01 11 ............ ..... ..... @ldst_uimm sign=1 ext=1 sz=1 452 453# PRFM 454NOP 11 111 0 01 10 ------------ ----- ----- 455 456STR_v_i sz:2 111 1 01 00 ............ ..... ..... @ldst_uimm sign=0 ext=0 457STR_v_i 00 111 1 01 10 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=4 458LDR_v_i sz:2 111 1 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=0 459LDR_v_i 00 111 1 01 11 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=4 460 461# Load/store with register offset 462&ldst rm rn rt sign ext sz opt s 463@ldst .. ... . .. .. . rm:5 opt:3 s:1 .. rn:5 rt:5 &ldst 464STR sz:2 111 0 00 00 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 465LDR 00 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=0 466LDR 01 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=1 467LDR 10 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=2 468LDR 11 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=3 469LDR 00 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=0 470LDR 01 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=1 471LDR 10 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=2 472LDR 00 111 0 00 11 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=1 sz=0 473LDR 01 111 0 00 11 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=1 sz=1 474 475# PRFM 476NOP 11 111 0 00 10 1 ----- -1- - 10 ----- ----- 477 478STR_v sz:2 111 1 00 00 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 479STR_v 00 111 1 00 10 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=4 480LDR_v sz:2 111 1 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 481LDR_v 00 111 1 00 11 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=4 482 483# Atomic memory operations 484&atomic rs rn rt a r sz 485@atomic sz:2 ... . .. a:1 r:1 . rs:5 . ... .. rn:5 rt:5 &atomic 486LDADD .. 111 0 00 . . 1 ..... 0000 00 ..... ..... @atomic 487LDCLR .. 111 0 00 . . 1 ..... 0001 00 ..... ..... @atomic 488LDEOR .. 111 0 00 . . 1 ..... 0010 00 ..... ..... @atomic 489LDSET .. 111 0 00 . . 1 ..... 0011 00 ..... ..... @atomic 490LDSMAX .. 111 0 00 . . 1 ..... 0100 00 ..... ..... @atomic 491LDSMIN .. 111 0 00 . . 1 ..... 0101 00 ..... ..... @atomic 492LDUMAX .. 111 0 00 . . 1 ..... 0110 00 ..... ..... @atomic 493LDUMIN .. 111 0 00 . . 1 ..... 0111 00 ..... ..... @atomic 494SWP .. 111 0 00 . . 1 ..... 1000 00 ..... ..... @atomic 495 496LDAPR sz:2 111 0 00 1 0 1 11111 1100 00 rn:5 rt:5 497 498# Load/store register (pointer authentication) 499 500# LDRA immediate is 10 bits signed and scaled, but the bits aren't all contiguous 501%ldra_imm 22:s1 12:9 !function=times_8 502 503LDRA 11 111 0 00 m:1 . 1 ......... w:1 1 rn:5 rt:5 imm=%ldra_imm 504 505&ldapr_stlr_i rn rt imm sz sign ext 506@ldapr_stlr_i .. ...... .. . imm:9 .. rn:5 rt:5 &ldapr_stlr_i 507STLR_i sz:2 011001 00 0 ......... 00 ..... ..... @ldapr_stlr_i sign=0 ext=0 508LDAPR_i sz:2 011001 01 0 ......... 00 ..... ..... @ldapr_stlr_i sign=0 ext=0 509LDAPR_i 00 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=0 510LDAPR_i 01 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=1 511LDAPR_i 10 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=2 512LDAPR_i 00 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=1 sz=0 513LDAPR_i 01 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=1 sz=1 514 515# Load/store multiple structures 516# The 4-bit opcode in [15:12] encodes repeat count and structure elements 517&ldst_mult rm rn rt sz q p rpt selem 518@ldst_mult . q:1 ...... p:1 . . rm:5 .... sz:2 rn:5 rt:5 &ldst_mult 519ST_mult 0 . 001100 . 0 0 ..... 0000 .. ..... ..... @ldst_mult rpt=1 selem=4 520ST_mult 0 . 001100 . 0 0 ..... 0010 .. ..... ..... @ldst_mult rpt=4 selem=1 521ST_mult 0 . 001100 . 0 0 ..... 0100 .. ..... ..... @ldst_mult rpt=1 selem=3 522ST_mult 0 . 001100 . 0 0 ..... 0110 .. ..... ..... @ldst_mult rpt=3 selem=1 523ST_mult 0 . 001100 . 0 0 ..... 0111 .. ..... ..... @ldst_mult rpt=1 selem=1 524ST_mult 0 . 001100 . 0 0 ..... 1000 .. ..... ..... @ldst_mult rpt=1 selem=2 525ST_mult 0 . 001100 . 0 0 ..... 1010 .. ..... ..... @ldst_mult rpt=2 selem=1 526 527LD_mult 0 . 001100 . 1 0 ..... 0000 .. ..... ..... @ldst_mult rpt=1 selem=4 528LD_mult 0 . 001100 . 1 0 ..... 0010 .. ..... ..... @ldst_mult rpt=4 selem=1 529LD_mult 0 . 001100 . 1 0 ..... 0100 .. ..... ..... @ldst_mult rpt=1 selem=3 530LD_mult 0 . 001100 . 1 0 ..... 0110 .. ..... ..... @ldst_mult rpt=3 selem=1 531LD_mult 0 . 001100 . 1 0 ..... 0111 .. ..... ..... @ldst_mult rpt=1 selem=1 532LD_mult 0 . 001100 . 1 0 ..... 1000 .. ..... ..... @ldst_mult rpt=1 selem=2 533LD_mult 0 . 001100 . 1 0 ..... 1010 .. ..... ..... @ldst_mult rpt=2 selem=1 534 535# Load/store single structure 536&ldst_single rm rn rt p selem index scale 537 538%ldst_single_selem 13:1 21:1 !function=plus_1 539 540%ldst_single_index_b 30:1 10:3 541%ldst_single_index_h 30:1 11:2 542%ldst_single_index_s 30:1 12:1 543 544@ldst_single_b .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \ 545 &ldst_single scale=0 selem=%ldst_single_selem \ 546 index=%ldst_single_index_b 547@ldst_single_h .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \ 548 &ldst_single scale=1 selem=%ldst_single_selem \ 549 index=%ldst_single_index_h 550@ldst_single_s .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \ 551 &ldst_single scale=2 selem=%ldst_single_selem \ 552 index=%ldst_single_index_s 553@ldst_single_d . index:1 ...... p:1 .. rm:5 ...... rn:5 rt:5 \ 554 &ldst_single scale=3 selem=%ldst_single_selem 555 556ST_single 0 . 001101 . 0 . ..... 00 . ... ..... ..... @ldst_single_b 557ST_single 0 . 001101 . 0 . ..... 01 . ..0 ..... ..... @ldst_single_h 558ST_single 0 . 001101 . 0 . ..... 10 . .00 ..... ..... @ldst_single_s 559ST_single 0 . 001101 . 0 . ..... 10 . 001 ..... ..... @ldst_single_d 560 561LD_single 0 . 001101 . 1 . ..... 00 . ... ..... ..... @ldst_single_b 562LD_single 0 . 001101 . 1 . ..... 01 . ..0 ..... ..... @ldst_single_h 563LD_single 0 . 001101 . 1 . ..... 10 . .00 ..... ..... @ldst_single_s 564LD_single 0 . 001101 . 1 . ..... 10 . 001 ..... ..... @ldst_single_d 565 566# Replicating load case 567LD_single_repl 0 q:1 001101 p:1 1 . rm:5 11 . 0 scale:2 rn:5 rt:5 selem=%ldst_single_selem 568 569%tag_offset 12:s9 !function=scale_by_log2_tag_granule 570&ldst_tag rn rt imm p w 571@ldst_tag ........ .. . ......... .. rn:5 rt:5 &ldst_tag imm=%tag_offset 572@ldst_tag_mult ........ .. . 000000000 .. rn:5 rt:5 &ldst_tag imm=0 573 574STZGM 11011001 00 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0 575STG 11011001 00 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 576STG 11011001 00 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 577STG 11011001 00 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 578 579LDG 11011001 01 1 ......... 00 ..... ..... @ldst_tag p=0 w=0 580STZG 11011001 01 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 581STZG 11011001 01 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 582STZG 11011001 01 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 583 584STGM 11011001 10 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0 585ST2G 11011001 10 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 586ST2G 11011001 10 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 587ST2G 11011001 10 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 588 589LDGM 11011001 11 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0 590STZ2G 11011001 11 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 591STZ2G 11011001 11 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 592STZ2G 11011001 11 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 593 594# Memory operations (memset, memcpy, memmove) 595# Each of these comes in a set of three, eg SETP (prologue), SETM (main), 596# SETE (epilogue), and each of those has different flavours to 597# indicate whether memory accesses should be unpriv or non-temporal. 598# We don't distinguish temporal and non-temporal accesses, but we 599# do need to report it in syndrome register values. 600 601# Memset 602&set rs rn rd unpriv nontemp 603# op2 bit 1 is nontemporal bit 604@set .. ......... rs:5 .. nontemp:1 unpriv:1 .. rn:5 rd:5 &set 605 606SETP 00 011001110 ..... 00 . . 01 ..... ..... @set 607SETM 00 011001110 ..... 01 . . 01 ..... ..... @set 608SETE 00 011001110 ..... 10 . . 01 ..... ..... @set 609 610# Like SET, but also setting MTE tags 611SETGP 00 011101110 ..... 00 . . 01 ..... ..... @set 612SETGM 00 011101110 ..... 01 . . 01 ..... ..... @set 613SETGE 00 011101110 ..... 10 . . 01 ..... ..... @set 614 615# Memmove/Memcopy: the CPY insns allow overlapping src/dest and 616# copy in the correct direction; the CPYF insns always copy forwards. 617# 618# options has the nontemporal and unpriv bits for src and dest 619&cpy rs rn rd options 620@cpy .. ... . ..... rs:5 options:4 .. rn:5 rd:5 &cpy 621 622CPYFP 00 011 0 01000 ..... .... 01 ..... ..... @cpy 623CPYFM 00 011 0 01010 ..... .... 01 ..... ..... @cpy 624CPYFE 00 011 0 01100 ..... .... 01 ..... ..... @cpy 625CPYP 00 011 1 01000 ..... .... 01 ..... ..... @cpy 626CPYM 00 011 1 01010 ..... .... 01 ..... ..... @cpy 627CPYE 00 011 1 01100 ..... .... 01 ..... ..... @cpy 628 629### Cryptographic AES 630 631AESE 01001110 00 10100 00100 10 ..... ..... @r2r_q1e0 632AESD 01001110 00 10100 00101 10 ..... ..... @r2r_q1e0 633AESMC 01001110 00 10100 00110 10 ..... ..... @rr_q1e0 634AESIMC 01001110 00 10100 00111 10 ..... ..... @rr_q1e0 635 636### Cryptographic three-register SHA 637 638SHA1C 0101 1110 000 ..... 000000 ..... ..... @rrr_q1e0 639SHA1P 0101 1110 000 ..... 000100 ..... ..... @rrr_q1e0 640SHA1M 0101 1110 000 ..... 001000 ..... ..... @rrr_q1e0 641SHA1SU0 0101 1110 000 ..... 001100 ..... ..... @rrr_q1e0 642SHA256H 0101 1110 000 ..... 010000 ..... ..... @rrr_q1e0 643SHA256H2 0101 1110 000 ..... 010100 ..... ..... @rrr_q1e0 644SHA256SU1 0101 1110 000 ..... 011000 ..... ..... @rrr_q1e0 645 646### Cryptographic two-register SHA 647 648SHA1H 0101 1110 0010 1000 0000 10 ..... ..... @rr_q1e0 649SHA1SU1 0101 1110 0010 1000 0001 10 ..... ..... @rr_q1e0 650SHA256SU0 0101 1110 0010 1000 0010 10 ..... ..... @rr_q1e0 651 652### Cryptographic three-register SHA512 653 654SHA512H 1100 1110 011 ..... 100000 ..... ..... @rrr_q1e0 655SHA512H2 1100 1110 011 ..... 100001 ..... ..... @rrr_q1e0 656SHA512SU1 1100 1110 011 ..... 100010 ..... ..... @rrr_q1e0 657RAX1 1100 1110 011 ..... 100011 ..... ..... @rrr_q1e3 658SM3PARTW1 1100 1110 011 ..... 110000 ..... ..... @rrr_q1e0 659SM3PARTW2 1100 1110 011 ..... 110001 ..... ..... @rrr_q1e0 660SM4EKEY 1100 1110 011 ..... 110010 ..... ..... @rrr_q1e0 661 662### Cryptographic two-register SHA512 663 664SHA512SU0 1100 1110 110 00000 100000 ..... ..... @rr_q1e0 665SM4E 1100 1110 110 00000 100001 ..... ..... @r2r_q1e0 666 667### Cryptographic four-register 668 669EOR3 1100 1110 000 ..... 0 ..... ..... ..... @rrrr_q1e3 670BCAX 1100 1110 001 ..... 0 ..... ..... ..... @rrrr_q1e3 671SM3SS1 1100 1110 010 ..... 0 ..... ..... ..... @rrrr_q1e3 672 673### Cryptographic three-register, imm2 674 675&crypto3i rd rn rm imm 676@crypto3i ........ ... rm:5 .. imm:2 .. rn:5 rd:5 &crypto3i 677 678SM3TT1A 11001110 010 ..... 10 .. 00 ..... ..... @crypto3i 679SM3TT1B 11001110 010 ..... 10 .. 01 ..... ..... @crypto3i 680SM3TT2A 11001110 010 ..... 10 .. 10 ..... ..... @crypto3i 681SM3TT2B 11001110 010 ..... 10 .. 11 ..... ..... @crypto3i 682 683### Cryptographic XAR 684 685XAR 1100 1110 100 rm:5 imm:6 rn:5 rd:5 686 687### Advanced SIMD scalar copy 688 689DUP_element_s 0101 1110 000 imm:5 0 0000 1 rn:5 rd:5 690 691### Advanced SIMD copy 692 693DUP_element_v 0 q:1 00 1110 000 imm:5 0 0000 1 rn:5 rd:5 694DUP_general 0 q:1 00 1110 000 imm:5 0 0001 1 rn:5 rd:5 695INS_general 0 1 00 1110 000 imm:5 0 0011 1 rn:5 rd:5 696SMOV 0 q:1 00 1110 000 imm:5 0 0101 1 rn:5 rd:5 697UMOV 0 q:1 00 1110 000 imm:5 0 0111 1 rn:5 rd:5 698INS_element 0 1 10 1110 000 di:5 0 si:4 1 rn:5 rd:5 699 700### Advanced SIMD scalar three same 701 702FADD_s 0001 1110 ..1 ..... 0010 10 ..... ..... @rrr_hsd 703FSUB_s 0001 1110 ..1 ..... 0011 10 ..... ..... @rrr_hsd 704FDIV_s 0001 1110 ..1 ..... 0001 10 ..... ..... @rrr_hsd 705FMUL_s 0001 1110 ..1 ..... 0000 10 ..... ..... @rrr_hsd 706FNMUL_s 0001 1110 ..1 ..... 1000 10 ..... ..... @rrr_hsd 707 708FMAX_s 0001 1110 ..1 ..... 0100 10 ..... ..... @rrr_hsd 709FMIN_s 0001 1110 ..1 ..... 0101 10 ..... ..... @rrr_hsd 710FMAXNM_s 0001 1110 ..1 ..... 0110 10 ..... ..... @rrr_hsd 711FMINNM_s 0001 1110 ..1 ..... 0111 10 ..... ..... @rrr_hsd 712 713FMULX_s 0101 1110 010 ..... 00011 1 ..... ..... @rrr_h 714FMULX_s 0101 1110 0.1 ..... 11011 1 ..... ..... @rrr_sd 715 716FCMEQ_s 0101 1110 010 ..... 00100 1 ..... ..... @rrr_h 717FCMEQ_s 0101 1110 0.1 ..... 11100 1 ..... ..... @rrr_sd 718 719FCMGE_s 0111 1110 010 ..... 00100 1 ..... ..... @rrr_h 720FCMGE_s 0111 1110 0.1 ..... 11100 1 ..... ..... @rrr_sd 721 722FCMGT_s 0111 1110 110 ..... 00100 1 ..... ..... @rrr_h 723FCMGT_s 0111 1110 1.1 ..... 11100 1 ..... ..... @rrr_sd 724 725FACGE_s 0111 1110 010 ..... 00101 1 ..... ..... @rrr_h 726FACGE_s 0111 1110 0.1 ..... 11101 1 ..... ..... @rrr_sd 727 728FACGT_s 0111 1110 110 ..... 00101 1 ..... ..... @rrr_h 729FACGT_s 0111 1110 1.1 ..... 11101 1 ..... ..... @rrr_sd 730 731FABD_s 0111 1110 110 ..... 00010 1 ..... ..... @rrr_h 732FABD_s 0111 1110 1.1 ..... 11010 1 ..... ..... @rrr_sd 733 734### Advanced SIMD three same 735 736FADD_v 0.00 1110 010 ..... 00010 1 ..... ..... @qrrr_h 737FADD_v 0.00 1110 0.1 ..... 11010 1 ..... ..... @qrrr_sd 738 739FSUB_v 0.00 1110 110 ..... 00010 1 ..... ..... @qrrr_h 740FSUB_v 0.00 1110 1.1 ..... 11010 1 ..... ..... @qrrr_sd 741 742FDIV_v 0.10 1110 010 ..... 00111 1 ..... ..... @qrrr_h 743FDIV_v 0.10 1110 0.1 ..... 11111 1 ..... ..... @qrrr_sd 744 745FMUL_v 0.10 1110 010 ..... 00011 1 ..... ..... @qrrr_h 746FMUL_v 0.10 1110 0.1 ..... 11011 1 ..... ..... @qrrr_sd 747 748FMAX_v 0.00 1110 010 ..... 00110 1 ..... ..... @qrrr_h 749FMAX_v 0.00 1110 0.1 ..... 11110 1 ..... ..... @qrrr_sd 750 751FMIN_v 0.00 1110 110 ..... 00110 1 ..... ..... @qrrr_h 752FMIN_v 0.00 1110 1.1 ..... 11110 1 ..... ..... @qrrr_sd 753 754FMAXNM_v 0.00 1110 010 ..... 00000 1 ..... ..... @qrrr_h 755FMAXNM_v 0.00 1110 0.1 ..... 11000 1 ..... ..... @qrrr_sd 756 757FMINNM_v 0.00 1110 110 ..... 00000 1 ..... ..... @qrrr_h 758FMINNM_v 0.00 1110 1.1 ..... 11000 1 ..... ..... @qrrr_sd 759 760FMULX_v 0.00 1110 010 ..... 00011 1 ..... ..... @qrrr_h 761FMULX_v 0.00 1110 0.1 ..... 11011 1 ..... ..... @qrrr_sd 762 763FMLA_v 0.00 1110 010 ..... 00001 1 ..... ..... @qrrr_h 764FMLA_v 0.00 1110 0.1 ..... 11001 1 ..... ..... @qrrr_sd 765 766FMLS_v 0.00 1110 110 ..... 00001 1 ..... ..... @qrrr_h 767FMLS_v 0.00 1110 1.1 ..... 11001 1 ..... ..... @qrrr_sd 768 769FCMEQ_v 0.00 1110 010 ..... 00100 1 ..... ..... @qrrr_h 770FCMEQ_v 0.00 1110 0.1 ..... 11100 1 ..... ..... @qrrr_sd 771 772FCMGE_v 0.10 1110 010 ..... 00100 1 ..... ..... @qrrr_h 773FCMGE_v 0.10 1110 0.1 ..... 11100 1 ..... ..... @qrrr_sd 774 775FCMGT_v 0.10 1110 110 ..... 00100 1 ..... ..... @qrrr_h 776FCMGT_v 0.10 1110 1.1 ..... 11100 1 ..... ..... @qrrr_sd 777 778FACGE_v 0.10 1110 010 ..... 00101 1 ..... ..... @qrrr_h 779FACGE_v 0.10 1110 0.1 ..... 11101 1 ..... ..... @qrrr_sd 780 781FACGT_v 0.10 1110 110 ..... 00101 1 ..... ..... @qrrr_h 782FACGT_v 0.10 1110 1.1 ..... 11101 1 ..... ..... @qrrr_sd 783 784FABD_v 0.10 1110 110 ..... 00010 1 ..... ..... @qrrr_h 785FABD_v 0.10 1110 1.1 ..... 11010 1 ..... ..... @qrrr_sd 786 787### Advanced SIMD scalar x indexed element 788 789FMUL_si 0101 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h 790FMUL_si 0101 1111 10 . ..... 1001 . 0 ..... ..... @rrx_s 791FMUL_si 0101 1111 11 0 ..... 1001 . 0 ..... ..... @rrx_d 792 793FMLA_si 0101 1111 00 .. .... 0001 . 0 ..... ..... @rrx_h 794FMLA_si 0101 1111 10 .. .... 0001 . 0 ..... ..... @rrx_s 795FMLA_si 0101 1111 11 0. .... 0001 . 0 ..... ..... @rrx_d 796 797FMLS_si 0101 1111 00 .. .... 0101 . 0 ..... ..... @rrx_h 798FMLS_si 0101 1111 10 .. .... 0101 . 0 ..... ..... @rrx_s 799FMLS_si 0101 1111 11 0. .... 0101 . 0 ..... ..... @rrx_d 800 801FMULX_si 0111 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h 802FMULX_si 0111 1111 10 . ..... 1001 . 0 ..... ..... @rrx_s 803FMULX_si 0111 1111 11 0 ..... 1001 . 0 ..... ..... @rrx_d 804 805### Advanced SIMD vector x indexed element 806 807FMUL_vi 0.00 1111 00 .. .... 1001 . 0 ..... ..... @qrrx_h 808FMUL_vi 0.00 1111 10 . ..... 1001 . 0 ..... ..... @qrrx_s 809FMUL_vi 0.00 1111 11 0 ..... 1001 . 0 ..... ..... @qrrx_d 810 811FMLA_vi 0.00 1111 00 .. .... 0001 . 0 ..... ..... @qrrx_h 812FMLA_vi 0.00 1111 10 . ..... 0001 . 0 ..... ..... @qrrx_s 813FMLA_vi 0.00 1111 11 0 ..... 0001 . 0 ..... ..... @qrrx_d 814 815FMLS_vi 0.00 1111 00 .. .... 0101 . 0 ..... ..... @qrrx_h 816FMLS_vi 0.00 1111 10 . ..... 0101 . 0 ..... ..... @qrrx_s 817FMLS_vi 0.00 1111 11 0 ..... 0101 . 0 ..... ..... @qrrx_d 818 819FMULX_vi 0.10 1111 00 .. .... 1001 . 0 ..... ..... @qrrx_h 820FMULX_vi 0.10 1111 10 . ..... 1001 . 0 ..... ..... @qrrx_s 821FMULX_vi 0.10 1111 11 0 ..... 1001 . 0 ..... ..... @qrrx_d 822