1# AArch64 A64 allowed instruction decoding 2# 3# Copyright (c) 2023 Linaro, Ltd 4# 5# This library is free software; you can redistribute it and/or 6# modify it under the terms of the GNU Lesser General Public 7# License as published by the Free Software Foundation; either 8# version 2.1 of the License, or (at your option) any later version. 9# 10# This library is distributed in the hope that it will be useful, 11# but WITHOUT ANY WARRANTY; without even the implied warranty of 12# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13# Lesser General Public License for more details. 14# 15# You should have received a copy of the GNU Lesser General Public 16# License along with this library; if not, see <http://www.gnu.org/licenses/>. 17 18# 19# This file is processed by scripts/decodetree.py 20# 21 22&r rn 23&ri rd imm 24&rri_sf rd rn imm sf 25&i imm 26 27 28### Data Processing - Immediate 29 30# PC-rel addressing 31 32%imm_pcrel 5:s19 29:2 33@pcrel . .. ..... ................... rd:5 &ri imm=%imm_pcrel 34 35ADR 0 .. 10000 ................... ..... @pcrel 36ADRP 1 .. 10000 ................... ..... @pcrel 37 38# Add/subtract (immediate) 39 40%imm12_sh12 10:12 !function=shl_12 41@addsub_imm sf:1 .. ...... . imm:12 rn:5 rd:5 42@addsub_imm12 sf:1 .. ...... . ............ rn:5 rd:5 imm=%imm12_sh12 43 44ADD_i . 00 100010 0 ............ ..... ..... @addsub_imm 45ADD_i . 00 100010 1 ............ ..... ..... @addsub_imm12 46ADDS_i . 01 100010 0 ............ ..... ..... @addsub_imm 47ADDS_i . 01 100010 1 ............ ..... ..... @addsub_imm12 48 49SUB_i . 10 100010 0 ............ ..... ..... @addsub_imm 50SUB_i . 10 100010 1 ............ ..... ..... @addsub_imm12 51SUBS_i . 11 100010 0 ............ ..... ..... @addsub_imm 52SUBS_i . 11 100010 1 ............ ..... ..... @addsub_imm12 53 54# Add/subtract (immediate with tags) 55 56&rri_tag rd rn uimm6 uimm4 57@addsub_imm_tag . .. ...... . uimm6:6 .. uimm4:4 rn:5 rd:5 &rri_tag 58 59ADDG_i 1 00 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag 60SUBG_i 1 10 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag 61 62# Logical (immediate) 63 64&rri_log rd rn sf dbm 65@logic_imm_64 1 .. ...... dbm:13 rn:5 rd:5 &rri_log sf=1 66@logic_imm_32 0 .. ...... 0 dbm:12 rn:5 rd:5 &rri_log sf=0 67 68AND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_64 69AND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_32 70ORR_i . 01 100100 . ...... ...... ..... ..... @logic_imm_64 71ORR_i . 01 100100 . ...... ...... ..... ..... @logic_imm_32 72EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_64 73EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_32 74ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_64 75ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_32 76 77# Move wide (immediate) 78 79&movw rd sf imm hw 80@movw_64 1 .. ...... hw:2 imm:16 rd:5 &movw sf=1 81@movw_32 0 .. ...... 0 hw:1 imm:16 rd:5 &movw sf=0 82 83MOVN . 00 100101 .. ................ ..... @movw_64 84MOVN . 00 100101 .. ................ ..... @movw_32 85MOVZ . 10 100101 .. ................ ..... @movw_64 86MOVZ . 10 100101 .. ................ ..... @movw_32 87MOVK . 11 100101 .. ................ ..... @movw_64 88MOVK . 11 100101 .. ................ ..... @movw_32 89 90# Bitfield 91 92&bitfield rd rn sf immr imms 93@bitfield_64 1 .. ...... 1 immr:6 imms:6 rn:5 rd:5 &bitfield sf=1 94@bitfield_32 0 .. ...... 0 0 immr:5 0 imms:5 rn:5 rd:5 &bitfield sf=0 95 96SBFM . 00 100110 . ...... ...... ..... ..... @bitfield_64 97SBFM . 00 100110 . ...... ...... ..... ..... @bitfield_32 98BFM . 01 100110 . ...... ...... ..... ..... @bitfield_64 99BFM . 01 100110 . ...... ...... ..... ..... @bitfield_32 100UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_64 101UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_32 102 103# Extract 104 105&extract rd rn rm imm sf 106 107EXTR 1 00 100111 1 0 rm:5 imm:6 rn:5 rd:5 &extract sf=1 108EXTR 0 00 100111 0 0 rm:5 0 imm:5 rn:5 rd:5 &extract sf=0 109 110# Branches 111 112%imm26 0:s26 !function=times_4 113@branch . ..... .......................... &i imm=%imm26 114 115B 0 00101 .......................... @branch 116BL 1 00101 .......................... @branch 117 118%imm19 5:s19 !function=times_4 119&cbz rt imm sf nz 120 121CBZ sf:1 011010 nz:1 ................... rt:5 &cbz imm=%imm19 122 123%imm14 5:s14 !function=times_4 124%imm31_19 31:1 19:5 125&tbz rt imm nz bitpos 126 127TBZ . 011011 nz:1 ..... .............. rt:5 &tbz imm=%imm14 bitpos=%imm31_19 128 129# B.cond and BC.cond 130B_cond 0101010 0 ................... c:1 cond:4 imm=%imm19 131 132BR 1101011 0000 11111 000000 rn:5 00000 &r 133BLR 1101011 0001 11111 000000 rn:5 00000 &r 134RET 1101011 0010 11111 000000 rn:5 00000 &r 135 136&braz rn m 137BRAZ 1101011 0000 11111 00001 m:1 rn:5 11111 &braz # BRAAZ, BRABZ 138BLRAZ 1101011 0001 11111 00001 m:1 rn:5 11111 &braz # BLRAAZ, BLRABZ 139 140&reta m 141RETA 1101011 0010 11111 00001 m:1 11111 11111 &reta # RETAA, RETAB 142 143&bra rn rm m 144BRA 1101011 1000 11111 00001 m:1 rn:5 rm:5 &bra # BRAA, BRAB 145BLRA 1101011 1001 11111 00001 m:1 rn:5 rm:5 &bra # BLRAA, BLRAB 146 147ERET 1101011 0100 11111 000000 11111 00000 148ERETA 1101011 0100 11111 00001 m:1 11111 11111 &reta # ERETAA, ERETAB 149 150# We don't need to decode DRPS because it always UNDEFs except when 151# the processor is in halting debug state (which we don't implement). 152# The pattern is listed here as documentation. 153# DRPS 1101011 0101 11111 000000 11111 00000 154 155# Hint instruction group 156{ 157 [ 158 YIELD 1101 0101 0000 0011 0010 0000 001 11111 159 WFE 1101 0101 0000 0011 0010 0000 010 11111 160 WFI 1101 0101 0000 0011 0010 0000 011 11111 161 # We implement WFE to never block, so our SEV/SEVL are NOPs 162 # SEV 1101 0101 0000 0011 0010 0000 100 11111 163 # SEVL 1101 0101 0000 0011 0010 0000 101 11111 164 # Our DGL is a NOP because we don't merge memory accesses anyway. 165 # DGL 1101 0101 0000 0011 0010 0000 110 11111 166 XPACLRI 1101 0101 0000 0011 0010 0000 111 11111 167 PACIA1716 1101 0101 0000 0011 0010 0001 000 11111 168 PACIB1716 1101 0101 0000 0011 0010 0001 010 11111 169 AUTIA1716 1101 0101 0000 0011 0010 0001 100 11111 170 AUTIB1716 1101 0101 0000 0011 0010 0001 110 11111 171 ESB 1101 0101 0000 0011 0010 0010 000 11111 172 PACIAZ 1101 0101 0000 0011 0010 0011 000 11111 173 PACIASP 1101 0101 0000 0011 0010 0011 001 11111 174 PACIBZ 1101 0101 0000 0011 0010 0011 010 11111 175 PACIBSP 1101 0101 0000 0011 0010 0011 011 11111 176 AUTIAZ 1101 0101 0000 0011 0010 0011 100 11111 177 AUTIASP 1101 0101 0000 0011 0010 0011 101 11111 178 AUTIBZ 1101 0101 0000 0011 0010 0011 110 11111 179 AUTIBSP 1101 0101 0000 0011 0010 0011 111 11111 180 ] 181 # The canonical NOP has CRm == op2 == 0, but all of the space 182 # that isn't specifically allocated to an instruction must NOP 183 NOP 1101 0101 0000 0011 0010 ---- --- 11111 184} 185 186# Barriers 187 188CLREX 1101 0101 0000 0011 0011 ---- 010 11111 189DSB_DMB 1101 0101 0000 0011 0011 domain:2 types:2 10- 11111 190ISB 1101 0101 0000 0011 0011 ---- 110 11111 191SB 1101 0101 0000 0011 0011 0000 111 11111 192 193# PSTATE 194 195CFINV 1101 0101 0000 0 000 0100 0000 000 11111 196XAFLAG 1101 0101 0000 0 000 0100 0000 001 11111 197AXFLAG 1101 0101 0000 0 000 0100 0000 010 11111 198 199# These are architecturally all "MSR (immediate)"; we decode the destination 200# register too because there is no commonality in our implementation. 201@msr_i .... .... .... . ... .... imm:4 ... ..... 202MSR_i_UAO 1101 0101 0000 0 000 0100 .... 011 11111 @msr_i 203MSR_i_PAN 1101 0101 0000 0 000 0100 .... 100 11111 @msr_i 204MSR_i_SPSEL 1101 0101 0000 0 000 0100 .... 101 11111 @msr_i 205MSR_i_SBSS 1101 0101 0000 0 011 0100 .... 001 11111 @msr_i 206MSR_i_DIT 1101 0101 0000 0 011 0100 .... 010 11111 @msr_i 207MSR_i_TCO 1101 0101 0000 0 011 0100 .... 100 11111 @msr_i 208MSR_i_DAIFSET 1101 0101 0000 0 011 0100 .... 110 11111 @msr_i 209MSR_i_DAIFCLEAR 1101 0101 0000 0 011 0100 .... 111 11111 @msr_i 210MSR_i_ALLINT 1101 0101 0000 0 001 0100 000 imm:1 000 11111 211MSR_i_SVCR 1101 0101 0000 0 011 0100 0 mask:2 imm:1 011 11111 212 213# MRS, MSR (register), SYS, SYSL. These are all essentially the 214# same instruction as far as QEMU is concerned. 215# NB: op0 is bits [20:19], but op0=0b00 is other insns, so we have 216# to hand-decode it. 217SYS 1101 0101 00 l:1 01 op1:3 crn:4 crm:4 op2:3 rt:5 op0=1 218SYS 1101 0101 00 l:1 10 op1:3 crn:4 crm:4 op2:3 rt:5 op0=2 219SYS 1101 0101 00 l:1 11 op1:3 crn:4 crm:4 op2:3 rt:5 op0=3 220 221# Exception generation 222 223@i16 .... .... ... imm:16 ... .. &i 224SVC 1101 0100 000 ................ 000 01 @i16 225HVC 1101 0100 000 ................ 000 10 @i16 226SMC 1101 0100 000 ................ 000 11 @i16 227BRK 1101 0100 001 ................ 000 00 @i16 228HLT 1101 0100 010 ................ 000 00 @i16 229# These insns always UNDEF unless in halting debug state, which 230# we don't implement. So we don't need to decode them. The patterns 231# are listed here as documentation. 232# DCPS1 1101 0100 101 ................ 000 01 @i16 233# DCPS2 1101 0100 101 ................ 000 10 @i16 234# DCPS3 1101 0100 101 ................ 000 11 @i16 235 236# Loads and stores 237 238&stxr rn rt rt2 rs sz lasr 239&stlr rn rt sz lasr 240@stxr sz:2 ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr 241@stlr sz:2 ...... ... ..... lasr:1 ..... rn:5 rt:5 &stlr 242%imm1_30_p2 30:1 !function=plus_2 243@stxp .. ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr sz=%imm1_30_p2 244STXR .. 001000 000 ..... . ..... ..... ..... @stxr # inc STLXR 245LDXR .. 001000 010 ..... . ..... ..... ..... @stxr # inc LDAXR 246STLR .. 001000 100 11111 . 11111 ..... ..... @stlr # inc STLLR 247LDAR .. 001000 110 11111 . 11111 ..... ..... @stlr # inc LDLAR 248 249STXP 1 . 001000 001 ..... . ..... ..... ..... @stxp # inc STLXP 250LDXP 1 . 001000 011 ..... . ..... ..... ..... @stxp # inc LDAXP 251 252# CASP, CASPA, CASPAL, CASPL (we don't decode the bits that determine 253# acquire/release semantics because QEMU's cmpxchg always has those) 254CASP 0 . 001000 0 - 1 rs:5 - 11111 rn:5 rt:5 sz=%imm1_30_p2 255# CAS, CASA, CASAL, CASL 256CAS sz:2 001000 1 - 1 rs:5 - 11111 rn:5 rt:5 257 258&ldlit rt imm sz sign 259@ldlit .. ... . .. ................... rt:5 &ldlit imm=%imm19 260 261LD_lit 00 011 0 00 ................... ..... @ldlit sz=2 sign=0 262LD_lit 01 011 0 00 ................... ..... @ldlit sz=3 sign=0 263LD_lit 10 011 0 00 ................... ..... @ldlit sz=2 sign=1 264LD_lit_v 00 011 1 00 ................... ..... @ldlit sz=2 sign=0 265LD_lit_v 01 011 1 00 ................... ..... @ldlit sz=3 sign=0 266LD_lit_v 10 011 1 00 ................... ..... @ldlit sz=4 sign=0 267 268# PRFM 269NOP 11 011 0 00 ------------------- ----- 270 271&ldstpair rt2 rt rn imm sz sign w p 272@ldstpair .. ... . ... . imm:s7 rt2:5 rn:5 rt:5 &ldstpair 273 274# STNP, LDNP: Signed offset, non-temporal hint. We don't emulate caches 275# so we ignore hints about data access patterns, and handle these like 276# plain signed offset. 277STP 00 101 0 000 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 278LDP 00 101 0 000 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 279STP 10 101 0 000 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 280LDP 10 101 0 000 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 281STP_v 00 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 282LDP_v 00 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 283STP_v 01 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 284LDP_v 01 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 285STP_v 10 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 286LDP_v 10 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 287 288# STP and LDP: post-indexed 289STP 00 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 290LDP 00 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 291LDP 01 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=1 w=1 292STP 10 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 293LDP 10 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 294STP_v 00 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 295LDP_v 00 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 296STP_v 01 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 297LDP_v 01 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 298STP_v 10 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=1 w=1 299LDP_v 10 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=1 w=1 300 301# STP and LDP: offset 302STP 00 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 303LDP 00 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 304LDP 01 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=0 w=0 305STP 10 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 306LDP 10 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 307STP_v 00 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 308LDP_v 00 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 309STP_v 01 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 310LDP_v 01 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 311STP_v 10 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 312LDP_v 10 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 313 314# STP and LDP: pre-indexed 315STP 00 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 316LDP 00 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 317LDP 01 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=0 w=1 318STP 10 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 319LDP 10 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 320STP_v 00 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 321LDP_v 00 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 322STP_v 01 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 323LDP_v 01 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 324STP_v 10 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=1 325LDP_v 10 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=1 326 327# STGP: store tag and pair 328STGP 01 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 329STGP 01 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 330STGP 01 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 331 332# Load/store register (unscaled immediate) 333&ldst_imm rt rn imm sz sign w p unpriv ext 334@ldst_imm .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=0 335@ldst_imm_pre .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=1 336@ldst_imm_post .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=1 w=1 337@ldst_imm_user .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=1 p=0 w=0 338 339STR_i sz:2 111 0 00 00 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 340LDR_i 00 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=0 341LDR_i 01 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=1 342LDR_i 10 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=2 343LDR_i 11 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=3 344LDR_i 00 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=0 345LDR_i 01 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=1 346LDR_i 10 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=2 347LDR_i 00 111 0 00 11 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=1 sz=0 348LDR_i 01 111 0 00 11 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=1 sz=1 349 350STR_i sz:2 111 0 00 00 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 351LDR_i 00 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=0 352LDR_i 01 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=1 353LDR_i 10 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=2 354LDR_i 11 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=3 355LDR_i 00 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=0 356LDR_i 01 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=1 357LDR_i 10 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=2 358LDR_i 00 111 0 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=1 sz=0 359LDR_i 01 111 0 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=1 sz=1 360 361STR_i sz:2 111 0 00 00 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=0 362LDR_i 00 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=0 363LDR_i 01 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=1 364LDR_i 10 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=2 365LDR_i 11 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=0 sz=3 366LDR_i 00 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=0 367LDR_i 01 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=1 368LDR_i 10 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=2 369LDR_i 00 111 0 00 11 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=1 sz=0 370LDR_i 01 111 0 00 11 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=1 sz=1 371 372STR_i sz:2 111 0 00 00 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 373LDR_i 00 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=0 374LDR_i 01 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=1 375LDR_i 10 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=2 376LDR_i 11 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=3 377LDR_i 00 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=0 378LDR_i 01 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=1 379LDR_i 10 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=2 380LDR_i 00 111 0 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=1 sz=0 381LDR_i 01 111 0 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=1 sz=1 382 383# PRFM : prefetch memory: a no-op for QEMU 384NOP 11 111 0 00 10 0 --------- 00 ----- ----- 385 386STR_v_i sz:2 111 1 00 00 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 387STR_v_i 00 111 1 00 10 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=4 388LDR_v_i sz:2 111 1 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 389LDR_v_i 00 111 1 00 11 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=4 390 391STR_v_i sz:2 111 1 00 00 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 392STR_v_i 00 111 1 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=4 393LDR_v_i sz:2 111 1 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 394LDR_v_i 00 111 1 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=4 395 396STR_v_i sz:2 111 1 00 00 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 397STR_v_i 00 111 1 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=4 398LDR_v_i sz:2 111 1 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 399LDR_v_i 00 111 1 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=4 400 401# Load/store with an unsigned 12 bit immediate, which is scaled by the 402# element size. The function gets the sz:imm and returns the scaled immediate. 403%uimm_scaled 10:12 sz:3 !function=uimm_scaled 404 405@ldst_uimm .. ... . .. .. ............ rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=0 imm=%uimm_scaled 406 407STR_i sz:2 111 0 01 00 ............ ..... ..... @ldst_uimm sign=0 ext=0 408LDR_i 00 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=0 409LDR_i 01 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=1 410LDR_i 10 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=2 411LDR_i 11 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=3 412LDR_i 00 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=0 413LDR_i 01 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=1 414LDR_i 10 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=2 415LDR_i 00 111 0 01 11 ............ ..... ..... @ldst_uimm sign=1 ext=1 sz=0 416LDR_i 01 111 0 01 11 ............ ..... ..... @ldst_uimm sign=1 ext=1 sz=1 417 418# PRFM 419NOP 11 111 0 01 10 ------------ ----- ----- 420 421STR_v_i sz:2 111 1 01 00 ............ ..... ..... @ldst_uimm sign=0 ext=0 422STR_v_i 00 111 1 01 10 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=4 423LDR_v_i sz:2 111 1 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=0 424LDR_v_i 00 111 1 01 11 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=4 425 426# Load/store with register offset 427&ldst rm rn rt sign ext sz opt s 428@ldst .. ... . .. .. . rm:5 opt:3 s:1 .. rn:5 rt:5 &ldst 429STR sz:2 111 0 00 00 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 430LDR 00 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=0 431LDR 01 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=1 432LDR 10 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=2 433LDR 11 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=3 434LDR 00 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=0 435LDR 01 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=1 436LDR 10 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=2 437LDR 00 111 0 00 11 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=1 sz=0 438LDR 01 111 0 00 11 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=1 sz=1 439 440# PRFM 441NOP 11 111 0 00 10 1 ----- -1- - 10 ----- ----- 442 443STR_v sz:2 111 1 00 00 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 444STR_v 00 111 1 00 10 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=4 445LDR_v sz:2 111 1 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 446LDR_v 00 111 1 00 11 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=4 447 448# Atomic memory operations 449&atomic rs rn rt a r sz 450@atomic sz:2 ... . .. a:1 r:1 . rs:5 . ... .. rn:5 rt:5 &atomic 451LDADD .. 111 0 00 . . 1 ..... 0000 00 ..... ..... @atomic 452LDCLR .. 111 0 00 . . 1 ..... 0001 00 ..... ..... @atomic 453LDEOR .. 111 0 00 . . 1 ..... 0010 00 ..... ..... @atomic 454LDSET .. 111 0 00 . . 1 ..... 0011 00 ..... ..... @atomic 455LDSMAX .. 111 0 00 . . 1 ..... 0100 00 ..... ..... @atomic 456LDSMIN .. 111 0 00 . . 1 ..... 0101 00 ..... ..... @atomic 457LDUMAX .. 111 0 00 . . 1 ..... 0110 00 ..... ..... @atomic 458LDUMIN .. 111 0 00 . . 1 ..... 0111 00 ..... ..... @atomic 459SWP .. 111 0 00 . . 1 ..... 1000 00 ..... ..... @atomic 460 461LDAPR sz:2 111 0 00 1 0 1 11111 1100 00 rn:5 rt:5 462 463# Load/store register (pointer authentication) 464 465# LDRA immediate is 10 bits signed and scaled, but the bits aren't all contiguous 466%ldra_imm 22:s1 12:9 !function=times_8 467 468LDRA 11 111 0 00 m:1 . 1 ......... w:1 1 rn:5 rt:5 imm=%ldra_imm 469 470&ldapr_stlr_i rn rt imm sz sign ext 471@ldapr_stlr_i .. ...... .. . imm:9 .. rn:5 rt:5 &ldapr_stlr_i 472STLR_i sz:2 011001 00 0 ......... 00 ..... ..... @ldapr_stlr_i sign=0 ext=0 473LDAPR_i sz:2 011001 01 0 ......... 00 ..... ..... @ldapr_stlr_i sign=0 ext=0 474LDAPR_i 00 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=0 475LDAPR_i 01 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=1 476LDAPR_i 10 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=2 477LDAPR_i 00 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=1 sz=0 478LDAPR_i 01 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=1 sz=1 479 480# Load/store multiple structures 481# The 4-bit opcode in [15:12] encodes repeat count and structure elements 482&ldst_mult rm rn rt sz q p rpt selem 483@ldst_mult . q:1 ...... p:1 . . rm:5 .... sz:2 rn:5 rt:5 &ldst_mult 484ST_mult 0 . 001100 . 0 0 ..... 0000 .. ..... ..... @ldst_mult rpt=1 selem=4 485ST_mult 0 . 001100 . 0 0 ..... 0010 .. ..... ..... @ldst_mult rpt=4 selem=1 486ST_mult 0 . 001100 . 0 0 ..... 0100 .. ..... ..... @ldst_mult rpt=1 selem=3 487ST_mult 0 . 001100 . 0 0 ..... 0110 .. ..... ..... @ldst_mult rpt=3 selem=1 488ST_mult 0 . 001100 . 0 0 ..... 0111 .. ..... ..... @ldst_mult rpt=1 selem=1 489ST_mult 0 . 001100 . 0 0 ..... 1000 .. ..... ..... @ldst_mult rpt=1 selem=2 490ST_mult 0 . 001100 . 0 0 ..... 1010 .. ..... ..... @ldst_mult rpt=2 selem=1 491 492LD_mult 0 . 001100 . 1 0 ..... 0000 .. ..... ..... @ldst_mult rpt=1 selem=4 493LD_mult 0 . 001100 . 1 0 ..... 0010 .. ..... ..... @ldst_mult rpt=4 selem=1 494LD_mult 0 . 001100 . 1 0 ..... 0100 .. ..... ..... @ldst_mult rpt=1 selem=3 495LD_mult 0 . 001100 . 1 0 ..... 0110 .. ..... ..... @ldst_mult rpt=3 selem=1 496LD_mult 0 . 001100 . 1 0 ..... 0111 .. ..... ..... @ldst_mult rpt=1 selem=1 497LD_mult 0 . 001100 . 1 0 ..... 1000 .. ..... ..... @ldst_mult rpt=1 selem=2 498LD_mult 0 . 001100 . 1 0 ..... 1010 .. ..... ..... @ldst_mult rpt=2 selem=1 499 500# Load/store single structure 501&ldst_single rm rn rt p selem index scale 502 503%ldst_single_selem 13:1 21:1 !function=plus_1 504 505%ldst_single_index_b 30:1 10:3 506%ldst_single_index_h 30:1 11:2 507%ldst_single_index_s 30:1 12:1 508 509@ldst_single_b .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \ 510 &ldst_single scale=0 selem=%ldst_single_selem \ 511 index=%ldst_single_index_b 512@ldst_single_h .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \ 513 &ldst_single scale=1 selem=%ldst_single_selem \ 514 index=%ldst_single_index_h 515@ldst_single_s .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \ 516 &ldst_single scale=2 selem=%ldst_single_selem \ 517 index=%ldst_single_index_s 518@ldst_single_d . index:1 ...... p:1 .. rm:5 ...... rn:5 rt:5 \ 519 &ldst_single scale=3 selem=%ldst_single_selem 520 521ST_single 0 . 001101 . 0 . ..... 00 . ... ..... ..... @ldst_single_b 522ST_single 0 . 001101 . 0 . ..... 01 . ..0 ..... ..... @ldst_single_h 523ST_single 0 . 001101 . 0 . ..... 10 . .00 ..... ..... @ldst_single_s 524ST_single 0 . 001101 . 0 . ..... 10 . 001 ..... ..... @ldst_single_d 525 526LD_single 0 . 001101 . 1 . ..... 00 . ... ..... ..... @ldst_single_b 527LD_single 0 . 001101 . 1 . ..... 01 . ..0 ..... ..... @ldst_single_h 528LD_single 0 . 001101 . 1 . ..... 10 . .00 ..... ..... @ldst_single_s 529LD_single 0 . 001101 . 1 . ..... 10 . 001 ..... ..... @ldst_single_d 530 531# Replicating load case 532LD_single_repl 0 q:1 001101 p:1 1 . rm:5 11 . 0 scale:2 rn:5 rt:5 selem=%ldst_single_selem 533 534%tag_offset 12:s9 !function=scale_by_log2_tag_granule 535&ldst_tag rn rt imm p w 536@ldst_tag ........ .. . ......... .. rn:5 rt:5 &ldst_tag imm=%tag_offset 537@ldst_tag_mult ........ .. . 000000000 .. rn:5 rt:5 &ldst_tag imm=0 538 539STZGM 11011001 00 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0 540STG 11011001 00 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 541STG 11011001 00 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 542STG 11011001 00 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 543 544LDG 11011001 01 1 ......... 00 ..... ..... @ldst_tag p=0 w=0 545STZG 11011001 01 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 546STZG 11011001 01 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 547STZG 11011001 01 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 548 549STGM 11011001 10 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0 550ST2G 11011001 10 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 551ST2G 11011001 10 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 552ST2G 11011001 10 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 553 554LDGM 11011001 11 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0 555STZ2G 11011001 11 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 556STZ2G 11011001 11 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 557STZ2G 11011001 11 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 558 559# Memory operations (memset, memcpy, memmove) 560# Each of these comes in a set of three, eg SETP (prologue), SETM (main), 561# SETE (epilogue), and each of those has different flavours to 562# indicate whether memory accesses should be unpriv or non-temporal. 563# We don't distinguish temporal and non-temporal accesses, but we 564# do need to report it in syndrome register values. 565 566# Memset 567&set rs rn rd unpriv nontemp 568# op2 bit 1 is nontemporal bit 569@set .. ......... rs:5 .. nontemp:1 unpriv:1 .. rn:5 rd:5 &set 570 571SETP 00 011001110 ..... 00 . . 01 ..... ..... @set 572SETM 00 011001110 ..... 01 . . 01 ..... ..... @set 573SETE 00 011001110 ..... 10 . . 01 ..... ..... @set 574 575# Like SET, but also setting MTE tags 576SETGP 00 011101110 ..... 00 . . 01 ..... ..... @set 577SETGM 00 011101110 ..... 01 . . 01 ..... ..... @set 578SETGE 00 011101110 ..... 10 . . 01 ..... ..... @set 579 580# Memmove/Memcopy: the CPY insns allow overlapping src/dest and 581# copy in the correct direction; the CPYF insns always copy forwards. 582# 583# options has the nontemporal and unpriv bits for src and dest 584&cpy rs rn rd options 585@cpy .. ... . ..... rs:5 options:4 .. rn:5 rd:5 &cpy 586 587CPYFP 00 011 0 01000 ..... .... 01 ..... ..... @cpy 588CPYFM 00 011 0 01010 ..... .... 01 ..... ..... @cpy 589CPYFE 00 011 0 01100 ..... .... 01 ..... ..... @cpy 590CPYP 00 011 1 01000 ..... .... 01 ..... ..... @cpy 591CPYM 00 011 1 01010 ..... .... 01 ..... ..... @cpy 592CPYE 00 011 1 01100 ..... .... 01 ..... ..... @cpy 593