18058c831SPeter Maydell# AArch64 A64 allowed instruction decoding 28058c831SPeter Maydell# 38058c831SPeter Maydell# Copyright (c) 2023 Linaro, Ltd 48058c831SPeter Maydell# 58058c831SPeter Maydell# This library is free software; you can redistribute it and/or 68058c831SPeter Maydell# modify it under the terms of the GNU Lesser General Public 78058c831SPeter Maydell# License as published by the Free Software Foundation; either 88058c831SPeter Maydell# version 2.1 of the License, or (at your option) any later version. 98058c831SPeter Maydell# 108058c831SPeter Maydell# This library is distributed in the hope that it will be useful, 118058c831SPeter Maydell# but WITHOUT ANY WARRANTY; without even the implied warranty of 128058c831SPeter Maydell# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 138058c831SPeter Maydell# Lesser General Public License for more details. 148058c831SPeter Maydell# 158058c831SPeter Maydell# You should have received a copy of the GNU Lesser General Public 168058c831SPeter Maydell# License along with this library; if not, see <http://www.gnu.org/licenses/>. 178058c831SPeter Maydell 188058c831SPeter Maydell# 198058c831SPeter Maydell# This file is processed by scripts/decodetree.py 208058c831SPeter Maydell# 2145fda88eSRichard Henderson 22c0b5e394SPeter Maydell&r rn 2345fda88eSRichard Henderson&ri rd imm 243ce7b5eaSRichard Henderson&rri_sf rd rn imm sf 256201b2a4SPeter Maydell&i imm 2645fda88eSRichard Henderson 2745fda88eSRichard Henderson 2845fda88eSRichard Henderson### Data Processing - Immediate 2945fda88eSRichard Henderson 3045fda88eSRichard Henderson# PC-rel addressing 3145fda88eSRichard Henderson 3245fda88eSRichard Henderson%imm_pcrel 5:s19 29:2 3345fda88eSRichard Henderson@pcrel . .. ..... ................... rd:5 &ri imm=%imm_pcrel 3445fda88eSRichard Henderson 3545fda88eSRichard HendersonADR 0 .. 10000 ................... ..... @pcrel 3645fda88eSRichard HendersonADRP 1 .. 10000 ................... ..... @pcrel 373ce7b5eaSRichard Henderson 383ce7b5eaSRichard Henderson# Add/subtract (immediate) 393ce7b5eaSRichard Henderson 403ce7b5eaSRichard Henderson%imm12_sh12 10:12 !function=shl_12 413ce7b5eaSRichard Henderson@addsub_imm sf:1 .. ...... . imm:12 rn:5 rd:5 423ce7b5eaSRichard Henderson@addsub_imm12 sf:1 .. ...... . ............ rn:5 rd:5 imm=%imm12_sh12 433ce7b5eaSRichard Henderson 443ce7b5eaSRichard HendersonADD_i . 00 100010 0 ............ ..... ..... @addsub_imm 453ce7b5eaSRichard HendersonADD_i . 00 100010 1 ............ ..... ..... @addsub_imm12 463ce7b5eaSRichard HendersonADDS_i . 01 100010 0 ............ ..... ..... @addsub_imm 473ce7b5eaSRichard HendersonADDS_i . 01 100010 1 ............ ..... ..... @addsub_imm12 483ce7b5eaSRichard Henderson 493ce7b5eaSRichard HendersonSUB_i . 10 100010 0 ............ ..... ..... @addsub_imm 503ce7b5eaSRichard HendersonSUB_i . 10 100010 1 ............ ..... ..... @addsub_imm12 513ce7b5eaSRichard HendersonSUBS_i . 11 100010 0 ............ ..... ..... @addsub_imm 523ce7b5eaSRichard HendersonSUBS_i . 11 100010 1 ............ ..... ..... @addsub_imm12 5386002eccSRichard Henderson 5486002eccSRichard Henderson# Add/subtract (immediate with tags) 5586002eccSRichard Henderson 5686002eccSRichard Henderson&rri_tag rd rn uimm6 uimm4 5786002eccSRichard Henderson@addsub_imm_tag . .. ...... . uimm6:6 .. uimm4:4 rn:5 rd:5 &rri_tag 5886002eccSRichard Henderson 5986002eccSRichard HendersonADDG_i 1 00 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag 6086002eccSRichard HendersonSUBG_i 1 10 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag 618127f46aSRichard Henderson 628127f46aSRichard Henderson# Logical (immediate) 638127f46aSRichard Henderson 648127f46aSRichard Henderson&rri_log rd rn sf dbm 658127f46aSRichard Henderson@logic_imm_64 1 .. ...... dbm:13 rn:5 rd:5 &rri_log sf=1 668127f46aSRichard Henderson@logic_imm_32 0 .. ...... 0 dbm:12 rn:5 rd:5 &rri_log sf=0 678127f46aSRichard Henderson 688127f46aSRichard HendersonAND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_64 698127f46aSRichard HendersonAND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_32 708127f46aSRichard HendersonORR_i . 01 100100 . ...... ...... ..... ..... @logic_imm_64 718127f46aSRichard HendersonORR_i . 01 100100 . ...... ...... ..... ..... @logic_imm_32 728127f46aSRichard HendersonEOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_64 738127f46aSRichard HendersonEOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_32 748127f46aSRichard HendersonANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_64 758127f46aSRichard HendersonANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_32 76ee0daeb9SRichard Henderson 77ee0daeb9SRichard Henderson# Move wide (immediate) 78ee0daeb9SRichard Henderson 79ee0daeb9SRichard Henderson&movw rd sf imm hw 80ee0daeb9SRichard Henderson@movw_64 1 .. ...... hw:2 imm:16 rd:5 &movw sf=1 81ee0daeb9SRichard Henderson@movw_32 0 .. ...... 0 hw:1 imm:16 rd:5 &movw sf=0 82ee0daeb9SRichard Henderson 83ee0daeb9SRichard HendersonMOVN . 00 100101 .. ................ ..... @movw_64 84ee0daeb9SRichard HendersonMOVN . 00 100101 .. ................ ..... @movw_32 85ee0daeb9SRichard HendersonMOVZ . 10 100101 .. ................ ..... @movw_64 86ee0daeb9SRichard HendersonMOVZ . 10 100101 .. ................ ..... @movw_32 87ee0daeb9SRichard HendersonMOVK . 11 100101 .. ................ ..... @movw_64 88ee0daeb9SRichard HendersonMOVK . 11 100101 .. ................ ..... @movw_32 895e451ae6SRichard Henderson 905e451ae6SRichard Henderson# Bitfield 915e451ae6SRichard Henderson 925e451ae6SRichard Henderson&bitfield rd rn sf immr imms 935e451ae6SRichard Henderson@bitfield_64 1 .. ...... 1 immr:6 imms:6 rn:5 rd:5 &bitfield sf=1 945e451ae6SRichard Henderson@bitfield_32 0 .. ...... 0 0 immr:5 0 imms:5 rn:5 rd:5 &bitfield sf=0 955e451ae6SRichard Henderson 965e451ae6SRichard HendersonSBFM . 00 100110 . ...... ...... ..... ..... @bitfield_64 975e451ae6SRichard HendersonSBFM . 00 100110 . ...... ...... ..... ..... @bitfield_32 985e451ae6SRichard HendersonBFM . 01 100110 . ...... ...... ..... ..... @bitfield_64 995e451ae6SRichard HendersonBFM . 01 100110 . ...... ...... ..... ..... @bitfield_32 1005e451ae6SRichard HendersonUBFM . 10 100110 . ...... ...... ..... ..... @bitfield_64 1015e451ae6SRichard HendersonUBFM . 10 100110 . ...... ...... ..... ..... @bitfield_32 1024240fb61SPeter Maydell 1034240fb61SPeter Maydell# Extract 1044240fb61SPeter Maydell 1054240fb61SPeter Maydell&extract rd rn rm imm sf 1064240fb61SPeter Maydell 1074240fb61SPeter MaydellEXTR 1 00 100111 1 0 rm:5 imm:6 rn:5 rd:5 &extract sf=1 1084240fb61SPeter MaydellEXTR 0 00 100111 0 0 rm:5 0 imm:5 rn:5 rd:5 &extract sf=0 1096201b2a4SPeter Maydell 1106201b2a4SPeter Maydell# Branches 1116201b2a4SPeter Maydell 1126201b2a4SPeter Maydell%imm26 0:s26 !function=times_4 1136201b2a4SPeter Maydell@branch . ..... .......................... &i imm=%imm26 1146201b2a4SPeter Maydell 1156201b2a4SPeter MaydellB 0 00101 .......................... @branch 1166201b2a4SPeter MaydellBL 1 00101 .......................... @branch 117f8977d50SPeter Maydell 118f8977d50SPeter Maydell%imm19 5:s19 !function=times_4 119f8977d50SPeter Maydell&cbz rt imm sf nz 120f8977d50SPeter Maydell 121f8977d50SPeter MaydellCBZ sf:1 011010 nz:1 ................... rt:5 &cbz imm=%imm19 122e505828dSPeter Maydell 123e505828dSPeter Maydell%imm14 5:s14 !function=times_4 124e505828dSPeter Maydell%imm31_19 31:1 19:5 125e505828dSPeter Maydell&tbz rt imm nz bitpos 126e505828dSPeter Maydell 127e505828dSPeter MaydellTBZ . 011011 nz:1 ..... .............. rt:5 &tbz imm=%imm14 bitpos=%imm31_19 128484df362SPeter Maydell 129484df362SPeter MaydellB_cond 0101010 0 ................... 0 cond:4 imm=%imm19 130c0b5e394SPeter Maydell 131c0b5e394SPeter MaydellBR 1101011 0000 11111 000000 rn:5 00000 &r 132c0b5e394SPeter MaydellBLR 1101011 0001 11111 000000 rn:5 00000 &r 133c0b5e394SPeter MaydellRET 1101011 0010 11111 000000 rn:5 00000 &r 1340ebbe902SPeter Maydell 1350ebbe902SPeter Maydell&braz rn m 1360ebbe902SPeter MaydellBRAZ 1101011 0000 11111 00001 m:1 rn:5 11111 &braz # BRAAZ, BRABZ 1370ebbe902SPeter MaydellBLRAZ 1101011 0001 11111 00001 m:1 rn:5 11111 &braz # BLRAAZ, BLRABZ 1380ebbe902SPeter Maydell 1390ebbe902SPeter Maydell&reta m 1400ebbe902SPeter MaydellRETA 1101011 0010 11111 00001 m:1 11111 11111 &reta # RETAA, RETAB 141c990fde6SPeter Maydell 142c990fde6SPeter Maydell&bra rn rm m 143c990fde6SPeter MaydellBRA 1101011 1000 11111 00001 m:1 rn:5 rm:5 &bra # BRAA, BRAB 144c990fde6SPeter MaydellBLRA 1101011 1001 11111 00001 m:1 rn:5 rm:5 &bra # BLRAA, BLRAB 145442c9d68SPeter Maydell 146442c9d68SPeter MaydellERET 1101011 0100 11111 000000 11111 00000 147442c9d68SPeter MaydellERETA 1101011 0100 11111 00001 m:1 11111 11111 &reta # ERETAA, ERETAB 148442c9d68SPeter Maydell 149442c9d68SPeter Maydell# We don't need to decode DRPS because it always UNDEFs except when 150442c9d68SPeter Maydell# the processor is in halting debug state (which we don't implement). 151442c9d68SPeter Maydell# The pattern is listed here as documentation. 152442c9d68SPeter Maydell# DRPS 1101011 0101 11111 000000 11111 00000 1537fefc706SPeter Maydell 1547fefc706SPeter Maydell# Hint instruction group 1557fefc706SPeter Maydell{ 1567fefc706SPeter Maydell [ 1577fefc706SPeter Maydell YIELD 1101 0101 0000 0011 0010 0000 001 11111 1587fefc706SPeter Maydell WFE 1101 0101 0000 0011 0010 0000 010 11111 1597fefc706SPeter Maydell WFI 1101 0101 0000 0011 0010 0000 011 11111 1607fefc706SPeter Maydell # We implement WFE to never block, so our SEV/SEVL are NOPs 1617fefc706SPeter Maydell # SEV 1101 0101 0000 0011 0010 0000 100 11111 1627fefc706SPeter Maydell # SEVL 1101 0101 0000 0011 0010 0000 101 11111 1637fefc706SPeter Maydell # Our DGL is a NOP because we don't merge memory accesses anyway. 1647fefc706SPeter Maydell # DGL 1101 0101 0000 0011 0010 0000 110 11111 1657fefc706SPeter Maydell XPACLRI 1101 0101 0000 0011 0010 0000 111 11111 1667fefc706SPeter Maydell PACIA1716 1101 0101 0000 0011 0010 0001 000 11111 1677fefc706SPeter Maydell PACIB1716 1101 0101 0000 0011 0010 0001 010 11111 1687fefc706SPeter Maydell AUTIA1716 1101 0101 0000 0011 0010 0001 100 11111 1697fefc706SPeter Maydell AUTIB1716 1101 0101 0000 0011 0010 0001 110 11111 1707fefc706SPeter Maydell ESB 1101 0101 0000 0011 0010 0010 000 11111 1717fefc706SPeter Maydell PACIAZ 1101 0101 0000 0011 0010 0011 000 11111 1727fefc706SPeter Maydell PACIASP 1101 0101 0000 0011 0010 0011 001 11111 1737fefc706SPeter Maydell PACIBZ 1101 0101 0000 0011 0010 0011 010 11111 1747fefc706SPeter Maydell PACIBSP 1101 0101 0000 0011 0010 0011 011 11111 1757fefc706SPeter Maydell AUTIAZ 1101 0101 0000 0011 0010 0011 100 11111 1767fefc706SPeter Maydell AUTIASP 1101 0101 0000 0011 0010 0011 101 11111 1777fefc706SPeter Maydell AUTIBZ 1101 0101 0000 0011 0010 0011 110 11111 1787fefc706SPeter Maydell AUTIBSP 1101 0101 0000 0011 0010 0011 111 11111 1797fefc706SPeter Maydell ] 1807fefc706SPeter Maydell # The canonical NOP has CRm == op2 == 0, but all of the space 1817fefc706SPeter Maydell # that isn't specifically allocated to an instruction must NOP 1827fefc706SPeter Maydell NOP 1101 0101 0000 0011 0010 ---- --- 11111 1837fefc706SPeter Maydell} 184*afcd5df5SPeter Maydell 185*afcd5df5SPeter Maydell# Barriers 186*afcd5df5SPeter Maydell 187*afcd5df5SPeter MaydellCLREX 1101 0101 0000 0011 0011 ---- 010 11111 188*afcd5df5SPeter MaydellDSB_DMB 1101 0101 0000 0011 0011 domain:2 types:2 10- 11111 189*afcd5df5SPeter MaydellISB 1101 0101 0000 0011 0011 ---- 110 11111 190*afcd5df5SPeter MaydellSB 1101 0101 0000 0011 0011 0000 111 11111 191