18058c831SPeter Maydell# AArch64 A64 allowed instruction decoding 28058c831SPeter Maydell# 38058c831SPeter Maydell# Copyright (c) 2023 Linaro, Ltd 48058c831SPeter Maydell# 58058c831SPeter Maydell# This library is free software; you can redistribute it and/or 68058c831SPeter Maydell# modify it under the terms of the GNU Lesser General Public 78058c831SPeter Maydell# License as published by the Free Software Foundation; either 88058c831SPeter Maydell# version 2.1 of the License, or (at your option) any later version. 98058c831SPeter Maydell# 108058c831SPeter Maydell# This library is distributed in the hope that it will be useful, 118058c831SPeter Maydell# but WITHOUT ANY WARRANTY; without even the implied warranty of 128058c831SPeter Maydell# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 138058c831SPeter Maydell# Lesser General Public License for more details. 148058c831SPeter Maydell# 158058c831SPeter Maydell# You should have received a copy of the GNU Lesser General Public 168058c831SPeter Maydell# License along with this library; if not, see <http://www.gnu.org/licenses/>. 178058c831SPeter Maydell 188058c831SPeter Maydell# 198058c831SPeter Maydell# This file is processed by scripts/decodetree.py 208058c831SPeter Maydell# 2145fda88eSRichard Henderson 22c0b5e394SPeter Maydell&r rn 2345fda88eSRichard Henderson&ri rd imm 243ce7b5eaSRichard Henderson&rri_sf rd rn imm sf 256201b2a4SPeter Maydell&i imm 2645fda88eSRichard Henderson 2745fda88eSRichard Henderson 2845fda88eSRichard Henderson### Data Processing - Immediate 2945fda88eSRichard Henderson 3045fda88eSRichard Henderson# PC-rel addressing 3145fda88eSRichard Henderson 3245fda88eSRichard Henderson%imm_pcrel 5:s19 29:2 3345fda88eSRichard Henderson@pcrel . .. ..... ................... rd:5 &ri imm=%imm_pcrel 3445fda88eSRichard Henderson 3545fda88eSRichard HendersonADR 0 .. 10000 ................... ..... @pcrel 3645fda88eSRichard HendersonADRP 1 .. 10000 ................... ..... @pcrel 373ce7b5eaSRichard Henderson 383ce7b5eaSRichard Henderson# Add/subtract (immediate) 393ce7b5eaSRichard Henderson 403ce7b5eaSRichard Henderson%imm12_sh12 10:12 !function=shl_12 413ce7b5eaSRichard Henderson@addsub_imm sf:1 .. ...... . imm:12 rn:5 rd:5 423ce7b5eaSRichard Henderson@addsub_imm12 sf:1 .. ...... . ............ rn:5 rd:5 imm=%imm12_sh12 433ce7b5eaSRichard Henderson 443ce7b5eaSRichard HendersonADD_i . 00 100010 0 ............ ..... ..... @addsub_imm 453ce7b5eaSRichard HendersonADD_i . 00 100010 1 ............ ..... ..... @addsub_imm12 463ce7b5eaSRichard HendersonADDS_i . 01 100010 0 ............ ..... ..... @addsub_imm 473ce7b5eaSRichard HendersonADDS_i . 01 100010 1 ............ ..... ..... @addsub_imm12 483ce7b5eaSRichard Henderson 493ce7b5eaSRichard HendersonSUB_i . 10 100010 0 ............ ..... ..... @addsub_imm 503ce7b5eaSRichard HendersonSUB_i . 10 100010 1 ............ ..... ..... @addsub_imm12 513ce7b5eaSRichard HendersonSUBS_i . 11 100010 0 ............ ..... ..... @addsub_imm 523ce7b5eaSRichard HendersonSUBS_i . 11 100010 1 ............ ..... ..... @addsub_imm12 5386002eccSRichard Henderson 5486002eccSRichard Henderson# Add/subtract (immediate with tags) 5586002eccSRichard Henderson 5686002eccSRichard Henderson&rri_tag rd rn uimm6 uimm4 5786002eccSRichard Henderson@addsub_imm_tag . .. ...... . uimm6:6 .. uimm4:4 rn:5 rd:5 &rri_tag 5886002eccSRichard Henderson 5986002eccSRichard HendersonADDG_i 1 00 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag 6086002eccSRichard HendersonSUBG_i 1 10 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag 618127f46aSRichard Henderson 628127f46aSRichard Henderson# Logical (immediate) 638127f46aSRichard Henderson 648127f46aSRichard Henderson&rri_log rd rn sf dbm 658127f46aSRichard Henderson@logic_imm_64 1 .. ...... dbm:13 rn:5 rd:5 &rri_log sf=1 668127f46aSRichard Henderson@logic_imm_32 0 .. ...... 0 dbm:12 rn:5 rd:5 &rri_log sf=0 678127f46aSRichard Henderson 688127f46aSRichard HendersonAND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_64 698127f46aSRichard HendersonAND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_32 708127f46aSRichard HendersonORR_i . 01 100100 . ...... ...... ..... ..... @logic_imm_64 718127f46aSRichard HendersonORR_i . 01 100100 . ...... ...... ..... ..... @logic_imm_32 728127f46aSRichard HendersonEOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_64 738127f46aSRichard HendersonEOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_32 748127f46aSRichard HendersonANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_64 758127f46aSRichard HendersonANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_32 76ee0daeb9SRichard Henderson 77ee0daeb9SRichard Henderson# Move wide (immediate) 78ee0daeb9SRichard Henderson 79ee0daeb9SRichard Henderson&movw rd sf imm hw 80ee0daeb9SRichard Henderson@movw_64 1 .. ...... hw:2 imm:16 rd:5 &movw sf=1 81ee0daeb9SRichard Henderson@movw_32 0 .. ...... 0 hw:1 imm:16 rd:5 &movw sf=0 82ee0daeb9SRichard Henderson 83ee0daeb9SRichard HendersonMOVN . 00 100101 .. ................ ..... @movw_64 84ee0daeb9SRichard HendersonMOVN . 00 100101 .. ................ ..... @movw_32 85ee0daeb9SRichard HendersonMOVZ . 10 100101 .. ................ ..... @movw_64 86ee0daeb9SRichard HendersonMOVZ . 10 100101 .. ................ ..... @movw_32 87ee0daeb9SRichard HendersonMOVK . 11 100101 .. ................ ..... @movw_64 88ee0daeb9SRichard HendersonMOVK . 11 100101 .. ................ ..... @movw_32 895e451ae6SRichard Henderson 905e451ae6SRichard Henderson# Bitfield 915e451ae6SRichard Henderson 925e451ae6SRichard Henderson&bitfield rd rn sf immr imms 935e451ae6SRichard Henderson@bitfield_64 1 .. ...... 1 immr:6 imms:6 rn:5 rd:5 &bitfield sf=1 945e451ae6SRichard Henderson@bitfield_32 0 .. ...... 0 0 immr:5 0 imms:5 rn:5 rd:5 &bitfield sf=0 955e451ae6SRichard Henderson 965e451ae6SRichard HendersonSBFM . 00 100110 . ...... ...... ..... ..... @bitfield_64 975e451ae6SRichard HendersonSBFM . 00 100110 . ...... ...... ..... ..... @bitfield_32 985e451ae6SRichard HendersonBFM . 01 100110 . ...... ...... ..... ..... @bitfield_64 995e451ae6SRichard HendersonBFM . 01 100110 . ...... ...... ..... ..... @bitfield_32 1005e451ae6SRichard HendersonUBFM . 10 100110 . ...... ...... ..... ..... @bitfield_64 1015e451ae6SRichard HendersonUBFM . 10 100110 . ...... ...... ..... ..... @bitfield_32 1024240fb61SPeter Maydell 1034240fb61SPeter Maydell# Extract 1044240fb61SPeter Maydell 1054240fb61SPeter Maydell&extract rd rn rm imm sf 1064240fb61SPeter Maydell 1074240fb61SPeter MaydellEXTR 1 00 100111 1 0 rm:5 imm:6 rn:5 rd:5 &extract sf=1 1084240fb61SPeter MaydellEXTR 0 00 100111 0 0 rm:5 0 imm:5 rn:5 rd:5 &extract sf=0 1096201b2a4SPeter Maydell 1106201b2a4SPeter Maydell# Branches 1116201b2a4SPeter Maydell 1126201b2a4SPeter Maydell%imm26 0:s26 !function=times_4 1136201b2a4SPeter Maydell@branch . ..... .......................... &i imm=%imm26 1146201b2a4SPeter Maydell 1156201b2a4SPeter MaydellB 0 00101 .......................... @branch 1166201b2a4SPeter MaydellBL 1 00101 .......................... @branch 117f8977d50SPeter Maydell 118f8977d50SPeter Maydell%imm19 5:s19 !function=times_4 119f8977d50SPeter Maydell&cbz rt imm sf nz 120f8977d50SPeter Maydell 121f8977d50SPeter MaydellCBZ sf:1 011010 nz:1 ................... rt:5 &cbz imm=%imm19 122e505828dSPeter Maydell 123e505828dSPeter Maydell%imm14 5:s14 !function=times_4 124e505828dSPeter Maydell%imm31_19 31:1 19:5 125e505828dSPeter Maydell&tbz rt imm nz bitpos 126e505828dSPeter Maydell 127e505828dSPeter MaydellTBZ . 011011 nz:1 ..... .............. rt:5 &tbz imm=%imm14 bitpos=%imm31_19 128484df362SPeter Maydell 1293039b090SPeter Maydell# B.cond and BC.cond 1303039b090SPeter MaydellB_cond 0101010 0 ................... c:1 cond:4 imm=%imm19 131c0b5e394SPeter Maydell 132c0b5e394SPeter MaydellBR 1101011 0000 11111 000000 rn:5 00000 &r 133c0b5e394SPeter MaydellBLR 1101011 0001 11111 000000 rn:5 00000 &r 134c0b5e394SPeter MaydellRET 1101011 0010 11111 000000 rn:5 00000 &r 1350ebbe902SPeter Maydell 1360ebbe902SPeter Maydell&braz rn m 1370ebbe902SPeter MaydellBRAZ 1101011 0000 11111 00001 m:1 rn:5 11111 &braz # BRAAZ, BRABZ 1380ebbe902SPeter MaydellBLRAZ 1101011 0001 11111 00001 m:1 rn:5 11111 &braz # BLRAAZ, BLRABZ 1390ebbe902SPeter Maydell 1400ebbe902SPeter Maydell&reta m 1410ebbe902SPeter MaydellRETA 1101011 0010 11111 00001 m:1 11111 11111 &reta # RETAA, RETAB 142c990fde6SPeter Maydell 143c990fde6SPeter Maydell&bra rn rm m 144c990fde6SPeter MaydellBRA 1101011 1000 11111 00001 m:1 rn:5 rm:5 &bra # BRAA, BRAB 145c990fde6SPeter MaydellBLRA 1101011 1001 11111 00001 m:1 rn:5 rm:5 &bra # BLRAA, BLRAB 146442c9d68SPeter Maydell 147442c9d68SPeter MaydellERET 1101011 0100 11111 000000 11111 00000 148442c9d68SPeter MaydellERETA 1101011 0100 11111 00001 m:1 11111 11111 &reta # ERETAA, ERETAB 149442c9d68SPeter Maydell 150442c9d68SPeter Maydell# We don't need to decode DRPS because it always UNDEFs except when 151442c9d68SPeter Maydell# the processor is in halting debug state (which we don't implement). 152442c9d68SPeter Maydell# The pattern is listed here as documentation. 153442c9d68SPeter Maydell# DRPS 1101011 0101 11111 000000 11111 00000 1547fefc706SPeter Maydell 1557fefc706SPeter Maydell# Hint instruction group 1567fefc706SPeter Maydell{ 1577fefc706SPeter Maydell [ 1587fefc706SPeter Maydell YIELD 1101 0101 0000 0011 0010 0000 001 11111 1597fefc706SPeter Maydell WFE 1101 0101 0000 0011 0010 0000 010 11111 1607fefc706SPeter Maydell WFI 1101 0101 0000 0011 0010 0000 011 11111 1617fefc706SPeter Maydell # We implement WFE to never block, so our SEV/SEVL are NOPs 1627fefc706SPeter Maydell # SEV 1101 0101 0000 0011 0010 0000 100 11111 1637fefc706SPeter Maydell # SEVL 1101 0101 0000 0011 0010 0000 101 11111 1647fefc706SPeter Maydell # Our DGL is a NOP because we don't merge memory accesses anyway. 1657fefc706SPeter Maydell # DGL 1101 0101 0000 0011 0010 0000 110 11111 1667fefc706SPeter Maydell XPACLRI 1101 0101 0000 0011 0010 0000 111 11111 1677fefc706SPeter Maydell PACIA1716 1101 0101 0000 0011 0010 0001 000 11111 1687fefc706SPeter Maydell PACIB1716 1101 0101 0000 0011 0010 0001 010 11111 1697fefc706SPeter Maydell AUTIA1716 1101 0101 0000 0011 0010 0001 100 11111 1707fefc706SPeter Maydell AUTIB1716 1101 0101 0000 0011 0010 0001 110 11111 1717fefc706SPeter Maydell ESB 1101 0101 0000 0011 0010 0010 000 11111 1727fefc706SPeter Maydell PACIAZ 1101 0101 0000 0011 0010 0011 000 11111 1737fefc706SPeter Maydell PACIASP 1101 0101 0000 0011 0010 0011 001 11111 1747fefc706SPeter Maydell PACIBZ 1101 0101 0000 0011 0010 0011 010 11111 1757fefc706SPeter Maydell PACIBSP 1101 0101 0000 0011 0010 0011 011 11111 1767fefc706SPeter Maydell AUTIAZ 1101 0101 0000 0011 0010 0011 100 11111 1777fefc706SPeter Maydell AUTIASP 1101 0101 0000 0011 0010 0011 101 11111 1787fefc706SPeter Maydell AUTIBZ 1101 0101 0000 0011 0010 0011 110 11111 1797fefc706SPeter Maydell AUTIBSP 1101 0101 0000 0011 0010 0011 111 11111 1807fefc706SPeter Maydell ] 1817fefc706SPeter Maydell # The canonical NOP has CRm == op2 == 0, but all of the space 1827fefc706SPeter Maydell # that isn't specifically allocated to an instruction must NOP 1837fefc706SPeter Maydell NOP 1101 0101 0000 0011 0010 ---- --- 11111 1847fefc706SPeter Maydell} 185afcd5df5SPeter Maydell 186afcd5df5SPeter Maydell# Barriers 187afcd5df5SPeter Maydell 188afcd5df5SPeter MaydellCLREX 1101 0101 0000 0011 0011 ---- 010 11111 189afcd5df5SPeter MaydellDSB_DMB 1101 0101 0000 0011 0011 domain:2 types:2 10- 11111 190afcd5df5SPeter MaydellISB 1101 0101 0000 0011 0011 ---- 110 11111 191afcd5df5SPeter MaydellSB 1101 0101 0000 0011 0011 0000 111 11111 192d78b662fSPeter Maydell 193d78b662fSPeter Maydell# PSTATE 194d78b662fSPeter Maydell 195d78b662fSPeter MaydellCFINV 1101 0101 0000 0 000 0100 0000 000 11111 196d78b662fSPeter MaydellXAFLAG 1101 0101 0000 0 000 0100 0000 001 11111 197d78b662fSPeter MaydellAXFLAG 1101 0101 0000 0 000 0100 0000 010 11111 19845d063d1SPeter Maydell 19945d063d1SPeter Maydell# These are architecturally all "MSR (immediate)"; we decode the destination 20045d063d1SPeter Maydell# register too because there is no commonality in our implementation. 20145d063d1SPeter Maydell@msr_i .... .... .... . ... .... imm:4 ... ..... 20245d063d1SPeter MaydellMSR_i_UAO 1101 0101 0000 0 000 0100 .... 011 11111 @msr_i 20345d063d1SPeter MaydellMSR_i_PAN 1101 0101 0000 0 000 0100 .... 100 11111 @msr_i 20445d063d1SPeter MaydellMSR_i_SPSEL 1101 0101 0000 0 000 0100 .... 101 11111 @msr_i 20545d063d1SPeter MaydellMSR_i_SBSS 1101 0101 0000 0 011 0100 .... 001 11111 @msr_i 20645d063d1SPeter MaydellMSR_i_DIT 1101 0101 0000 0 011 0100 .... 010 11111 @msr_i 20745d063d1SPeter MaydellMSR_i_TCO 1101 0101 0000 0 011 0100 .... 100 11111 @msr_i 20845d063d1SPeter MaydellMSR_i_DAIFSET 1101 0101 0000 0 011 0100 .... 110 11111 @msr_i 20945d063d1SPeter MaydellMSR_i_DAIFCLEAR 1101 0101 0000 0 011 0100 .... 111 11111 @msr_i 21045d063d1SPeter MaydellMSR_i_SVCR 1101 0101 0000 0 011 0100 0 mask:2 imm:1 011 11111 2116e3c8049SPeter Maydell 2126e3c8049SPeter Maydell# MRS, MSR (register), SYS, SYSL. These are all essentially the 2136e3c8049SPeter Maydell# same instruction as far as QEMU is concerned. 2146e3c8049SPeter Maydell# NB: op0 is bits [20:19], but op0=0b00 is other insns, so we have 2156e3c8049SPeter Maydell# to hand-decode it. 2166e3c8049SPeter MaydellSYS 1101 0101 00 l:1 01 op1:3 crn:4 crm:4 op2:3 rt:5 op0=1 2176e3c8049SPeter MaydellSYS 1101 0101 00 l:1 10 op1:3 crn:4 crm:4 op2:3 rt:5 op0=2 2186e3c8049SPeter MaydellSYS 1101 0101 00 l:1 11 op1:3 crn:4 crm:4 op2:3 rt:5 op0=3 219a97d3c18SPeter Maydell 220a97d3c18SPeter Maydell# Exception generation 221a97d3c18SPeter Maydell 222a97d3c18SPeter Maydell@i16 .... .... ... imm:16 ... .. &i 223a97d3c18SPeter MaydellSVC 1101 0100 000 ................ 000 01 @i16 224a97d3c18SPeter MaydellHVC 1101 0100 000 ................ 000 10 @i16 225a97d3c18SPeter MaydellSMC 1101 0100 000 ................ 000 11 @i16 226a97d3c18SPeter MaydellBRK 1101 0100 001 ................ 000 00 @i16 227a97d3c18SPeter MaydellHLT 1101 0100 010 ................ 000 00 @i16 228a97d3c18SPeter Maydell# These insns always UNDEF unless in halting debug state, which 229a97d3c18SPeter Maydell# we don't implement. So we don't need to decode them. The patterns 230a97d3c18SPeter Maydell# are listed here as documentation. 231a97d3c18SPeter Maydell# DCPS1 1101 0100 101 ................ 000 01 @i16 232a97d3c18SPeter Maydell# DCPS2 1101 0100 101 ................ 000 10 @i16 233a97d3c18SPeter Maydell# DCPS3 1101 0100 101 ................ 000 11 @i16 23484693e67SPeter Maydell 23584693e67SPeter Maydell# Loads and stores 23684693e67SPeter Maydell 23784693e67SPeter Maydell&stxr rn rt rt2 rs sz lasr 23884693e67SPeter Maydell&stlr rn rt sz lasr 23984693e67SPeter Maydell@stxr sz:2 ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr 24084693e67SPeter Maydell@stlr sz:2 ...... ... ..... lasr:1 ..... rn:5 rt:5 &stlr 241e8a149a3SPeter Maydell%imm1_30_p2 30:1 !function=plus_2 242e8a149a3SPeter Maydell@stxp .. ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr sz=%imm1_30_p2 24384693e67SPeter MaydellSTXR .. 001000 000 ..... . ..... ..... ..... @stxr # inc STLXR 24484693e67SPeter MaydellLDXR .. 001000 010 ..... . ..... ..... ..... @stxr # inc LDAXR 24584693e67SPeter MaydellSTLR .. 001000 100 11111 . 11111 ..... ..... @stlr # inc STLLR 24684693e67SPeter MaydellLDAR .. 001000 110 11111 . 11111 ..... ..... @stlr # inc LDLAR 247e8a149a3SPeter Maydell 248e8a149a3SPeter MaydellSTXP 1 . 001000 001 ..... . ..... ..... ..... @stxp # inc STLXP 249e8a149a3SPeter MaydellLDXP 1 . 001000 011 ..... . ..... ..... ..... @stxp # inc LDAXP 250e8a149a3SPeter Maydell 251e8a149a3SPeter Maydell# CASP, CASPA, CASPAL, CASPL (we don't decode the bits that determine 252e8a149a3SPeter Maydell# acquire/release semantics because QEMU's cmpxchg always has those) 253e8a149a3SPeter MaydellCASP 0 . 001000 0 - 1 rs:5 - 11111 rn:5 rt:5 sz=%imm1_30_p2 254e8a149a3SPeter Maydell# CAS, CASA, CASAL, CASL 255e8a149a3SPeter MaydellCAS sz:2 001000 1 - 1 rs:5 - 11111 rn:5 rt:5 256a752c2f4SPeter Maydell 257a752c2f4SPeter Maydell&ldlit rt imm sz sign 258a752c2f4SPeter Maydell@ldlit .. ... . .. ................... rt:5 &ldlit imm=%imm19 259a752c2f4SPeter Maydell 260a752c2f4SPeter MaydellLD_lit 00 011 0 00 ................... ..... @ldlit sz=2 sign=0 261a752c2f4SPeter MaydellLD_lit 01 011 0 00 ................... ..... @ldlit sz=3 sign=0 262a752c2f4SPeter MaydellLD_lit 10 011 0 00 ................... ..... @ldlit sz=2 sign=1 263a752c2f4SPeter MaydellLD_lit_v 00 011 1 00 ................... ..... @ldlit sz=2 sign=0 264a752c2f4SPeter MaydellLD_lit_v 01 011 1 00 ................... ..... @ldlit sz=3 sign=0 265a752c2f4SPeter MaydellLD_lit_v 10 011 1 00 ................... ..... @ldlit sz=4 sign=0 266a752c2f4SPeter Maydell 267a752c2f4SPeter Maydell# PRFM 268a752c2f4SPeter MaydellNOP 11 011 0 00 ------------------- ----- 2698c212eb6SPeter Maydell 2708c212eb6SPeter Maydell&ldstpair rt2 rt rn imm sz sign w p 2718c212eb6SPeter Maydell@ldstpair .. ... . ... . imm:s7 rt2:5 rn:5 rt:5 &ldstpair 2728c212eb6SPeter Maydell 2738c212eb6SPeter Maydell# STNP, LDNP: Signed offset, non-temporal hint. We don't emulate caches 2748c212eb6SPeter Maydell# so we ignore hints about data access patterns, and handle these like 2758c212eb6SPeter Maydell# plain signed offset. 2768c212eb6SPeter MaydellSTP 00 101 0 000 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 2778c212eb6SPeter MaydellLDP 00 101 0 000 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 2788c212eb6SPeter MaydellSTP 10 101 0 000 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 2798c212eb6SPeter MaydellLDP 10 101 0 000 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 2808c212eb6SPeter MaydellSTP_v 00 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 2818c212eb6SPeter MaydellLDP_v 00 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 2828c212eb6SPeter MaydellSTP_v 01 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 2838c212eb6SPeter MaydellLDP_v 01 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 2848c212eb6SPeter MaydellSTP_v 10 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 2858c212eb6SPeter MaydellLDP_v 10 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 2868c212eb6SPeter Maydell 2878c212eb6SPeter Maydell# STP and LDP: post-indexed 2888c212eb6SPeter MaydellSTP 00 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 2898c212eb6SPeter MaydellLDP 00 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 2908c212eb6SPeter MaydellLDP 01 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=1 w=1 2918c212eb6SPeter MaydellSTP 10 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 2928c212eb6SPeter MaydellLDP 10 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 2938c212eb6SPeter MaydellSTP_v 00 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 2948c212eb6SPeter MaydellLDP_v 00 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 2958c212eb6SPeter MaydellSTP_v 01 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 2968c212eb6SPeter MaydellLDP_v 01 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 2978c212eb6SPeter MaydellSTP_v 10 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=1 w=1 2988c212eb6SPeter MaydellLDP_v 10 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=1 w=1 2998c212eb6SPeter Maydell 3008c212eb6SPeter Maydell# STP and LDP: offset 3018c212eb6SPeter MaydellSTP 00 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 3028c212eb6SPeter MaydellLDP 00 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 3038c212eb6SPeter MaydellLDP 01 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=0 w=0 3048c212eb6SPeter MaydellSTP 10 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 3058c212eb6SPeter MaydellLDP 10 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 3068c212eb6SPeter MaydellSTP_v 00 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 3078c212eb6SPeter MaydellLDP_v 00 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 3088c212eb6SPeter MaydellSTP_v 01 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 3098c212eb6SPeter MaydellLDP_v 01 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 3108c212eb6SPeter MaydellSTP_v 10 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 3118c212eb6SPeter MaydellLDP_v 10 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 3128c212eb6SPeter Maydell 3138c212eb6SPeter Maydell# STP and LDP: pre-indexed 3148c212eb6SPeter MaydellSTP 00 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 3158c212eb6SPeter MaydellLDP 00 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 3168c212eb6SPeter MaydellLDP 01 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=0 w=1 3178c212eb6SPeter MaydellSTP 10 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 3188c212eb6SPeter MaydellLDP 10 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 3198c212eb6SPeter MaydellSTP_v 00 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 3208c212eb6SPeter MaydellLDP_v 00 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 3218c212eb6SPeter MaydellSTP_v 01 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 3228c212eb6SPeter MaydellLDP_v 01 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 3238c212eb6SPeter MaydellSTP_v 10 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=1 3248c212eb6SPeter MaydellLDP_v 10 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=1 3258c212eb6SPeter Maydell 3268c212eb6SPeter Maydell# STGP: store tag and pair 3278c212eb6SPeter MaydellSTGP 01 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 3288c212eb6SPeter MaydellSTGP 01 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 3298c212eb6SPeter MaydellSTGP 01 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 33060cd7ba9SPeter Maydell 33160cd7ba9SPeter Maydell# Load/store register (unscaled immediate) 33260cd7ba9SPeter Maydell&ldst_imm rt rn imm sz sign w p unpriv ext 33360cd7ba9SPeter Maydell@ldst_imm .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=0 33460cd7ba9SPeter Maydell@ldst_imm_pre .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=1 33560cd7ba9SPeter Maydell@ldst_imm_post .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=1 w=1 33660cd7ba9SPeter Maydell@ldst_imm_user .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=1 p=0 w=0 33760cd7ba9SPeter Maydell 33860cd7ba9SPeter MaydellSTR_i sz:2 111 0 00 00 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 33960cd7ba9SPeter MaydellLDR_i 00 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=0 34060cd7ba9SPeter MaydellLDR_i 01 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=1 34160cd7ba9SPeter MaydellLDR_i 10 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=2 34260cd7ba9SPeter MaydellLDR_i 11 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=3 34360cd7ba9SPeter MaydellLDR_i 00 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=0 34460cd7ba9SPeter MaydellLDR_i 01 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=1 34560cd7ba9SPeter MaydellLDR_i 10 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=2 34660cd7ba9SPeter MaydellLDR_i 00 111 0 00 11 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=1 sz=0 34760cd7ba9SPeter MaydellLDR_i 01 111 0 00 11 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=1 sz=1 34860cd7ba9SPeter Maydell 34960cd7ba9SPeter MaydellSTR_i sz:2 111 0 00 00 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 35060cd7ba9SPeter MaydellLDR_i 00 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=0 35160cd7ba9SPeter MaydellLDR_i 01 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=1 35260cd7ba9SPeter MaydellLDR_i 10 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=2 35360cd7ba9SPeter MaydellLDR_i 11 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=3 35460cd7ba9SPeter MaydellLDR_i 00 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=0 35560cd7ba9SPeter MaydellLDR_i 01 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=1 35660cd7ba9SPeter MaydellLDR_i 10 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=2 35760cd7ba9SPeter MaydellLDR_i 00 111 0 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=1 sz=0 35860cd7ba9SPeter MaydellLDR_i 01 111 0 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=1 sz=1 35960cd7ba9SPeter Maydell 36060cd7ba9SPeter MaydellSTR_i sz:2 111 0 00 00 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=0 36160cd7ba9SPeter MaydellLDR_i 00 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=0 36260cd7ba9SPeter MaydellLDR_i 01 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=1 36360cd7ba9SPeter MaydellLDR_i 10 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=2 36460cd7ba9SPeter MaydellLDR_i 11 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=0 sz=3 36560cd7ba9SPeter MaydellLDR_i 00 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=0 36660cd7ba9SPeter MaydellLDR_i 01 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=1 36760cd7ba9SPeter MaydellLDR_i 10 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=2 36860cd7ba9SPeter MaydellLDR_i 00 111 0 00 11 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=1 sz=0 36960cd7ba9SPeter MaydellLDR_i 01 111 0 00 11 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=1 sz=1 37060cd7ba9SPeter Maydell 37160cd7ba9SPeter MaydellSTR_i sz:2 111 0 00 00 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 37260cd7ba9SPeter MaydellLDR_i 00 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=0 37360cd7ba9SPeter MaydellLDR_i 01 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=1 37460cd7ba9SPeter MaydellLDR_i 10 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=2 37560cd7ba9SPeter MaydellLDR_i 11 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=3 37660cd7ba9SPeter MaydellLDR_i 00 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=0 37760cd7ba9SPeter MaydellLDR_i 01 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=1 37860cd7ba9SPeter MaydellLDR_i 10 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=2 37960cd7ba9SPeter MaydellLDR_i 00 111 0 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=1 sz=0 38060cd7ba9SPeter MaydellLDR_i 01 111 0 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=1 sz=1 38160cd7ba9SPeter Maydell 38260cd7ba9SPeter Maydell# PRFM : prefetch memory: a no-op for QEMU 38360cd7ba9SPeter MaydellNOP 11 111 0 00 10 0 --------- 00 ----- ----- 38460cd7ba9SPeter Maydell 38560cd7ba9SPeter MaydellSTR_v_i sz:2 111 1 00 00 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 38660cd7ba9SPeter MaydellSTR_v_i 00 111 1 00 10 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=4 38760cd7ba9SPeter MaydellLDR_v_i sz:2 111 1 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 38860cd7ba9SPeter MaydellLDR_v_i 00 111 1 00 11 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=4 38960cd7ba9SPeter Maydell 39060cd7ba9SPeter MaydellSTR_v_i sz:2 111 1 00 00 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 39160cd7ba9SPeter MaydellSTR_v_i 00 111 1 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=4 39260cd7ba9SPeter MaydellLDR_v_i sz:2 111 1 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 39360cd7ba9SPeter MaydellLDR_v_i 00 111 1 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=4 39460cd7ba9SPeter Maydell 39560cd7ba9SPeter MaydellSTR_v_i sz:2 111 1 00 00 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 39660cd7ba9SPeter MaydellSTR_v_i 00 111 1 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=4 39760cd7ba9SPeter MaydellLDR_v_i sz:2 111 1 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 39860cd7ba9SPeter MaydellLDR_v_i 00 111 1 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=4 39961edd8f8SPeter Maydell 40061edd8f8SPeter Maydell# Load/store with an unsigned 12 bit immediate, which is scaled by the 40161edd8f8SPeter Maydell# element size. The function gets the sz:imm and returns the scaled immediate. 40261edd8f8SPeter Maydell%uimm_scaled 10:12 sz:3 !function=uimm_scaled 40361edd8f8SPeter Maydell 40461edd8f8SPeter Maydell@ldst_uimm .. ... . .. .. ............ rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=0 imm=%uimm_scaled 40561edd8f8SPeter Maydell 40661edd8f8SPeter MaydellSTR_i sz:2 111 0 01 00 ............ ..... ..... @ldst_uimm sign=0 ext=0 40761edd8f8SPeter MaydellLDR_i 00 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=0 40861edd8f8SPeter MaydellLDR_i 01 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=1 40961edd8f8SPeter MaydellLDR_i 10 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=2 41061edd8f8SPeter MaydellLDR_i 11 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=3 41161edd8f8SPeter MaydellLDR_i 00 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=0 41261edd8f8SPeter MaydellLDR_i 01 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=1 41361edd8f8SPeter MaydellLDR_i 10 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=2 41461edd8f8SPeter MaydellLDR_i 00 111 0 01 11 ............ ..... ..... @ldst_uimm sign=1 ext=1 sz=0 41561edd8f8SPeter MaydellLDR_i 01 111 0 01 11 ............ ..... ..... @ldst_uimm sign=1 ext=1 sz=1 41661edd8f8SPeter Maydell 41761edd8f8SPeter Maydell# PRFM 41861edd8f8SPeter MaydellNOP 11 111 0 01 10 ------------ ----- ----- 41961edd8f8SPeter Maydell 42061edd8f8SPeter MaydellSTR_v_i sz:2 111 1 01 00 ............ ..... ..... @ldst_uimm sign=0 ext=0 42161edd8f8SPeter MaydellSTR_v_i 00 111 1 01 10 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=4 42261edd8f8SPeter MaydellLDR_v_i sz:2 111 1 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=0 42361edd8f8SPeter MaydellLDR_v_i 00 111 1 01 11 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=4 424f36bf0c1SPeter Maydell 425f36bf0c1SPeter Maydell# Load/store with register offset 426f36bf0c1SPeter Maydell&ldst rm rn rt sign ext sz opt s 427f36bf0c1SPeter Maydell@ldst .. ... . .. .. . rm:5 opt:3 s:1 .. rn:5 rt:5 &ldst 428f36bf0c1SPeter MaydellSTR sz:2 111 0 00 00 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 429f36bf0c1SPeter MaydellLDR 00 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=0 430f36bf0c1SPeter MaydellLDR 01 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=1 431f36bf0c1SPeter MaydellLDR 10 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=2 432f36bf0c1SPeter MaydellLDR 11 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=3 433f36bf0c1SPeter MaydellLDR 00 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=0 434f36bf0c1SPeter MaydellLDR 01 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=1 435f36bf0c1SPeter MaydellLDR 10 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=2 436f36bf0c1SPeter MaydellLDR 00 111 0 00 11 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=1 sz=0 437f36bf0c1SPeter MaydellLDR 01 111 0 00 11 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=1 sz=1 438f36bf0c1SPeter Maydell 439f36bf0c1SPeter Maydell# PRFM 440f36bf0c1SPeter MaydellNOP 11 111 0 00 10 1 ----- -1- - 10 ----- ----- 441f36bf0c1SPeter Maydell 442f36bf0c1SPeter MaydellSTR_v sz:2 111 1 00 00 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 443f36bf0c1SPeter MaydellSTR_v 00 111 1 00 10 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=4 444f36bf0c1SPeter MaydellLDR_v sz:2 111 1 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 445f36bf0c1SPeter MaydellLDR_v 00 111 1 00 11 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=4 44654a9ab74SPeter Maydell 44754a9ab74SPeter Maydell# Atomic memory operations 44854a9ab74SPeter Maydell&atomic rs rn rt a r sz 44954a9ab74SPeter Maydell@atomic sz:2 ... . .. a:1 r:1 . rs:5 . ... .. rn:5 rt:5 &atomic 45054a9ab74SPeter MaydellLDADD .. 111 0 00 . . 1 ..... 0000 00 ..... ..... @atomic 45154a9ab74SPeter MaydellLDCLR .. 111 0 00 . . 1 ..... 0001 00 ..... ..... @atomic 45254a9ab74SPeter MaydellLDEOR .. 111 0 00 . . 1 ..... 0010 00 ..... ..... @atomic 45354a9ab74SPeter MaydellLDSET .. 111 0 00 . . 1 ..... 0011 00 ..... ..... @atomic 45454a9ab74SPeter MaydellLDSMAX .. 111 0 00 . . 1 ..... 0100 00 ..... ..... @atomic 45554a9ab74SPeter MaydellLDSMIN .. 111 0 00 . . 1 ..... 0101 00 ..... ..... @atomic 45654a9ab74SPeter MaydellLDUMAX .. 111 0 00 . . 1 ..... 0110 00 ..... ..... @atomic 45754a9ab74SPeter MaydellLDUMIN .. 111 0 00 . . 1 ..... 0111 00 ..... ..... @atomic 45854a9ab74SPeter MaydellSWP .. 111 0 00 . . 1 ..... 1000 00 ..... ..... @atomic 45954a9ab74SPeter Maydell 46054a9ab74SPeter MaydellLDAPR sz:2 111 0 00 1 0 1 11111 1100 00 rn:5 rt:5 461be23a049SPeter Maydell 462be23a049SPeter Maydell# Load/store register (pointer authentication) 463be23a049SPeter Maydell 464be23a049SPeter Maydell# LDRA immediate is 10 bits signed and scaled, but the bits aren't all contiguous 465*5722fc47SPeter Maydell%ldra_imm 22:s1 12:9 !function=times_8 466be23a049SPeter Maydell 467be23a049SPeter MaydellLDRA 11 111 0 00 m:1 . 1 ......... w:1 1 rn:5 rt:5 imm=%ldra_imm 4682521b607SPeter Maydell 4692521b607SPeter Maydell&ldapr_stlr_i rn rt imm sz sign ext 4702521b607SPeter Maydell@ldapr_stlr_i .. ...... .. . imm:9 .. rn:5 rt:5 &ldapr_stlr_i 4712521b607SPeter MaydellSTLR_i sz:2 011001 00 0 ......... 00 ..... ..... @ldapr_stlr_i sign=0 ext=0 4722521b607SPeter MaydellLDAPR_i sz:2 011001 01 0 ......... 00 ..... ..... @ldapr_stlr_i sign=0 ext=0 4732521b607SPeter MaydellLDAPR_i 00 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=0 4742521b607SPeter MaydellLDAPR_i 01 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=1 4752521b607SPeter MaydellLDAPR_i 10 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=2 4762521b607SPeter MaydellLDAPR_i 00 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=1 sz=0 4772521b607SPeter MaydellLDAPR_i 01 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=1 sz=1 478e25ba1faSPeter Maydell 479e25ba1faSPeter Maydell# Load/store multiple structures 480e25ba1faSPeter Maydell# The 4-bit opcode in [15:12] encodes repeat count and structure elements 481e25ba1faSPeter Maydell&ldst_mult rm rn rt sz q p rpt selem 482e25ba1faSPeter Maydell@ldst_mult . q:1 ...... p:1 . . rm:5 .... sz:2 rn:5 rt:5 &ldst_mult 483e25ba1faSPeter MaydellST_mult 0 . 001100 . 0 0 ..... 0000 .. ..... ..... @ldst_mult rpt=1 selem=4 484e25ba1faSPeter MaydellST_mult 0 . 001100 . 0 0 ..... 0010 .. ..... ..... @ldst_mult rpt=4 selem=1 485e25ba1faSPeter MaydellST_mult 0 . 001100 . 0 0 ..... 0100 .. ..... ..... @ldst_mult rpt=1 selem=3 486e25ba1faSPeter MaydellST_mult 0 . 001100 . 0 0 ..... 0110 .. ..... ..... @ldst_mult rpt=3 selem=1 487e25ba1faSPeter MaydellST_mult 0 . 001100 . 0 0 ..... 0111 .. ..... ..... @ldst_mult rpt=1 selem=1 488e25ba1faSPeter MaydellST_mult 0 . 001100 . 0 0 ..... 1000 .. ..... ..... @ldst_mult rpt=1 selem=2 489e25ba1faSPeter MaydellST_mult 0 . 001100 . 0 0 ..... 1010 .. ..... ..... @ldst_mult rpt=2 selem=1 490e25ba1faSPeter Maydell 491e25ba1faSPeter MaydellLD_mult 0 . 001100 . 1 0 ..... 0000 .. ..... ..... @ldst_mult rpt=1 selem=4 492e25ba1faSPeter MaydellLD_mult 0 . 001100 . 1 0 ..... 0010 .. ..... ..... @ldst_mult rpt=4 selem=1 493e25ba1faSPeter MaydellLD_mult 0 . 001100 . 1 0 ..... 0100 .. ..... ..... @ldst_mult rpt=1 selem=3 494e25ba1faSPeter MaydellLD_mult 0 . 001100 . 1 0 ..... 0110 .. ..... ..... @ldst_mult rpt=3 selem=1 495e25ba1faSPeter MaydellLD_mult 0 . 001100 . 1 0 ..... 0111 .. ..... ..... @ldst_mult rpt=1 selem=1 496e25ba1faSPeter MaydellLD_mult 0 . 001100 . 1 0 ..... 1000 .. ..... ..... @ldst_mult rpt=1 selem=2 497e25ba1faSPeter MaydellLD_mult 0 . 001100 . 1 0 ..... 1010 .. ..... ..... @ldst_mult rpt=2 selem=1 4983d507213SPeter Maydell 4993d507213SPeter Maydell# Load/store single structure 5003d507213SPeter Maydell&ldst_single rm rn rt p selem index scale 5013d507213SPeter Maydell 5023d507213SPeter Maydell%ldst_single_selem 13:1 21:1 !function=plus_1 5033d507213SPeter Maydell 5043d507213SPeter Maydell%ldst_single_index_b 30:1 10:3 5053d507213SPeter Maydell%ldst_single_index_h 30:1 11:2 5063d507213SPeter Maydell%ldst_single_index_s 30:1 12:1 5073d507213SPeter Maydell 5083d507213SPeter Maydell@ldst_single_b .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \ 5093d507213SPeter Maydell &ldst_single scale=0 selem=%ldst_single_selem \ 5103d507213SPeter Maydell index=%ldst_single_index_b 5113d507213SPeter Maydell@ldst_single_h .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \ 5123d507213SPeter Maydell &ldst_single scale=1 selem=%ldst_single_selem \ 5133d507213SPeter Maydell index=%ldst_single_index_h 5143d507213SPeter Maydell@ldst_single_s .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \ 5153d507213SPeter Maydell &ldst_single scale=2 selem=%ldst_single_selem \ 5163d507213SPeter Maydell index=%ldst_single_index_s 5173d507213SPeter Maydell@ldst_single_d . index:1 ...... p:1 .. rm:5 ...... rn:5 rt:5 \ 5183d507213SPeter Maydell &ldst_single scale=3 selem=%ldst_single_selem 5193d507213SPeter Maydell 5203d507213SPeter MaydellST_single 0 . 001101 . 0 . ..... 00 . ... ..... ..... @ldst_single_b 5213d507213SPeter MaydellST_single 0 . 001101 . 0 . ..... 01 . ..0 ..... ..... @ldst_single_h 5223d507213SPeter MaydellST_single 0 . 001101 . 0 . ..... 10 . .00 ..... ..... @ldst_single_s 5233d507213SPeter MaydellST_single 0 . 001101 . 0 . ..... 10 . 001 ..... ..... @ldst_single_d 5243d507213SPeter Maydell 5253d507213SPeter MaydellLD_single 0 . 001101 . 1 . ..... 00 . ... ..... ..... @ldst_single_b 5263d507213SPeter MaydellLD_single 0 . 001101 . 1 . ..... 01 . ..0 ..... ..... @ldst_single_h 5273d507213SPeter MaydellLD_single 0 . 001101 . 1 . ..... 10 . .00 ..... ..... @ldst_single_s 5283d507213SPeter MaydellLD_single 0 . 001101 . 1 . ..... 10 . 001 ..... ..... @ldst_single_d 5293d507213SPeter Maydell 5303d507213SPeter Maydell# Replicating load case 5313d507213SPeter MaydellLD_single_repl 0 q:1 001101 p:1 1 . rm:5 11 . 0 scale:2 rn:5 rt:5 selem=%ldst_single_selem 532946ccfd5SPeter Maydell 533946ccfd5SPeter Maydell%tag_offset 12:s9 !function=scale_by_log2_tag_granule 534946ccfd5SPeter Maydell&ldst_tag rn rt imm p w 535946ccfd5SPeter Maydell@ldst_tag ........ .. . ......... .. rn:5 rt:5 &ldst_tag imm=%tag_offset 536946ccfd5SPeter Maydell@ldst_tag_mult ........ .. . 000000000 .. rn:5 rt:5 &ldst_tag imm=0 537946ccfd5SPeter Maydell 538946ccfd5SPeter MaydellSTZGM 11011001 00 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0 539946ccfd5SPeter MaydellSTG 11011001 00 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 540946ccfd5SPeter MaydellSTG 11011001 00 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 541946ccfd5SPeter MaydellSTG 11011001 00 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 542946ccfd5SPeter Maydell 543946ccfd5SPeter MaydellLDG 11011001 01 1 ......... 00 ..... ..... @ldst_tag p=0 w=0 544946ccfd5SPeter MaydellSTZG 11011001 01 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 545946ccfd5SPeter MaydellSTZG 11011001 01 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 546946ccfd5SPeter MaydellSTZG 11011001 01 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 547946ccfd5SPeter Maydell 548946ccfd5SPeter MaydellSTGM 11011001 10 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0 549946ccfd5SPeter MaydellST2G 11011001 10 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 550946ccfd5SPeter MaydellST2G 11011001 10 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 551946ccfd5SPeter MaydellST2G 11011001 10 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 552946ccfd5SPeter Maydell 553946ccfd5SPeter MaydellLDGM 11011001 11 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0 554946ccfd5SPeter MaydellSTZ2G 11011001 11 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 555946ccfd5SPeter MaydellSTZ2G 11011001 11 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 556946ccfd5SPeter MaydellSTZ2G 11011001 11 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 5570e928188SPeter Maydell 5580e928188SPeter Maydell# Memory operations (memset, memcpy, memmove) 5590e928188SPeter Maydell# Each of these comes in a set of three, eg SETP (prologue), SETM (main), 5600e928188SPeter Maydell# SETE (epilogue), and each of those has different flavours to 5610e928188SPeter Maydell# indicate whether memory accesses should be unpriv or non-temporal. 5620e928188SPeter Maydell# We don't distinguish temporal and non-temporal accesses, but we 5630e928188SPeter Maydell# do need to report it in syndrome register values. 5640e928188SPeter Maydell 5650e928188SPeter Maydell# Memset 5660e928188SPeter Maydell&set rs rn rd unpriv nontemp 5670e928188SPeter Maydell# op2 bit 1 is nontemporal bit 5680e928188SPeter Maydell@set .. ......... rs:5 .. nontemp:1 unpriv:1 .. rn:5 rd:5 &set 5690e928188SPeter Maydell 5700e928188SPeter MaydellSETP 00 011001110 ..... 00 . . 01 ..... ..... @set 5710e928188SPeter MaydellSETM 00 011001110 ..... 01 . . 01 ..... ..... @set 5720e928188SPeter MaydellSETE 00 011001110 ..... 10 . . 01 ..... ..... @set 5736087df57SPeter Maydell 5746087df57SPeter Maydell# Like SET, but also setting MTE tags 5756087df57SPeter MaydellSETGP 00 011101110 ..... 00 . . 01 ..... ..... @set 5766087df57SPeter MaydellSETGM 00 011101110 ..... 01 . . 01 ..... ..... @set 5776087df57SPeter MaydellSETGE 00 011101110 ..... 10 . . 01 ..... ..... @set 5785d7b37b5SPeter Maydell 5795d7b37b5SPeter Maydell# Memmove/Memcopy: the CPY insns allow overlapping src/dest and 5805d7b37b5SPeter Maydell# copy in the correct direction; the CPYF insns always copy forwards. 5815d7b37b5SPeter Maydell# 5825d7b37b5SPeter Maydell# options has the nontemporal and unpriv bits for src and dest 5835d7b37b5SPeter Maydell&cpy rs rn rd options 5845d7b37b5SPeter Maydell@cpy .. ... . ..... rs:5 options:4 .. rn:5 rd:5 &cpy 5855d7b37b5SPeter Maydell 5865d7b37b5SPeter MaydellCPYFP 00 011 0 01000 ..... .... 01 ..... ..... @cpy 5875d7b37b5SPeter MaydellCPYFM 00 011 0 01010 ..... .... 01 ..... ..... @cpy 5885d7b37b5SPeter MaydellCPYFE 00 011 0 01100 ..... .... 01 ..... ..... @cpy 5895d7b37b5SPeter MaydellCPYP 00 011 1 01000 ..... .... 01 ..... ..... @cpy 5905d7b37b5SPeter MaydellCPYM 00 011 1 01010 ..... .... 01 ..... ..... @cpy 5915d7b37b5SPeter MaydellCPYE 00 011 1 01100 ..... .... 01 ..... ..... @cpy 592