1 /* 2 * QEMU ARM CPU -- syndrome functions and types 3 * 4 * Copyright (c) 2014 Linaro Ltd 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 * 20 * This header defines functions, types, etc which need to be shared 21 * between different source files within target/arm/ but which are 22 * private to it and not required by the rest of QEMU. 23 */ 24 25 #ifndef TARGET_ARM_SYNDROME_H 26 #define TARGET_ARM_SYNDROME_H 27 28 /* Valid Syndrome Register EC field values */ 29 enum arm_exception_class { 30 EC_UNCATEGORIZED = 0x00, 31 EC_WFX_TRAP = 0x01, 32 EC_CP15RTTRAP = 0x03, 33 EC_CP15RRTTRAP = 0x04, 34 EC_CP14RTTRAP = 0x05, 35 EC_CP14DTTRAP = 0x06, 36 EC_ADVSIMDFPACCESSTRAP = 0x07, 37 EC_FPIDTRAP = 0x08, 38 EC_PACTRAP = 0x09, 39 EC_BXJTRAP = 0x0a, 40 EC_CP14RRTTRAP = 0x0c, 41 EC_BTITRAP = 0x0d, 42 EC_ILLEGALSTATE = 0x0e, 43 EC_AA32_SVC = 0x11, 44 EC_AA32_HVC = 0x12, 45 EC_AA32_SMC = 0x13, 46 EC_AA64_SVC = 0x15, 47 EC_AA64_HVC = 0x16, 48 EC_AA64_SMC = 0x17, 49 EC_SYSTEMREGISTERTRAP = 0x18, 50 EC_SVEACCESSTRAP = 0x19, 51 EC_ERETTRAP = 0x1a, 52 EC_PACFAIL = 0x1c, 53 EC_SMETRAP = 0x1d, 54 EC_GPC = 0x1e, 55 EC_INSNABORT = 0x20, 56 EC_INSNABORT_SAME_EL = 0x21, 57 EC_PCALIGNMENT = 0x22, 58 EC_DATAABORT = 0x24, 59 EC_DATAABORT_SAME_EL = 0x25, 60 EC_SPALIGNMENT = 0x26, 61 EC_MOP = 0x27, 62 EC_AA32_FPTRAP = 0x28, 63 EC_AA64_FPTRAP = 0x2c, 64 EC_SERROR = 0x2f, 65 EC_BREAKPOINT = 0x30, 66 EC_BREAKPOINT_SAME_EL = 0x31, 67 EC_SOFTWARESTEP = 0x32, 68 EC_SOFTWARESTEP_SAME_EL = 0x33, 69 EC_WATCHPOINT = 0x34, 70 EC_WATCHPOINT_SAME_EL = 0x35, 71 EC_AA32_BKPT = 0x38, 72 EC_VECTORCATCH = 0x3a, 73 EC_AA64_BKPT = 0x3c, 74 }; 75 76 typedef enum { 77 SME_ET_AccessTrap, 78 SME_ET_Streaming, 79 SME_ET_NotStreaming, 80 SME_ET_InactiveZA, 81 } SMEExceptionType; 82 83 #define ARM_EL_EC_SHIFT 26 84 #define ARM_EL_IL_SHIFT 25 85 #define ARM_EL_ISV_SHIFT 24 86 #define ARM_EL_IL (1 << ARM_EL_IL_SHIFT) 87 #define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT) 88 89 /* In the Data Abort syndrome */ 90 #define ARM_EL_VNCR (1 << 13) 91 92 static inline uint32_t syn_get_ec(uint32_t syn) 93 { 94 return syn >> ARM_EL_EC_SHIFT; 95 } 96 97 /* 98 * Utility functions for constructing various kinds of syndrome value. 99 * Note that in general we follow the AArch64 syndrome values; in a 100 * few cases the value in HSR for exceptions taken to AArch32 Hyp 101 * mode differs slightly, and we fix this up when populating HSR in 102 * arm_cpu_do_interrupt_aarch32_hyp(). 103 * The exception is FP/SIMD access traps -- these report extra information 104 * when taking an exception to AArch32. For those we include the extra coproc 105 * and TA fields, and mask them out when taking the exception to AArch64. 106 */ 107 static inline uint32_t syn_uncategorized(void) 108 { 109 return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL; 110 } 111 112 static inline uint32_t syn_aa64_svc(uint32_t imm16) 113 { 114 return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 115 } 116 117 static inline uint32_t syn_aa64_hvc(uint32_t imm16) 118 { 119 return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 120 } 121 122 static inline uint32_t syn_aa64_smc(uint32_t imm16) 123 { 124 return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 125 } 126 127 static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit) 128 { 129 return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) 130 | (is_16bit ? 0 : ARM_EL_IL); 131 } 132 133 static inline uint32_t syn_aa32_hvc(uint32_t imm16) 134 { 135 return (EC_AA32_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 136 } 137 138 static inline uint32_t syn_aa32_smc(void) 139 { 140 return (EC_AA32_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL; 141 } 142 143 static inline uint32_t syn_aa64_bkpt(uint32_t imm16) 144 { 145 return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 146 } 147 148 static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit) 149 { 150 return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) 151 | (is_16bit ? 0 : ARM_EL_IL); 152 } 153 154 static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2, 155 int crn, int crm, int rt, 156 int isread) 157 { 158 return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL 159 | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5) 160 | (crm << 1) | isread; 161 } 162 163 static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2, 164 int crn, int crm, int rt, int isread, 165 bool is_16bit) 166 { 167 return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT) 168 | (is_16bit ? 0 : ARM_EL_IL) 169 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) 170 | (crn << 10) | (rt << 5) | (crm << 1) | isread; 171 } 172 173 static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2, 174 int crn, int crm, int rt, int isread, 175 bool is_16bit) 176 { 177 return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT) 178 | (is_16bit ? 0 : ARM_EL_IL) 179 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) 180 | (crn << 10) | (rt << 5) | (crm << 1) | isread; 181 } 182 183 static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm, 184 int rt, int rt2, int isread, 185 bool is_16bit) 186 { 187 return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT) 188 | (is_16bit ? 0 : ARM_EL_IL) 189 | (cv << 24) | (cond << 20) | (opc1 << 16) 190 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; 191 } 192 193 static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm, 194 int rt, int rt2, int isread, 195 bool is_16bit) 196 { 197 return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT) 198 | (is_16bit ? 0 : ARM_EL_IL) 199 | (cv << 24) | (cond << 20) | (opc1 << 16) 200 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; 201 } 202 203 static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit, 204 int coproc) 205 { 206 /* AArch32 FP trap or any AArch64 FP/SIMD trap: TA == 0 */ 207 return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) 208 | (is_16bit ? 0 : ARM_EL_IL) 209 | (cv << 24) | (cond << 20) | coproc; 210 } 211 212 static inline uint32_t syn_simd_access_trap(int cv, int cond, bool is_16bit) 213 { 214 /* AArch32 SIMD trap: TA == 1 coproc == 0 */ 215 return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) 216 | (is_16bit ? 0 : ARM_EL_IL) 217 | (cv << 24) | (cond << 20) | (1 << 5); 218 } 219 220 static inline uint32_t syn_sve_access_trap(void) 221 { 222 return (EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL; 223 } 224 225 /* 226 * eret_op is bits [1:0] of the ERET instruction, so: 227 * 0 for ERET, 2 for ERETAA, 3 for ERETAB. 228 */ 229 static inline uint32_t syn_erettrap(int eret_op) 230 { 231 return (EC_ERETTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL | eret_op; 232 } 233 234 static inline uint32_t syn_smetrap(SMEExceptionType etype, bool is_16bit) 235 { 236 return (EC_SMETRAP << ARM_EL_EC_SHIFT) 237 | (is_16bit ? 0 : ARM_EL_IL) | etype; 238 } 239 240 static inline uint32_t syn_pacfail(bool data, int keynumber) 241 { 242 int error_code = (data << 1) | keynumber; 243 return (EC_PACFAIL << ARM_EL_EC_SHIFT) | ARM_EL_IL | error_code; 244 } 245 246 static inline uint32_t syn_pactrap(void) 247 { 248 return (EC_PACTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL; 249 } 250 251 static inline uint32_t syn_btitrap(int btype) 252 { 253 return (EC_BTITRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL | btype; 254 } 255 256 static inline uint32_t syn_bxjtrap(int cv, int cond, int rm) 257 { 258 return (EC_BXJTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL | 259 (cv << 24) | (cond << 20) | rm; 260 } 261 262 static inline uint32_t syn_gpc(int s2ptw, int ind, int gpcsc, int vncr, 263 int cm, int s1ptw, int wnr, int fsc) 264 { 265 return (EC_GPC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (s2ptw << 21) 266 | (ind << 20) | (gpcsc << 14) | (vncr << 13) | (cm << 8) 267 | (s1ptw << 7) | (wnr << 6) | fsc; 268 } 269 270 static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc) 271 { 272 return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 273 | ARM_EL_IL | (ea << 9) | (s1ptw << 7) | fsc; 274 } 275 276 static inline uint32_t syn_data_abort_no_iss(int same_el, int fnv, 277 int ea, int cm, int s1ptw, 278 int wnr, int fsc) 279 { 280 return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 281 | ARM_EL_IL 282 | (fnv << 10) | (ea << 9) | (cm << 8) | (s1ptw << 7) 283 | (wnr << 6) | fsc; 284 } 285 286 static inline uint32_t syn_data_abort_with_iss(int same_el, 287 int sas, int sse, int srt, 288 int sf, int ar, 289 int ea, int cm, int s1ptw, 290 int wnr, int fsc, 291 bool is_16bit) 292 { 293 return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 294 | (is_16bit ? 0 : ARM_EL_IL) 295 | ARM_EL_ISV | (sas << 22) | (sse << 21) | (srt << 16) 296 | (sf << 15) | (ar << 14) 297 | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc; 298 } 299 300 /* 301 * Faults due to FEAT_NV2 VNCR_EL2-based accesses report as same-EL 302 * Data Aborts with the VNCR bit set. 303 */ 304 static inline uint32_t syn_data_abort_vncr(int ea, int wnr, int fsc) 305 { 306 return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (1 << ARM_EL_EC_SHIFT) 307 | ARM_EL_IL | ARM_EL_VNCR | (wnr << 6) | fsc; 308 } 309 310 static inline uint32_t syn_swstep(int same_el, int isv, int ex) 311 { 312 return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 313 | ARM_EL_IL | (isv << 24) | (ex << 6) | 0x22; 314 } 315 316 static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr) 317 { 318 return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 319 | ARM_EL_IL | (cm << 8) | (wnr << 6) | 0x22; 320 } 321 322 static inline uint32_t syn_breakpoint(int same_el) 323 { 324 return (EC_BREAKPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 325 | ARM_EL_IL | 0x22; 326 } 327 328 static inline uint32_t syn_wfx(int cv, int cond, int ti, bool is_16bit) 329 { 330 return (EC_WFX_TRAP << ARM_EL_EC_SHIFT) | 331 (is_16bit ? 0 : (1 << ARM_EL_IL_SHIFT)) | 332 (cv << 24) | (cond << 20) | ti; 333 } 334 335 static inline uint32_t syn_illegalstate(void) 336 { 337 return (EC_ILLEGALSTATE << ARM_EL_EC_SHIFT) | ARM_EL_IL; 338 } 339 340 static inline uint32_t syn_pcalignment(void) 341 { 342 return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL; 343 } 344 345 static inline uint32_t syn_serror(uint32_t extra) 346 { 347 return (EC_SERROR << ARM_EL_EC_SHIFT) | ARM_EL_IL | extra; 348 } 349 350 static inline uint32_t syn_mop(bool is_set, bool is_setg, int options, 351 bool epilogue, bool wrong_option, bool option_a, 352 int destreg, int srcreg, int sizereg) 353 { 354 return (EC_MOP << ARM_EL_EC_SHIFT) | ARM_EL_IL | 355 (is_set << 24) | (is_setg << 23) | (options << 19) | 356 (epilogue << 18) | (wrong_option << 17) | (option_a << 16) | 357 (destreg << 10) | (srcreg << 5) | sizereg; 358 } 359 360 361 #endif /* TARGET_ARM_SYNDROME_H */ 362