1 /* 2 * QEMU ARM CPU -- syndrome functions and types 3 * 4 * Copyright (c) 2014 Linaro Ltd 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 * 20 * This header defines functions, types, etc which need to be shared 21 * between different source files within target/arm/ but which are 22 * private to it and not required by the rest of QEMU. 23 */ 24 25 #ifndef TARGET_ARM_SYNDROME_H 26 #define TARGET_ARM_SYNDROME_H 27 28 #include "qemu/bitops.h" 29 30 /* Valid Syndrome Register EC field values */ 31 enum arm_exception_class { 32 EC_UNCATEGORIZED = 0x00, 33 EC_WFX_TRAP = 0x01, 34 EC_CP15RTTRAP = 0x03, 35 EC_CP15RRTTRAP = 0x04, 36 EC_CP14RTTRAP = 0x05, 37 EC_CP14DTTRAP = 0x06, 38 EC_ADVSIMDFPACCESSTRAP = 0x07, 39 EC_FPIDTRAP = 0x08, 40 EC_PACTRAP = 0x09, 41 EC_BXJTRAP = 0x0a, 42 EC_CP14RRTTRAP = 0x0c, 43 EC_BTITRAP = 0x0d, 44 EC_ILLEGALSTATE = 0x0e, 45 EC_AA32_SVC = 0x11, 46 EC_AA32_HVC = 0x12, 47 EC_AA32_SMC = 0x13, 48 EC_AA64_SVC = 0x15, 49 EC_AA64_HVC = 0x16, 50 EC_AA64_SMC = 0x17, 51 EC_SYSTEMREGISTERTRAP = 0x18, 52 EC_SVEACCESSTRAP = 0x19, 53 EC_ERETTRAP = 0x1a, 54 EC_PACFAIL = 0x1c, 55 EC_SMETRAP = 0x1d, 56 EC_GPC = 0x1e, 57 EC_INSNABORT = 0x20, 58 EC_INSNABORT_SAME_EL = 0x21, 59 EC_PCALIGNMENT = 0x22, 60 EC_DATAABORT = 0x24, 61 EC_DATAABORT_SAME_EL = 0x25, 62 EC_SPALIGNMENT = 0x26, 63 EC_MOP = 0x27, 64 EC_AA32_FPTRAP = 0x28, 65 EC_AA64_FPTRAP = 0x2c, 66 EC_SERROR = 0x2f, 67 EC_BREAKPOINT = 0x30, 68 EC_BREAKPOINT_SAME_EL = 0x31, 69 EC_SOFTWARESTEP = 0x32, 70 EC_SOFTWARESTEP_SAME_EL = 0x33, 71 EC_WATCHPOINT = 0x34, 72 EC_WATCHPOINT_SAME_EL = 0x35, 73 EC_AA32_BKPT = 0x38, 74 EC_VECTORCATCH = 0x3a, 75 EC_AA64_BKPT = 0x3c, 76 }; 77 78 typedef enum { 79 SME_ET_AccessTrap, 80 SME_ET_Streaming, 81 SME_ET_NotStreaming, 82 SME_ET_InactiveZA, 83 } SMEExceptionType; 84 85 #define ARM_EL_EC_LENGTH 6 86 #define ARM_EL_EC_SHIFT 26 87 #define ARM_EL_IL_SHIFT 25 88 #define ARM_EL_ISV_SHIFT 24 89 #define ARM_EL_IL (1 << ARM_EL_IL_SHIFT) 90 #define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT) 91 92 /* In the Data Abort syndrome */ 93 #define ARM_EL_VNCR (1 << 13) 94 95 static inline uint32_t syn_get_ec(uint32_t syn) 96 { 97 return syn >> ARM_EL_EC_SHIFT; 98 } 99 100 static inline uint32_t syn_set_ec(uint32_t syn, uint32_t ec) 101 { 102 return deposit32(syn, ARM_EL_EC_SHIFT, ARM_EL_EC_LENGTH, ec); 103 } 104 105 /* 106 * Utility functions for constructing various kinds of syndrome value. 107 * Note that in general we follow the AArch64 syndrome values; in a 108 * few cases the value in HSR for exceptions taken to AArch32 Hyp 109 * mode differs slightly, and we fix this up when populating HSR in 110 * arm_cpu_do_interrupt_aarch32_hyp(). 111 * The exception is FP/SIMD access traps -- these report extra information 112 * when taking an exception to AArch32. For those we include the extra coproc 113 * and TA fields, and mask them out when taking the exception to AArch64. 114 */ 115 static inline uint32_t syn_uncategorized(void) 116 { 117 return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL; 118 } 119 120 static inline uint32_t syn_aa64_svc(uint32_t imm16) 121 { 122 return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 123 } 124 125 static inline uint32_t syn_aa64_hvc(uint32_t imm16) 126 { 127 return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 128 } 129 130 static inline uint32_t syn_aa64_smc(uint32_t imm16) 131 { 132 return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 133 } 134 135 static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit) 136 { 137 return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) 138 | (is_16bit ? 0 : ARM_EL_IL); 139 } 140 141 static inline uint32_t syn_aa32_hvc(uint32_t imm16) 142 { 143 return (EC_AA32_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 144 } 145 146 static inline uint32_t syn_aa32_smc(void) 147 { 148 return (EC_AA32_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL; 149 } 150 151 static inline uint32_t syn_aa64_bkpt(uint32_t imm16) 152 { 153 return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 154 } 155 156 static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit) 157 { 158 return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) 159 | (is_16bit ? 0 : ARM_EL_IL); 160 } 161 162 static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2, 163 int crn, int crm, int rt, 164 int isread) 165 { 166 return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL 167 | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5) 168 | (crm << 1) | isread; 169 } 170 171 static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2, 172 int crn, int crm, int rt, int isread, 173 bool is_16bit) 174 { 175 return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT) 176 | (is_16bit ? 0 : ARM_EL_IL) 177 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) 178 | (crn << 10) | (rt << 5) | (crm << 1) | isread; 179 } 180 181 static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2, 182 int crn, int crm, int rt, int isread, 183 bool is_16bit) 184 { 185 return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT) 186 | (is_16bit ? 0 : ARM_EL_IL) 187 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) 188 | (crn << 10) | (rt << 5) | (crm << 1) | isread; 189 } 190 191 static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm, 192 int rt, int rt2, int isread, 193 bool is_16bit) 194 { 195 return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT) 196 | (is_16bit ? 0 : ARM_EL_IL) 197 | (cv << 24) | (cond << 20) | (opc1 << 16) 198 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; 199 } 200 201 static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm, 202 int rt, int rt2, int isread, 203 bool is_16bit) 204 { 205 return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT) 206 | (is_16bit ? 0 : ARM_EL_IL) 207 | (cv << 24) | (cond << 20) | (opc1 << 16) 208 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; 209 } 210 211 static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit, 212 int coproc) 213 { 214 /* AArch32 FP trap or any AArch64 FP/SIMD trap: TA == 0 */ 215 return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) 216 | (is_16bit ? 0 : ARM_EL_IL) 217 | (cv << 24) | (cond << 20) | coproc; 218 } 219 220 static inline uint32_t syn_simd_access_trap(int cv, int cond, bool is_16bit) 221 { 222 /* AArch32 SIMD trap: TA == 1 coproc == 0 */ 223 return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) 224 | (is_16bit ? 0 : ARM_EL_IL) 225 | (cv << 24) | (cond << 20) | (1 << 5); 226 } 227 228 static inline uint32_t syn_sve_access_trap(void) 229 { 230 return (EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL; 231 } 232 233 /* 234 * eret_op is bits [1:0] of the ERET instruction, so: 235 * 0 for ERET, 2 for ERETAA, 3 for ERETAB. 236 */ 237 static inline uint32_t syn_erettrap(int eret_op) 238 { 239 return (EC_ERETTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL | eret_op; 240 } 241 242 static inline uint32_t syn_smetrap(SMEExceptionType etype, bool is_16bit) 243 { 244 return (EC_SMETRAP << ARM_EL_EC_SHIFT) 245 | (is_16bit ? 0 : ARM_EL_IL) | etype; 246 } 247 248 static inline uint32_t syn_pacfail(bool data, int keynumber) 249 { 250 int error_code = (data << 1) | keynumber; 251 return (EC_PACFAIL << ARM_EL_EC_SHIFT) | ARM_EL_IL | error_code; 252 } 253 254 static inline uint32_t syn_pactrap(void) 255 { 256 return (EC_PACTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL; 257 } 258 259 static inline uint32_t syn_btitrap(int btype) 260 { 261 return (EC_BTITRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL | btype; 262 } 263 264 static inline uint32_t syn_bxjtrap(int cv, int cond, int rm) 265 { 266 return (EC_BXJTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL | 267 (cv << 24) | (cond << 20) | rm; 268 } 269 270 static inline uint32_t syn_gpc(int s2ptw, int ind, int gpcsc, int vncr, 271 int cm, int s1ptw, int wnr, int fsc) 272 { 273 return (EC_GPC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (s2ptw << 21) 274 | (ind << 20) | (gpcsc << 14) | (vncr << 13) | (cm << 8) 275 | (s1ptw << 7) | (wnr << 6) | fsc; 276 } 277 278 static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc) 279 { 280 return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 281 | ARM_EL_IL | (ea << 9) | (s1ptw << 7) | fsc; 282 } 283 284 static inline uint32_t syn_data_abort_no_iss(int same_el, int fnv, 285 int ea, int cm, int s1ptw, 286 int wnr, int fsc) 287 { 288 return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 289 | ARM_EL_IL 290 | (fnv << 10) | (ea << 9) | (cm << 8) | (s1ptw << 7) 291 | (wnr << 6) | fsc; 292 } 293 294 static inline uint32_t syn_data_abort_with_iss(int same_el, 295 int sas, int sse, int srt, 296 int sf, int ar, 297 int ea, int cm, int s1ptw, 298 int wnr, int fsc, 299 bool is_16bit) 300 { 301 return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 302 | (is_16bit ? 0 : ARM_EL_IL) 303 | ARM_EL_ISV | (sas << 22) | (sse << 21) | (srt << 16) 304 | (sf << 15) | (ar << 14) 305 | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc; 306 } 307 308 /* 309 * Faults due to FEAT_NV2 VNCR_EL2-based accesses report as same-EL 310 * Data Aborts with the VNCR bit set. 311 */ 312 static inline uint32_t syn_data_abort_vncr(int ea, int wnr, int fsc) 313 { 314 return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (1 << ARM_EL_EC_SHIFT) 315 | ARM_EL_IL | ARM_EL_VNCR | (wnr << 6) | fsc; 316 } 317 318 static inline uint32_t syn_swstep(int same_el, int isv, int ex) 319 { 320 return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 321 | ARM_EL_IL | (isv << 24) | (ex << 6) | 0x22; 322 } 323 324 static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr) 325 { 326 return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 327 | ARM_EL_IL | (cm << 8) | (wnr << 6) | 0x22; 328 } 329 330 static inline uint32_t syn_breakpoint(int same_el) 331 { 332 return (EC_BREAKPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 333 | ARM_EL_IL | 0x22; 334 } 335 336 static inline uint32_t syn_wfx(int cv, int cond, int ti, bool is_16bit) 337 { 338 return (EC_WFX_TRAP << ARM_EL_EC_SHIFT) | 339 (is_16bit ? 0 : (1 << ARM_EL_IL_SHIFT)) | 340 (cv << 24) | (cond << 20) | ti; 341 } 342 343 static inline uint32_t syn_illegalstate(void) 344 { 345 return (EC_ILLEGALSTATE << ARM_EL_EC_SHIFT) | ARM_EL_IL; 346 } 347 348 static inline uint32_t syn_pcalignment(void) 349 { 350 return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL; 351 } 352 353 static inline uint32_t syn_serror(uint32_t extra) 354 { 355 return (EC_SERROR << ARM_EL_EC_SHIFT) | ARM_EL_IL | extra; 356 } 357 358 static inline uint32_t syn_mop(bool is_set, bool is_setg, int options, 359 bool epilogue, bool wrong_option, bool option_a, 360 int destreg, int srcreg, int sizereg) 361 { 362 return (EC_MOP << ARM_EL_EC_SHIFT) | ARM_EL_IL | 363 (is_set << 24) | (is_setg << 23) | (options << 19) | 364 (epilogue << 18) | (wrong_option << 17) | (option_a << 16) | 365 (destreg << 10) | (srcreg << 5) | sizereg; 366 } 367 368 369 #endif /* TARGET_ARM_SYNDROME_H */ 370