1 /* 2 * QEMU ARM CPU -- syndrome functions and types 3 * 4 * Copyright (c) 2014 Linaro Ltd 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 * 20 * This header defines functions, types, etc which need to be shared 21 * between different source files within target/arm/ but which are 22 * private to it and not required by the rest of QEMU. 23 */ 24 25 #ifndef TARGET_ARM_SYNDROME_H 26 #define TARGET_ARM_SYNDROME_H 27 28 /* Valid Syndrome Register EC field values */ 29 enum arm_exception_class { 30 EC_UNCATEGORIZED = 0x00, 31 EC_WFX_TRAP = 0x01, 32 EC_CP15RTTRAP = 0x03, 33 EC_CP15RRTTRAP = 0x04, 34 EC_CP14RTTRAP = 0x05, 35 EC_CP14DTTRAP = 0x06, 36 EC_ADVSIMDFPACCESSTRAP = 0x07, 37 EC_FPIDTRAP = 0x08, 38 EC_PACTRAP = 0x09, 39 EC_BXJTRAP = 0x0a, 40 EC_CP14RRTTRAP = 0x0c, 41 EC_BTITRAP = 0x0d, 42 EC_ILLEGALSTATE = 0x0e, 43 EC_AA32_SVC = 0x11, 44 EC_AA32_HVC = 0x12, 45 EC_AA32_SMC = 0x13, 46 EC_AA64_SVC = 0x15, 47 EC_AA64_HVC = 0x16, 48 EC_AA64_SMC = 0x17, 49 EC_SYSTEMREGISTERTRAP = 0x18, 50 EC_SVEACCESSTRAP = 0x19, 51 EC_ERETTRAP = 0x1a, 52 EC_PACFAIL = 0x1c, 53 EC_SMETRAP = 0x1d, 54 EC_GPC = 0x1e, 55 EC_INSNABORT = 0x20, 56 EC_INSNABORT_SAME_EL = 0x21, 57 EC_PCALIGNMENT = 0x22, 58 EC_DATAABORT = 0x24, 59 EC_DATAABORT_SAME_EL = 0x25, 60 EC_SPALIGNMENT = 0x26, 61 EC_AA32_FPTRAP = 0x28, 62 EC_AA64_FPTRAP = 0x2c, 63 EC_SERROR = 0x2f, 64 EC_BREAKPOINT = 0x30, 65 EC_BREAKPOINT_SAME_EL = 0x31, 66 EC_SOFTWARESTEP = 0x32, 67 EC_SOFTWARESTEP_SAME_EL = 0x33, 68 EC_WATCHPOINT = 0x34, 69 EC_WATCHPOINT_SAME_EL = 0x35, 70 EC_AA32_BKPT = 0x38, 71 EC_VECTORCATCH = 0x3a, 72 EC_AA64_BKPT = 0x3c, 73 }; 74 75 typedef enum { 76 SME_ET_AccessTrap, 77 SME_ET_Streaming, 78 SME_ET_NotStreaming, 79 SME_ET_InactiveZA, 80 } SMEExceptionType; 81 82 #define ARM_EL_EC_SHIFT 26 83 #define ARM_EL_IL_SHIFT 25 84 #define ARM_EL_ISV_SHIFT 24 85 #define ARM_EL_IL (1 << ARM_EL_IL_SHIFT) 86 #define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT) 87 88 static inline uint32_t syn_get_ec(uint32_t syn) 89 { 90 return syn >> ARM_EL_EC_SHIFT; 91 } 92 93 /* 94 * Utility functions for constructing various kinds of syndrome value. 95 * Note that in general we follow the AArch64 syndrome values; in a 96 * few cases the value in HSR for exceptions taken to AArch32 Hyp 97 * mode differs slightly, and we fix this up when populating HSR in 98 * arm_cpu_do_interrupt_aarch32_hyp(). 99 * The exception is FP/SIMD access traps -- these report extra information 100 * when taking an exception to AArch32. For those we include the extra coproc 101 * and TA fields, and mask them out when taking the exception to AArch64. 102 */ 103 static inline uint32_t syn_uncategorized(void) 104 { 105 return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL; 106 } 107 108 static inline uint32_t syn_aa64_svc(uint32_t imm16) 109 { 110 return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 111 } 112 113 static inline uint32_t syn_aa64_hvc(uint32_t imm16) 114 { 115 return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 116 } 117 118 static inline uint32_t syn_aa64_smc(uint32_t imm16) 119 { 120 return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 121 } 122 123 static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit) 124 { 125 return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) 126 | (is_16bit ? 0 : ARM_EL_IL); 127 } 128 129 static inline uint32_t syn_aa32_hvc(uint32_t imm16) 130 { 131 return (EC_AA32_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 132 } 133 134 static inline uint32_t syn_aa32_smc(void) 135 { 136 return (EC_AA32_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL; 137 } 138 139 static inline uint32_t syn_aa64_bkpt(uint32_t imm16) 140 { 141 return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 142 } 143 144 static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit) 145 { 146 return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) 147 | (is_16bit ? 0 : ARM_EL_IL); 148 } 149 150 static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2, 151 int crn, int crm, int rt, 152 int isread) 153 { 154 return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL 155 | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5) 156 | (crm << 1) | isread; 157 } 158 159 static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2, 160 int crn, int crm, int rt, int isread, 161 bool is_16bit) 162 { 163 return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT) 164 | (is_16bit ? 0 : ARM_EL_IL) 165 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) 166 | (crn << 10) | (rt << 5) | (crm << 1) | isread; 167 } 168 169 static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2, 170 int crn, int crm, int rt, int isread, 171 bool is_16bit) 172 { 173 return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT) 174 | (is_16bit ? 0 : ARM_EL_IL) 175 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) 176 | (crn << 10) | (rt << 5) | (crm << 1) | isread; 177 } 178 179 static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm, 180 int rt, int rt2, int isread, 181 bool is_16bit) 182 { 183 return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT) 184 | (is_16bit ? 0 : ARM_EL_IL) 185 | (cv << 24) | (cond << 20) | (opc1 << 16) 186 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; 187 } 188 189 static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm, 190 int rt, int rt2, int isread, 191 bool is_16bit) 192 { 193 return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT) 194 | (is_16bit ? 0 : ARM_EL_IL) 195 | (cv << 24) | (cond << 20) | (opc1 << 16) 196 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; 197 } 198 199 static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit, 200 int coproc) 201 { 202 /* AArch32 FP trap or any AArch64 FP/SIMD trap: TA == 0 */ 203 return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) 204 | (is_16bit ? 0 : ARM_EL_IL) 205 | (cv << 24) | (cond << 20) | coproc; 206 } 207 208 static inline uint32_t syn_simd_access_trap(int cv, int cond, bool is_16bit) 209 { 210 /* AArch32 SIMD trap: TA == 1 coproc == 0 */ 211 return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) 212 | (is_16bit ? 0 : ARM_EL_IL) 213 | (cv << 24) | (cond << 20) | (1 << 5); 214 } 215 216 static inline uint32_t syn_sve_access_trap(void) 217 { 218 return EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT; 219 } 220 221 /* 222 * eret_op is bits [1:0] of the ERET instruction, so: 223 * 0 for ERET, 2 for ERETAA, 3 for ERETAB. 224 */ 225 static inline uint32_t syn_erettrap(int eret_op) 226 { 227 return (EC_ERETTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL | eret_op; 228 } 229 230 static inline uint32_t syn_smetrap(SMEExceptionType etype, bool is_16bit) 231 { 232 return (EC_SMETRAP << ARM_EL_EC_SHIFT) 233 | (is_16bit ? 0 : ARM_EL_IL) | etype; 234 } 235 236 static inline uint32_t syn_pacfail(bool data, int keynumber) 237 { 238 int error_code = (data << 1) | keynumber; 239 return (EC_PACFAIL << ARM_EL_EC_SHIFT) | ARM_EL_IL | error_code; 240 } 241 242 static inline uint32_t syn_pactrap(void) 243 { 244 return EC_PACTRAP << ARM_EL_EC_SHIFT; 245 } 246 247 static inline uint32_t syn_btitrap(int btype) 248 { 249 return (EC_BTITRAP << ARM_EL_EC_SHIFT) | btype; 250 } 251 252 static inline uint32_t syn_bxjtrap(int cv, int cond, int rm) 253 { 254 return (EC_BXJTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL | 255 (cv << 24) | (cond << 20) | rm; 256 } 257 258 static inline uint32_t syn_gpc(int s2ptw, int ind, int gpcsc, 259 int cm, int s1ptw, int wnr, int fsc) 260 { 261 /* TODO: FEAT_NV2 adds VNCR */ 262 return (EC_GPC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (s2ptw << 21) 263 | (ind << 20) | (gpcsc << 14) | (cm << 8) | (s1ptw << 7) 264 | (wnr << 6) | fsc; 265 } 266 267 static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc) 268 { 269 return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 270 | ARM_EL_IL | (ea << 9) | (s1ptw << 7) | fsc; 271 } 272 273 static inline uint32_t syn_data_abort_no_iss(int same_el, int fnv, 274 int ea, int cm, int s1ptw, 275 int wnr, int fsc) 276 { 277 return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 278 | ARM_EL_IL 279 | (fnv << 10) | (ea << 9) | (cm << 8) | (s1ptw << 7) 280 | (wnr << 6) | fsc; 281 } 282 283 static inline uint32_t syn_data_abort_with_iss(int same_el, 284 int sas, int sse, int srt, 285 int sf, int ar, 286 int ea, int cm, int s1ptw, 287 int wnr, int fsc, 288 bool is_16bit) 289 { 290 return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 291 | (is_16bit ? 0 : ARM_EL_IL) 292 | ARM_EL_ISV | (sas << 22) | (sse << 21) | (srt << 16) 293 | (sf << 15) | (ar << 14) 294 | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc; 295 } 296 297 static inline uint32_t syn_swstep(int same_el, int isv, int ex) 298 { 299 return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 300 | ARM_EL_IL | (isv << 24) | (ex << 6) | 0x22; 301 } 302 303 static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr) 304 { 305 return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 306 | ARM_EL_IL | (cm << 8) | (wnr << 6) | 0x22; 307 } 308 309 static inline uint32_t syn_breakpoint(int same_el) 310 { 311 return (EC_BREAKPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 312 | ARM_EL_IL | 0x22; 313 } 314 315 static inline uint32_t syn_wfx(int cv, int cond, int ti, bool is_16bit) 316 { 317 return (EC_WFX_TRAP << ARM_EL_EC_SHIFT) | 318 (is_16bit ? 0 : (1 << ARM_EL_IL_SHIFT)) | 319 (cv << 24) | (cond << 20) | ti; 320 } 321 322 static inline uint32_t syn_illegalstate(void) 323 { 324 return (EC_ILLEGALSTATE << ARM_EL_EC_SHIFT) | ARM_EL_IL; 325 } 326 327 static inline uint32_t syn_pcalignment(void) 328 { 329 return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL; 330 } 331 332 static inline uint32_t syn_serror(uint32_t extra) 333 { 334 return (EC_SERROR << ARM_EL_EC_SHIFT) | ARM_EL_IL | extra; 335 } 336 337 #endif /* TARGET_ARM_SYNDROME_H */ 338