1 /* 2 * QEMU ARM CPU -- syndrome functions and types 3 * 4 * Copyright (c) 2014 Linaro Ltd 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 * 20 * This header defines functions, types, etc which need to be shared 21 * between different source files within target/arm/ but which are 22 * private to it and not required by the rest of QEMU. 23 */ 24 25 #ifndef TARGET_ARM_SYNDROME_H 26 #define TARGET_ARM_SYNDROME_H 27 28 /* Valid Syndrome Register EC field values */ 29 enum arm_exception_class { 30 EC_UNCATEGORIZED = 0x00, 31 EC_WFX_TRAP = 0x01, 32 EC_CP15RTTRAP = 0x03, 33 EC_CP15RRTTRAP = 0x04, 34 EC_CP14RTTRAP = 0x05, 35 EC_CP14DTTRAP = 0x06, 36 EC_ADVSIMDFPACCESSTRAP = 0x07, 37 EC_FPIDTRAP = 0x08, 38 EC_PACTRAP = 0x09, 39 EC_BXJTRAP = 0x0a, 40 EC_CP14RRTTRAP = 0x0c, 41 EC_BTITRAP = 0x0d, 42 EC_ILLEGALSTATE = 0x0e, 43 EC_AA32_SVC = 0x11, 44 EC_AA32_HVC = 0x12, 45 EC_AA32_SMC = 0x13, 46 EC_AA64_SVC = 0x15, 47 EC_AA64_HVC = 0x16, 48 EC_AA64_SMC = 0x17, 49 EC_SYSTEMREGISTERTRAP = 0x18, 50 EC_SVEACCESSTRAP = 0x19, 51 EC_ERETTRAP = 0x1a, 52 EC_PACFAIL = 0x1c, 53 EC_SMETRAP = 0x1d, 54 EC_GPC = 0x1e, 55 EC_INSNABORT = 0x20, 56 EC_INSNABORT_SAME_EL = 0x21, 57 EC_PCALIGNMENT = 0x22, 58 EC_DATAABORT = 0x24, 59 EC_DATAABORT_SAME_EL = 0x25, 60 EC_SPALIGNMENT = 0x26, 61 EC_MOP = 0x27, 62 EC_AA32_FPTRAP = 0x28, 63 EC_AA64_FPTRAP = 0x2c, 64 EC_SERROR = 0x2f, 65 EC_BREAKPOINT = 0x30, 66 EC_BREAKPOINT_SAME_EL = 0x31, 67 EC_SOFTWARESTEP = 0x32, 68 EC_SOFTWARESTEP_SAME_EL = 0x33, 69 EC_WATCHPOINT = 0x34, 70 EC_WATCHPOINT_SAME_EL = 0x35, 71 EC_AA32_BKPT = 0x38, 72 EC_VECTORCATCH = 0x3a, 73 EC_AA64_BKPT = 0x3c, 74 }; 75 76 typedef enum { 77 SME_ET_AccessTrap, 78 SME_ET_Streaming, 79 SME_ET_NotStreaming, 80 SME_ET_InactiveZA, 81 } SMEExceptionType; 82 83 #define ARM_EL_EC_SHIFT 26 84 #define ARM_EL_IL_SHIFT 25 85 #define ARM_EL_ISV_SHIFT 24 86 #define ARM_EL_IL (1 << ARM_EL_IL_SHIFT) 87 #define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT) 88 89 static inline uint32_t syn_get_ec(uint32_t syn) 90 { 91 return syn >> ARM_EL_EC_SHIFT; 92 } 93 94 /* 95 * Utility functions for constructing various kinds of syndrome value. 96 * Note that in general we follow the AArch64 syndrome values; in a 97 * few cases the value in HSR for exceptions taken to AArch32 Hyp 98 * mode differs slightly, and we fix this up when populating HSR in 99 * arm_cpu_do_interrupt_aarch32_hyp(). 100 * The exception is FP/SIMD access traps -- these report extra information 101 * when taking an exception to AArch32. For those we include the extra coproc 102 * and TA fields, and mask them out when taking the exception to AArch64. 103 */ 104 static inline uint32_t syn_uncategorized(void) 105 { 106 return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL; 107 } 108 109 static inline uint32_t syn_aa64_svc(uint32_t imm16) 110 { 111 return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 112 } 113 114 static inline uint32_t syn_aa64_hvc(uint32_t imm16) 115 { 116 return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 117 } 118 119 static inline uint32_t syn_aa64_smc(uint32_t imm16) 120 { 121 return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 122 } 123 124 static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit) 125 { 126 return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) 127 | (is_16bit ? 0 : ARM_EL_IL); 128 } 129 130 static inline uint32_t syn_aa32_hvc(uint32_t imm16) 131 { 132 return (EC_AA32_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 133 } 134 135 static inline uint32_t syn_aa32_smc(void) 136 { 137 return (EC_AA32_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL; 138 } 139 140 static inline uint32_t syn_aa64_bkpt(uint32_t imm16) 141 { 142 return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 143 } 144 145 static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit) 146 { 147 return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) 148 | (is_16bit ? 0 : ARM_EL_IL); 149 } 150 151 static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2, 152 int crn, int crm, int rt, 153 int isread) 154 { 155 return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL 156 | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5) 157 | (crm << 1) | isread; 158 } 159 160 static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2, 161 int crn, int crm, int rt, int isread, 162 bool is_16bit) 163 { 164 return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT) 165 | (is_16bit ? 0 : ARM_EL_IL) 166 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) 167 | (crn << 10) | (rt << 5) | (crm << 1) | isread; 168 } 169 170 static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2, 171 int crn, int crm, int rt, int isread, 172 bool is_16bit) 173 { 174 return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT) 175 | (is_16bit ? 0 : ARM_EL_IL) 176 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) 177 | (crn << 10) | (rt << 5) | (crm << 1) | isread; 178 } 179 180 static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm, 181 int rt, int rt2, int isread, 182 bool is_16bit) 183 { 184 return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT) 185 | (is_16bit ? 0 : ARM_EL_IL) 186 | (cv << 24) | (cond << 20) | (opc1 << 16) 187 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; 188 } 189 190 static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm, 191 int rt, int rt2, int isread, 192 bool is_16bit) 193 { 194 return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT) 195 | (is_16bit ? 0 : ARM_EL_IL) 196 | (cv << 24) | (cond << 20) | (opc1 << 16) 197 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; 198 } 199 200 static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit, 201 int coproc) 202 { 203 /* AArch32 FP trap or any AArch64 FP/SIMD trap: TA == 0 */ 204 return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) 205 | (is_16bit ? 0 : ARM_EL_IL) 206 | (cv << 24) | (cond << 20) | coproc; 207 } 208 209 static inline uint32_t syn_simd_access_trap(int cv, int cond, bool is_16bit) 210 { 211 /* AArch32 SIMD trap: TA == 1 coproc == 0 */ 212 return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) 213 | (is_16bit ? 0 : ARM_EL_IL) 214 | (cv << 24) | (cond << 20) | (1 << 5); 215 } 216 217 static inline uint32_t syn_sve_access_trap(void) 218 { 219 return EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT; 220 } 221 222 /* 223 * eret_op is bits [1:0] of the ERET instruction, so: 224 * 0 for ERET, 2 for ERETAA, 3 for ERETAB. 225 */ 226 static inline uint32_t syn_erettrap(int eret_op) 227 { 228 return (EC_ERETTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL | eret_op; 229 } 230 231 static inline uint32_t syn_smetrap(SMEExceptionType etype, bool is_16bit) 232 { 233 return (EC_SMETRAP << ARM_EL_EC_SHIFT) 234 | (is_16bit ? 0 : ARM_EL_IL) | etype; 235 } 236 237 static inline uint32_t syn_pacfail(bool data, int keynumber) 238 { 239 int error_code = (data << 1) | keynumber; 240 return (EC_PACFAIL << ARM_EL_EC_SHIFT) | ARM_EL_IL | error_code; 241 } 242 243 static inline uint32_t syn_pactrap(void) 244 { 245 return EC_PACTRAP << ARM_EL_EC_SHIFT; 246 } 247 248 static inline uint32_t syn_btitrap(int btype) 249 { 250 return (EC_BTITRAP << ARM_EL_EC_SHIFT) | btype; 251 } 252 253 static inline uint32_t syn_bxjtrap(int cv, int cond, int rm) 254 { 255 return (EC_BXJTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL | 256 (cv << 24) | (cond << 20) | rm; 257 } 258 259 static inline uint32_t syn_gpc(int s2ptw, int ind, int gpcsc, 260 int cm, int s1ptw, int wnr, int fsc) 261 { 262 /* TODO: FEAT_NV2 adds VNCR */ 263 return (EC_GPC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (s2ptw << 21) 264 | (ind << 20) | (gpcsc << 14) | (cm << 8) | (s1ptw << 7) 265 | (wnr << 6) | fsc; 266 } 267 268 static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc) 269 { 270 return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 271 | ARM_EL_IL | (ea << 9) | (s1ptw << 7) | fsc; 272 } 273 274 static inline uint32_t syn_data_abort_no_iss(int same_el, int fnv, 275 int ea, int cm, int s1ptw, 276 int wnr, int fsc) 277 { 278 return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 279 | ARM_EL_IL 280 | (fnv << 10) | (ea << 9) | (cm << 8) | (s1ptw << 7) 281 | (wnr << 6) | fsc; 282 } 283 284 static inline uint32_t syn_data_abort_with_iss(int same_el, 285 int sas, int sse, int srt, 286 int sf, int ar, 287 int ea, int cm, int s1ptw, 288 int wnr, int fsc, 289 bool is_16bit) 290 { 291 return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 292 | (is_16bit ? 0 : ARM_EL_IL) 293 | ARM_EL_ISV | (sas << 22) | (sse << 21) | (srt << 16) 294 | (sf << 15) | (ar << 14) 295 | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc; 296 } 297 298 static inline uint32_t syn_swstep(int same_el, int isv, int ex) 299 { 300 return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 301 | ARM_EL_IL | (isv << 24) | (ex << 6) | 0x22; 302 } 303 304 static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr) 305 { 306 return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 307 | ARM_EL_IL | (cm << 8) | (wnr << 6) | 0x22; 308 } 309 310 static inline uint32_t syn_breakpoint(int same_el) 311 { 312 return (EC_BREAKPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 313 | ARM_EL_IL | 0x22; 314 } 315 316 static inline uint32_t syn_wfx(int cv, int cond, int ti, bool is_16bit) 317 { 318 return (EC_WFX_TRAP << ARM_EL_EC_SHIFT) | 319 (is_16bit ? 0 : (1 << ARM_EL_IL_SHIFT)) | 320 (cv << 24) | (cond << 20) | ti; 321 } 322 323 static inline uint32_t syn_illegalstate(void) 324 { 325 return (EC_ILLEGALSTATE << ARM_EL_EC_SHIFT) | ARM_EL_IL; 326 } 327 328 static inline uint32_t syn_pcalignment(void) 329 { 330 return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL; 331 } 332 333 static inline uint32_t syn_serror(uint32_t extra) 334 { 335 return (EC_SERROR << ARM_EL_EC_SHIFT) | ARM_EL_IL | extra; 336 } 337 338 static inline uint32_t syn_mop(bool is_set, bool is_setg, int options, 339 bool epilogue, bool wrong_option, bool option_a, 340 int destreg, int srcreg, int sizereg) 341 { 342 return (EC_MOP << ARM_EL_EC_SHIFT) | ARM_EL_IL | 343 (is_set << 24) | (is_setg << 23) | (options << 19) | 344 (epilogue << 18) | (wrong_option << 17) | (option_a << 16) | 345 (destreg << 10) | (srcreg << 5) | sizereg; 346 } 347 348 349 #endif /* TARGET_ARM_SYNDROME_H */ 350