1 /* 2 * QEMU ARM CPU -- syndrome functions and types 3 * 4 * Copyright (c) 2014 Linaro Ltd 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 * 20 * This header defines functions, types, etc which need to be shared 21 * between different source files within target/arm/ but which are 22 * private to it and not required by the rest of QEMU. 23 */ 24 25 #ifndef TARGET_ARM_SYNDROME_H 26 #define TARGET_ARM_SYNDROME_H 27 28 /* Valid Syndrome Register EC field values */ 29 enum arm_exception_class { 30 EC_UNCATEGORIZED = 0x00, 31 EC_WFX_TRAP = 0x01, 32 EC_CP15RTTRAP = 0x03, 33 EC_CP15RRTTRAP = 0x04, 34 EC_CP14RTTRAP = 0x05, 35 EC_CP14DTTRAP = 0x06, 36 EC_ADVSIMDFPACCESSTRAP = 0x07, 37 EC_FPIDTRAP = 0x08, 38 EC_PACTRAP = 0x09, 39 EC_BXJTRAP = 0x0a, 40 EC_CP14RRTTRAP = 0x0c, 41 EC_BTITRAP = 0x0d, 42 EC_ILLEGALSTATE = 0x0e, 43 EC_AA32_SVC = 0x11, 44 EC_AA32_HVC = 0x12, 45 EC_AA32_SMC = 0x13, 46 EC_AA64_SVC = 0x15, 47 EC_AA64_HVC = 0x16, 48 EC_AA64_SMC = 0x17, 49 EC_SYSTEMREGISTERTRAP = 0x18, 50 EC_SVEACCESSTRAP = 0x19, 51 EC_ERETTRAP = 0x1a, 52 EC_SMETRAP = 0x1d, 53 EC_GPC = 0x1e, 54 EC_INSNABORT = 0x20, 55 EC_INSNABORT_SAME_EL = 0x21, 56 EC_PCALIGNMENT = 0x22, 57 EC_DATAABORT = 0x24, 58 EC_DATAABORT_SAME_EL = 0x25, 59 EC_SPALIGNMENT = 0x26, 60 EC_AA32_FPTRAP = 0x28, 61 EC_AA64_FPTRAP = 0x2c, 62 EC_SERROR = 0x2f, 63 EC_BREAKPOINT = 0x30, 64 EC_BREAKPOINT_SAME_EL = 0x31, 65 EC_SOFTWARESTEP = 0x32, 66 EC_SOFTWARESTEP_SAME_EL = 0x33, 67 EC_WATCHPOINT = 0x34, 68 EC_WATCHPOINT_SAME_EL = 0x35, 69 EC_AA32_BKPT = 0x38, 70 EC_VECTORCATCH = 0x3a, 71 EC_AA64_BKPT = 0x3c, 72 }; 73 74 typedef enum { 75 SME_ET_AccessTrap, 76 SME_ET_Streaming, 77 SME_ET_NotStreaming, 78 SME_ET_InactiveZA, 79 } SMEExceptionType; 80 81 #define ARM_EL_EC_SHIFT 26 82 #define ARM_EL_IL_SHIFT 25 83 #define ARM_EL_ISV_SHIFT 24 84 #define ARM_EL_IL (1 << ARM_EL_IL_SHIFT) 85 #define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT) 86 87 static inline uint32_t syn_get_ec(uint32_t syn) 88 { 89 return syn >> ARM_EL_EC_SHIFT; 90 } 91 92 /* 93 * Utility functions for constructing various kinds of syndrome value. 94 * Note that in general we follow the AArch64 syndrome values; in a 95 * few cases the value in HSR for exceptions taken to AArch32 Hyp 96 * mode differs slightly, and we fix this up when populating HSR in 97 * arm_cpu_do_interrupt_aarch32_hyp(). 98 * The exception is FP/SIMD access traps -- these report extra information 99 * when taking an exception to AArch32. For those we include the extra coproc 100 * and TA fields, and mask them out when taking the exception to AArch64. 101 */ 102 static inline uint32_t syn_uncategorized(void) 103 { 104 return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL; 105 } 106 107 static inline uint32_t syn_aa64_svc(uint32_t imm16) 108 { 109 return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 110 } 111 112 static inline uint32_t syn_aa64_hvc(uint32_t imm16) 113 { 114 return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 115 } 116 117 static inline uint32_t syn_aa64_smc(uint32_t imm16) 118 { 119 return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 120 } 121 122 static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit) 123 { 124 return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) 125 | (is_16bit ? 0 : ARM_EL_IL); 126 } 127 128 static inline uint32_t syn_aa32_hvc(uint32_t imm16) 129 { 130 return (EC_AA32_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 131 } 132 133 static inline uint32_t syn_aa32_smc(void) 134 { 135 return (EC_AA32_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL; 136 } 137 138 static inline uint32_t syn_aa64_bkpt(uint32_t imm16) 139 { 140 return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 141 } 142 143 static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit) 144 { 145 return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) 146 | (is_16bit ? 0 : ARM_EL_IL); 147 } 148 149 static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2, 150 int crn, int crm, int rt, 151 int isread) 152 { 153 return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL 154 | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5) 155 | (crm << 1) | isread; 156 } 157 158 static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2, 159 int crn, int crm, int rt, int isread, 160 bool is_16bit) 161 { 162 return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT) 163 | (is_16bit ? 0 : ARM_EL_IL) 164 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) 165 | (crn << 10) | (rt << 5) | (crm << 1) | isread; 166 } 167 168 static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2, 169 int crn, int crm, int rt, int isread, 170 bool is_16bit) 171 { 172 return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT) 173 | (is_16bit ? 0 : ARM_EL_IL) 174 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) 175 | (crn << 10) | (rt << 5) | (crm << 1) | isread; 176 } 177 178 static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm, 179 int rt, int rt2, int isread, 180 bool is_16bit) 181 { 182 return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT) 183 | (is_16bit ? 0 : ARM_EL_IL) 184 | (cv << 24) | (cond << 20) | (opc1 << 16) 185 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; 186 } 187 188 static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm, 189 int rt, int rt2, int isread, 190 bool is_16bit) 191 { 192 return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT) 193 | (is_16bit ? 0 : ARM_EL_IL) 194 | (cv << 24) | (cond << 20) | (opc1 << 16) 195 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; 196 } 197 198 static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit, 199 int coproc) 200 { 201 /* AArch32 FP trap or any AArch64 FP/SIMD trap: TA == 0 */ 202 return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) 203 | (is_16bit ? 0 : ARM_EL_IL) 204 | (cv << 24) | (cond << 20) | coproc; 205 } 206 207 static inline uint32_t syn_simd_access_trap(int cv, int cond, bool is_16bit) 208 { 209 /* AArch32 SIMD trap: TA == 1 coproc == 0 */ 210 return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) 211 | (is_16bit ? 0 : ARM_EL_IL) 212 | (cv << 24) | (cond << 20) | (1 << 5); 213 } 214 215 static inline uint32_t syn_sve_access_trap(void) 216 { 217 return EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT; 218 } 219 220 /* 221 * eret_op is bits [1:0] of the ERET instruction, so: 222 * 0 for ERET, 2 for ERETAA, 3 for ERETAB. 223 */ 224 static inline uint32_t syn_erettrap(int eret_op) 225 { 226 return (EC_ERETTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL | eret_op; 227 } 228 229 static inline uint32_t syn_smetrap(SMEExceptionType etype, bool is_16bit) 230 { 231 return (EC_SMETRAP << ARM_EL_EC_SHIFT) 232 | (is_16bit ? 0 : ARM_EL_IL) | etype; 233 } 234 235 static inline uint32_t syn_pactrap(void) 236 { 237 return EC_PACTRAP << ARM_EL_EC_SHIFT; 238 } 239 240 static inline uint32_t syn_btitrap(int btype) 241 { 242 return (EC_BTITRAP << ARM_EL_EC_SHIFT) | btype; 243 } 244 245 static inline uint32_t syn_bxjtrap(int cv, int cond, int rm) 246 { 247 return (EC_BXJTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL | 248 (cv << 24) | (cond << 20) | rm; 249 } 250 251 static inline uint32_t syn_gpc(int s2ptw, int ind, int gpcsc, 252 int cm, int s1ptw, int wnr, int fsc) 253 { 254 /* TODO: FEAT_NV2 adds VNCR */ 255 return (EC_GPC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (s2ptw << 21) 256 | (ind << 20) | (gpcsc << 14) | (cm << 8) | (s1ptw << 7) 257 | (wnr << 6) | fsc; 258 } 259 260 static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc) 261 { 262 return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 263 | ARM_EL_IL | (ea << 9) | (s1ptw << 7) | fsc; 264 } 265 266 static inline uint32_t syn_data_abort_no_iss(int same_el, int fnv, 267 int ea, int cm, int s1ptw, 268 int wnr, int fsc) 269 { 270 return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 271 | ARM_EL_IL 272 | (fnv << 10) | (ea << 9) | (cm << 8) | (s1ptw << 7) 273 | (wnr << 6) | fsc; 274 } 275 276 static inline uint32_t syn_data_abort_with_iss(int same_el, 277 int sas, int sse, int srt, 278 int sf, int ar, 279 int ea, int cm, int s1ptw, 280 int wnr, int fsc, 281 bool is_16bit) 282 { 283 return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 284 | (is_16bit ? 0 : ARM_EL_IL) 285 | ARM_EL_ISV | (sas << 22) | (sse << 21) | (srt << 16) 286 | (sf << 15) | (ar << 14) 287 | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc; 288 } 289 290 static inline uint32_t syn_swstep(int same_el, int isv, int ex) 291 { 292 return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 293 | ARM_EL_IL | (isv << 24) | (ex << 6) | 0x22; 294 } 295 296 static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr) 297 { 298 return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 299 | ARM_EL_IL | (cm << 8) | (wnr << 6) | 0x22; 300 } 301 302 static inline uint32_t syn_breakpoint(int same_el) 303 { 304 return (EC_BREAKPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 305 | ARM_EL_IL | 0x22; 306 } 307 308 static inline uint32_t syn_wfx(int cv, int cond, int ti, bool is_16bit) 309 { 310 return (EC_WFX_TRAP << ARM_EL_EC_SHIFT) | 311 (is_16bit ? 0 : (1 << ARM_EL_IL_SHIFT)) | 312 (cv << 24) | (cond << 20) | ti; 313 } 314 315 static inline uint32_t syn_illegalstate(void) 316 { 317 return (EC_ILLEGALSTATE << ARM_EL_EC_SHIFT) | ARM_EL_IL; 318 } 319 320 static inline uint32_t syn_pcalignment(void) 321 { 322 return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL; 323 } 324 325 static inline uint32_t syn_serror(uint32_t extra) 326 { 327 return (EC_SERROR << ARM_EL_EC_SHIFT) | ARM_EL_IL | extra; 328 } 329 330 #endif /* TARGET_ARM_SYNDROME_H */ 331