1 /* 2 * QEMU ARM CPU -- syndrome functions and types 3 * 4 * Copyright (c) 2014 Linaro Ltd 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 * 20 * This header defines functions, types, etc which need to be shared 21 * between different source files within target/arm/ but which are 22 * private to it and not required by the rest of QEMU. 23 */ 24 25 #ifndef TARGET_ARM_SYNDROME_H 26 #define TARGET_ARM_SYNDROME_H 27 28 /* Valid Syndrome Register EC field values */ 29 enum arm_exception_class { 30 EC_UNCATEGORIZED = 0x00, 31 EC_WFX_TRAP = 0x01, 32 EC_CP15RTTRAP = 0x03, 33 EC_CP15RRTTRAP = 0x04, 34 EC_CP14RTTRAP = 0x05, 35 EC_CP14DTTRAP = 0x06, 36 EC_ADVSIMDFPACCESSTRAP = 0x07, 37 EC_FPIDTRAP = 0x08, 38 EC_PACTRAP = 0x09, 39 EC_BXJTRAP = 0x0a, 40 EC_CP14RRTTRAP = 0x0c, 41 EC_BTITRAP = 0x0d, 42 EC_ILLEGALSTATE = 0x0e, 43 EC_AA32_SVC = 0x11, 44 EC_AA32_HVC = 0x12, 45 EC_AA32_SMC = 0x13, 46 EC_AA64_SVC = 0x15, 47 EC_AA64_HVC = 0x16, 48 EC_AA64_SMC = 0x17, 49 EC_SYSTEMREGISTERTRAP = 0x18, 50 EC_SVEACCESSTRAP = 0x19, 51 EC_ERETTRAP = 0x1a, 52 EC_SMETRAP = 0x1d, 53 EC_INSNABORT = 0x20, 54 EC_INSNABORT_SAME_EL = 0x21, 55 EC_PCALIGNMENT = 0x22, 56 EC_DATAABORT = 0x24, 57 EC_DATAABORT_SAME_EL = 0x25, 58 EC_SPALIGNMENT = 0x26, 59 EC_AA32_FPTRAP = 0x28, 60 EC_AA64_FPTRAP = 0x2c, 61 EC_SERROR = 0x2f, 62 EC_BREAKPOINT = 0x30, 63 EC_BREAKPOINT_SAME_EL = 0x31, 64 EC_SOFTWARESTEP = 0x32, 65 EC_SOFTWARESTEP_SAME_EL = 0x33, 66 EC_WATCHPOINT = 0x34, 67 EC_WATCHPOINT_SAME_EL = 0x35, 68 EC_AA32_BKPT = 0x38, 69 EC_VECTORCATCH = 0x3a, 70 EC_AA64_BKPT = 0x3c, 71 }; 72 73 typedef enum { 74 SME_ET_AccessTrap, 75 SME_ET_Streaming, 76 SME_ET_NotStreaming, 77 SME_ET_InactiveZA, 78 } SMEExceptionType; 79 80 #define ARM_EL_EC_SHIFT 26 81 #define ARM_EL_IL_SHIFT 25 82 #define ARM_EL_ISV_SHIFT 24 83 #define ARM_EL_IL (1 << ARM_EL_IL_SHIFT) 84 #define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT) 85 86 static inline uint32_t syn_get_ec(uint32_t syn) 87 { 88 return syn >> ARM_EL_EC_SHIFT; 89 } 90 91 /* 92 * Utility functions for constructing various kinds of syndrome value. 93 * Note that in general we follow the AArch64 syndrome values; in a 94 * few cases the value in HSR for exceptions taken to AArch32 Hyp 95 * mode differs slightly, and we fix this up when populating HSR in 96 * arm_cpu_do_interrupt_aarch32_hyp(). 97 * The exception is FP/SIMD access traps -- these report extra information 98 * when taking an exception to AArch32. For those we include the extra coproc 99 * and TA fields, and mask them out when taking the exception to AArch64. 100 */ 101 static inline uint32_t syn_uncategorized(void) 102 { 103 return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL; 104 } 105 106 static inline uint32_t syn_aa64_svc(uint32_t imm16) 107 { 108 return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 109 } 110 111 static inline uint32_t syn_aa64_hvc(uint32_t imm16) 112 { 113 return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 114 } 115 116 static inline uint32_t syn_aa64_smc(uint32_t imm16) 117 { 118 return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 119 } 120 121 static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit) 122 { 123 return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) 124 | (is_16bit ? 0 : ARM_EL_IL); 125 } 126 127 static inline uint32_t syn_aa32_hvc(uint32_t imm16) 128 { 129 return (EC_AA32_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 130 } 131 132 static inline uint32_t syn_aa32_smc(void) 133 { 134 return (EC_AA32_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL; 135 } 136 137 static inline uint32_t syn_aa64_bkpt(uint32_t imm16) 138 { 139 return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 140 } 141 142 static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit) 143 { 144 return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) 145 | (is_16bit ? 0 : ARM_EL_IL); 146 } 147 148 static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2, 149 int crn, int crm, int rt, 150 int isread) 151 { 152 return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL 153 | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5) 154 | (crm << 1) | isread; 155 } 156 157 static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2, 158 int crn, int crm, int rt, int isread, 159 bool is_16bit) 160 { 161 return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT) 162 | (is_16bit ? 0 : ARM_EL_IL) 163 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) 164 | (crn << 10) | (rt << 5) | (crm << 1) | isread; 165 } 166 167 static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2, 168 int crn, int crm, int rt, int isread, 169 bool is_16bit) 170 { 171 return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT) 172 | (is_16bit ? 0 : ARM_EL_IL) 173 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) 174 | (crn << 10) | (rt << 5) | (crm << 1) | isread; 175 } 176 177 static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm, 178 int rt, int rt2, int isread, 179 bool is_16bit) 180 { 181 return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT) 182 | (is_16bit ? 0 : ARM_EL_IL) 183 | (cv << 24) | (cond << 20) | (opc1 << 16) 184 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; 185 } 186 187 static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm, 188 int rt, int rt2, int isread, 189 bool is_16bit) 190 { 191 return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT) 192 | (is_16bit ? 0 : ARM_EL_IL) 193 | (cv << 24) | (cond << 20) | (opc1 << 16) 194 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; 195 } 196 197 static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit, 198 int coproc) 199 { 200 /* AArch32 FP trap or any AArch64 FP/SIMD trap: TA == 0 */ 201 return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) 202 | (is_16bit ? 0 : ARM_EL_IL) 203 | (cv << 24) | (cond << 20) | coproc; 204 } 205 206 static inline uint32_t syn_simd_access_trap(int cv, int cond, bool is_16bit) 207 { 208 /* AArch32 SIMD trap: TA == 1 coproc == 0 */ 209 return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) 210 | (is_16bit ? 0 : ARM_EL_IL) 211 | (cv << 24) | (cond << 20) | (1 << 5); 212 } 213 214 static inline uint32_t syn_sve_access_trap(void) 215 { 216 return EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT; 217 } 218 219 /* 220 * eret_op is bits [1:0] of the ERET instruction, so: 221 * 0 for ERET, 2 for ERETAA, 3 for ERETAB. 222 */ 223 static inline uint32_t syn_erettrap(int eret_op) 224 { 225 return (EC_ERETTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL | eret_op; 226 } 227 228 static inline uint32_t syn_smetrap(SMEExceptionType etype, bool is_16bit) 229 { 230 return (EC_SMETRAP << ARM_EL_EC_SHIFT) 231 | (is_16bit ? 0 : ARM_EL_IL) | etype; 232 } 233 234 static inline uint32_t syn_pactrap(void) 235 { 236 return EC_PACTRAP << ARM_EL_EC_SHIFT; 237 } 238 239 static inline uint32_t syn_btitrap(int btype) 240 { 241 return (EC_BTITRAP << ARM_EL_EC_SHIFT) | btype; 242 } 243 244 static inline uint32_t syn_bxjtrap(int cv, int cond, int rm) 245 { 246 return (EC_BXJTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL | 247 (cv << 24) | (cond << 20) | rm; 248 } 249 250 static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc) 251 { 252 return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 253 | ARM_EL_IL | (ea << 9) | (s1ptw << 7) | fsc; 254 } 255 256 static inline uint32_t syn_data_abort_no_iss(int same_el, int fnv, 257 int ea, int cm, int s1ptw, 258 int wnr, int fsc) 259 { 260 return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 261 | ARM_EL_IL 262 | (fnv << 10) | (ea << 9) | (cm << 8) | (s1ptw << 7) 263 | (wnr << 6) | fsc; 264 } 265 266 static inline uint32_t syn_data_abort_with_iss(int same_el, 267 int sas, int sse, int srt, 268 int sf, int ar, 269 int ea, int cm, int s1ptw, 270 int wnr, int fsc, 271 bool is_16bit) 272 { 273 return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 274 | (is_16bit ? 0 : ARM_EL_IL) 275 | ARM_EL_ISV | (sas << 22) | (sse << 21) | (srt << 16) 276 | (sf << 15) | (ar << 14) 277 | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc; 278 } 279 280 static inline uint32_t syn_swstep(int same_el, int isv, int ex) 281 { 282 return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 283 | ARM_EL_IL | (isv << 24) | (ex << 6) | 0x22; 284 } 285 286 static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr) 287 { 288 return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 289 | ARM_EL_IL | (cm << 8) | (wnr << 6) | 0x22; 290 } 291 292 static inline uint32_t syn_breakpoint(int same_el) 293 { 294 return (EC_BREAKPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 295 | ARM_EL_IL | 0x22; 296 } 297 298 static inline uint32_t syn_wfx(int cv, int cond, int ti, bool is_16bit) 299 { 300 return (EC_WFX_TRAP << ARM_EL_EC_SHIFT) | 301 (is_16bit ? 0 : (1 << ARM_EL_IL_SHIFT)) | 302 (cv << 24) | (cond << 20) | ti; 303 } 304 305 static inline uint32_t syn_illegalstate(void) 306 { 307 return (EC_ILLEGALSTATE << ARM_EL_EC_SHIFT) | ARM_EL_IL; 308 } 309 310 static inline uint32_t syn_pcalignment(void) 311 { 312 return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL; 313 } 314 315 static inline uint32_t syn_serror(uint32_t extra) 316 { 317 return (EC_SERROR << ARM_EL_EC_SHIFT) | ARM_EL_IL | extra; 318 } 319 320 #endif /* TARGET_ARM_SYNDROME_H */ 321