1 /* 2 * QEMU ARM CPU -- syndrome functions and types 3 * 4 * Copyright (c) 2014 Linaro Ltd 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 * 20 * This header defines functions, types, etc which need to be shared 21 * between different source files within target/arm/ but which are 22 * private to it and not required by the rest of QEMU. 23 */ 24 25 #ifndef TARGET_ARM_SYNDROME_H 26 #define TARGET_ARM_SYNDROME_H 27 28 #include "qemu/bitops.h" 29 30 /* Valid Syndrome Register EC field values */ 31 enum arm_exception_class { 32 EC_UNCATEGORIZED = 0x00, 33 EC_WFX_TRAP = 0x01, 34 EC_CP15RTTRAP = 0x03, 35 EC_CP15RRTTRAP = 0x04, 36 EC_CP14RTTRAP = 0x05, 37 EC_CP14DTTRAP = 0x06, 38 EC_ADVSIMDFPACCESSTRAP = 0x07, 39 EC_FPIDTRAP = 0x08, 40 EC_PACTRAP = 0x09, 41 EC_BXJTRAP = 0x0a, 42 EC_CP14RRTTRAP = 0x0c, 43 EC_BTITRAP = 0x0d, 44 EC_ILLEGALSTATE = 0x0e, 45 EC_AA32_SVC = 0x11, 46 EC_AA32_HVC = 0x12, 47 EC_AA32_SMC = 0x13, 48 EC_AA64_SVC = 0x15, 49 EC_AA64_HVC = 0x16, 50 EC_AA64_SMC = 0x17, 51 EC_SYSTEMREGISTERTRAP = 0x18, 52 EC_SVEACCESSTRAP = 0x19, 53 EC_ERETTRAP = 0x1a, 54 EC_PACFAIL = 0x1c, 55 EC_SMETRAP = 0x1d, 56 EC_GPC = 0x1e, 57 EC_INSNABORT = 0x20, 58 EC_INSNABORT_SAME_EL = 0x21, 59 EC_PCALIGNMENT = 0x22, 60 EC_DATAABORT = 0x24, 61 EC_DATAABORT_SAME_EL = 0x25, 62 EC_SPALIGNMENT = 0x26, 63 EC_MOP = 0x27, 64 EC_AA32_FPTRAP = 0x28, 65 EC_AA64_FPTRAP = 0x2c, 66 EC_SERROR = 0x2f, 67 EC_BREAKPOINT = 0x30, 68 EC_BREAKPOINT_SAME_EL = 0x31, 69 EC_SOFTWARESTEP = 0x32, 70 EC_SOFTWARESTEP_SAME_EL = 0x33, 71 EC_WATCHPOINT = 0x34, 72 EC_WATCHPOINT_SAME_EL = 0x35, 73 EC_AA32_BKPT = 0x38, 74 EC_VECTORCATCH = 0x3a, 75 EC_AA64_BKPT = 0x3c, 76 }; 77 78 typedef enum { 79 SME_ET_AccessTrap, 80 SME_ET_Streaming, 81 SME_ET_NotStreaming, 82 SME_ET_InactiveZA, 83 SME_ET_InaccessibleZT0, 84 } SMEExceptionType; 85 86 #define ARM_EL_EC_LENGTH 6 87 #define ARM_EL_EC_SHIFT 26 88 #define ARM_EL_IL_SHIFT 25 89 #define ARM_EL_ISV_SHIFT 24 90 #define ARM_EL_IL (1 << ARM_EL_IL_SHIFT) 91 #define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT) 92 93 /* In the Data Abort syndrome */ 94 #define ARM_EL_VNCR (1 << 13) 95 96 static inline uint32_t syn_get_ec(uint32_t syn) 97 { 98 return syn >> ARM_EL_EC_SHIFT; 99 } 100 101 static inline uint32_t syn_set_ec(uint32_t syn, uint32_t ec) 102 { 103 return deposit32(syn, ARM_EL_EC_SHIFT, ARM_EL_EC_LENGTH, ec); 104 } 105 106 /* 107 * Utility functions for constructing various kinds of syndrome value. 108 * Note that in general we follow the AArch64 syndrome values; in a 109 * few cases the value in HSR for exceptions taken to AArch32 Hyp 110 * mode differs slightly, and we fix this up when populating HSR in 111 * arm_cpu_do_interrupt_aarch32_hyp(). 112 * The exception is FP/SIMD access traps -- these report extra information 113 * when taking an exception to AArch32. For those we include the extra coproc 114 * and TA fields, and mask them out when taking the exception to AArch64. 115 */ 116 static inline uint32_t syn_uncategorized(void) 117 { 118 return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL; 119 } 120 121 static inline uint32_t syn_aa64_svc(uint32_t imm16) 122 { 123 return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 124 } 125 126 static inline uint32_t syn_aa64_hvc(uint32_t imm16) 127 { 128 return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 129 } 130 131 static inline uint32_t syn_aa64_smc(uint32_t imm16) 132 { 133 return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 134 } 135 136 static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit) 137 { 138 return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) 139 | (is_16bit ? 0 : ARM_EL_IL); 140 } 141 142 static inline uint32_t syn_aa32_hvc(uint32_t imm16) 143 { 144 return (EC_AA32_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 145 } 146 147 static inline uint32_t syn_aa32_smc(void) 148 { 149 return (EC_AA32_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL; 150 } 151 152 static inline uint32_t syn_aa64_bkpt(uint32_t imm16) 153 { 154 return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 155 } 156 157 static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit) 158 { 159 return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) 160 | (is_16bit ? 0 : ARM_EL_IL); 161 } 162 163 static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2, 164 int crn, int crm, int rt, 165 int isread) 166 { 167 return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL 168 | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5) 169 | (crm << 1) | isread; 170 } 171 172 static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2, 173 int crn, int crm, int rt, int isread, 174 bool is_16bit) 175 { 176 return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT) 177 | (is_16bit ? 0 : ARM_EL_IL) 178 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) 179 | (crn << 10) | (rt << 5) | (crm << 1) | isread; 180 } 181 182 static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2, 183 int crn, int crm, int rt, int isread, 184 bool is_16bit) 185 { 186 return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT) 187 | (is_16bit ? 0 : ARM_EL_IL) 188 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) 189 | (crn << 10) | (rt << 5) | (crm << 1) | isread; 190 } 191 192 static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm, 193 int rt, int rt2, int isread, 194 bool is_16bit) 195 { 196 return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT) 197 | (is_16bit ? 0 : ARM_EL_IL) 198 | (cv << 24) | (cond << 20) | (opc1 << 16) 199 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; 200 } 201 202 static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm, 203 int rt, int rt2, int isread, 204 bool is_16bit) 205 { 206 return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT) 207 | (is_16bit ? 0 : ARM_EL_IL) 208 | (cv << 24) | (cond << 20) | (opc1 << 16) 209 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; 210 } 211 212 static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit, 213 int coproc) 214 { 215 /* AArch32 FP trap or any AArch64 FP/SIMD trap: TA == 0 */ 216 return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) 217 | (is_16bit ? 0 : ARM_EL_IL) 218 | (cv << 24) | (cond << 20) | coproc; 219 } 220 221 static inline uint32_t syn_simd_access_trap(int cv, int cond, bool is_16bit) 222 { 223 /* AArch32 SIMD trap: TA == 1 coproc == 0 */ 224 return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) 225 | (is_16bit ? 0 : ARM_EL_IL) 226 | (cv << 24) | (cond << 20) | (1 << 5); 227 } 228 229 static inline uint32_t syn_sve_access_trap(void) 230 { 231 return (EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL; 232 } 233 234 /* 235 * eret_op is bits [1:0] of the ERET instruction, so: 236 * 0 for ERET, 2 for ERETAA, 3 for ERETAB. 237 */ 238 static inline uint32_t syn_erettrap(int eret_op) 239 { 240 return (EC_ERETTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL | eret_op; 241 } 242 243 static inline uint32_t syn_smetrap(SMEExceptionType etype, bool is_16bit) 244 { 245 return (EC_SMETRAP << ARM_EL_EC_SHIFT) 246 | (is_16bit ? 0 : ARM_EL_IL) | etype; 247 } 248 249 static inline uint32_t syn_pacfail(bool data, int keynumber) 250 { 251 int error_code = (data << 1) | keynumber; 252 return (EC_PACFAIL << ARM_EL_EC_SHIFT) | ARM_EL_IL | error_code; 253 } 254 255 static inline uint32_t syn_pactrap(void) 256 { 257 return (EC_PACTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL; 258 } 259 260 static inline uint32_t syn_btitrap(int btype) 261 { 262 return (EC_BTITRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL | btype; 263 } 264 265 static inline uint32_t syn_bxjtrap(int cv, int cond, int rm) 266 { 267 return (EC_BXJTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL | 268 (cv << 24) | (cond << 20) | rm; 269 } 270 271 static inline uint32_t syn_gpc(int s2ptw, int ind, int gpcsc, int vncr, 272 int cm, int s1ptw, int wnr, int fsc) 273 { 274 return (EC_GPC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (s2ptw << 21) 275 | (ind << 20) | (gpcsc << 14) | (vncr << 13) | (cm << 8) 276 | (s1ptw << 7) | (wnr << 6) | fsc; 277 } 278 279 static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc) 280 { 281 return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 282 | ARM_EL_IL | (ea << 9) | (s1ptw << 7) | fsc; 283 } 284 285 static inline uint32_t syn_data_abort_no_iss(int same_el, int fnv, 286 int ea, int cm, int s1ptw, 287 int wnr, int fsc) 288 { 289 return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 290 | ARM_EL_IL 291 | (fnv << 10) | (ea << 9) | (cm << 8) | (s1ptw << 7) 292 | (wnr << 6) | fsc; 293 } 294 295 static inline uint32_t syn_data_abort_with_iss(int same_el, 296 int sas, int sse, int srt, 297 int sf, int ar, 298 int ea, int cm, int s1ptw, 299 int wnr, int fsc, 300 bool is_16bit) 301 { 302 return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 303 | (is_16bit ? 0 : ARM_EL_IL) 304 | ARM_EL_ISV | (sas << 22) | (sse << 21) | (srt << 16) 305 | (sf << 15) | (ar << 14) 306 | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc; 307 } 308 309 /* 310 * Faults due to FEAT_NV2 VNCR_EL2-based accesses report as same-EL 311 * Data Aborts with the VNCR bit set. 312 */ 313 static inline uint32_t syn_data_abort_vncr(int ea, int wnr, int fsc) 314 { 315 return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (1 << ARM_EL_EC_SHIFT) 316 | ARM_EL_IL | ARM_EL_VNCR | (wnr << 6) | fsc; 317 } 318 319 static inline uint32_t syn_swstep(int same_el, int isv, int ex) 320 { 321 return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 322 | ARM_EL_IL | (isv << 24) | (ex << 6) | 0x22; 323 } 324 325 static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr) 326 { 327 return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 328 | ARM_EL_IL | (cm << 8) | (wnr << 6) | 0x22; 329 } 330 331 static inline uint32_t syn_breakpoint(int same_el) 332 { 333 return (EC_BREAKPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 334 | ARM_EL_IL | 0x22; 335 } 336 337 static inline uint32_t syn_wfx(int cv, int cond, int ti, bool is_16bit) 338 { 339 return (EC_WFX_TRAP << ARM_EL_EC_SHIFT) | 340 (is_16bit ? 0 : (1 << ARM_EL_IL_SHIFT)) | 341 (cv << 24) | (cond << 20) | ti; 342 } 343 344 static inline uint32_t syn_illegalstate(void) 345 { 346 return (EC_ILLEGALSTATE << ARM_EL_EC_SHIFT) | ARM_EL_IL; 347 } 348 349 static inline uint32_t syn_pcalignment(void) 350 { 351 return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL; 352 } 353 354 static inline uint32_t syn_serror(uint32_t extra) 355 { 356 return (EC_SERROR << ARM_EL_EC_SHIFT) | ARM_EL_IL | extra; 357 } 358 359 static inline uint32_t syn_mop(bool is_set, bool is_setg, int options, 360 bool epilogue, bool wrong_option, bool option_a, 361 int destreg, int srcreg, int sizereg) 362 { 363 return (EC_MOP << ARM_EL_EC_SHIFT) | ARM_EL_IL | 364 (is_set << 24) | (is_setg << 23) | (options << 19) | 365 (epilogue << 18) | (wrong_option << 17) | (option_a << 16) | 366 (destreg << 10) | (srcreg << 5) | sizereg; 367 } 368 369 370 #endif /* TARGET_ARM_SYNDROME_H */ 371