xref: /openbmc/qemu/target/arm/meson.build (revision b7bc6b18)
1gen = [
2  decodetree.process('sve.decode', extra_args: '--decode=disas_sve'),
3  decodetree.process('neon-shared.decode', extra_args: '--decode=disas_neon_shared'),
4  decodetree.process('neon-dp.decode', extra_args: '--decode=disas_neon_dp'),
5  decodetree.process('neon-ls.decode', extra_args: '--decode=disas_neon_ls'),
6  decodetree.process('vfp.decode', extra_args: '--decode=disas_vfp'),
7  decodetree.process('vfp-uncond.decode', extra_args: '--decode=disas_vfp_uncond'),
8  decodetree.process('m-nocp.decode', extra_args: '--decode=disas_m_nocp'),
9  decodetree.process('mve.decode', extra_args: '--decode=disas_mve'),
10  decodetree.process('a32.decode', extra_args: '--static-decode=disas_a32'),
11  decodetree.process('a32-uncond.decode', extra_args: '--static-decode=disas_a32_uncond'),
12  decodetree.process('t32.decode', extra_args: '--static-decode=disas_t32'),
13  decodetree.process('t16.decode', extra_args: ['-w', '16', '--static-decode=disas_t16']),
14]
15
16arm_ss = ss.source_set()
17arm_ss.add(gen)
18arm_ss.add(files(
19  'cpu.c',
20  'crypto_helper.c',
21  'debug_helper.c',
22  'gdbstub.c',
23  'helper.c',
24  'iwmmxt_helper.c',
25  'm_helper.c',
26  'mve_helper.c',
27  'neon_helper.c',
28  'op_helper.c',
29  'tlb_helper.c',
30  'translate.c',
31  'translate-m-nocp.c',
32  'translate-mve.c',
33  'translate-neon.c',
34  'translate-vfp.c',
35  'vec_helper.c',
36  'vfp_helper.c',
37  'cpu_tcg.c',
38))
39arm_ss.add(zlib)
40
41arm_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c', 'kvm64.c'), if_false: files('kvm-stub.c'))
42
43arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
44  'cpu64.c',
45  'gdbstub64.c',
46  'helper-a64.c',
47  'mte_helper.c',
48  'pauth_helper.c',
49  'sve_helper.c',
50  'translate-a64.c',
51  'translate-sve.c',
52))
53
54arm_softmmu_ss = ss.source_set()
55arm_softmmu_ss.add(files(
56  'arch_dump.c',
57  'arm-powerctl.c',
58  'machine.c',
59  'monitor.c',
60  'psci.c',
61))
62
63subdir('hvf')
64
65target_arch += {'arm': arm_ss}
66target_softmmu_arch += {'arm': arm_softmmu_ss}
67