1 #include "qemu/osdep.h" 2 #include "qemu-common.h" 3 #include "cpu.h" 4 #include "hw/hw.h" 5 #include "hw/boards.h" 6 #include "qemu/error-report.h" 7 #include "sysemu/kvm.h" 8 #include "kvm_arm.h" 9 #include "internals.h" 10 #include "migration/cpu.h" 11 12 static bool vfp_needed(void *opaque) 13 { 14 ARMCPU *cpu = opaque; 15 CPUARMState *env = &cpu->env; 16 17 return arm_feature(env, ARM_FEATURE_VFP); 18 } 19 20 static int get_fpscr(QEMUFile *f, void *opaque, size_t size, 21 VMStateField *field) 22 { 23 ARMCPU *cpu = opaque; 24 CPUARMState *env = &cpu->env; 25 uint32_t val = qemu_get_be32(f); 26 27 vfp_set_fpscr(env, val); 28 return 0; 29 } 30 31 static int put_fpscr(QEMUFile *f, void *opaque, size_t size, 32 VMStateField *field, QJSON *vmdesc) 33 { 34 ARMCPU *cpu = opaque; 35 CPUARMState *env = &cpu->env; 36 37 qemu_put_be32(f, vfp_get_fpscr(env)); 38 return 0; 39 } 40 41 static const VMStateInfo vmstate_fpscr = { 42 .name = "fpscr", 43 .get = get_fpscr, 44 .put = put_fpscr, 45 }; 46 47 static const VMStateDescription vmstate_vfp = { 48 .name = "cpu/vfp", 49 .version_id = 3, 50 .minimum_version_id = 3, 51 .needed = vfp_needed, 52 .fields = (VMStateField[]) { 53 VMSTATE_FLOAT64_ARRAY(env.vfp.regs, ARMCPU, 64), 54 /* The xregs array is a little awkward because element 1 (FPSCR) 55 * requires a specific accessor, so we have to split it up in 56 * the vmstate: 57 */ 58 VMSTATE_UINT32(env.vfp.xregs[0], ARMCPU), 59 VMSTATE_UINT32_SUB_ARRAY(env.vfp.xregs, ARMCPU, 2, 14), 60 { 61 .name = "fpscr", 62 .version_id = 0, 63 .size = sizeof(uint32_t), 64 .info = &vmstate_fpscr, 65 .flags = VMS_SINGLE, 66 .offset = 0, 67 }, 68 VMSTATE_END_OF_LIST() 69 } 70 }; 71 72 static bool iwmmxt_needed(void *opaque) 73 { 74 ARMCPU *cpu = opaque; 75 CPUARMState *env = &cpu->env; 76 77 return arm_feature(env, ARM_FEATURE_IWMMXT); 78 } 79 80 static const VMStateDescription vmstate_iwmmxt = { 81 .name = "cpu/iwmmxt", 82 .version_id = 1, 83 .minimum_version_id = 1, 84 .needed = iwmmxt_needed, 85 .fields = (VMStateField[]) { 86 VMSTATE_UINT64_ARRAY(env.iwmmxt.regs, ARMCPU, 16), 87 VMSTATE_UINT32_ARRAY(env.iwmmxt.cregs, ARMCPU, 16), 88 VMSTATE_END_OF_LIST() 89 } 90 }; 91 92 static bool m_needed(void *opaque) 93 { 94 ARMCPU *cpu = opaque; 95 CPUARMState *env = &cpu->env; 96 97 return arm_feature(env, ARM_FEATURE_M); 98 } 99 100 static const VMStateDescription vmstate_m = { 101 .name = "cpu/m", 102 .version_id = 1, 103 .minimum_version_id = 1, 104 .needed = m_needed, 105 .fields = (VMStateField[]) { 106 VMSTATE_UINT32(env.v7m.other_sp, ARMCPU), 107 VMSTATE_UINT32(env.v7m.vecbase, ARMCPU), 108 VMSTATE_UINT32(env.v7m.basepri, ARMCPU), 109 VMSTATE_UINT32(env.v7m.control, ARMCPU), 110 VMSTATE_INT32(env.v7m.current_sp, ARMCPU), 111 VMSTATE_INT32(env.v7m.exception, ARMCPU), 112 VMSTATE_END_OF_LIST() 113 } 114 }; 115 116 static bool thumb2ee_needed(void *opaque) 117 { 118 ARMCPU *cpu = opaque; 119 CPUARMState *env = &cpu->env; 120 121 return arm_feature(env, ARM_FEATURE_THUMB2EE); 122 } 123 124 static const VMStateDescription vmstate_thumb2ee = { 125 .name = "cpu/thumb2ee", 126 .version_id = 1, 127 .minimum_version_id = 1, 128 .needed = thumb2ee_needed, 129 .fields = (VMStateField[]) { 130 VMSTATE_UINT32(env.teecr, ARMCPU), 131 VMSTATE_UINT32(env.teehbr, ARMCPU), 132 VMSTATE_END_OF_LIST() 133 } 134 }; 135 136 static bool pmsav7_needed(void *opaque) 137 { 138 ARMCPU *cpu = opaque; 139 CPUARMState *env = &cpu->env; 140 141 return arm_feature(env, ARM_FEATURE_MPU) && 142 arm_feature(env, ARM_FEATURE_V7); 143 } 144 145 static bool pmsav7_rgnr_vmstate_validate(void *opaque, int version_id) 146 { 147 ARMCPU *cpu = opaque; 148 149 return cpu->env.cp15.c6_rgnr < cpu->pmsav7_dregion; 150 } 151 152 static const VMStateDescription vmstate_pmsav7 = { 153 .name = "cpu/pmsav7", 154 .version_id = 1, 155 .minimum_version_id = 1, 156 .needed = pmsav7_needed, 157 .fields = (VMStateField[]) { 158 VMSTATE_VARRAY_UINT32(env.pmsav7.drbar, ARMCPU, pmsav7_dregion, 0, 159 vmstate_info_uint32, uint32_t), 160 VMSTATE_VARRAY_UINT32(env.pmsav7.drsr, ARMCPU, pmsav7_dregion, 0, 161 vmstate_info_uint32, uint32_t), 162 VMSTATE_VARRAY_UINT32(env.pmsav7.dracr, ARMCPU, pmsav7_dregion, 0, 163 vmstate_info_uint32, uint32_t), 164 VMSTATE_VALIDATE("rgnr is valid", pmsav7_rgnr_vmstate_validate), 165 VMSTATE_END_OF_LIST() 166 } 167 }; 168 169 static int get_cpsr(QEMUFile *f, void *opaque, size_t size, 170 VMStateField *field) 171 { 172 ARMCPU *cpu = opaque; 173 CPUARMState *env = &cpu->env; 174 uint32_t val = qemu_get_be32(f); 175 176 env->aarch64 = ((val & PSTATE_nRW) == 0); 177 178 if (is_a64(env)) { 179 pstate_write(env, val); 180 return 0; 181 } 182 183 cpsr_write(env, val, 0xffffffff, CPSRWriteRaw); 184 return 0; 185 } 186 187 static int put_cpsr(QEMUFile *f, void *opaque, size_t size, 188 VMStateField *field, QJSON *vmdesc) 189 { 190 ARMCPU *cpu = opaque; 191 CPUARMState *env = &cpu->env; 192 uint32_t val; 193 194 if (is_a64(env)) { 195 val = pstate_read(env); 196 } else { 197 val = cpsr_read(env); 198 } 199 200 qemu_put_be32(f, val); 201 return 0; 202 } 203 204 static const VMStateInfo vmstate_cpsr = { 205 .name = "cpsr", 206 .get = get_cpsr, 207 .put = put_cpsr, 208 }; 209 210 static void cpu_pre_save(void *opaque) 211 { 212 ARMCPU *cpu = opaque; 213 214 if (kvm_enabled()) { 215 if (!write_kvmstate_to_list(cpu)) { 216 /* This should never fail */ 217 abort(); 218 } 219 } else { 220 if (!write_cpustate_to_list(cpu)) { 221 /* This should never fail. */ 222 abort(); 223 } 224 } 225 226 cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len; 227 memcpy(cpu->cpreg_vmstate_indexes, cpu->cpreg_indexes, 228 cpu->cpreg_array_len * sizeof(uint64_t)); 229 memcpy(cpu->cpreg_vmstate_values, cpu->cpreg_values, 230 cpu->cpreg_array_len * sizeof(uint64_t)); 231 } 232 233 static int cpu_post_load(void *opaque, int version_id) 234 { 235 ARMCPU *cpu = opaque; 236 int i, v; 237 238 /* Update the values list from the incoming migration data. 239 * Anything in the incoming data which we don't know about is 240 * a migration failure; anything we know about but the incoming 241 * data doesn't specify retains its current (reset) value. 242 * The indexes list remains untouched -- we only inspect the 243 * incoming migration index list so we can match the values array 244 * entries with the right slots in our own values array. 245 */ 246 247 for (i = 0, v = 0; i < cpu->cpreg_array_len 248 && v < cpu->cpreg_vmstate_array_len; i++) { 249 if (cpu->cpreg_vmstate_indexes[v] > cpu->cpreg_indexes[i]) { 250 /* register in our list but not incoming : skip it */ 251 continue; 252 } 253 if (cpu->cpreg_vmstate_indexes[v] < cpu->cpreg_indexes[i]) { 254 /* register in their list but not ours: fail migration */ 255 return -1; 256 } 257 /* matching register, copy the value over */ 258 cpu->cpreg_values[i] = cpu->cpreg_vmstate_values[v]; 259 v++; 260 } 261 262 if (kvm_enabled()) { 263 if (!write_list_to_kvmstate(cpu, KVM_PUT_FULL_STATE)) { 264 return -1; 265 } 266 /* Note that it's OK for the TCG side not to know about 267 * every register in the list; KVM is authoritative if 268 * we're using it. 269 */ 270 write_list_to_cpustate(cpu); 271 } else { 272 if (!write_list_to_cpustate(cpu)) { 273 return -1; 274 } 275 } 276 277 hw_breakpoint_update_all(cpu); 278 hw_watchpoint_update_all(cpu); 279 280 return 0; 281 } 282 283 const VMStateDescription vmstate_arm_cpu = { 284 .name = "cpu", 285 .version_id = 22, 286 .minimum_version_id = 22, 287 .pre_save = cpu_pre_save, 288 .post_load = cpu_post_load, 289 .fields = (VMStateField[]) { 290 VMSTATE_UINT32_ARRAY(env.regs, ARMCPU, 16), 291 VMSTATE_UINT64_ARRAY(env.xregs, ARMCPU, 32), 292 VMSTATE_UINT64(env.pc, ARMCPU), 293 { 294 .name = "cpsr", 295 .version_id = 0, 296 .size = sizeof(uint32_t), 297 .info = &vmstate_cpsr, 298 .flags = VMS_SINGLE, 299 .offset = 0, 300 }, 301 VMSTATE_UINT32(env.spsr, ARMCPU), 302 VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 8), 303 VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 8), 304 VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 8), 305 VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5), 306 VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5), 307 VMSTATE_UINT64_ARRAY(env.elr_el, ARMCPU, 4), 308 VMSTATE_UINT64_ARRAY(env.sp_el, ARMCPU, 4), 309 /* The length-check must come before the arrays to avoid 310 * incoming data possibly overflowing the array. 311 */ 312 VMSTATE_INT32_POSITIVE_LE(cpreg_vmstate_array_len, ARMCPU), 313 VMSTATE_VARRAY_INT32(cpreg_vmstate_indexes, ARMCPU, 314 cpreg_vmstate_array_len, 315 0, vmstate_info_uint64, uint64_t), 316 VMSTATE_VARRAY_INT32(cpreg_vmstate_values, ARMCPU, 317 cpreg_vmstate_array_len, 318 0, vmstate_info_uint64, uint64_t), 319 VMSTATE_UINT64(env.exclusive_addr, ARMCPU), 320 VMSTATE_UINT64(env.exclusive_val, ARMCPU), 321 VMSTATE_UINT64(env.exclusive_high, ARMCPU), 322 VMSTATE_UINT64(env.features, ARMCPU), 323 VMSTATE_UINT32(env.exception.syndrome, ARMCPU), 324 VMSTATE_UINT32(env.exception.fsr, ARMCPU), 325 VMSTATE_UINT64(env.exception.vaddress, ARMCPU), 326 VMSTATE_TIMER_PTR(gt_timer[GTIMER_PHYS], ARMCPU), 327 VMSTATE_TIMER_PTR(gt_timer[GTIMER_VIRT], ARMCPU), 328 VMSTATE_BOOL(powered_off, ARMCPU), 329 VMSTATE_END_OF_LIST() 330 }, 331 .subsections = (const VMStateDescription*[]) { 332 &vmstate_vfp, 333 &vmstate_iwmmxt, 334 &vmstate_m, 335 &vmstate_thumb2ee, 336 &vmstate_pmsav7, 337 NULL 338 } 339 }; 340