1 #include "qemu/osdep.h" 2 #include "qemu-common.h" 3 #include "cpu.h" 4 #include "hw/hw.h" 5 #include "hw/boards.h" 6 #include "qemu/error-report.h" 7 #include "sysemu/kvm.h" 8 #include "kvm_arm.h" 9 #include "internals.h" 10 #include "migration/cpu.h" 11 12 static bool vfp_needed(void *opaque) 13 { 14 ARMCPU *cpu = opaque; 15 CPUARMState *env = &cpu->env; 16 17 return arm_feature(env, ARM_FEATURE_VFP); 18 } 19 20 static int get_fpscr(QEMUFile *f, void *opaque, size_t size, 21 VMStateField *field) 22 { 23 ARMCPU *cpu = opaque; 24 CPUARMState *env = &cpu->env; 25 uint32_t val = qemu_get_be32(f); 26 27 vfp_set_fpscr(env, val); 28 return 0; 29 } 30 31 static int put_fpscr(QEMUFile *f, void *opaque, size_t size, 32 VMStateField *field, QJSON *vmdesc) 33 { 34 ARMCPU *cpu = opaque; 35 CPUARMState *env = &cpu->env; 36 37 qemu_put_be32(f, vfp_get_fpscr(env)); 38 return 0; 39 } 40 41 static const VMStateInfo vmstate_fpscr = { 42 .name = "fpscr", 43 .get = get_fpscr, 44 .put = put_fpscr, 45 }; 46 47 static const VMStateDescription vmstate_vfp = { 48 .name = "cpu/vfp", 49 .version_id = 3, 50 .minimum_version_id = 3, 51 .needed = vfp_needed, 52 .fields = (VMStateField[]) { 53 VMSTATE_FLOAT64_ARRAY(env.vfp.regs, ARMCPU, 64), 54 /* The xregs array is a little awkward because element 1 (FPSCR) 55 * requires a specific accessor, so we have to split it up in 56 * the vmstate: 57 */ 58 VMSTATE_UINT32(env.vfp.xregs[0], ARMCPU), 59 VMSTATE_UINT32_SUB_ARRAY(env.vfp.xregs, ARMCPU, 2, 14), 60 { 61 .name = "fpscr", 62 .version_id = 0, 63 .size = sizeof(uint32_t), 64 .info = &vmstate_fpscr, 65 .flags = VMS_SINGLE, 66 .offset = 0, 67 }, 68 VMSTATE_END_OF_LIST() 69 } 70 }; 71 72 static bool iwmmxt_needed(void *opaque) 73 { 74 ARMCPU *cpu = opaque; 75 CPUARMState *env = &cpu->env; 76 77 return arm_feature(env, ARM_FEATURE_IWMMXT); 78 } 79 80 static const VMStateDescription vmstate_iwmmxt = { 81 .name = "cpu/iwmmxt", 82 .version_id = 1, 83 .minimum_version_id = 1, 84 .needed = iwmmxt_needed, 85 .fields = (VMStateField[]) { 86 VMSTATE_UINT64_ARRAY(env.iwmmxt.regs, ARMCPU, 16), 87 VMSTATE_UINT32_ARRAY(env.iwmmxt.cregs, ARMCPU, 16), 88 VMSTATE_END_OF_LIST() 89 } 90 }; 91 92 static bool m_needed(void *opaque) 93 { 94 ARMCPU *cpu = opaque; 95 CPUARMState *env = &cpu->env; 96 97 return arm_feature(env, ARM_FEATURE_M); 98 } 99 100 static const VMStateDescription vmstate_m_faultmask_primask = { 101 .name = "cpu/m/faultmask-primask", 102 .version_id = 1, 103 .minimum_version_id = 1, 104 .fields = (VMStateField[]) { 105 VMSTATE_UINT32(env.v7m.faultmask, ARMCPU), 106 VMSTATE_UINT32(env.v7m.primask, ARMCPU), 107 VMSTATE_END_OF_LIST() 108 } 109 }; 110 111 static const VMStateDescription vmstate_m = { 112 .name = "cpu/m", 113 .version_id = 4, 114 .minimum_version_id = 4, 115 .needed = m_needed, 116 .fields = (VMStateField[]) { 117 VMSTATE_UINT32(env.v7m.vecbase, ARMCPU), 118 VMSTATE_UINT32(env.v7m.basepri, ARMCPU), 119 VMSTATE_UINT32(env.v7m.control, ARMCPU), 120 VMSTATE_UINT32(env.v7m.ccr, ARMCPU), 121 VMSTATE_UINT32(env.v7m.cfsr, ARMCPU), 122 VMSTATE_UINT32(env.v7m.hfsr, ARMCPU), 123 VMSTATE_UINT32(env.v7m.dfsr, ARMCPU), 124 VMSTATE_UINT32(env.v7m.mmfar, ARMCPU), 125 VMSTATE_UINT32(env.v7m.bfar, ARMCPU), 126 VMSTATE_UINT32(env.v7m.mpu_ctrl, ARMCPU), 127 VMSTATE_INT32(env.v7m.exception, ARMCPU), 128 VMSTATE_END_OF_LIST() 129 }, 130 .subsections = (const VMStateDescription*[]) { 131 &vmstate_m_faultmask_primask, 132 NULL 133 } 134 }; 135 136 static bool thumb2ee_needed(void *opaque) 137 { 138 ARMCPU *cpu = opaque; 139 CPUARMState *env = &cpu->env; 140 141 return arm_feature(env, ARM_FEATURE_THUMB2EE); 142 } 143 144 static const VMStateDescription vmstate_thumb2ee = { 145 .name = "cpu/thumb2ee", 146 .version_id = 1, 147 .minimum_version_id = 1, 148 .needed = thumb2ee_needed, 149 .fields = (VMStateField[]) { 150 VMSTATE_UINT32(env.teecr, ARMCPU), 151 VMSTATE_UINT32(env.teehbr, ARMCPU), 152 VMSTATE_END_OF_LIST() 153 } 154 }; 155 156 static bool pmsav7_needed(void *opaque) 157 { 158 ARMCPU *cpu = opaque; 159 CPUARMState *env = &cpu->env; 160 161 return arm_feature(env, ARM_FEATURE_PMSA) && 162 arm_feature(env, ARM_FEATURE_V7); 163 } 164 165 static bool pmsav7_rgnr_vmstate_validate(void *opaque, int version_id) 166 { 167 ARMCPU *cpu = opaque; 168 169 return cpu->env.pmsav7.rnr < cpu->pmsav7_dregion; 170 } 171 172 static const VMStateDescription vmstate_pmsav7 = { 173 .name = "cpu/pmsav7", 174 .version_id = 1, 175 .minimum_version_id = 1, 176 .needed = pmsav7_needed, 177 .fields = (VMStateField[]) { 178 VMSTATE_VARRAY_UINT32(env.pmsav7.drbar, ARMCPU, pmsav7_dregion, 0, 179 vmstate_info_uint32, uint32_t), 180 VMSTATE_VARRAY_UINT32(env.pmsav7.drsr, ARMCPU, pmsav7_dregion, 0, 181 vmstate_info_uint32, uint32_t), 182 VMSTATE_VARRAY_UINT32(env.pmsav7.dracr, ARMCPU, pmsav7_dregion, 0, 183 vmstate_info_uint32, uint32_t), 184 VMSTATE_VALIDATE("rgnr is valid", pmsav7_rgnr_vmstate_validate), 185 VMSTATE_END_OF_LIST() 186 } 187 }; 188 189 static bool pmsav7_rnr_needed(void *opaque) 190 { 191 ARMCPU *cpu = opaque; 192 CPUARMState *env = &cpu->env; 193 194 /* For R profile cores pmsav7.rnr is migrated via the cpreg 195 * "RGNR" definition in helper.h. For M profile we have to 196 * migrate it separately. 197 */ 198 return arm_feature(env, ARM_FEATURE_M); 199 } 200 201 static const VMStateDescription vmstate_pmsav7_rnr = { 202 .name = "cpu/pmsav7-rnr", 203 .version_id = 1, 204 .minimum_version_id = 1, 205 .needed = pmsav7_rnr_needed, 206 .fields = (VMStateField[]) { 207 VMSTATE_UINT32(env.pmsav7.rnr, ARMCPU), 208 VMSTATE_END_OF_LIST() 209 } 210 }; 211 212 static int get_cpsr(QEMUFile *f, void *opaque, size_t size, 213 VMStateField *field) 214 { 215 ARMCPU *cpu = opaque; 216 CPUARMState *env = &cpu->env; 217 uint32_t val = qemu_get_be32(f); 218 219 if (arm_feature(env, ARM_FEATURE_M)) { 220 /* If the I or F bits are set then this is a migration from 221 * an old QEMU which still stored the M profile FAULTMASK 222 * and PRIMASK in env->daif. Set v7m.faultmask and v7m.primask 223 * accordingly, and then clear the bits so they don't confuse 224 * cpsr_write(). For a new QEMU, the bits here will always be 225 * clear, and the data is transferred using the 226 * vmstate_m_faultmask_primask subsection. 227 */ 228 if (val & CPSR_F) { 229 env->v7m.faultmask = 1; 230 } 231 if (val & CPSR_I) { 232 env->v7m.primask = 1; 233 } 234 val &= ~(CPSR_F | CPSR_I); 235 } 236 237 env->aarch64 = ((val & PSTATE_nRW) == 0); 238 239 if (is_a64(env)) { 240 pstate_write(env, val); 241 return 0; 242 } 243 244 cpsr_write(env, val, 0xffffffff, CPSRWriteRaw); 245 return 0; 246 } 247 248 static int put_cpsr(QEMUFile *f, void *opaque, size_t size, 249 VMStateField *field, QJSON *vmdesc) 250 { 251 ARMCPU *cpu = opaque; 252 CPUARMState *env = &cpu->env; 253 uint32_t val; 254 255 if (is_a64(env)) { 256 val = pstate_read(env); 257 } else { 258 val = cpsr_read(env); 259 } 260 261 qemu_put_be32(f, val); 262 return 0; 263 } 264 265 static const VMStateInfo vmstate_cpsr = { 266 .name = "cpsr", 267 .get = get_cpsr, 268 .put = put_cpsr, 269 }; 270 271 static int get_power(QEMUFile *f, void *opaque, size_t size, 272 VMStateField *field) 273 { 274 ARMCPU *cpu = opaque; 275 bool powered_off = qemu_get_byte(f); 276 cpu->power_state = powered_off ? PSCI_OFF : PSCI_ON; 277 return 0; 278 } 279 280 static int put_power(QEMUFile *f, void *opaque, size_t size, 281 VMStateField *field, QJSON *vmdesc) 282 { 283 ARMCPU *cpu = opaque; 284 285 /* Migration should never happen while we transition power states */ 286 287 if (cpu->power_state == PSCI_ON || 288 cpu->power_state == PSCI_OFF) { 289 bool powered_off = (cpu->power_state == PSCI_OFF) ? true : false; 290 qemu_put_byte(f, powered_off); 291 return 0; 292 } else { 293 return 1; 294 } 295 } 296 297 static const VMStateInfo vmstate_powered_off = { 298 .name = "powered_off", 299 .get = get_power, 300 .put = put_power, 301 }; 302 303 static void cpu_pre_save(void *opaque) 304 { 305 ARMCPU *cpu = opaque; 306 307 if (kvm_enabled()) { 308 if (!write_kvmstate_to_list(cpu)) { 309 /* This should never fail */ 310 abort(); 311 } 312 } else { 313 if (!write_cpustate_to_list(cpu)) { 314 /* This should never fail. */ 315 abort(); 316 } 317 } 318 319 cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len; 320 memcpy(cpu->cpreg_vmstate_indexes, cpu->cpreg_indexes, 321 cpu->cpreg_array_len * sizeof(uint64_t)); 322 memcpy(cpu->cpreg_vmstate_values, cpu->cpreg_values, 323 cpu->cpreg_array_len * sizeof(uint64_t)); 324 } 325 326 static int cpu_post_load(void *opaque, int version_id) 327 { 328 ARMCPU *cpu = opaque; 329 int i, v; 330 331 /* Update the values list from the incoming migration data. 332 * Anything in the incoming data which we don't know about is 333 * a migration failure; anything we know about but the incoming 334 * data doesn't specify retains its current (reset) value. 335 * The indexes list remains untouched -- we only inspect the 336 * incoming migration index list so we can match the values array 337 * entries with the right slots in our own values array. 338 */ 339 340 for (i = 0, v = 0; i < cpu->cpreg_array_len 341 && v < cpu->cpreg_vmstate_array_len; i++) { 342 if (cpu->cpreg_vmstate_indexes[v] > cpu->cpreg_indexes[i]) { 343 /* register in our list but not incoming : skip it */ 344 continue; 345 } 346 if (cpu->cpreg_vmstate_indexes[v] < cpu->cpreg_indexes[i]) { 347 /* register in their list but not ours: fail migration */ 348 return -1; 349 } 350 /* matching register, copy the value over */ 351 cpu->cpreg_values[i] = cpu->cpreg_vmstate_values[v]; 352 v++; 353 } 354 355 if (kvm_enabled()) { 356 if (!write_list_to_kvmstate(cpu, KVM_PUT_FULL_STATE)) { 357 return -1; 358 } 359 /* Note that it's OK for the TCG side not to know about 360 * every register in the list; KVM is authoritative if 361 * we're using it. 362 */ 363 write_list_to_cpustate(cpu); 364 } else { 365 if (!write_list_to_cpustate(cpu)) { 366 return -1; 367 } 368 } 369 370 hw_breakpoint_update_all(cpu); 371 hw_watchpoint_update_all(cpu); 372 373 return 0; 374 } 375 376 const VMStateDescription vmstate_arm_cpu = { 377 .name = "cpu", 378 .version_id = 22, 379 .minimum_version_id = 22, 380 .pre_save = cpu_pre_save, 381 .post_load = cpu_post_load, 382 .fields = (VMStateField[]) { 383 VMSTATE_UINT32_ARRAY(env.regs, ARMCPU, 16), 384 VMSTATE_UINT64_ARRAY(env.xregs, ARMCPU, 32), 385 VMSTATE_UINT64(env.pc, ARMCPU), 386 { 387 .name = "cpsr", 388 .version_id = 0, 389 .size = sizeof(uint32_t), 390 .info = &vmstate_cpsr, 391 .flags = VMS_SINGLE, 392 .offset = 0, 393 }, 394 VMSTATE_UINT32(env.spsr, ARMCPU), 395 VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 8), 396 VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 8), 397 VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 8), 398 VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5), 399 VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5), 400 VMSTATE_UINT64_ARRAY(env.elr_el, ARMCPU, 4), 401 VMSTATE_UINT64_ARRAY(env.sp_el, ARMCPU, 4), 402 /* The length-check must come before the arrays to avoid 403 * incoming data possibly overflowing the array. 404 */ 405 VMSTATE_INT32_POSITIVE_LE(cpreg_vmstate_array_len, ARMCPU), 406 VMSTATE_VARRAY_INT32(cpreg_vmstate_indexes, ARMCPU, 407 cpreg_vmstate_array_len, 408 0, vmstate_info_uint64, uint64_t), 409 VMSTATE_VARRAY_INT32(cpreg_vmstate_values, ARMCPU, 410 cpreg_vmstate_array_len, 411 0, vmstate_info_uint64, uint64_t), 412 VMSTATE_UINT64(env.exclusive_addr, ARMCPU), 413 VMSTATE_UINT64(env.exclusive_val, ARMCPU), 414 VMSTATE_UINT64(env.exclusive_high, ARMCPU), 415 VMSTATE_UINT64(env.features, ARMCPU), 416 VMSTATE_UINT32(env.exception.syndrome, ARMCPU), 417 VMSTATE_UINT32(env.exception.fsr, ARMCPU), 418 VMSTATE_UINT64(env.exception.vaddress, ARMCPU), 419 VMSTATE_TIMER_PTR(gt_timer[GTIMER_PHYS], ARMCPU), 420 VMSTATE_TIMER_PTR(gt_timer[GTIMER_VIRT], ARMCPU), 421 { 422 .name = "power_state", 423 .version_id = 0, 424 .size = sizeof(bool), 425 .info = &vmstate_powered_off, 426 .flags = VMS_SINGLE, 427 .offset = 0, 428 }, 429 VMSTATE_END_OF_LIST() 430 }, 431 .subsections = (const VMStateDescription*[]) { 432 &vmstate_vfp, 433 &vmstate_iwmmxt, 434 &vmstate_m, 435 &vmstate_thumb2ee, 436 /* pmsav7_rnr must come before pmsav7 so that we have the 437 * region number before we test it in the VMSTATE_VALIDATE 438 * in vmstate_pmsav7. 439 */ 440 &vmstate_pmsav7_rnr, 441 &vmstate_pmsav7, 442 NULL 443 } 444 }; 445