xref: /openbmc/qemu/target/arm/machine.c (revision bed079da04dd9e0e249b9bc22bca8dce58b67f40)
1 #include "qemu/osdep.h"
2 #include "qemu-common.h"
3 #include "cpu.h"
4 #include "hw/hw.h"
5 #include "hw/boards.h"
6 #include "qemu/error-report.h"
7 #include "sysemu/kvm.h"
8 #include "kvm_arm.h"
9 #include "internals.h"
10 #include "migration/cpu.h"
11 
12 static bool vfp_needed(void *opaque)
13 {
14     ARMCPU *cpu = opaque;
15     CPUARMState *env = &cpu->env;
16 
17     return arm_feature(env, ARM_FEATURE_VFP);
18 }
19 
20 static int get_fpscr(QEMUFile *f, void *opaque, size_t size,
21                      VMStateField *field)
22 {
23     ARMCPU *cpu = opaque;
24     CPUARMState *env = &cpu->env;
25     uint32_t val = qemu_get_be32(f);
26 
27     vfp_set_fpscr(env, val);
28     return 0;
29 }
30 
31 static int put_fpscr(QEMUFile *f, void *opaque, size_t size,
32                      VMStateField *field, QJSON *vmdesc)
33 {
34     ARMCPU *cpu = opaque;
35     CPUARMState *env = &cpu->env;
36 
37     qemu_put_be32(f, vfp_get_fpscr(env));
38     return 0;
39 }
40 
41 static const VMStateInfo vmstate_fpscr = {
42     .name = "fpscr",
43     .get = get_fpscr,
44     .put = put_fpscr,
45 };
46 
47 static const VMStateDescription vmstate_vfp = {
48     .name = "cpu/vfp",
49     .version_id = 3,
50     .minimum_version_id = 3,
51     .needed = vfp_needed,
52     .fields = (VMStateField[]) {
53         VMSTATE_FLOAT64_ARRAY(env.vfp.regs, ARMCPU, 64),
54         /* The xregs array is a little awkward because element 1 (FPSCR)
55          * requires a specific accessor, so we have to split it up in
56          * the vmstate:
57          */
58         VMSTATE_UINT32(env.vfp.xregs[0], ARMCPU),
59         VMSTATE_UINT32_SUB_ARRAY(env.vfp.xregs, ARMCPU, 2, 14),
60         {
61             .name = "fpscr",
62             .version_id = 0,
63             .size = sizeof(uint32_t),
64             .info = &vmstate_fpscr,
65             .flags = VMS_SINGLE,
66             .offset = 0,
67         },
68         VMSTATE_END_OF_LIST()
69     }
70 };
71 
72 static bool iwmmxt_needed(void *opaque)
73 {
74     ARMCPU *cpu = opaque;
75     CPUARMState *env = &cpu->env;
76 
77     return arm_feature(env, ARM_FEATURE_IWMMXT);
78 }
79 
80 static const VMStateDescription vmstate_iwmmxt = {
81     .name = "cpu/iwmmxt",
82     .version_id = 1,
83     .minimum_version_id = 1,
84     .needed = iwmmxt_needed,
85     .fields = (VMStateField[]) {
86         VMSTATE_UINT64_ARRAY(env.iwmmxt.regs, ARMCPU, 16),
87         VMSTATE_UINT32_ARRAY(env.iwmmxt.cregs, ARMCPU, 16),
88         VMSTATE_END_OF_LIST()
89     }
90 };
91 
92 static bool m_needed(void *opaque)
93 {
94     ARMCPU *cpu = opaque;
95     CPUARMState *env = &cpu->env;
96 
97     return arm_feature(env, ARM_FEATURE_M);
98 }
99 
100 static const VMStateDescription vmstate_m_faultmask_primask = {
101     .name = "cpu/m/faultmask-primask",
102     .version_id = 1,
103     .minimum_version_id = 1,
104     .fields = (VMStateField[]) {
105         VMSTATE_UINT32(env.v7m.faultmask[M_REG_NS], ARMCPU),
106         VMSTATE_UINT32(env.v7m.primask[M_REG_NS], ARMCPU),
107         VMSTATE_END_OF_LIST()
108     }
109 };
110 
111 static const VMStateDescription vmstate_m = {
112     .name = "cpu/m",
113     .version_id = 4,
114     .minimum_version_id = 4,
115     .needed = m_needed,
116     .fields = (VMStateField[]) {
117         VMSTATE_UINT32(env.v7m.vecbase[M_REG_NS], ARMCPU),
118         VMSTATE_UINT32(env.v7m.basepri[M_REG_NS], ARMCPU),
119         VMSTATE_UINT32(env.v7m.control[M_REG_NS], ARMCPU),
120         VMSTATE_UINT32(env.v7m.ccr[M_REG_NS], ARMCPU),
121         VMSTATE_UINT32(env.v7m.cfsr[M_REG_NS], ARMCPU),
122         VMSTATE_UINT32(env.v7m.hfsr, ARMCPU),
123         VMSTATE_UINT32(env.v7m.dfsr, ARMCPU),
124         VMSTATE_UINT32(env.v7m.mmfar[M_REG_NS], ARMCPU),
125         VMSTATE_UINT32(env.v7m.bfar, ARMCPU),
126         VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_NS], ARMCPU),
127         VMSTATE_INT32(env.v7m.exception, ARMCPU),
128         VMSTATE_END_OF_LIST()
129     },
130     .subsections = (const VMStateDescription*[]) {
131         &vmstate_m_faultmask_primask,
132         NULL
133     }
134 };
135 
136 static bool thumb2ee_needed(void *opaque)
137 {
138     ARMCPU *cpu = opaque;
139     CPUARMState *env = &cpu->env;
140 
141     return arm_feature(env, ARM_FEATURE_THUMB2EE);
142 }
143 
144 static const VMStateDescription vmstate_thumb2ee = {
145     .name = "cpu/thumb2ee",
146     .version_id = 1,
147     .minimum_version_id = 1,
148     .needed = thumb2ee_needed,
149     .fields = (VMStateField[]) {
150         VMSTATE_UINT32(env.teecr, ARMCPU),
151         VMSTATE_UINT32(env.teehbr, ARMCPU),
152         VMSTATE_END_OF_LIST()
153     }
154 };
155 
156 static bool pmsav7_needed(void *opaque)
157 {
158     ARMCPU *cpu = opaque;
159     CPUARMState *env = &cpu->env;
160 
161     return arm_feature(env, ARM_FEATURE_PMSA) &&
162            arm_feature(env, ARM_FEATURE_V7) &&
163            !arm_feature(env, ARM_FEATURE_V8);
164 }
165 
166 static bool pmsav7_rgnr_vmstate_validate(void *opaque, int version_id)
167 {
168     ARMCPU *cpu = opaque;
169 
170     return cpu->env.pmsav7.rnr[M_REG_NS] < cpu->pmsav7_dregion;
171 }
172 
173 static const VMStateDescription vmstate_pmsav7 = {
174     .name = "cpu/pmsav7",
175     .version_id = 1,
176     .minimum_version_id = 1,
177     .needed = pmsav7_needed,
178     .fields = (VMStateField[]) {
179         VMSTATE_VARRAY_UINT32(env.pmsav7.drbar, ARMCPU, pmsav7_dregion, 0,
180                               vmstate_info_uint32, uint32_t),
181         VMSTATE_VARRAY_UINT32(env.pmsav7.drsr, ARMCPU, pmsav7_dregion, 0,
182                               vmstate_info_uint32, uint32_t),
183         VMSTATE_VARRAY_UINT32(env.pmsav7.dracr, ARMCPU, pmsav7_dregion, 0,
184                               vmstate_info_uint32, uint32_t),
185         VMSTATE_VALIDATE("rgnr is valid", pmsav7_rgnr_vmstate_validate),
186         VMSTATE_END_OF_LIST()
187     }
188 };
189 
190 static bool pmsav7_rnr_needed(void *opaque)
191 {
192     ARMCPU *cpu = opaque;
193     CPUARMState *env = &cpu->env;
194 
195     /* For R profile cores pmsav7.rnr is migrated via the cpreg
196      * "RGNR" definition in helper.h. For M profile we have to
197      * migrate it separately.
198      */
199     return arm_feature(env, ARM_FEATURE_M);
200 }
201 
202 static const VMStateDescription vmstate_pmsav7_rnr = {
203     .name = "cpu/pmsav7-rnr",
204     .version_id = 1,
205     .minimum_version_id = 1,
206     .needed = pmsav7_rnr_needed,
207     .fields = (VMStateField[]) {
208         VMSTATE_UINT32(env.pmsav7.rnr[M_REG_NS], ARMCPU),
209         VMSTATE_END_OF_LIST()
210     }
211 };
212 
213 static bool pmsav8_needed(void *opaque)
214 {
215     ARMCPU *cpu = opaque;
216     CPUARMState *env = &cpu->env;
217 
218     return arm_feature(env, ARM_FEATURE_PMSA) &&
219         arm_feature(env, ARM_FEATURE_V8);
220 }
221 
222 static const VMStateDescription vmstate_pmsav8 = {
223     .name = "cpu/pmsav8",
224     .version_id = 1,
225     .minimum_version_id = 1,
226     .needed = pmsav8_needed,
227     .fields = (VMStateField[]) {
228         VMSTATE_VARRAY_UINT32(env.pmsav8.rbar[M_REG_NS], ARMCPU, pmsav7_dregion,
229                               0, vmstate_info_uint32, uint32_t),
230         VMSTATE_VARRAY_UINT32(env.pmsav8.rlar[M_REG_NS], ARMCPU, pmsav7_dregion,
231                               0, vmstate_info_uint32, uint32_t),
232         VMSTATE_UINT32(env.pmsav8.mair0[M_REG_NS], ARMCPU),
233         VMSTATE_UINT32(env.pmsav8.mair1[M_REG_NS], ARMCPU),
234         VMSTATE_END_OF_LIST()
235     }
236 };
237 
238 static bool s_rnr_vmstate_validate(void *opaque, int version_id)
239 {
240     ARMCPU *cpu = opaque;
241 
242     return cpu->env.pmsav7.rnr[M_REG_S] < cpu->pmsav7_dregion;
243 }
244 
245 static bool m_security_needed(void *opaque)
246 {
247     ARMCPU *cpu = opaque;
248     CPUARMState *env = &cpu->env;
249 
250     return arm_feature(env, ARM_FEATURE_M_SECURITY);
251 }
252 
253 static const VMStateDescription vmstate_m_security = {
254     .name = "cpu/m-security",
255     .version_id = 1,
256     .minimum_version_id = 1,
257     .needed = m_security_needed,
258     .fields = (VMStateField[]) {
259         VMSTATE_UINT32(env.v7m.secure, ARMCPU),
260         VMSTATE_UINT32(env.v7m.other_ss_msp, ARMCPU),
261         VMSTATE_UINT32(env.v7m.other_ss_psp, ARMCPU),
262         VMSTATE_UINT32(env.v7m.basepri[M_REG_S], ARMCPU),
263         VMSTATE_UINT32(env.v7m.primask[M_REG_S], ARMCPU),
264         VMSTATE_UINT32(env.v7m.faultmask[M_REG_S], ARMCPU),
265         VMSTATE_UINT32(env.v7m.control[M_REG_S], ARMCPU),
266         VMSTATE_UINT32(env.v7m.vecbase[M_REG_S], ARMCPU),
267         VMSTATE_UINT32(env.pmsav8.mair0[M_REG_S], ARMCPU),
268         VMSTATE_UINT32(env.pmsav8.mair1[M_REG_S], ARMCPU),
269         VMSTATE_VARRAY_UINT32(env.pmsav8.rbar[M_REG_S], ARMCPU, pmsav7_dregion,
270                               0, vmstate_info_uint32, uint32_t),
271         VMSTATE_VARRAY_UINT32(env.pmsav8.rlar[M_REG_S], ARMCPU, pmsav7_dregion,
272                               0, vmstate_info_uint32, uint32_t),
273         VMSTATE_UINT32(env.pmsav7.rnr[M_REG_S], ARMCPU),
274         VMSTATE_VALIDATE("secure MPU_RNR is valid", s_rnr_vmstate_validate),
275         VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_S], ARMCPU),
276         VMSTATE_UINT32(env.v7m.ccr[M_REG_S], ARMCPU),
277         VMSTATE_UINT32(env.v7m.mmfar[M_REG_S], ARMCPU),
278         VMSTATE_UINT32(env.v7m.cfsr[M_REG_S], ARMCPU),
279         VMSTATE_UINT32(env.v7m.sfsr, ARMCPU),
280         VMSTATE_UINT32(env.v7m.sfar, ARMCPU),
281         VMSTATE_END_OF_LIST()
282     }
283 };
284 
285 static int get_cpsr(QEMUFile *f, void *opaque, size_t size,
286                     VMStateField *field)
287 {
288     ARMCPU *cpu = opaque;
289     CPUARMState *env = &cpu->env;
290     uint32_t val = qemu_get_be32(f);
291 
292     if (arm_feature(env, ARM_FEATURE_M)) {
293         if (val & XPSR_EXCP) {
294             /* This is a CPSR format value from an older QEMU. (We can tell
295              * because values transferred in XPSR format always have zero
296              * for the EXCP field, and CPSR format will always have bit 4
297              * set in CPSR_M.) Rearrange it into XPSR format. The significant
298              * differences are that the T bit is not in the same place, the
299              * primask/faultmask info may be in the CPSR I and F bits, and
300              * we do not want the mode bits.
301              * We know that this cleanup happened before v8M, so there
302              * is no complication with banked primask/faultmask.
303              */
304             uint32_t newval = val;
305 
306             assert(!arm_feature(env, ARM_FEATURE_M_SECURITY));
307 
308             newval &= (CPSR_NZCV | CPSR_Q | CPSR_IT | CPSR_GE);
309             if (val & CPSR_T) {
310                 newval |= XPSR_T;
311             }
312             /* If the I or F bits are set then this is a migration from
313              * an old QEMU which still stored the M profile FAULTMASK
314              * and PRIMASK in env->daif. For a new QEMU, the data is
315              * transferred using the vmstate_m_faultmask_primask subsection.
316              */
317             if (val & CPSR_F) {
318                 env->v7m.faultmask[M_REG_NS] = 1;
319             }
320             if (val & CPSR_I) {
321                 env->v7m.primask[M_REG_NS] = 1;
322             }
323             val = newval;
324         }
325         /* Ignore the low bits, they are handled by vmstate_m. */
326         xpsr_write(env, val, ~XPSR_EXCP);
327         return 0;
328     }
329 
330     env->aarch64 = ((val & PSTATE_nRW) == 0);
331 
332     if (is_a64(env)) {
333         pstate_write(env, val);
334         return 0;
335     }
336 
337     cpsr_write(env, val, 0xffffffff, CPSRWriteRaw);
338     return 0;
339 }
340 
341 static int put_cpsr(QEMUFile *f, void *opaque, size_t size,
342                     VMStateField *field, QJSON *vmdesc)
343 {
344     ARMCPU *cpu = opaque;
345     CPUARMState *env = &cpu->env;
346     uint32_t val;
347 
348     if (arm_feature(env, ARM_FEATURE_M)) {
349         /* The low 9 bits are v7m.exception, which is handled by vmstate_m. */
350         val = xpsr_read(env) & ~XPSR_EXCP;
351     } else if (is_a64(env)) {
352         val = pstate_read(env);
353     } else {
354         val = cpsr_read(env);
355     }
356 
357     qemu_put_be32(f, val);
358     return 0;
359 }
360 
361 static const VMStateInfo vmstate_cpsr = {
362     .name = "cpsr",
363     .get = get_cpsr,
364     .put = put_cpsr,
365 };
366 
367 static int get_power(QEMUFile *f, void *opaque, size_t size,
368                     VMStateField *field)
369 {
370     ARMCPU *cpu = opaque;
371     bool powered_off = qemu_get_byte(f);
372     cpu->power_state = powered_off ? PSCI_OFF : PSCI_ON;
373     return 0;
374 }
375 
376 static int put_power(QEMUFile *f, void *opaque, size_t size,
377                     VMStateField *field, QJSON *vmdesc)
378 {
379     ARMCPU *cpu = opaque;
380 
381     /* Migration should never happen while we transition power states */
382 
383     if (cpu->power_state == PSCI_ON ||
384         cpu->power_state == PSCI_OFF) {
385         bool powered_off = (cpu->power_state == PSCI_OFF) ? true : false;
386         qemu_put_byte(f, powered_off);
387         return 0;
388     } else {
389         return 1;
390     }
391 }
392 
393 static const VMStateInfo vmstate_powered_off = {
394     .name = "powered_off",
395     .get = get_power,
396     .put = put_power,
397 };
398 
399 static int cpu_pre_save(void *opaque)
400 {
401     ARMCPU *cpu = opaque;
402 
403     if (kvm_enabled()) {
404         if (!write_kvmstate_to_list(cpu)) {
405             /* This should never fail */
406             abort();
407         }
408     } else {
409         if (!write_cpustate_to_list(cpu)) {
410             /* This should never fail. */
411             abort();
412         }
413     }
414 
415     cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
416     memcpy(cpu->cpreg_vmstate_indexes, cpu->cpreg_indexes,
417            cpu->cpreg_array_len * sizeof(uint64_t));
418     memcpy(cpu->cpreg_vmstate_values, cpu->cpreg_values,
419            cpu->cpreg_array_len * sizeof(uint64_t));
420 
421     return 0;
422 }
423 
424 static int cpu_post_load(void *opaque, int version_id)
425 {
426     ARMCPU *cpu = opaque;
427     int i, v;
428 
429     /* Update the values list from the incoming migration data.
430      * Anything in the incoming data which we don't know about is
431      * a migration failure; anything we know about but the incoming
432      * data doesn't specify retains its current (reset) value.
433      * The indexes list remains untouched -- we only inspect the
434      * incoming migration index list so we can match the values array
435      * entries with the right slots in our own values array.
436      */
437 
438     for (i = 0, v = 0; i < cpu->cpreg_array_len
439              && v < cpu->cpreg_vmstate_array_len; i++) {
440         if (cpu->cpreg_vmstate_indexes[v] > cpu->cpreg_indexes[i]) {
441             /* register in our list but not incoming : skip it */
442             continue;
443         }
444         if (cpu->cpreg_vmstate_indexes[v] < cpu->cpreg_indexes[i]) {
445             /* register in their list but not ours: fail migration */
446             return -1;
447         }
448         /* matching register, copy the value over */
449         cpu->cpreg_values[i] = cpu->cpreg_vmstate_values[v];
450         v++;
451     }
452 
453     if (kvm_enabled()) {
454         if (!write_list_to_kvmstate(cpu, KVM_PUT_FULL_STATE)) {
455             return -1;
456         }
457         /* Note that it's OK for the TCG side not to know about
458          * every register in the list; KVM is authoritative if
459          * we're using it.
460          */
461         write_list_to_cpustate(cpu);
462     } else {
463         if (!write_list_to_cpustate(cpu)) {
464             return -1;
465         }
466     }
467 
468     hw_breakpoint_update_all(cpu);
469     hw_watchpoint_update_all(cpu);
470 
471     return 0;
472 }
473 
474 const VMStateDescription vmstate_arm_cpu = {
475     .name = "cpu",
476     .version_id = 22,
477     .minimum_version_id = 22,
478     .pre_save = cpu_pre_save,
479     .post_load = cpu_post_load,
480     .fields = (VMStateField[]) {
481         VMSTATE_UINT32_ARRAY(env.regs, ARMCPU, 16),
482         VMSTATE_UINT64_ARRAY(env.xregs, ARMCPU, 32),
483         VMSTATE_UINT64(env.pc, ARMCPU),
484         {
485             .name = "cpsr",
486             .version_id = 0,
487             .size = sizeof(uint32_t),
488             .info = &vmstate_cpsr,
489             .flags = VMS_SINGLE,
490             .offset = 0,
491         },
492         VMSTATE_UINT32(env.spsr, ARMCPU),
493         VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 8),
494         VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 8),
495         VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 8),
496         VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5),
497         VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5),
498         VMSTATE_UINT64_ARRAY(env.elr_el, ARMCPU, 4),
499         VMSTATE_UINT64_ARRAY(env.sp_el, ARMCPU, 4),
500         /* The length-check must come before the arrays to avoid
501          * incoming data possibly overflowing the array.
502          */
503         VMSTATE_INT32_POSITIVE_LE(cpreg_vmstate_array_len, ARMCPU),
504         VMSTATE_VARRAY_INT32(cpreg_vmstate_indexes, ARMCPU,
505                              cpreg_vmstate_array_len,
506                              0, vmstate_info_uint64, uint64_t),
507         VMSTATE_VARRAY_INT32(cpreg_vmstate_values, ARMCPU,
508                              cpreg_vmstate_array_len,
509                              0, vmstate_info_uint64, uint64_t),
510         VMSTATE_UINT64(env.exclusive_addr, ARMCPU),
511         VMSTATE_UINT64(env.exclusive_val, ARMCPU),
512         VMSTATE_UINT64(env.exclusive_high, ARMCPU),
513         VMSTATE_UINT64(env.features, ARMCPU),
514         VMSTATE_UINT32(env.exception.syndrome, ARMCPU),
515         VMSTATE_UINT32(env.exception.fsr, ARMCPU),
516         VMSTATE_UINT64(env.exception.vaddress, ARMCPU),
517         VMSTATE_TIMER_PTR(gt_timer[GTIMER_PHYS], ARMCPU),
518         VMSTATE_TIMER_PTR(gt_timer[GTIMER_VIRT], ARMCPU),
519         {
520             .name = "power_state",
521             .version_id = 0,
522             .size = sizeof(bool),
523             .info = &vmstate_powered_off,
524             .flags = VMS_SINGLE,
525             .offset = 0,
526         },
527         VMSTATE_END_OF_LIST()
528     },
529     .subsections = (const VMStateDescription*[]) {
530         &vmstate_vfp,
531         &vmstate_iwmmxt,
532         &vmstate_m,
533         &vmstate_thumb2ee,
534         /* pmsav7_rnr must come before pmsav7 so that we have the
535          * region number before we test it in the VMSTATE_VALIDATE
536          * in vmstate_pmsav7.
537          */
538         &vmstate_pmsav7_rnr,
539         &vmstate_pmsav7,
540         &vmstate_pmsav8,
541         &vmstate_m_security,
542         NULL
543     }
544 };
545