1 #include "qemu/osdep.h" 2 #include "qemu-common.h" 3 #include "cpu.h" 4 #include "hw/hw.h" 5 #include "hw/boards.h" 6 #include "qemu/error-report.h" 7 #include "sysemu/kvm.h" 8 #include "kvm_arm.h" 9 #include "internals.h" 10 #include "migration/cpu.h" 11 12 static bool vfp_needed(void *opaque) 13 { 14 ARMCPU *cpu = opaque; 15 CPUARMState *env = &cpu->env; 16 17 return arm_feature(env, ARM_FEATURE_VFP); 18 } 19 20 static int get_fpscr(QEMUFile *f, void *opaque, size_t size, 21 VMStateField *field) 22 { 23 ARMCPU *cpu = opaque; 24 CPUARMState *env = &cpu->env; 25 uint32_t val = qemu_get_be32(f); 26 27 vfp_set_fpscr(env, val); 28 return 0; 29 } 30 31 static int put_fpscr(QEMUFile *f, void *opaque, size_t size, 32 VMStateField *field, QJSON *vmdesc) 33 { 34 ARMCPU *cpu = opaque; 35 CPUARMState *env = &cpu->env; 36 37 qemu_put_be32(f, vfp_get_fpscr(env)); 38 return 0; 39 } 40 41 static const VMStateInfo vmstate_fpscr = { 42 .name = "fpscr", 43 .get = get_fpscr, 44 .put = put_fpscr, 45 }; 46 47 static const VMStateDescription vmstate_vfp = { 48 .name = "cpu/vfp", 49 .version_id = 3, 50 .minimum_version_id = 3, 51 .needed = vfp_needed, 52 .fields = (VMStateField[]) { 53 VMSTATE_FLOAT64_ARRAY(env.vfp.regs, ARMCPU, 64), 54 /* The xregs array is a little awkward because element 1 (FPSCR) 55 * requires a specific accessor, so we have to split it up in 56 * the vmstate: 57 */ 58 VMSTATE_UINT32(env.vfp.xregs[0], ARMCPU), 59 VMSTATE_UINT32_SUB_ARRAY(env.vfp.xregs, ARMCPU, 2, 14), 60 { 61 .name = "fpscr", 62 .version_id = 0, 63 .size = sizeof(uint32_t), 64 .info = &vmstate_fpscr, 65 .flags = VMS_SINGLE, 66 .offset = 0, 67 }, 68 VMSTATE_END_OF_LIST() 69 } 70 }; 71 72 static bool iwmmxt_needed(void *opaque) 73 { 74 ARMCPU *cpu = opaque; 75 CPUARMState *env = &cpu->env; 76 77 return arm_feature(env, ARM_FEATURE_IWMMXT); 78 } 79 80 static const VMStateDescription vmstate_iwmmxt = { 81 .name = "cpu/iwmmxt", 82 .version_id = 1, 83 .minimum_version_id = 1, 84 .needed = iwmmxt_needed, 85 .fields = (VMStateField[]) { 86 VMSTATE_UINT64_ARRAY(env.iwmmxt.regs, ARMCPU, 16), 87 VMSTATE_UINT32_ARRAY(env.iwmmxt.cregs, ARMCPU, 16), 88 VMSTATE_END_OF_LIST() 89 } 90 }; 91 92 static bool m_needed(void *opaque) 93 { 94 ARMCPU *cpu = opaque; 95 CPUARMState *env = &cpu->env; 96 97 return arm_feature(env, ARM_FEATURE_M); 98 } 99 100 static const VMStateDescription vmstate_m_faultmask_primask = { 101 .name = "cpu/m/faultmask-primask", 102 .version_id = 1, 103 .minimum_version_id = 1, 104 .fields = (VMStateField[]) { 105 VMSTATE_UINT32(env.v7m.faultmask[M_REG_NS], ARMCPU), 106 VMSTATE_UINT32(env.v7m.primask[M_REG_NS], ARMCPU), 107 VMSTATE_END_OF_LIST() 108 } 109 }; 110 111 static const VMStateDescription vmstate_m = { 112 .name = "cpu/m", 113 .version_id = 4, 114 .minimum_version_id = 4, 115 .needed = m_needed, 116 .fields = (VMStateField[]) { 117 VMSTATE_UINT32(env.v7m.vecbase[M_REG_NS], ARMCPU), 118 VMSTATE_UINT32(env.v7m.basepri[M_REG_NS], ARMCPU), 119 VMSTATE_UINT32(env.v7m.control[M_REG_NS], ARMCPU), 120 VMSTATE_UINT32(env.v7m.ccr[M_REG_NS], ARMCPU), 121 VMSTATE_UINT32(env.v7m.cfsr, ARMCPU), 122 VMSTATE_UINT32(env.v7m.hfsr, ARMCPU), 123 VMSTATE_UINT32(env.v7m.dfsr, ARMCPU), 124 VMSTATE_UINT32(env.v7m.mmfar, ARMCPU), 125 VMSTATE_UINT32(env.v7m.bfar, ARMCPU), 126 VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_NS], ARMCPU), 127 VMSTATE_INT32(env.v7m.exception, ARMCPU), 128 VMSTATE_END_OF_LIST() 129 }, 130 .subsections = (const VMStateDescription*[]) { 131 &vmstate_m_faultmask_primask, 132 NULL 133 } 134 }; 135 136 static bool thumb2ee_needed(void *opaque) 137 { 138 ARMCPU *cpu = opaque; 139 CPUARMState *env = &cpu->env; 140 141 return arm_feature(env, ARM_FEATURE_THUMB2EE); 142 } 143 144 static const VMStateDescription vmstate_thumb2ee = { 145 .name = "cpu/thumb2ee", 146 .version_id = 1, 147 .minimum_version_id = 1, 148 .needed = thumb2ee_needed, 149 .fields = (VMStateField[]) { 150 VMSTATE_UINT32(env.teecr, ARMCPU), 151 VMSTATE_UINT32(env.teehbr, ARMCPU), 152 VMSTATE_END_OF_LIST() 153 } 154 }; 155 156 static bool pmsav7_needed(void *opaque) 157 { 158 ARMCPU *cpu = opaque; 159 CPUARMState *env = &cpu->env; 160 161 return arm_feature(env, ARM_FEATURE_PMSA) && 162 arm_feature(env, ARM_FEATURE_V7) && 163 !arm_feature(env, ARM_FEATURE_V8); 164 } 165 166 static bool pmsav7_rgnr_vmstate_validate(void *opaque, int version_id) 167 { 168 ARMCPU *cpu = opaque; 169 170 return cpu->env.pmsav7.rnr[M_REG_NS] < cpu->pmsav7_dregion; 171 } 172 173 static const VMStateDescription vmstate_pmsav7 = { 174 .name = "cpu/pmsav7", 175 .version_id = 1, 176 .minimum_version_id = 1, 177 .needed = pmsav7_needed, 178 .fields = (VMStateField[]) { 179 VMSTATE_VARRAY_UINT32(env.pmsav7.drbar, ARMCPU, pmsav7_dregion, 0, 180 vmstate_info_uint32, uint32_t), 181 VMSTATE_VARRAY_UINT32(env.pmsav7.drsr, ARMCPU, pmsav7_dregion, 0, 182 vmstate_info_uint32, uint32_t), 183 VMSTATE_VARRAY_UINT32(env.pmsav7.dracr, ARMCPU, pmsav7_dregion, 0, 184 vmstate_info_uint32, uint32_t), 185 VMSTATE_VALIDATE("rgnr is valid", pmsav7_rgnr_vmstate_validate), 186 VMSTATE_END_OF_LIST() 187 } 188 }; 189 190 static bool pmsav7_rnr_needed(void *opaque) 191 { 192 ARMCPU *cpu = opaque; 193 CPUARMState *env = &cpu->env; 194 195 /* For R profile cores pmsav7.rnr is migrated via the cpreg 196 * "RGNR" definition in helper.h. For M profile we have to 197 * migrate it separately. 198 */ 199 return arm_feature(env, ARM_FEATURE_M); 200 } 201 202 static const VMStateDescription vmstate_pmsav7_rnr = { 203 .name = "cpu/pmsav7-rnr", 204 .version_id = 1, 205 .minimum_version_id = 1, 206 .needed = pmsav7_rnr_needed, 207 .fields = (VMStateField[]) { 208 VMSTATE_UINT32(env.pmsav7.rnr[M_REG_NS], ARMCPU), 209 VMSTATE_END_OF_LIST() 210 } 211 }; 212 213 static bool pmsav8_needed(void *opaque) 214 { 215 ARMCPU *cpu = opaque; 216 CPUARMState *env = &cpu->env; 217 218 return arm_feature(env, ARM_FEATURE_PMSA) && 219 arm_feature(env, ARM_FEATURE_V8); 220 } 221 222 static const VMStateDescription vmstate_pmsav8 = { 223 .name = "cpu/pmsav8", 224 .version_id = 1, 225 .minimum_version_id = 1, 226 .needed = pmsav8_needed, 227 .fields = (VMStateField[]) { 228 VMSTATE_VARRAY_UINT32(env.pmsav8.rbar[M_REG_NS], ARMCPU, pmsav7_dregion, 229 0, vmstate_info_uint32, uint32_t), 230 VMSTATE_VARRAY_UINT32(env.pmsav8.rlar[M_REG_NS], ARMCPU, pmsav7_dregion, 231 0, vmstate_info_uint32, uint32_t), 232 VMSTATE_UINT32(env.pmsav8.mair0[M_REG_NS], ARMCPU), 233 VMSTATE_UINT32(env.pmsav8.mair1[M_REG_NS], ARMCPU), 234 VMSTATE_END_OF_LIST() 235 } 236 }; 237 238 static bool s_rnr_vmstate_validate(void *opaque, int version_id) 239 { 240 ARMCPU *cpu = opaque; 241 242 return cpu->env.pmsav7.rnr[M_REG_S] < cpu->pmsav7_dregion; 243 } 244 245 static bool m_security_needed(void *opaque) 246 { 247 ARMCPU *cpu = opaque; 248 CPUARMState *env = &cpu->env; 249 250 return arm_feature(env, ARM_FEATURE_M_SECURITY); 251 } 252 253 static const VMStateDescription vmstate_m_security = { 254 .name = "cpu/m-security", 255 .version_id = 1, 256 .minimum_version_id = 1, 257 .needed = m_security_needed, 258 .fields = (VMStateField[]) { 259 VMSTATE_UINT32(env.v7m.secure, ARMCPU), 260 VMSTATE_UINT32(env.v7m.basepri[M_REG_S], ARMCPU), 261 VMSTATE_UINT32(env.v7m.primask[M_REG_S], ARMCPU), 262 VMSTATE_UINT32(env.v7m.faultmask[M_REG_S], ARMCPU), 263 VMSTATE_UINT32(env.v7m.control[M_REG_S], ARMCPU), 264 VMSTATE_UINT32(env.v7m.vecbase[M_REG_S], ARMCPU), 265 VMSTATE_UINT32(env.pmsav8.mair0[M_REG_S], ARMCPU), 266 VMSTATE_UINT32(env.pmsav8.mair1[M_REG_S], ARMCPU), 267 VMSTATE_VARRAY_UINT32(env.pmsav8.rbar[M_REG_S], ARMCPU, pmsav7_dregion, 268 0, vmstate_info_uint32, uint32_t), 269 VMSTATE_VARRAY_UINT32(env.pmsav8.rlar[M_REG_S], ARMCPU, pmsav7_dregion, 270 0, vmstate_info_uint32, uint32_t), 271 VMSTATE_UINT32(env.pmsav7.rnr[M_REG_S], ARMCPU), 272 VMSTATE_VALIDATE("secure MPU_RNR is valid", s_rnr_vmstate_validate), 273 VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_S], ARMCPU), 274 VMSTATE_UINT32(env.v7m.ccr[M_REG_S], ARMCPU), 275 VMSTATE_END_OF_LIST() 276 } 277 }; 278 279 static int get_cpsr(QEMUFile *f, void *opaque, size_t size, 280 VMStateField *field) 281 { 282 ARMCPU *cpu = opaque; 283 CPUARMState *env = &cpu->env; 284 uint32_t val = qemu_get_be32(f); 285 286 if (arm_feature(env, ARM_FEATURE_M)) { 287 if (val & XPSR_EXCP) { 288 /* This is a CPSR format value from an older QEMU. (We can tell 289 * because values transferred in XPSR format always have zero 290 * for the EXCP field, and CPSR format will always have bit 4 291 * set in CPSR_M.) Rearrange it into XPSR format. The significant 292 * differences are that the T bit is not in the same place, the 293 * primask/faultmask info may be in the CPSR I and F bits, and 294 * we do not want the mode bits. 295 * We know that this cleanup happened before v8M, so there 296 * is no complication with banked primask/faultmask. 297 */ 298 uint32_t newval = val; 299 300 assert(!arm_feature(env, ARM_FEATURE_M_SECURITY)); 301 302 newval &= (CPSR_NZCV | CPSR_Q | CPSR_IT | CPSR_GE); 303 if (val & CPSR_T) { 304 newval |= XPSR_T; 305 } 306 /* If the I or F bits are set then this is a migration from 307 * an old QEMU which still stored the M profile FAULTMASK 308 * and PRIMASK in env->daif. For a new QEMU, the data is 309 * transferred using the vmstate_m_faultmask_primask subsection. 310 */ 311 if (val & CPSR_F) { 312 env->v7m.faultmask[M_REG_NS] = 1; 313 } 314 if (val & CPSR_I) { 315 env->v7m.primask[M_REG_NS] = 1; 316 } 317 val = newval; 318 } 319 /* Ignore the low bits, they are handled by vmstate_m. */ 320 xpsr_write(env, val, ~XPSR_EXCP); 321 return 0; 322 } 323 324 env->aarch64 = ((val & PSTATE_nRW) == 0); 325 326 if (is_a64(env)) { 327 pstate_write(env, val); 328 return 0; 329 } 330 331 cpsr_write(env, val, 0xffffffff, CPSRWriteRaw); 332 return 0; 333 } 334 335 static int put_cpsr(QEMUFile *f, void *opaque, size_t size, 336 VMStateField *field, QJSON *vmdesc) 337 { 338 ARMCPU *cpu = opaque; 339 CPUARMState *env = &cpu->env; 340 uint32_t val; 341 342 if (arm_feature(env, ARM_FEATURE_M)) { 343 /* The low 9 bits are v7m.exception, which is handled by vmstate_m. */ 344 val = xpsr_read(env) & ~XPSR_EXCP; 345 } else if (is_a64(env)) { 346 val = pstate_read(env); 347 } else { 348 val = cpsr_read(env); 349 } 350 351 qemu_put_be32(f, val); 352 return 0; 353 } 354 355 static const VMStateInfo vmstate_cpsr = { 356 .name = "cpsr", 357 .get = get_cpsr, 358 .put = put_cpsr, 359 }; 360 361 static int get_power(QEMUFile *f, void *opaque, size_t size, 362 VMStateField *field) 363 { 364 ARMCPU *cpu = opaque; 365 bool powered_off = qemu_get_byte(f); 366 cpu->power_state = powered_off ? PSCI_OFF : PSCI_ON; 367 return 0; 368 } 369 370 static int put_power(QEMUFile *f, void *opaque, size_t size, 371 VMStateField *field, QJSON *vmdesc) 372 { 373 ARMCPU *cpu = opaque; 374 375 /* Migration should never happen while we transition power states */ 376 377 if (cpu->power_state == PSCI_ON || 378 cpu->power_state == PSCI_OFF) { 379 bool powered_off = (cpu->power_state == PSCI_OFF) ? true : false; 380 qemu_put_byte(f, powered_off); 381 return 0; 382 } else { 383 return 1; 384 } 385 } 386 387 static const VMStateInfo vmstate_powered_off = { 388 .name = "powered_off", 389 .get = get_power, 390 .put = put_power, 391 }; 392 393 static void cpu_pre_save(void *opaque) 394 { 395 ARMCPU *cpu = opaque; 396 397 if (kvm_enabled()) { 398 if (!write_kvmstate_to_list(cpu)) { 399 /* This should never fail */ 400 abort(); 401 } 402 } else { 403 if (!write_cpustate_to_list(cpu)) { 404 /* This should never fail. */ 405 abort(); 406 } 407 } 408 409 cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len; 410 memcpy(cpu->cpreg_vmstate_indexes, cpu->cpreg_indexes, 411 cpu->cpreg_array_len * sizeof(uint64_t)); 412 memcpy(cpu->cpreg_vmstate_values, cpu->cpreg_values, 413 cpu->cpreg_array_len * sizeof(uint64_t)); 414 } 415 416 static int cpu_post_load(void *opaque, int version_id) 417 { 418 ARMCPU *cpu = opaque; 419 int i, v; 420 421 /* Update the values list from the incoming migration data. 422 * Anything in the incoming data which we don't know about is 423 * a migration failure; anything we know about but the incoming 424 * data doesn't specify retains its current (reset) value. 425 * The indexes list remains untouched -- we only inspect the 426 * incoming migration index list so we can match the values array 427 * entries with the right slots in our own values array. 428 */ 429 430 for (i = 0, v = 0; i < cpu->cpreg_array_len 431 && v < cpu->cpreg_vmstate_array_len; i++) { 432 if (cpu->cpreg_vmstate_indexes[v] > cpu->cpreg_indexes[i]) { 433 /* register in our list but not incoming : skip it */ 434 continue; 435 } 436 if (cpu->cpreg_vmstate_indexes[v] < cpu->cpreg_indexes[i]) { 437 /* register in their list but not ours: fail migration */ 438 return -1; 439 } 440 /* matching register, copy the value over */ 441 cpu->cpreg_values[i] = cpu->cpreg_vmstate_values[v]; 442 v++; 443 } 444 445 if (kvm_enabled()) { 446 if (!write_list_to_kvmstate(cpu, KVM_PUT_FULL_STATE)) { 447 return -1; 448 } 449 /* Note that it's OK for the TCG side not to know about 450 * every register in the list; KVM is authoritative if 451 * we're using it. 452 */ 453 write_list_to_cpustate(cpu); 454 } else { 455 if (!write_list_to_cpustate(cpu)) { 456 return -1; 457 } 458 } 459 460 hw_breakpoint_update_all(cpu); 461 hw_watchpoint_update_all(cpu); 462 463 return 0; 464 } 465 466 const VMStateDescription vmstate_arm_cpu = { 467 .name = "cpu", 468 .version_id = 22, 469 .minimum_version_id = 22, 470 .pre_save = cpu_pre_save, 471 .post_load = cpu_post_load, 472 .fields = (VMStateField[]) { 473 VMSTATE_UINT32_ARRAY(env.regs, ARMCPU, 16), 474 VMSTATE_UINT64_ARRAY(env.xregs, ARMCPU, 32), 475 VMSTATE_UINT64(env.pc, ARMCPU), 476 { 477 .name = "cpsr", 478 .version_id = 0, 479 .size = sizeof(uint32_t), 480 .info = &vmstate_cpsr, 481 .flags = VMS_SINGLE, 482 .offset = 0, 483 }, 484 VMSTATE_UINT32(env.spsr, ARMCPU), 485 VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 8), 486 VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 8), 487 VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 8), 488 VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5), 489 VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5), 490 VMSTATE_UINT64_ARRAY(env.elr_el, ARMCPU, 4), 491 VMSTATE_UINT64_ARRAY(env.sp_el, ARMCPU, 4), 492 /* The length-check must come before the arrays to avoid 493 * incoming data possibly overflowing the array. 494 */ 495 VMSTATE_INT32_POSITIVE_LE(cpreg_vmstate_array_len, ARMCPU), 496 VMSTATE_VARRAY_INT32(cpreg_vmstate_indexes, ARMCPU, 497 cpreg_vmstate_array_len, 498 0, vmstate_info_uint64, uint64_t), 499 VMSTATE_VARRAY_INT32(cpreg_vmstate_values, ARMCPU, 500 cpreg_vmstate_array_len, 501 0, vmstate_info_uint64, uint64_t), 502 VMSTATE_UINT64(env.exclusive_addr, ARMCPU), 503 VMSTATE_UINT64(env.exclusive_val, ARMCPU), 504 VMSTATE_UINT64(env.exclusive_high, ARMCPU), 505 VMSTATE_UINT64(env.features, ARMCPU), 506 VMSTATE_UINT32(env.exception.syndrome, ARMCPU), 507 VMSTATE_UINT32(env.exception.fsr, ARMCPU), 508 VMSTATE_UINT64(env.exception.vaddress, ARMCPU), 509 VMSTATE_TIMER_PTR(gt_timer[GTIMER_PHYS], ARMCPU), 510 VMSTATE_TIMER_PTR(gt_timer[GTIMER_VIRT], ARMCPU), 511 { 512 .name = "power_state", 513 .version_id = 0, 514 .size = sizeof(bool), 515 .info = &vmstate_powered_off, 516 .flags = VMS_SINGLE, 517 .offset = 0, 518 }, 519 VMSTATE_END_OF_LIST() 520 }, 521 .subsections = (const VMStateDescription*[]) { 522 &vmstate_vfp, 523 &vmstate_iwmmxt, 524 &vmstate_m, 525 &vmstate_thumb2ee, 526 /* pmsav7_rnr must come before pmsav7 so that we have the 527 * region number before we test it in the VMSTATE_VALIDATE 528 * in vmstate_pmsav7. 529 */ 530 &vmstate_pmsav7_rnr, 531 &vmstate_pmsav7, 532 &vmstate_pmsav8, 533 &vmstate_m_security, 534 NULL 535 } 536 }; 537