xref: /openbmc/qemu/target/arm/machine.c (revision 80adf54e)
1 #include "qemu/osdep.h"
2 #include "qemu-common.h"
3 #include "cpu.h"
4 #include "hw/hw.h"
5 #include "hw/boards.h"
6 #include "qemu/error-report.h"
7 #include "sysemu/kvm.h"
8 #include "kvm_arm.h"
9 #include "internals.h"
10 #include "migration/cpu.h"
11 
12 static bool vfp_needed(void *opaque)
13 {
14     ARMCPU *cpu = opaque;
15     CPUARMState *env = &cpu->env;
16 
17     return arm_feature(env, ARM_FEATURE_VFP);
18 }
19 
20 static int get_fpscr(QEMUFile *f, void *opaque, size_t size,
21                      VMStateField *field)
22 {
23     ARMCPU *cpu = opaque;
24     CPUARMState *env = &cpu->env;
25     uint32_t val = qemu_get_be32(f);
26 
27     vfp_set_fpscr(env, val);
28     return 0;
29 }
30 
31 static int put_fpscr(QEMUFile *f, void *opaque, size_t size,
32                      VMStateField *field, QJSON *vmdesc)
33 {
34     ARMCPU *cpu = opaque;
35     CPUARMState *env = &cpu->env;
36 
37     qemu_put_be32(f, vfp_get_fpscr(env));
38     return 0;
39 }
40 
41 static const VMStateInfo vmstate_fpscr = {
42     .name = "fpscr",
43     .get = get_fpscr,
44     .put = put_fpscr,
45 };
46 
47 static const VMStateDescription vmstate_vfp = {
48     .name = "cpu/vfp",
49     .version_id = 3,
50     .minimum_version_id = 3,
51     .needed = vfp_needed,
52     .fields = (VMStateField[]) {
53         VMSTATE_FLOAT64_ARRAY(env.vfp.regs, ARMCPU, 64),
54         /* The xregs array is a little awkward because element 1 (FPSCR)
55          * requires a specific accessor, so we have to split it up in
56          * the vmstate:
57          */
58         VMSTATE_UINT32(env.vfp.xregs[0], ARMCPU),
59         VMSTATE_UINT32_SUB_ARRAY(env.vfp.xregs, ARMCPU, 2, 14),
60         {
61             .name = "fpscr",
62             .version_id = 0,
63             .size = sizeof(uint32_t),
64             .info = &vmstate_fpscr,
65             .flags = VMS_SINGLE,
66             .offset = 0,
67         },
68         VMSTATE_END_OF_LIST()
69     }
70 };
71 
72 static bool iwmmxt_needed(void *opaque)
73 {
74     ARMCPU *cpu = opaque;
75     CPUARMState *env = &cpu->env;
76 
77     return arm_feature(env, ARM_FEATURE_IWMMXT);
78 }
79 
80 static const VMStateDescription vmstate_iwmmxt = {
81     .name = "cpu/iwmmxt",
82     .version_id = 1,
83     .minimum_version_id = 1,
84     .needed = iwmmxt_needed,
85     .fields = (VMStateField[]) {
86         VMSTATE_UINT64_ARRAY(env.iwmmxt.regs, ARMCPU, 16),
87         VMSTATE_UINT32_ARRAY(env.iwmmxt.cregs, ARMCPU, 16),
88         VMSTATE_END_OF_LIST()
89     }
90 };
91 
92 static bool m_needed(void *opaque)
93 {
94     ARMCPU *cpu = opaque;
95     CPUARMState *env = &cpu->env;
96 
97     return arm_feature(env, ARM_FEATURE_M);
98 }
99 
100 static const VMStateDescription vmstate_m = {
101     .name = "cpu/m",
102     .version_id = 4,
103     .minimum_version_id = 4,
104     .needed = m_needed,
105     .fields = (VMStateField[]) {
106         VMSTATE_UINT32(env.v7m.vecbase, ARMCPU),
107         VMSTATE_UINT32(env.v7m.basepri, ARMCPU),
108         VMSTATE_UINT32(env.v7m.control, ARMCPU),
109         VMSTATE_UINT32(env.v7m.ccr, ARMCPU),
110         VMSTATE_UINT32(env.v7m.cfsr, ARMCPU),
111         VMSTATE_UINT32(env.v7m.hfsr, ARMCPU),
112         VMSTATE_UINT32(env.v7m.dfsr, ARMCPU),
113         VMSTATE_UINT32(env.v7m.mmfar, ARMCPU),
114         VMSTATE_UINT32(env.v7m.bfar, ARMCPU),
115         VMSTATE_UINT32(env.v7m.mpu_ctrl, ARMCPU),
116         VMSTATE_INT32(env.v7m.exception, ARMCPU),
117         VMSTATE_END_OF_LIST()
118     }
119 };
120 
121 static bool thumb2ee_needed(void *opaque)
122 {
123     ARMCPU *cpu = opaque;
124     CPUARMState *env = &cpu->env;
125 
126     return arm_feature(env, ARM_FEATURE_THUMB2EE);
127 }
128 
129 static const VMStateDescription vmstate_thumb2ee = {
130     .name = "cpu/thumb2ee",
131     .version_id = 1,
132     .minimum_version_id = 1,
133     .needed = thumb2ee_needed,
134     .fields = (VMStateField[]) {
135         VMSTATE_UINT32(env.teecr, ARMCPU),
136         VMSTATE_UINT32(env.teehbr, ARMCPU),
137         VMSTATE_END_OF_LIST()
138     }
139 };
140 
141 static bool pmsav7_needed(void *opaque)
142 {
143     ARMCPU *cpu = opaque;
144     CPUARMState *env = &cpu->env;
145 
146     return arm_feature(env, ARM_FEATURE_PMSA) &&
147            arm_feature(env, ARM_FEATURE_V7);
148 }
149 
150 static bool pmsav7_rgnr_vmstate_validate(void *opaque, int version_id)
151 {
152     ARMCPU *cpu = opaque;
153 
154     return cpu->env.pmsav7.rnr < cpu->pmsav7_dregion;
155 }
156 
157 static const VMStateDescription vmstate_pmsav7 = {
158     .name = "cpu/pmsav7",
159     .version_id = 1,
160     .minimum_version_id = 1,
161     .needed = pmsav7_needed,
162     .fields = (VMStateField[]) {
163         VMSTATE_VARRAY_UINT32(env.pmsav7.drbar, ARMCPU, pmsav7_dregion, 0,
164                               vmstate_info_uint32, uint32_t),
165         VMSTATE_VARRAY_UINT32(env.pmsav7.drsr, ARMCPU, pmsav7_dregion, 0,
166                               vmstate_info_uint32, uint32_t),
167         VMSTATE_VARRAY_UINT32(env.pmsav7.dracr, ARMCPU, pmsav7_dregion, 0,
168                               vmstate_info_uint32, uint32_t),
169         VMSTATE_VALIDATE("rgnr is valid", pmsav7_rgnr_vmstate_validate),
170         VMSTATE_END_OF_LIST()
171     }
172 };
173 
174 static bool pmsav7_rnr_needed(void *opaque)
175 {
176     ARMCPU *cpu = opaque;
177     CPUARMState *env = &cpu->env;
178 
179     /* For R profile cores pmsav7.rnr is migrated via the cpreg
180      * "RGNR" definition in helper.h. For M profile we have to
181      * migrate it separately.
182      */
183     return arm_feature(env, ARM_FEATURE_M);
184 }
185 
186 static const VMStateDescription vmstate_pmsav7_rnr = {
187     .name = "cpu/pmsav7-rnr",
188     .version_id = 1,
189     .minimum_version_id = 1,
190     .needed = pmsav7_rnr_needed,
191     .fields = (VMStateField[]) {
192         VMSTATE_UINT32(env.pmsav7.rnr, ARMCPU),
193         VMSTATE_END_OF_LIST()
194     }
195 };
196 
197 static int get_cpsr(QEMUFile *f, void *opaque, size_t size,
198                     VMStateField *field)
199 {
200     ARMCPU *cpu = opaque;
201     CPUARMState *env = &cpu->env;
202     uint32_t val = qemu_get_be32(f);
203 
204     env->aarch64 = ((val & PSTATE_nRW) == 0);
205 
206     if (is_a64(env)) {
207         pstate_write(env, val);
208         return 0;
209     }
210 
211     cpsr_write(env, val, 0xffffffff, CPSRWriteRaw);
212     return 0;
213 }
214 
215 static int put_cpsr(QEMUFile *f, void *opaque, size_t size,
216                     VMStateField *field, QJSON *vmdesc)
217 {
218     ARMCPU *cpu = opaque;
219     CPUARMState *env = &cpu->env;
220     uint32_t val;
221 
222     if (is_a64(env)) {
223         val = pstate_read(env);
224     } else {
225         val = cpsr_read(env);
226     }
227 
228     qemu_put_be32(f, val);
229     return 0;
230 }
231 
232 static const VMStateInfo vmstate_cpsr = {
233     .name = "cpsr",
234     .get = get_cpsr,
235     .put = put_cpsr,
236 };
237 
238 static int get_power(QEMUFile *f, void *opaque, size_t size,
239                     VMStateField *field)
240 {
241     ARMCPU *cpu = opaque;
242     bool powered_off = qemu_get_byte(f);
243     cpu->power_state = powered_off ? PSCI_OFF : PSCI_ON;
244     return 0;
245 }
246 
247 static int put_power(QEMUFile *f, void *opaque, size_t size,
248                     VMStateField *field, QJSON *vmdesc)
249 {
250     ARMCPU *cpu = opaque;
251 
252     /* Migration should never happen while we transition power states */
253 
254     if (cpu->power_state == PSCI_ON ||
255         cpu->power_state == PSCI_OFF) {
256         bool powered_off = (cpu->power_state == PSCI_OFF) ? true : false;
257         qemu_put_byte(f, powered_off);
258         return 0;
259     } else {
260         return 1;
261     }
262 }
263 
264 static const VMStateInfo vmstate_powered_off = {
265     .name = "powered_off",
266     .get = get_power,
267     .put = put_power,
268 };
269 
270 static void cpu_pre_save(void *opaque)
271 {
272     ARMCPU *cpu = opaque;
273 
274     if (kvm_enabled()) {
275         if (!write_kvmstate_to_list(cpu)) {
276             /* This should never fail */
277             abort();
278         }
279     } else {
280         if (!write_cpustate_to_list(cpu)) {
281             /* This should never fail. */
282             abort();
283         }
284     }
285 
286     cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
287     memcpy(cpu->cpreg_vmstate_indexes, cpu->cpreg_indexes,
288            cpu->cpreg_array_len * sizeof(uint64_t));
289     memcpy(cpu->cpreg_vmstate_values, cpu->cpreg_values,
290            cpu->cpreg_array_len * sizeof(uint64_t));
291 }
292 
293 static int cpu_post_load(void *opaque, int version_id)
294 {
295     ARMCPU *cpu = opaque;
296     int i, v;
297 
298     /* Update the values list from the incoming migration data.
299      * Anything in the incoming data which we don't know about is
300      * a migration failure; anything we know about but the incoming
301      * data doesn't specify retains its current (reset) value.
302      * The indexes list remains untouched -- we only inspect the
303      * incoming migration index list so we can match the values array
304      * entries with the right slots in our own values array.
305      */
306 
307     for (i = 0, v = 0; i < cpu->cpreg_array_len
308              && v < cpu->cpreg_vmstate_array_len; i++) {
309         if (cpu->cpreg_vmstate_indexes[v] > cpu->cpreg_indexes[i]) {
310             /* register in our list but not incoming : skip it */
311             continue;
312         }
313         if (cpu->cpreg_vmstate_indexes[v] < cpu->cpreg_indexes[i]) {
314             /* register in their list but not ours: fail migration */
315             return -1;
316         }
317         /* matching register, copy the value over */
318         cpu->cpreg_values[i] = cpu->cpreg_vmstate_values[v];
319         v++;
320     }
321 
322     if (kvm_enabled()) {
323         if (!write_list_to_kvmstate(cpu, KVM_PUT_FULL_STATE)) {
324             return -1;
325         }
326         /* Note that it's OK for the TCG side not to know about
327          * every register in the list; KVM is authoritative if
328          * we're using it.
329          */
330         write_list_to_cpustate(cpu);
331     } else {
332         if (!write_list_to_cpustate(cpu)) {
333             return -1;
334         }
335     }
336 
337     hw_breakpoint_update_all(cpu);
338     hw_watchpoint_update_all(cpu);
339 
340     return 0;
341 }
342 
343 const VMStateDescription vmstate_arm_cpu = {
344     .name = "cpu",
345     .version_id = 22,
346     .minimum_version_id = 22,
347     .pre_save = cpu_pre_save,
348     .post_load = cpu_post_load,
349     .fields = (VMStateField[]) {
350         VMSTATE_UINT32_ARRAY(env.regs, ARMCPU, 16),
351         VMSTATE_UINT64_ARRAY(env.xregs, ARMCPU, 32),
352         VMSTATE_UINT64(env.pc, ARMCPU),
353         {
354             .name = "cpsr",
355             .version_id = 0,
356             .size = sizeof(uint32_t),
357             .info = &vmstate_cpsr,
358             .flags = VMS_SINGLE,
359             .offset = 0,
360         },
361         VMSTATE_UINT32(env.spsr, ARMCPU),
362         VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 8),
363         VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 8),
364         VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 8),
365         VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5),
366         VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5),
367         VMSTATE_UINT64_ARRAY(env.elr_el, ARMCPU, 4),
368         VMSTATE_UINT64_ARRAY(env.sp_el, ARMCPU, 4),
369         /* The length-check must come before the arrays to avoid
370          * incoming data possibly overflowing the array.
371          */
372         VMSTATE_INT32_POSITIVE_LE(cpreg_vmstate_array_len, ARMCPU),
373         VMSTATE_VARRAY_INT32(cpreg_vmstate_indexes, ARMCPU,
374                              cpreg_vmstate_array_len,
375                              0, vmstate_info_uint64, uint64_t),
376         VMSTATE_VARRAY_INT32(cpreg_vmstate_values, ARMCPU,
377                              cpreg_vmstate_array_len,
378                              0, vmstate_info_uint64, uint64_t),
379         VMSTATE_UINT64(env.exclusive_addr, ARMCPU),
380         VMSTATE_UINT64(env.exclusive_val, ARMCPU),
381         VMSTATE_UINT64(env.exclusive_high, ARMCPU),
382         VMSTATE_UINT64(env.features, ARMCPU),
383         VMSTATE_UINT32(env.exception.syndrome, ARMCPU),
384         VMSTATE_UINT32(env.exception.fsr, ARMCPU),
385         VMSTATE_UINT64(env.exception.vaddress, ARMCPU),
386         VMSTATE_TIMER_PTR(gt_timer[GTIMER_PHYS], ARMCPU),
387         VMSTATE_TIMER_PTR(gt_timer[GTIMER_VIRT], ARMCPU),
388         {
389             .name = "power_state",
390             .version_id = 0,
391             .size = sizeof(bool),
392             .info = &vmstate_powered_off,
393             .flags = VMS_SINGLE,
394             .offset = 0,
395         },
396         VMSTATE_END_OF_LIST()
397     },
398     .subsections = (const VMStateDescription*[]) {
399         &vmstate_vfp,
400         &vmstate_iwmmxt,
401         &vmstate_m,
402         &vmstate_thumb2ee,
403         /* pmsav7_rnr must come before pmsav7 so that we have the
404          * region number before we test it in the VMSTATE_VALIDATE
405          * in vmstate_pmsav7.
406          */
407         &vmstate_pmsav7_rnr,
408         &vmstate_pmsav7,
409         NULL
410     }
411 };
412