1 #include "qemu/osdep.h" 2 #include "qemu-common.h" 3 #include "cpu.h" 4 #include "hw/hw.h" 5 #include "hw/boards.h" 6 #include "qemu/error-report.h" 7 #include "sysemu/kvm.h" 8 #include "kvm_arm.h" 9 #include "internals.h" 10 #include "migration/cpu.h" 11 12 static bool vfp_needed(void *opaque) 13 { 14 ARMCPU *cpu = opaque; 15 CPUARMState *env = &cpu->env; 16 17 return arm_feature(env, ARM_FEATURE_VFP); 18 } 19 20 static int get_fpscr(QEMUFile *f, void *opaque, size_t size, 21 VMStateField *field) 22 { 23 ARMCPU *cpu = opaque; 24 CPUARMState *env = &cpu->env; 25 uint32_t val = qemu_get_be32(f); 26 27 vfp_set_fpscr(env, val); 28 return 0; 29 } 30 31 static int put_fpscr(QEMUFile *f, void *opaque, size_t size, 32 VMStateField *field, QJSON *vmdesc) 33 { 34 ARMCPU *cpu = opaque; 35 CPUARMState *env = &cpu->env; 36 37 qemu_put_be32(f, vfp_get_fpscr(env)); 38 return 0; 39 } 40 41 static const VMStateInfo vmstate_fpscr = { 42 .name = "fpscr", 43 .get = get_fpscr, 44 .put = put_fpscr, 45 }; 46 47 static const VMStateDescription vmstate_vfp = { 48 .name = "cpu/vfp", 49 .version_id = 3, 50 .minimum_version_id = 3, 51 .needed = vfp_needed, 52 .fields = (VMStateField[]) { 53 VMSTATE_FLOAT64_ARRAY(env.vfp.regs, ARMCPU, 64), 54 /* The xregs array is a little awkward because element 1 (FPSCR) 55 * requires a specific accessor, so we have to split it up in 56 * the vmstate: 57 */ 58 VMSTATE_UINT32(env.vfp.xregs[0], ARMCPU), 59 VMSTATE_UINT32_SUB_ARRAY(env.vfp.xregs, ARMCPU, 2, 14), 60 { 61 .name = "fpscr", 62 .version_id = 0, 63 .size = sizeof(uint32_t), 64 .info = &vmstate_fpscr, 65 .flags = VMS_SINGLE, 66 .offset = 0, 67 }, 68 VMSTATE_END_OF_LIST() 69 } 70 }; 71 72 static bool iwmmxt_needed(void *opaque) 73 { 74 ARMCPU *cpu = opaque; 75 CPUARMState *env = &cpu->env; 76 77 return arm_feature(env, ARM_FEATURE_IWMMXT); 78 } 79 80 static const VMStateDescription vmstate_iwmmxt = { 81 .name = "cpu/iwmmxt", 82 .version_id = 1, 83 .minimum_version_id = 1, 84 .needed = iwmmxt_needed, 85 .fields = (VMStateField[]) { 86 VMSTATE_UINT64_ARRAY(env.iwmmxt.regs, ARMCPU, 16), 87 VMSTATE_UINT32_ARRAY(env.iwmmxt.cregs, ARMCPU, 16), 88 VMSTATE_END_OF_LIST() 89 } 90 }; 91 92 static bool m_needed(void *opaque) 93 { 94 ARMCPU *cpu = opaque; 95 CPUARMState *env = &cpu->env; 96 97 return arm_feature(env, ARM_FEATURE_M); 98 } 99 100 static const VMStateDescription vmstate_m_faultmask_primask = { 101 .name = "cpu/m/faultmask-primask", 102 .version_id = 1, 103 .minimum_version_id = 1, 104 .fields = (VMStateField[]) { 105 VMSTATE_UINT32(env.v7m.faultmask, ARMCPU), 106 VMSTATE_UINT32(env.v7m.primask[M_REG_NS], ARMCPU), 107 VMSTATE_END_OF_LIST() 108 } 109 }; 110 111 static const VMStateDescription vmstate_m = { 112 .name = "cpu/m", 113 .version_id = 4, 114 .minimum_version_id = 4, 115 .needed = m_needed, 116 .fields = (VMStateField[]) { 117 VMSTATE_UINT32(env.v7m.vecbase, ARMCPU), 118 VMSTATE_UINT32(env.v7m.basepri[M_REG_NS], ARMCPU), 119 VMSTATE_UINT32(env.v7m.control, ARMCPU), 120 VMSTATE_UINT32(env.v7m.ccr, ARMCPU), 121 VMSTATE_UINT32(env.v7m.cfsr, ARMCPU), 122 VMSTATE_UINT32(env.v7m.hfsr, ARMCPU), 123 VMSTATE_UINT32(env.v7m.dfsr, ARMCPU), 124 VMSTATE_UINT32(env.v7m.mmfar, ARMCPU), 125 VMSTATE_UINT32(env.v7m.bfar, ARMCPU), 126 VMSTATE_UINT32(env.v7m.mpu_ctrl, ARMCPU), 127 VMSTATE_INT32(env.v7m.exception, ARMCPU), 128 VMSTATE_END_OF_LIST() 129 }, 130 .subsections = (const VMStateDescription*[]) { 131 &vmstate_m_faultmask_primask, 132 NULL 133 } 134 }; 135 136 static bool thumb2ee_needed(void *opaque) 137 { 138 ARMCPU *cpu = opaque; 139 CPUARMState *env = &cpu->env; 140 141 return arm_feature(env, ARM_FEATURE_THUMB2EE); 142 } 143 144 static const VMStateDescription vmstate_thumb2ee = { 145 .name = "cpu/thumb2ee", 146 .version_id = 1, 147 .minimum_version_id = 1, 148 .needed = thumb2ee_needed, 149 .fields = (VMStateField[]) { 150 VMSTATE_UINT32(env.teecr, ARMCPU), 151 VMSTATE_UINT32(env.teehbr, ARMCPU), 152 VMSTATE_END_OF_LIST() 153 } 154 }; 155 156 static bool pmsav7_needed(void *opaque) 157 { 158 ARMCPU *cpu = opaque; 159 CPUARMState *env = &cpu->env; 160 161 return arm_feature(env, ARM_FEATURE_PMSA) && 162 arm_feature(env, ARM_FEATURE_V7) && 163 !arm_feature(env, ARM_FEATURE_V8); 164 } 165 166 static bool pmsav7_rgnr_vmstate_validate(void *opaque, int version_id) 167 { 168 ARMCPU *cpu = opaque; 169 170 return cpu->env.pmsav7.rnr < cpu->pmsav7_dregion; 171 } 172 173 static const VMStateDescription vmstate_pmsav7 = { 174 .name = "cpu/pmsav7", 175 .version_id = 1, 176 .minimum_version_id = 1, 177 .needed = pmsav7_needed, 178 .fields = (VMStateField[]) { 179 VMSTATE_VARRAY_UINT32(env.pmsav7.drbar, ARMCPU, pmsav7_dregion, 0, 180 vmstate_info_uint32, uint32_t), 181 VMSTATE_VARRAY_UINT32(env.pmsav7.drsr, ARMCPU, pmsav7_dregion, 0, 182 vmstate_info_uint32, uint32_t), 183 VMSTATE_VARRAY_UINT32(env.pmsav7.dracr, ARMCPU, pmsav7_dregion, 0, 184 vmstate_info_uint32, uint32_t), 185 VMSTATE_VALIDATE("rgnr is valid", pmsav7_rgnr_vmstate_validate), 186 VMSTATE_END_OF_LIST() 187 } 188 }; 189 190 static bool pmsav7_rnr_needed(void *opaque) 191 { 192 ARMCPU *cpu = opaque; 193 CPUARMState *env = &cpu->env; 194 195 /* For R profile cores pmsav7.rnr is migrated via the cpreg 196 * "RGNR" definition in helper.h. For M profile we have to 197 * migrate it separately. 198 */ 199 return arm_feature(env, ARM_FEATURE_M); 200 } 201 202 static const VMStateDescription vmstate_pmsav7_rnr = { 203 .name = "cpu/pmsav7-rnr", 204 .version_id = 1, 205 .minimum_version_id = 1, 206 .needed = pmsav7_rnr_needed, 207 .fields = (VMStateField[]) { 208 VMSTATE_UINT32(env.pmsav7.rnr, ARMCPU), 209 VMSTATE_END_OF_LIST() 210 } 211 }; 212 213 static bool pmsav8_needed(void *opaque) 214 { 215 ARMCPU *cpu = opaque; 216 CPUARMState *env = &cpu->env; 217 218 return arm_feature(env, ARM_FEATURE_PMSA) && 219 arm_feature(env, ARM_FEATURE_V8); 220 } 221 222 static const VMStateDescription vmstate_pmsav8 = { 223 .name = "cpu/pmsav8", 224 .version_id = 1, 225 .minimum_version_id = 1, 226 .needed = pmsav8_needed, 227 .fields = (VMStateField[]) { 228 VMSTATE_VARRAY_UINT32(env.pmsav8.rbar, ARMCPU, pmsav7_dregion, 0, 229 vmstate_info_uint32, uint32_t), 230 VMSTATE_VARRAY_UINT32(env.pmsav8.rlar, ARMCPU, pmsav7_dregion, 0, 231 vmstate_info_uint32, uint32_t), 232 VMSTATE_UINT32(env.pmsav8.mair0, ARMCPU), 233 VMSTATE_UINT32(env.pmsav8.mair1, ARMCPU), 234 VMSTATE_END_OF_LIST() 235 } 236 }; 237 238 static bool m_security_needed(void *opaque) 239 { 240 ARMCPU *cpu = opaque; 241 CPUARMState *env = &cpu->env; 242 243 return arm_feature(env, ARM_FEATURE_M_SECURITY); 244 } 245 246 static const VMStateDescription vmstate_m_security = { 247 .name = "cpu/m-security", 248 .version_id = 1, 249 .minimum_version_id = 1, 250 .needed = m_security_needed, 251 .fields = (VMStateField[]) { 252 VMSTATE_UINT32(env.v7m.secure, ARMCPU), 253 VMSTATE_UINT32(env.v7m.basepri[M_REG_S], ARMCPU), 254 VMSTATE_UINT32(env.v7m.primask[M_REG_S], ARMCPU), 255 VMSTATE_END_OF_LIST() 256 } 257 }; 258 259 static int get_cpsr(QEMUFile *f, void *opaque, size_t size, 260 VMStateField *field) 261 { 262 ARMCPU *cpu = opaque; 263 CPUARMState *env = &cpu->env; 264 uint32_t val = qemu_get_be32(f); 265 266 if (arm_feature(env, ARM_FEATURE_M)) { 267 if (val & XPSR_EXCP) { 268 /* This is a CPSR format value from an older QEMU. (We can tell 269 * because values transferred in XPSR format always have zero 270 * for the EXCP field, and CPSR format will always have bit 4 271 * set in CPSR_M.) Rearrange it into XPSR format. The significant 272 * differences are that the T bit is not in the same place, the 273 * primask/faultmask info may be in the CPSR I and F bits, and 274 * we do not want the mode bits. 275 * We know that this cleanup happened before v8M, so there 276 * is no complication with banked primask/faultmask. 277 */ 278 uint32_t newval = val; 279 280 assert(!arm_feature(env, ARM_FEATURE_M_SECURITY)); 281 282 newval &= (CPSR_NZCV | CPSR_Q | CPSR_IT | CPSR_GE); 283 if (val & CPSR_T) { 284 newval |= XPSR_T; 285 } 286 /* If the I or F bits are set then this is a migration from 287 * an old QEMU which still stored the M profile FAULTMASK 288 * and PRIMASK in env->daif. For a new QEMU, the data is 289 * transferred using the vmstate_m_faultmask_primask subsection. 290 */ 291 if (val & CPSR_F) { 292 env->v7m.faultmask = 1; 293 } 294 if (val & CPSR_I) { 295 env->v7m.primask[M_REG_NS] = 1; 296 } 297 val = newval; 298 } 299 /* Ignore the low bits, they are handled by vmstate_m. */ 300 xpsr_write(env, val, ~XPSR_EXCP); 301 return 0; 302 } 303 304 env->aarch64 = ((val & PSTATE_nRW) == 0); 305 306 if (is_a64(env)) { 307 pstate_write(env, val); 308 return 0; 309 } 310 311 cpsr_write(env, val, 0xffffffff, CPSRWriteRaw); 312 return 0; 313 } 314 315 static int put_cpsr(QEMUFile *f, void *opaque, size_t size, 316 VMStateField *field, QJSON *vmdesc) 317 { 318 ARMCPU *cpu = opaque; 319 CPUARMState *env = &cpu->env; 320 uint32_t val; 321 322 if (arm_feature(env, ARM_FEATURE_M)) { 323 /* The low 9 bits are v7m.exception, which is handled by vmstate_m. */ 324 val = xpsr_read(env) & ~XPSR_EXCP; 325 } else if (is_a64(env)) { 326 val = pstate_read(env); 327 } else { 328 val = cpsr_read(env); 329 } 330 331 qemu_put_be32(f, val); 332 return 0; 333 } 334 335 static const VMStateInfo vmstate_cpsr = { 336 .name = "cpsr", 337 .get = get_cpsr, 338 .put = put_cpsr, 339 }; 340 341 static int get_power(QEMUFile *f, void *opaque, size_t size, 342 VMStateField *field) 343 { 344 ARMCPU *cpu = opaque; 345 bool powered_off = qemu_get_byte(f); 346 cpu->power_state = powered_off ? PSCI_OFF : PSCI_ON; 347 return 0; 348 } 349 350 static int put_power(QEMUFile *f, void *opaque, size_t size, 351 VMStateField *field, QJSON *vmdesc) 352 { 353 ARMCPU *cpu = opaque; 354 355 /* Migration should never happen while we transition power states */ 356 357 if (cpu->power_state == PSCI_ON || 358 cpu->power_state == PSCI_OFF) { 359 bool powered_off = (cpu->power_state == PSCI_OFF) ? true : false; 360 qemu_put_byte(f, powered_off); 361 return 0; 362 } else { 363 return 1; 364 } 365 } 366 367 static const VMStateInfo vmstate_powered_off = { 368 .name = "powered_off", 369 .get = get_power, 370 .put = put_power, 371 }; 372 373 static void cpu_pre_save(void *opaque) 374 { 375 ARMCPU *cpu = opaque; 376 377 if (kvm_enabled()) { 378 if (!write_kvmstate_to_list(cpu)) { 379 /* This should never fail */ 380 abort(); 381 } 382 } else { 383 if (!write_cpustate_to_list(cpu)) { 384 /* This should never fail. */ 385 abort(); 386 } 387 } 388 389 cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len; 390 memcpy(cpu->cpreg_vmstate_indexes, cpu->cpreg_indexes, 391 cpu->cpreg_array_len * sizeof(uint64_t)); 392 memcpy(cpu->cpreg_vmstate_values, cpu->cpreg_values, 393 cpu->cpreg_array_len * sizeof(uint64_t)); 394 } 395 396 static int cpu_post_load(void *opaque, int version_id) 397 { 398 ARMCPU *cpu = opaque; 399 int i, v; 400 401 /* Update the values list from the incoming migration data. 402 * Anything in the incoming data which we don't know about is 403 * a migration failure; anything we know about but the incoming 404 * data doesn't specify retains its current (reset) value. 405 * The indexes list remains untouched -- we only inspect the 406 * incoming migration index list so we can match the values array 407 * entries with the right slots in our own values array. 408 */ 409 410 for (i = 0, v = 0; i < cpu->cpreg_array_len 411 && v < cpu->cpreg_vmstate_array_len; i++) { 412 if (cpu->cpreg_vmstate_indexes[v] > cpu->cpreg_indexes[i]) { 413 /* register in our list but not incoming : skip it */ 414 continue; 415 } 416 if (cpu->cpreg_vmstate_indexes[v] < cpu->cpreg_indexes[i]) { 417 /* register in their list but not ours: fail migration */ 418 return -1; 419 } 420 /* matching register, copy the value over */ 421 cpu->cpreg_values[i] = cpu->cpreg_vmstate_values[v]; 422 v++; 423 } 424 425 if (kvm_enabled()) { 426 if (!write_list_to_kvmstate(cpu, KVM_PUT_FULL_STATE)) { 427 return -1; 428 } 429 /* Note that it's OK for the TCG side not to know about 430 * every register in the list; KVM is authoritative if 431 * we're using it. 432 */ 433 write_list_to_cpustate(cpu); 434 } else { 435 if (!write_list_to_cpustate(cpu)) { 436 return -1; 437 } 438 } 439 440 hw_breakpoint_update_all(cpu); 441 hw_watchpoint_update_all(cpu); 442 443 return 0; 444 } 445 446 const VMStateDescription vmstate_arm_cpu = { 447 .name = "cpu", 448 .version_id = 22, 449 .minimum_version_id = 22, 450 .pre_save = cpu_pre_save, 451 .post_load = cpu_post_load, 452 .fields = (VMStateField[]) { 453 VMSTATE_UINT32_ARRAY(env.regs, ARMCPU, 16), 454 VMSTATE_UINT64_ARRAY(env.xregs, ARMCPU, 32), 455 VMSTATE_UINT64(env.pc, ARMCPU), 456 { 457 .name = "cpsr", 458 .version_id = 0, 459 .size = sizeof(uint32_t), 460 .info = &vmstate_cpsr, 461 .flags = VMS_SINGLE, 462 .offset = 0, 463 }, 464 VMSTATE_UINT32(env.spsr, ARMCPU), 465 VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 8), 466 VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 8), 467 VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 8), 468 VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5), 469 VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5), 470 VMSTATE_UINT64_ARRAY(env.elr_el, ARMCPU, 4), 471 VMSTATE_UINT64_ARRAY(env.sp_el, ARMCPU, 4), 472 /* The length-check must come before the arrays to avoid 473 * incoming data possibly overflowing the array. 474 */ 475 VMSTATE_INT32_POSITIVE_LE(cpreg_vmstate_array_len, ARMCPU), 476 VMSTATE_VARRAY_INT32(cpreg_vmstate_indexes, ARMCPU, 477 cpreg_vmstate_array_len, 478 0, vmstate_info_uint64, uint64_t), 479 VMSTATE_VARRAY_INT32(cpreg_vmstate_values, ARMCPU, 480 cpreg_vmstate_array_len, 481 0, vmstate_info_uint64, uint64_t), 482 VMSTATE_UINT64(env.exclusive_addr, ARMCPU), 483 VMSTATE_UINT64(env.exclusive_val, ARMCPU), 484 VMSTATE_UINT64(env.exclusive_high, ARMCPU), 485 VMSTATE_UINT64(env.features, ARMCPU), 486 VMSTATE_UINT32(env.exception.syndrome, ARMCPU), 487 VMSTATE_UINT32(env.exception.fsr, ARMCPU), 488 VMSTATE_UINT64(env.exception.vaddress, ARMCPU), 489 VMSTATE_TIMER_PTR(gt_timer[GTIMER_PHYS], ARMCPU), 490 VMSTATE_TIMER_PTR(gt_timer[GTIMER_VIRT], ARMCPU), 491 { 492 .name = "power_state", 493 .version_id = 0, 494 .size = sizeof(bool), 495 .info = &vmstate_powered_off, 496 .flags = VMS_SINGLE, 497 .offset = 0, 498 }, 499 VMSTATE_END_OF_LIST() 500 }, 501 .subsections = (const VMStateDescription*[]) { 502 &vmstate_vfp, 503 &vmstate_iwmmxt, 504 &vmstate_m, 505 &vmstate_thumb2ee, 506 /* pmsav7_rnr must come before pmsav7 so that we have the 507 * region number before we test it in the VMSTATE_VALIDATE 508 * in vmstate_pmsav7. 509 */ 510 &vmstate_pmsav7_rnr, 511 &vmstate_pmsav7, 512 &vmstate_pmsav8, 513 &vmstate_m_security, 514 NULL 515 } 516 }; 517