1 #include "qemu/osdep.h" 2 #include "qemu-common.h" 3 #include "cpu.h" 4 #include "hw/hw.h" 5 #include "hw/boards.h" 6 #include "qemu/error-report.h" 7 #include "sysemu/kvm.h" 8 #include "kvm_arm.h" 9 #include "internals.h" 10 #include "migration/cpu.h" 11 12 static bool vfp_needed(void *opaque) 13 { 14 ARMCPU *cpu = opaque; 15 CPUARMState *env = &cpu->env; 16 17 return arm_feature(env, ARM_FEATURE_VFP); 18 } 19 20 static int get_fpscr(QEMUFile *f, void *opaque, size_t size, 21 VMStateField *field) 22 { 23 ARMCPU *cpu = opaque; 24 CPUARMState *env = &cpu->env; 25 uint32_t val = qemu_get_be32(f); 26 27 vfp_set_fpscr(env, val); 28 return 0; 29 } 30 31 static int put_fpscr(QEMUFile *f, void *opaque, size_t size, 32 VMStateField *field, QJSON *vmdesc) 33 { 34 ARMCPU *cpu = opaque; 35 CPUARMState *env = &cpu->env; 36 37 qemu_put_be32(f, vfp_get_fpscr(env)); 38 return 0; 39 } 40 41 static const VMStateInfo vmstate_fpscr = { 42 .name = "fpscr", 43 .get = get_fpscr, 44 .put = put_fpscr, 45 }; 46 47 static const VMStateDescription vmstate_vfp = { 48 .name = "cpu/vfp", 49 .version_id = 3, 50 .minimum_version_id = 3, 51 .needed = vfp_needed, 52 .fields = (VMStateField[]) { 53 VMSTATE_FLOAT64_ARRAY(env.vfp.regs, ARMCPU, 64), 54 /* The xregs array is a little awkward because element 1 (FPSCR) 55 * requires a specific accessor, so we have to split it up in 56 * the vmstate: 57 */ 58 VMSTATE_UINT32(env.vfp.xregs[0], ARMCPU), 59 VMSTATE_UINT32_SUB_ARRAY(env.vfp.xregs, ARMCPU, 2, 14), 60 { 61 .name = "fpscr", 62 .version_id = 0, 63 .size = sizeof(uint32_t), 64 .info = &vmstate_fpscr, 65 .flags = VMS_SINGLE, 66 .offset = 0, 67 }, 68 VMSTATE_END_OF_LIST() 69 } 70 }; 71 72 static bool iwmmxt_needed(void *opaque) 73 { 74 ARMCPU *cpu = opaque; 75 CPUARMState *env = &cpu->env; 76 77 return arm_feature(env, ARM_FEATURE_IWMMXT); 78 } 79 80 static const VMStateDescription vmstate_iwmmxt = { 81 .name = "cpu/iwmmxt", 82 .version_id = 1, 83 .minimum_version_id = 1, 84 .needed = iwmmxt_needed, 85 .fields = (VMStateField[]) { 86 VMSTATE_UINT64_ARRAY(env.iwmmxt.regs, ARMCPU, 16), 87 VMSTATE_UINT32_ARRAY(env.iwmmxt.cregs, ARMCPU, 16), 88 VMSTATE_END_OF_LIST() 89 } 90 }; 91 92 static bool m_needed(void *opaque) 93 { 94 ARMCPU *cpu = opaque; 95 CPUARMState *env = &cpu->env; 96 97 return arm_feature(env, ARM_FEATURE_M); 98 } 99 100 static const VMStateDescription vmstate_m_faultmask_primask = { 101 .name = "cpu/m/faultmask-primask", 102 .version_id = 1, 103 .minimum_version_id = 1, 104 .fields = (VMStateField[]) { 105 VMSTATE_UINT32(env.v7m.faultmask[M_REG_NS], ARMCPU), 106 VMSTATE_UINT32(env.v7m.primask[M_REG_NS], ARMCPU), 107 VMSTATE_END_OF_LIST() 108 } 109 }; 110 111 static const VMStateDescription vmstate_m = { 112 .name = "cpu/m", 113 .version_id = 4, 114 .minimum_version_id = 4, 115 .needed = m_needed, 116 .fields = (VMStateField[]) { 117 VMSTATE_UINT32(env.v7m.vecbase[M_REG_NS], ARMCPU), 118 VMSTATE_UINT32(env.v7m.basepri[M_REG_NS], ARMCPU), 119 VMSTATE_UINT32(env.v7m.control[M_REG_NS], ARMCPU), 120 VMSTATE_UINT32(env.v7m.ccr, ARMCPU), 121 VMSTATE_UINT32(env.v7m.cfsr, ARMCPU), 122 VMSTATE_UINT32(env.v7m.hfsr, ARMCPU), 123 VMSTATE_UINT32(env.v7m.dfsr, ARMCPU), 124 VMSTATE_UINT32(env.v7m.mmfar, ARMCPU), 125 VMSTATE_UINT32(env.v7m.bfar, ARMCPU), 126 VMSTATE_UINT32(env.v7m.mpu_ctrl, ARMCPU), 127 VMSTATE_INT32(env.v7m.exception, ARMCPU), 128 VMSTATE_END_OF_LIST() 129 }, 130 .subsections = (const VMStateDescription*[]) { 131 &vmstate_m_faultmask_primask, 132 NULL 133 } 134 }; 135 136 static bool thumb2ee_needed(void *opaque) 137 { 138 ARMCPU *cpu = opaque; 139 CPUARMState *env = &cpu->env; 140 141 return arm_feature(env, ARM_FEATURE_THUMB2EE); 142 } 143 144 static const VMStateDescription vmstate_thumb2ee = { 145 .name = "cpu/thumb2ee", 146 .version_id = 1, 147 .minimum_version_id = 1, 148 .needed = thumb2ee_needed, 149 .fields = (VMStateField[]) { 150 VMSTATE_UINT32(env.teecr, ARMCPU), 151 VMSTATE_UINT32(env.teehbr, ARMCPU), 152 VMSTATE_END_OF_LIST() 153 } 154 }; 155 156 static bool pmsav7_needed(void *opaque) 157 { 158 ARMCPU *cpu = opaque; 159 CPUARMState *env = &cpu->env; 160 161 return arm_feature(env, ARM_FEATURE_PMSA) && 162 arm_feature(env, ARM_FEATURE_V7) && 163 !arm_feature(env, ARM_FEATURE_V8); 164 } 165 166 static bool pmsav7_rgnr_vmstate_validate(void *opaque, int version_id) 167 { 168 ARMCPU *cpu = opaque; 169 170 return cpu->env.pmsav7.rnr < cpu->pmsav7_dregion; 171 } 172 173 static const VMStateDescription vmstate_pmsav7 = { 174 .name = "cpu/pmsav7", 175 .version_id = 1, 176 .minimum_version_id = 1, 177 .needed = pmsav7_needed, 178 .fields = (VMStateField[]) { 179 VMSTATE_VARRAY_UINT32(env.pmsav7.drbar, ARMCPU, pmsav7_dregion, 0, 180 vmstate_info_uint32, uint32_t), 181 VMSTATE_VARRAY_UINT32(env.pmsav7.drsr, ARMCPU, pmsav7_dregion, 0, 182 vmstate_info_uint32, uint32_t), 183 VMSTATE_VARRAY_UINT32(env.pmsav7.dracr, ARMCPU, pmsav7_dregion, 0, 184 vmstate_info_uint32, uint32_t), 185 VMSTATE_VALIDATE("rgnr is valid", pmsav7_rgnr_vmstate_validate), 186 VMSTATE_END_OF_LIST() 187 } 188 }; 189 190 static bool pmsav7_rnr_needed(void *opaque) 191 { 192 ARMCPU *cpu = opaque; 193 CPUARMState *env = &cpu->env; 194 195 /* For R profile cores pmsav7.rnr is migrated via the cpreg 196 * "RGNR" definition in helper.h. For M profile we have to 197 * migrate it separately. 198 */ 199 return arm_feature(env, ARM_FEATURE_M); 200 } 201 202 static const VMStateDescription vmstate_pmsav7_rnr = { 203 .name = "cpu/pmsav7-rnr", 204 .version_id = 1, 205 .minimum_version_id = 1, 206 .needed = pmsav7_rnr_needed, 207 .fields = (VMStateField[]) { 208 VMSTATE_UINT32(env.pmsav7.rnr, ARMCPU), 209 VMSTATE_END_OF_LIST() 210 } 211 }; 212 213 static bool pmsav8_needed(void *opaque) 214 { 215 ARMCPU *cpu = opaque; 216 CPUARMState *env = &cpu->env; 217 218 return arm_feature(env, ARM_FEATURE_PMSA) && 219 arm_feature(env, ARM_FEATURE_V8); 220 } 221 222 static const VMStateDescription vmstate_pmsav8 = { 223 .name = "cpu/pmsav8", 224 .version_id = 1, 225 .minimum_version_id = 1, 226 .needed = pmsav8_needed, 227 .fields = (VMStateField[]) { 228 VMSTATE_VARRAY_UINT32(env.pmsav8.rbar[M_REG_NS], ARMCPU, pmsav7_dregion, 229 0, vmstate_info_uint32, uint32_t), 230 VMSTATE_VARRAY_UINT32(env.pmsav8.rlar[M_REG_NS], ARMCPU, pmsav7_dregion, 231 0, vmstate_info_uint32, uint32_t), 232 VMSTATE_UINT32(env.pmsav8.mair0[M_REG_NS], ARMCPU), 233 VMSTATE_UINT32(env.pmsav8.mair1[M_REG_NS], ARMCPU), 234 VMSTATE_END_OF_LIST() 235 } 236 }; 237 238 static bool m_security_needed(void *opaque) 239 { 240 ARMCPU *cpu = opaque; 241 CPUARMState *env = &cpu->env; 242 243 return arm_feature(env, ARM_FEATURE_M_SECURITY); 244 } 245 246 static const VMStateDescription vmstate_m_security = { 247 .name = "cpu/m-security", 248 .version_id = 1, 249 .minimum_version_id = 1, 250 .needed = m_security_needed, 251 .fields = (VMStateField[]) { 252 VMSTATE_UINT32(env.v7m.secure, ARMCPU), 253 VMSTATE_UINT32(env.v7m.basepri[M_REG_S], ARMCPU), 254 VMSTATE_UINT32(env.v7m.primask[M_REG_S], ARMCPU), 255 VMSTATE_UINT32(env.v7m.faultmask[M_REG_S], ARMCPU), 256 VMSTATE_UINT32(env.v7m.control[M_REG_S], ARMCPU), 257 VMSTATE_UINT32(env.v7m.vecbase[M_REG_S], ARMCPU), 258 VMSTATE_UINT32(env.pmsav8.mair0[M_REG_S], ARMCPU), 259 VMSTATE_UINT32(env.pmsav8.mair1[M_REG_S], ARMCPU), 260 VMSTATE_VARRAY_UINT32(env.pmsav8.rbar[M_REG_S], ARMCPU, pmsav7_dregion, 261 0, vmstate_info_uint32, uint32_t), 262 VMSTATE_VARRAY_UINT32(env.pmsav8.rlar[M_REG_S], ARMCPU, pmsav7_dregion, 263 0, vmstate_info_uint32, uint32_t), 264 VMSTATE_END_OF_LIST() 265 } 266 }; 267 268 static int get_cpsr(QEMUFile *f, void *opaque, size_t size, 269 VMStateField *field) 270 { 271 ARMCPU *cpu = opaque; 272 CPUARMState *env = &cpu->env; 273 uint32_t val = qemu_get_be32(f); 274 275 if (arm_feature(env, ARM_FEATURE_M)) { 276 if (val & XPSR_EXCP) { 277 /* This is a CPSR format value from an older QEMU. (We can tell 278 * because values transferred in XPSR format always have zero 279 * for the EXCP field, and CPSR format will always have bit 4 280 * set in CPSR_M.) Rearrange it into XPSR format. The significant 281 * differences are that the T bit is not in the same place, the 282 * primask/faultmask info may be in the CPSR I and F bits, and 283 * we do not want the mode bits. 284 * We know that this cleanup happened before v8M, so there 285 * is no complication with banked primask/faultmask. 286 */ 287 uint32_t newval = val; 288 289 assert(!arm_feature(env, ARM_FEATURE_M_SECURITY)); 290 291 newval &= (CPSR_NZCV | CPSR_Q | CPSR_IT | CPSR_GE); 292 if (val & CPSR_T) { 293 newval |= XPSR_T; 294 } 295 /* If the I or F bits are set then this is a migration from 296 * an old QEMU which still stored the M profile FAULTMASK 297 * and PRIMASK in env->daif. For a new QEMU, the data is 298 * transferred using the vmstate_m_faultmask_primask subsection. 299 */ 300 if (val & CPSR_F) { 301 env->v7m.faultmask[M_REG_NS] = 1; 302 } 303 if (val & CPSR_I) { 304 env->v7m.primask[M_REG_NS] = 1; 305 } 306 val = newval; 307 } 308 /* Ignore the low bits, they are handled by vmstate_m. */ 309 xpsr_write(env, val, ~XPSR_EXCP); 310 return 0; 311 } 312 313 env->aarch64 = ((val & PSTATE_nRW) == 0); 314 315 if (is_a64(env)) { 316 pstate_write(env, val); 317 return 0; 318 } 319 320 cpsr_write(env, val, 0xffffffff, CPSRWriteRaw); 321 return 0; 322 } 323 324 static int put_cpsr(QEMUFile *f, void *opaque, size_t size, 325 VMStateField *field, QJSON *vmdesc) 326 { 327 ARMCPU *cpu = opaque; 328 CPUARMState *env = &cpu->env; 329 uint32_t val; 330 331 if (arm_feature(env, ARM_FEATURE_M)) { 332 /* The low 9 bits are v7m.exception, which is handled by vmstate_m. */ 333 val = xpsr_read(env) & ~XPSR_EXCP; 334 } else if (is_a64(env)) { 335 val = pstate_read(env); 336 } else { 337 val = cpsr_read(env); 338 } 339 340 qemu_put_be32(f, val); 341 return 0; 342 } 343 344 static const VMStateInfo vmstate_cpsr = { 345 .name = "cpsr", 346 .get = get_cpsr, 347 .put = put_cpsr, 348 }; 349 350 static int get_power(QEMUFile *f, void *opaque, size_t size, 351 VMStateField *field) 352 { 353 ARMCPU *cpu = opaque; 354 bool powered_off = qemu_get_byte(f); 355 cpu->power_state = powered_off ? PSCI_OFF : PSCI_ON; 356 return 0; 357 } 358 359 static int put_power(QEMUFile *f, void *opaque, size_t size, 360 VMStateField *field, QJSON *vmdesc) 361 { 362 ARMCPU *cpu = opaque; 363 364 /* Migration should never happen while we transition power states */ 365 366 if (cpu->power_state == PSCI_ON || 367 cpu->power_state == PSCI_OFF) { 368 bool powered_off = (cpu->power_state == PSCI_OFF) ? true : false; 369 qemu_put_byte(f, powered_off); 370 return 0; 371 } else { 372 return 1; 373 } 374 } 375 376 static const VMStateInfo vmstate_powered_off = { 377 .name = "powered_off", 378 .get = get_power, 379 .put = put_power, 380 }; 381 382 static void cpu_pre_save(void *opaque) 383 { 384 ARMCPU *cpu = opaque; 385 386 if (kvm_enabled()) { 387 if (!write_kvmstate_to_list(cpu)) { 388 /* This should never fail */ 389 abort(); 390 } 391 } else { 392 if (!write_cpustate_to_list(cpu)) { 393 /* This should never fail. */ 394 abort(); 395 } 396 } 397 398 cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len; 399 memcpy(cpu->cpreg_vmstate_indexes, cpu->cpreg_indexes, 400 cpu->cpreg_array_len * sizeof(uint64_t)); 401 memcpy(cpu->cpreg_vmstate_values, cpu->cpreg_values, 402 cpu->cpreg_array_len * sizeof(uint64_t)); 403 } 404 405 static int cpu_post_load(void *opaque, int version_id) 406 { 407 ARMCPU *cpu = opaque; 408 int i, v; 409 410 /* Update the values list from the incoming migration data. 411 * Anything in the incoming data which we don't know about is 412 * a migration failure; anything we know about but the incoming 413 * data doesn't specify retains its current (reset) value. 414 * The indexes list remains untouched -- we only inspect the 415 * incoming migration index list so we can match the values array 416 * entries with the right slots in our own values array. 417 */ 418 419 for (i = 0, v = 0; i < cpu->cpreg_array_len 420 && v < cpu->cpreg_vmstate_array_len; i++) { 421 if (cpu->cpreg_vmstate_indexes[v] > cpu->cpreg_indexes[i]) { 422 /* register in our list but not incoming : skip it */ 423 continue; 424 } 425 if (cpu->cpreg_vmstate_indexes[v] < cpu->cpreg_indexes[i]) { 426 /* register in their list but not ours: fail migration */ 427 return -1; 428 } 429 /* matching register, copy the value over */ 430 cpu->cpreg_values[i] = cpu->cpreg_vmstate_values[v]; 431 v++; 432 } 433 434 if (kvm_enabled()) { 435 if (!write_list_to_kvmstate(cpu, KVM_PUT_FULL_STATE)) { 436 return -1; 437 } 438 /* Note that it's OK for the TCG side not to know about 439 * every register in the list; KVM is authoritative if 440 * we're using it. 441 */ 442 write_list_to_cpustate(cpu); 443 } else { 444 if (!write_list_to_cpustate(cpu)) { 445 return -1; 446 } 447 } 448 449 hw_breakpoint_update_all(cpu); 450 hw_watchpoint_update_all(cpu); 451 452 return 0; 453 } 454 455 const VMStateDescription vmstate_arm_cpu = { 456 .name = "cpu", 457 .version_id = 22, 458 .minimum_version_id = 22, 459 .pre_save = cpu_pre_save, 460 .post_load = cpu_post_load, 461 .fields = (VMStateField[]) { 462 VMSTATE_UINT32_ARRAY(env.regs, ARMCPU, 16), 463 VMSTATE_UINT64_ARRAY(env.xregs, ARMCPU, 32), 464 VMSTATE_UINT64(env.pc, ARMCPU), 465 { 466 .name = "cpsr", 467 .version_id = 0, 468 .size = sizeof(uint32_t), 469 .info = &vmstate_cpsr, 470 .flags = VMS_SINGLE, 471 .offset = 0, 472 }, 473 VMSTATE_UINT32(env.spsr, ARMCPU), 474 VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 8), 475 VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 8), 476 VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 8), 477 VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5), 478 VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5), 479 VMSTATE_UINT64_ARRAY(env.elr_el, ARMCPU, 4), 480 VMSTATE_UINT64_ARRAY(env.sp_el, ARMCPU, 4), 481 /* The length-check must come before the arrays to avoid 482 * incoming data possibly overflowing the array. 483 */ 484 VMSTATE_INT32_POSITIVE_LE(cpreg_vmstate_array_len, ARMCPU), 485 VMSTATE_VARRAY_INT32(cpreg_vmstate_indexes, ARMCPU, 486 cpreg_vmstate_array_len, 487 0, vmstate_info_uint64, uint64_t), 488 VMSTATE_VARRAY_INT32(cpreg_vmstate_values, ARMCPU, 489 cpreg_vmstate_array_len, 490 0, vmstate_info_uint64, uint64_t), 491 VMSTATE_UINT64(env.exclusive_addr, ARMCPU), 492 VMSTATE_UINT64(env.exclusive_val, ARMCPU), 493 VMSTATE_UINT64(env.exclusive_high, ARMCPU), 494 VMSTATE_UINT64(env.features, ARMCPU), 495 VMSTATE_UINT32(env.exception.syndrome, ARMCPU), 496 VMSTATE_UINT32(env.exception.fsr, ARMCPU), 497 VMSTATE_UINT64(env.exception.vaddress, ARMCPU), 498 VMSTATE_TIMER_PTR(gt_timer[GTIMER_PHYS], ARMCPU), 499 VMSTATE_TIMER_PTR(gt_timer[GTIMER_VIRT], ARMCPU), 500 { 501 .name = "power_state", 502 .version_id = 0, 503 .size = sizeof(bool), 504 .info = &vmstate_powered_off, 505 .flags = VMS_SINGLE, 506 .offset = 0, 507 }, 508 VMSTATE_END_OF_LIST() 509 }, 510 .subsections = (const VMStateDescription*[]) { 511 &vmstate_vfp, 512 &vmstate_iwmmxt, 513 &vmstate_m, 514 &vmstate_thumb2ee, 515 /* pmsav7_rnr must come before pmsav7 so that we have the 516 * region number before we test it in the VMSTATE_VALIDATE 517 * in vmstate_pmsav7. 518 */ 519 &vmstate_pmsav7_rnr, 520 &vmstate_pmsav7, 521 &vmstate_pmsav8, 522 &vmstate_m_security, 523 NULL 524 } 525 }; 526