1 #include "qemu/osdep.h" 2 #include "qemu-common.h" 3 #include "cpu.h" 4 #include "hw/hw.h" 5 #include "hw/boards.h" 6 #include "qemu/error-report.h" 7 #include "sysemu/kvm.h" 8 #include "kvm_arm.h" 9 #include "internals.h" 10 #include "migration/cpu.h" 11 12 static bool vfp_needed(void *opaque) 13 { 14 ARMCPU *cpu = opaque; 15 CPUARMState *env = &cpu->env; 16 17 return arm_feature(env, ARM_FEATURE_VFP); 18 } 19 20 static int get_fpscr(QEMUFile *f, void *opaque, size_t size, 21 const VMStateField *field) 22 { 23 ARMCPU *cpu = opaque; 24 CPUARMState *env = &cpu->env; 25 uint32_t val = qemu_get_be32(f); 26 27 vfp_set_fpscr(env, val); 28 return 0; 29 } 30 31 static int put_fpscr(QEMUFile *f, void *opaque, size_t size, 32 const VMStateField *field, QJSON *vmdesc) 33 { 34 ARMCPU *cpu = opaque; 35 CPUARMState *env = &cpu->env; 36 37 qemu_put_be32(f, vfp_get_fpscr(env)); 38 return 0; 39 } 40 41 static const VMStateInfo vmstate_fpscr = { 42 .name = "fpscr", 43 .get = get_fpscr, 44 .put = put_fpscr, 45 }; 46 47 static const VMStateDescription vmstate_vfp = { 48 .name = "cpu/vfp", 49 .version_id = 3, 50 .minimum_version_id = 3, 51 .needed = vfp_needed, 52 .fields = (VMStateField[]) { 53 /* For compatibility, store Qn out of Zn here. */ 54 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[0].d, ARMCPU, 0, 2), 55 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[1].d, ARMCPU, 0, 2), 56 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[2].d, ARMCPU, 0, 2), 57 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[3].d, ARMCPU, 0, 2), 58 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[4].d, ARMCPU, 0, 2), 59 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[5].d, ARMCPU, 0, 2), 60 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[6].d, ARMCPU, 0, 2), 61 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[7].d, ARMCPU, 0, 2), 62 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[8].d, ARMCPU, 0, 2), 63 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[9].d, ARMCPU, 0, 2), 64 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[10].d, ARMCPU, 0, 2), 65 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[11].d, ARMCPU, 0, 2), 66 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[12].d, ARMCPU, 0, 2), 67 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[13].d, ARMCPU, 0, 2), 68 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[14].d, ARMCPU, 0, 2), 69 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[15].d, ARMCPU, 0, 2), 70 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[16].d, ARMCPU, 0, 2), 71 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[17].d, ARMCPU, 0, 2), 72 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[18].d, ARMCPU, 0, 2), 73 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[19].d, ARMCPU, 0, 2), 74 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[20].d, ARMCPU, 0, 2), 75 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[21].d, ARMCPU, 0, 2), 76 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[22].d, ARMCPU, 0, 2), 77 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[23].d, ARMCPU, 0, 2), 78 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[24].d, ARMCPU, 0, 2), 79 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[25].d, ARMCPU, 0, 2), 80 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[26].d, ARMCPU, 0, 2), 81 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[27].d, ARMCPU, 0, 2), 82 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[28].d, ARMCPU, 0, 2), 83 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[29].d, ARMCPU, 0, 2), 84 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[30].d, ARMCPU, 0, 2), 85 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[31].d, ARMCPU, 0, 2), 86 87 /* The xregs array is a little awkward because element 1 (FPSCR) 88 * requires a specific accessor, so we have to split it up in 89 * the vmstate: 90 */ 91 VMSTATE_UINT32(env.vfp.xregs[0], ARMCPU), 92 VMSTATE_UINT32_SUB_ARRAY(env.vfp.xregs, ARMCPU, 2, 14), 93 { 94 .name = "fpscr", 95 .version_id = 0, 96 .size = sizeof(uint32_t), 97 .info = &vmstate_fpscr, 98 .flags = VMS_SINGLE, 99 .offset = 0, 100 }, 101 VMSTATE_END_OF_LIST() 102 } 103 }; 104 105 static bool iwmmxt_needed(void *opaque) 106 { 107 ARMCPU *cpu = opaque; 108 CPUARMState *env = &cpu->env; 109 110 return arm_feature(env, ARM_FEATURE_IWMMXT); 111 } 112 113 static const VMStateDescription vmstate_iwmmxt = { 114 .name = "cpu/iwmmxt", 115 .version_id = 1, 116 .minimum_version_id = 1, 117 .needed = iwmmxt_needed, 118 .fields = (VMStateField[]) { 119 VMSTATE_UINT64_ARRAY(env.iwmmxt.regs, ARMCPU, 16), 120 VMSTATE_UINT32_ARRAY(env.iwmmxt.cregs, ARMCPU, 16), 121 VMSTATE_END_OF_LIST() 122 } 123 }; 124 125 #ifdef TARGET_AARCH64 126 /* The expression ARM_MAX_VQ - 2 is 0 for pure AArch32 build, 127 * and ARMPredicateReg is actively empty. This triggers errors 128 * in the expansion of the VMSTATE macros. 129 */ 130 131 static bool sve_needed(void *opaque) 132 { 133 ARMCPU *cpu = opaque; 134 135 return cpu_isar_feature(aa64_sve, cpu); 136 } 137 138 /* The first two words of each Zreg is stored in VFP state. */ 139 static const VMStateDescription vmstate_zreg_hi_reg = { 140 .name = "cpu/sve/zreg_hi", 141 .version_id = 1, 142 .minimum_version_id = 1, 143 .fields = (VMStateField[]) { 144 VMSTATE_UINT64_SUB_ARRAY(d, ARMVectorReg, 2, ARM_MAX_VQ - 2), 145 VMSTATE_END_OF_LIST() 146 } 147 }; 148 149 static const VMStateDescription vmstate_preg_reg = { 150 .name = "cpu/sve/preg", 151 .version_id = 1, 152 .minimum_version_id = 1, 153 .fields = (VMStateField[]) { 154 VMSTATE_UINT64_ARRAY(p, ARMPredicateReg, 2 * ARM_MAX_VQ / 8), 155 VMSTATE_END_OF_LIST() 156 } 157 }; 158 159 static const VMStateDescription vmstate_sve = { 160 .name = "cpu/sve", 161 .version_id = 1, 162 .minimum_version_id = 1, 163 .needed = sve_needed, 164 .fields = (VMStateField[]) { 165 VMSTATE_STRUCT_ARRAY(env.vfp.zregs, ARMCPU, 32, 0, 166 vmstate_zreg_hi_reg, ARMVectorReg), 167 VMSTATE_STRUCT_ARRAY(env.vfp.pregs, ARMCPU, 17, 0, 168 vmstate_preg_reg, ARMPredicateReg), 169 VMSTATE_END_OF_LIST() 170 } 171 }; 172 #endif /* AARCH64 */ 173 174 static bool serror_needed(void *opaque) 175 { 176 ARMCPU *cpu = opaque; 177 CPUARMState *env = &cpu->env; 178 179 return env->serror.pending != 0; 180 } 181 182 static const VMStateDescription vmstate_serror = { 183 .name = "cpu/serror", 184 .version_id = 1, 185 .minimum_version_id = 1, 186 .needed = serror_needed, 187 .fields = (VMStateField[]) { 188 VMSTATE_UINT8(env.serror.pending, ARMCPU), 189 VMSTATE_UINT8(env.serror.has_esr, ARMCPU), 190 VMSTATE_UINT64(env.serror.esr, ARMCPU), 191 VMSTATE_END_OF_LIST() 192 } 193 }; 194 195 static bool irq_line_state_needed(void *opaque) 196 { 197 return true; 198 } 199 200 static const VMStateDescription vmstate_irq_line_state = { 201 .name = "cpu/irq-line-state", 202 .version_id = 1, 203 .minimum_version_id = 1, 204 .needed = irq_line_state_needed, 205 .fields = (VMStateField[]) { 206 VMSTATE_UINT32(env.irq_line_state, ARMCPU), 207 VMSTATE_END_OF_LIST() 208 } 209 }; 210 211 static bool m_needed(void *opaque) 212 { 213 ARMCPU *cpu = opaque; 214 CPUARMState *env = &cpu->env; 215 216 return arm_feature(env, ARM_FEATURE_M); 217 } 218 219 static const VMStateDescription vmstate_m_faultmask_primask = { 220 .name = "cpu/m/faultmask-primask", 221 .version_id = 1, 222 .minimum_version_id = 1, 223 .needed = m_needed, 224 .fields = (VMStateField[]) { 225 VMSTATE_UINT32(env.v7m.faultmask[M_REG_NS], ARMCPU), 226 VMSTATE_UINT32(env.v7m.primask[M_REG_NS], ARMCPU), 227 VMSTATE_END_OF_LIST() 228 } 229 }; 230 231 /* CSSELR is in a subsection because we didn't implement it previously. 232 * Migration from an old implementation will leave it at zero, which 233 * is OK since the only CPUs in the old implementation make the 234 * register RAZ/WI. 235 * Since there was no version of QEMU which implemented the CSSELR for 236 * just non-secure, we transfer both banks here rather than putting 237 * the secure banked version in the m-security subsection. 238 */ 239 static bool csselr_vmstate_validate(void *opaque, int version_id) 240 { 241 ARMCPU *cpu = opaque; 242 243 return cpu->env.v7m.csselr[M_REG_NS] <= R_V7M_CSSELR_INDEX_MASK 244 && cpu->env.v7m.csselr[M_REG_S] <= R_V7M_CSSELR_INDEX_MASK; 245 } 246 247 static bool m_csselr_needed(void *opaque) 248 { 249 ARMCPU *cpu = opaque; 250 251 return !arm_v7m_csselr_razwi(cpu); 252 } 253 254 static const VMStateDescription vmstate_m_csselr = { 255 .name = "cpu/m/csselr", 256 .version_id = 1, 257 .minimum_version_id = 1, 258 .needed = m_csselr_needed, 259 .fields = (VMStateField[]) { 260 VMSTATE_UINT32_ARRAY(env.v7m.csselr, ARMCPU, M_REG_NUM_BANKS), 261 VMSTATE_VALIDATE("CSSELR is valid", csselr_vmstate_validate), 262 VMSTATE_END_OF_LIST() 263 } 264 }; 265 266 static const VMStateDescription vmstate_m_scr = { 267 .name = "cpu/m/scr", 268 .version_id = 1, 269 .minimum_version_id = 1, 270 .needed = m_needed, 271 .fields = (VMStateField[]) { 272 VMSTATE_UINT32(env.v7m.scr[M_REG_NS], ARMCPU), 273 VMSTATE_END_OF_LIST() 274 } 275 }; 276 277 static const VMStateDescription vmstate_m_other_sp = { 278 .name = "cpu/m/other-sp", 279 .version_id = 1, 280 .minimum_version_id = 1, 281 .needed = m_needed, 282 .fields = (VMStateField[]) { 283 VMSTATE_UINT32(env.v7m.other_sp, ARMCPU), 284 VMSTATE_END_OF_LIST() 285 } 286 }; 287 288 static bool m_v8m_needed(void *opaque) 289 { 290 ARMCPU *cpu = opaque; 291 CPUARMState *env = &cpu->env; 292 293 return arm_feature(env, ARM_FEATURE_M) && arm_feature(env, ARM_FEATURE_V8); 294 } 295 296 static const VMStateDescription vmstate_m_v8m = { 297 .name = "cpu/m/v8m", 298 .version_id = 1, 299 .minimum_version_id = 1, 300 .needed = m_v8m_needed, 301 .fields = (VMStateField[]) { 302 VMSTATE_UINT32_ARRAY(env.v7m.msplim, ARMCPU, M_REG_NUM_BANKS), 303 VMSTATE_UINT32_ARRAY(env.v7m.psplim, ARMCPU, M_REG_NUM_BANKS), 304 VMSTATE_END_OF_LIST() 305 } 306 }; 307 308 static const VMStateDescription vmstate_m_fp = { 309 .name = "cpu/m/fp", 310 .version_id = 1, 311 .minimum_version_id = 1, 312 .needed = vfp_needed, 313 .fields = (VMStateField[]) { 314 VMSTATE_UINT32_ARRAY(env.v7m.fpcar, ARMCPU, M_REG_NUM_BANKS), 315 VMSTATE_UINT32_ARRAY(env.v7m.fpccr, ARMCPU, M_REG_NUM_BANKS), 316 VMSTATE_UINT32_ARRAY(env.v7m.fpdscr, ARMCPU, M_REG_NUM_BANKS), 317 VMSTATE_UINT32_ARRAY(env.v7m.cpacr, ARMCPU, M_REG_NUM_BANKS), 318 VMSTATE_UINT32(env.v7m.nsacr, ARMCPU), 319 VMSTATE_END_OF_LIST() 320 } 321 }; 322 323 static const VMStateDescription vmstate_m = { 324 .name = "cpu/m", 325 .version_id = 4, 326 .minimum_version_id = 4, 327 .needed = m_needed, 328 .fields = (VMStateField[]) { 329 VMSTATE_UINT32(env.v7m.vecbase[M_REG_NS], ARMCPU), 330 VMSTATE_UINT32(env.v7m.basepri[M_REG_NS], ARMCPU), 331 VMSTATE_UINT32(env.v7m.control[M_REG_NS], ARMCPU), 332 VMSTATE_UINT32(env.v7m.ccr[M_REG_NS], ARMCPU), 333 VMSTATE_UINT32(env.v7m.cfsr[M_REG_NS], ARMCPU), 334 VMSTATE_UINT32(env.v7m.hfsr, ARMCPU), 335 VMSTATE_UINT32(env.v7m.dfsr, ARMCPU), 336 VMSTATE_UINT32(env.v7m.mmfar[M_REG_NS], ARMCPU), 337 VMSTATE_UINT32(env.v7m.bfar, ARMCPU), 338 VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_NS], ARMCPU), 339 VMSTATE_INT32(env.v7m.exception, ARMCPU), 340 VMSTATE_END_OF_LIST() 341 }, 342 .subsections = (const VMStateDescription*[]) { 343 &vmstate_m_faultmask_primask, 344 &vmstate_m_csselr, 345 &vmstate_m_scr, 346 &vmstate_m_other_sp, 347 &vmstate_m_v8m, 348 &vmstate_m_fp, 349 NULL 350 } 351 }; 352 353 static bool thumb2ee_needed(void *opaque) 354 { 355 ARMCPU *cpu = opaque; 356 CPUARMState *env = &cpu->env; 357 358 return arm_feature(env, ARM_FEATURE_THUMB2EE); 359 } 360 361 static const VMStateDescription vmstate_thumb2ee = { 362 .name = "cpu/thumb2ee", 363 .version_id = 1, 364 .minimum_version_id = 1, 365 .needed = thumb2ee_needed, 366 .fields = (VMStateField[]) { 367 VMSTATE_UINT32(env.teecr, ARMCPU), 368 VMSTATE_UINT32(env.teehbr, ARMCPU), 369 VMSTATE_END_OF_LIST() 370 } 371 }; 372 373 static bool pmsav7_needed(void *opaque) 374 { 375 ARMCPU *cpu = opaque; 376 CPUARMState *env = &cpu->env; 377 378 return arm_feature(env, ARM_FEATURE_PMSA) && 379 arm_feature(env, ARM_FEATURE_V7) && 380 !arm_feature(env, ARM_FEATURE_V8); 381 } 382 383 static bool pmsav7_rgnr_vmstate_validate(void *opaque, int version_id) 384 { 385 ARMCPU *cpu = opaque; 386 387 return cpu->env.pmsav7.rnr[M_REG_NS] < cpu->pmsav7_dregion; 388 } 389 390 static const VMStateDescription vmstate_pmsav7 = { 391 .name = "cpu/pmsav7", 392 .version_id = 1, 393 .minimum_version_id = 1, 394 .needed = pmsav7_needed, 395 .fields = (VMStateField[]) { 396 VMSTATE_VARRAY_UINT32(env.pmsav7.drbar, ARMCPU, pmsav7_dregion, 0, 397 vmstate_info_uint32, uint32_t), 398 VMSTATE_VARRAY_UINT32(env.pmsav7.drsr, ARMCPU, pmsav7_dregion, 0, 399 vmstate_info_uint32, uint32_t), 400 VMSTATE_VARRAY_UINT32(env.pmsav7.dracr, ARMCPU, pmsav7_dregion, 0, 401 vmstate_info_uint32, uint32_t), 402 VMSTATE_VALIDATE("rgnr is valid", pmsav7_rgnr_vmstate_validate), 403 VMSTATE_END_OF_LIST() 404 } 405 }; 406 407 static bool pmsav7_rnr_needed(void *opaque) 408 { 409 ARMCPU *cpu = opaque; 410 CPUARMState *env = &cpu->env; 411 412 /* For R profile cores pmsav7.rnr is migrated via the cpreg 413 * "RGNR" definition in helper.h. For M profile we have to 414 * migrate it separately. 415 */ 416 return arm_feature(env, ARM_FEATURE_M); 417 } 418 419 static const VMStateDescription vmstate_pmsav7_rnr = { 420 .name = "cpu/pmsav7-rnr", 421 .version_id = 1, 422 .minimum_version_id = 1, 423 .needed = pmsav7_rnr_needed, 424 .fields = (VMStateField[]) { 425 VMSTATE_UINT32(env.pmsav7.rnr[M_REG_NS], ARMCPU), 426 VMSTATE_END_OF_LIST() 427 } 428 }; 429 430 static bool pmsav8_needed(void *opaque) 431 { 432 ARMCPU *cpu = opaque; 433 CPUARMState *env = &cpu->env; 434 435 return arm_feature(env, ARM_FEATURE_PMSA) && 436 arm_feature(env, ARM_FEATURE_V8); 437 } 438 439 static const VMStateDescription vmstate_pmsav8 = { 440 .name = "cpu/pmsav8", 441 .version_id = 1, 442 .minimum_version_id = 1, 443 .needed = pmsav8_needed, 444 .fields = (VMStateField[]) { 445 VMSTATE_VARRAY_UINT32(env.pmsav8.rbar[M_REG_NS], ARMCPU, pmsav7_dregion, 446 0, vmstate_info_uint32, uint32_t), 447 VMSTATE_VARRAY_UINT32(env.pmsav8.rlar[M_REG_NS], ARMCPU, pmsav7_dregion, 448 0, vmstate_info_uint32, uint32_t), 449 VMSTATE_UINT32(env.pmsav8.mair0[M_REG_NS], ARMCPU), 450 VMSTATE_UINT32(env.pmsav8.mair1[M_REG_NS], ARMCPU), 451 VMSTATE_END_OF_LIST() 452 } 453 }; 454 455 static bool s_rnr_vmstate_validate(void *opaque, int version_id) 456 { 457 ARMCPU *cpu = opaque; 458 459 return cpu->env.pmsav7.rnr[M_REG_S] < cpu->pmsav7_dregion; 460 } 461 462 static bool sau_rnr_vmstate_validate(void *opaque, int version_id) 463 { 464 ARMCPU *cpu = opaque; 465 466 return cpu->env.sau.rnr < cpu->sau_sregion; 467 } 468 469 static bool m_security_needed(void *opaque) 470 { 471 ARMCPU *cpu = opaque; 472 CPUARMState *env = &cpu->env; 473 474 return arm_feature(env, ARM_FEATURE_M_SECURITY); 475 } 476 477 static const VMStateDescription vmstate_m_security = { 478 .name = "cpu/m-security", 479 .version_id = 1, 480 .minimum_version_id = 1, 481 .needed = m_security_needed, 482 .fields = (VMStateField[]) { 483 VMSTATE_UINT32(env.v7m.secure, ARMCPU), 484 VMSTATE_UINT32(env.v7m.other_ss_msp, ARMCPU), 485 VMSTATE_UINT32(env.v7m.other_ss_psp, ARMCPU), 486 VMSTATE_UINT32(env.v7m.basepri[M_REG_S], ARMCPU), 487 VMSTATE_UINT32(env.v7m.primask[M_REG_S], ARMCPU), 488 VMSTATE_UINT32(env.v7m.faultmask[M_REG_S], ARMCPU), 489 VMSTATE_UINT32(env.v7m.control[M_REG_S], ARMCPU), 490 VMSTATE_UINT32(env.v7m.vecbase[M_REG_S], ARMCPU), 491 VMSTATE_UINT32(env.pmsav8.mair0[M_REG_S], ARMCPU), 492 VMSTATE_UINT32(env.pmsav8.mair1[M_REG_S], ARMCPU), 493 VMSTATE_VARRAY_UINT32(env.pmsav8.rbar[M_REG_S], ARMCPU, pmsav7_dregion, 494 0, vmstate_info_uint32, uint32_t), 495 VMSTATE_VARRAY_UINT32(env.pmsav8.rlar[M_REG_S], ARMCPU, pmsav7_dregion, 496 0, vmstate_info_uint32, uint32_t), 497 VMSTATE_UINT32(env.pmsav7.rnr[M_REG_S], ARMCPU), 498 VMSTATE_VALIDATE("secure MPU_RNR is valid", s_rnr_vmstate_validate), 499 VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_S], ARMCPU), 500 VMSTATE_UINT32(env.v7m.ccr[M_REG_S], ARMCPU), 501 VMSTATE_UINT32(env.v7m.mmfar[M_REG_S], ARMCPU), 502 VMSTATE_UINT32(env.v7m.cfsr[M_REG_S], ARMCPU), 503 VMSTATE_UINT32(env.v7m.sfsr, ARMCPU), 504 VMSTATE_UINT32(env.v7m.sfar, ARMCPU), 505 VMSTATE_VARRAY_UINT32(env.sau.rbar, ARMCPU, sau_sregion, 0, 506 vmstate_info_uint32, uint32_t), 507 VMSTATE_VARRAY_UINT32(env.sau.rlar, ARMCPU, sau_sregion, 0, 508 vmstate_info_uint32, uint32_t), 509 VMSTATE_UINT32(env.sau.rnr, ARMCPU), 510 VMSTATE_VALIDATE("SAU_RNR is valid", sau_rnr_vmstate_validate), 511 VMSTATE_UINT32(env.sau.ctrl, ARMCPU), 512 VMSTATE_UINT32(env.v7m.scr[M_REG_S], ARMCPU), 513 /* AIRCR is not secure-only, but our implementation is R/O if the 514 * security extension is unimplemented, so we migrate it here. 515 */ 516 VMSTATE_UINT32(env.v7m.aircr, ARMCPU), 517 VMSTATE_END_OF_LIST() 518 } 519 }; 520 521 static int get_cpsr(QEMUFile *f, void *opaque, size_t size, 522 const VMStateField *field) 523 { 524 ARMCPU *cpu = opaque; 525 CPUARMState *env = &cpu->env; 526 uint32_t val = qemu_get_be32(f); 527 528 if (arm_feature(env, ARM_FEATURE_M)) { 529 if (val & XPSR_EXCP) { 530 /* This is a CPSR format value from an older QEMU. (We can tell 531 * because values transferred in XPSR format always have zero 532 * for the EXCP field, and CPSR format will always have bit 4 533 * set in CPSR_M.) Rearrange it into XPSR format. The significant 534 * differences are that the T bit is not in the same place, the 535 * primask/faultmask info may be in the CPSR I and F bits, and 536 * we do not want the mode bits. 537 * We know that this cleanup happened before v8M, so there 538 * is no complication with banked primask/faultmask. 539 */ 540 uint32_t newval = val; 541 542 assert(!arm_feature(env, ARM_FEATURE_M_SECURITY)); 543 544 newval &= (CPSR_NZCV | CPSR_Q | CPSR_IT | CPSR_GE); 545 if (val & CPSR_T) { 546 newval |= XPSR_T; 547 } 548 /* If the I or F bits are set then this is a migration from 549 * an old QEMU which still stored the M profile FAULTMASK 550 * and PRIMASK in env->daif. For a new QEMU, the data is 551 * transferred using the vmstate_m_faultmask_primask subsection. 552 */ 553 if (val & CPSR_F) { 554 env->v7m.faultmask[M_REG_NS] = 1; 555 } 556 if (val & CPSR_I) { 557 env->v7m.primask[M_REG_NS] = 1; 558 } 559 val = newval; 560 } 561 /* Ignore the low bits, they are handled by vmstate_m. */ 562 xpsr_write(env, val, ~XPSR_EXCP); 563 return 0; 564 } 565 566 env->aarch64 = ((val & PSTATE_nRW) == 0); 567 568 if (is_a64(env)) { 569 pstate_write(env, val); 570 return 0; 571 } 572 573 cpsr_write(env, val, 0xffffffff, CPSRWriteRaw); 574 return 0; 575 } 576 577 static int put_cpsr(QEMUFile *f, void *opaque, size_t size, 578 const VMStateField *field, QJSON *vmdesc) 579 { 580 ARMCPU *cpu = opaque; 581 CPUARMState *env = &cpu->env; 582 uint32_t val; 583 584 if (arm_feature(env, ARM_FEATURE_M)) { 585 /* The low 9 bits are v7m.exception, which is handled by vmstate_m. */ 586 val = xpsr_read(env) & ~XPSR_EXCP; 587 } else if (is_a64(env)) { 588 val = pstate_read(env); 589 } else { 590 val = cpsr_read(env); 591 } 592 593 qemu_put_be32(f, val); 594 return 0; 595 } 596 597 static const VMStateInfo vmstate_cpsr = { 598 .name = "cpsr", 599 .get = get_cpsr, 600 .put = put_cpsr, 601 }; 602 603 static int get_power(QEMUFile *f, void *opaque, size_t size, 604 const VMStateField *field) 605 { 606 ARMCPU *cpu = opaque; 607 bool powered_off = qemu_get_byte(f); 608 cpu->power_state = powered_off ? PSCI_OFF : PSCI_ON; 609 return 0; 610 } 611 612 static int put_power(QEMUFile *f, void *opaque, size_t size, 613 const VMStateField *field, QJSON *vmdesc) 614 { 615 ARMCPU *cpu = opaque; 616 617 /* Migration should never happen while we transition power states */ 618 619 if (cpu->power_state == PSCI_ON || 620 cpu->power_state == PSCI_OFF) { 621 bool powered_off = (cpu->power_state == PSCI_OFF) ? true : false; 622 qemu_put_byte(f, powered_off); 623 return 0; 624 } else { 625 return 1; 626 } 627 } 628 629 static const VMStateInfo vmstate_powered_off = { 630 .name = "powered_off", 631 .get = get_power, 632 .put = put_power, 633 }; 634 635 static int cpu_pre_save(void *opaque) 636 { 637 ARMCPU *cpu = opaque; 638 639 if (!kvm_enabled()) { 640 pmu_op_start(&cpu->env); 641 } 642 643 if (kvm_enabled()) { 644 if (!write_kvmstate_to_list(cpu)) { 645 /* This should never fail */ 646 abort(); 647 } 648 } else { 649 if (!write_cpustate_to_list(cpu, false)) { 650 /* This should never fail. */ 651 abort(); 652 } 653 } 654 655 cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len; 656 memcpy(cpu->cpreg_vmstate_indexes, cpu->cpreg_indexes, 657 cpu->cpreg_array_len * sizeof(uint64_t)); 658 memcpy(cpu->cpreg_vmstate_values, cpu->cpreg_values, 659 cpu->cpreg_array_len * sizeof(uint64_t)); 660 661 return 0; 662 } 663 664 static int cpu_post_save(void *opaque) 665 { 666 ARMCPU *cpu = opaque; 667 668 if (!kvm_enabled()) { 669 pmu_op_finish(&cpu->env); 670 } 671 672 return 0; 673 } 674 675 static int cpu_pre_load(void *opaque) 676 { 677 ARMCPU *cpu = opaque; 678 CPUARMState *env = &cpu->env; 679 680 /* 681 * Pre-initialize irq_line_state to a value that's never valid as 682 * real data, so cpu_post_load() can tell whether we've seen the 683 * irq-line-state subsection in the incoming migration state. 684 */ 685 env->irq_line_state = UINT32_MAX; 686 687 if (!kvm_enabled()) { 688 pmu_op_start(&cpu->env); 689 } 690 691 return 0; 692 } 693 694 static int cpu_post_load(void *opaque, int version_id) 695 { 696 ARMCPU *cpu = opaque; 697 CPUARMState *env = &cpu->env; 698 int i, v; 699 700 /* 701 * Handle migration compatibility from old QEMU which didn't 702 * send the irq-line-state subsection. A QEMU without it did not 703 * implement the HCR_EL2.{VI,VF} bits as generating interrupts, 704 * so for TCG the line state matches the bits set in cs->interrupt_request. 705 * For KVM the line state is not stored in cs->interrupt_request 706 * and so this will leave irq_line_state as 0, but this is OK because 707 * we only need to care about it for TCG. 708 */ 709 if (env->irq_line_state == UINT32_MAX) { 710 CPUState *cs = CPU(cpu); 711 712 env->irq_line_state = cs->interrupt_request & 713 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIQ | 714 CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VFIQ); 715 } 716 717 /* Update the values list from the incoming migration data. 718 * Anything in the incoming data which we don't know about is 719 * a migration failure; anything we know about but the incoming 720 * data doesn't specify retains its current (reset) value. 721 * The indexes list remains untouched -- we only inspect the 722 * incoming migration index list so we can match the values array 723 * entries with the right slots in our own values array. 724 */ 725 726 for (i = 0, v = 0; i < cpu->cpreg_array_len 727 && v < cpu->cpreg_vmstate_array_len; i++) { 728 if (cpu->cpreg_vmstate_indexes[v] > cpu->cpreg_indexes[i]) { 729 /* register in our list but not incoming : skip it */ 730 continue; 731 } 732 if (cpu->cpreg_vmstate_indexes[v] < cpu->cpreg_indexes[i]) { 733 /* register in their list but not ours: fail migration */ 734 return -1; 735 } 736 /* matching register, copy the value over */ 737 cpu->cpreg_values[i] = cpu->cpreg_vmstate_values[v]; 738 v++; 739 } 740 741 if (kvm_enabled()) { 742 if (!write_list_to_kvmstate(cpu, KVM_PUT_FULL_STATE)) { 743 return -1; 744 } 745 /* Note that it's OK for the TCG side not to know about 746 * every register in the list; KVM is authoritative if 747 * we're using it. 748 */ 749 write_list_to_cpustate(cpu); 750 } else { 751 if (!write_list_to_cpustate(cpu)) { 752 return -1; 753 } 754 } 755 756 hw_breakpoint_update_all(cpu); 757 hw_watchpoint_update_all(cpu); 758 759 if (!kvm_enabled()) { 760 pmu_op_finish(&cpu->env); 761 } 762 763 return 0; 764 } 765 766 const VMStateDescription vmstate_arm_cpu = { 767 .name = "cpu", 768 .version_id = 22, 769 .minimum_version_id = 22, 770 .pre_save = cpu_pre_save, 771 .post_save = cpu_post_save, 772 .pre_load = cpu_pre_load, 773 .post_load = cpu_post_load, 774 .fields = (VMStateField[]) { 775 VMSTATE_UINT32_ARRAY(env.regs, ARMCPU, 16), 776 VMSTATE_UINT64_ARRAY(env.xregs, ARMCPU, 32), 777 VMSTATE_UINT64(env.pc, ARMCPU), 778 { 779 .name = "cpsr", 780 .version_id = 0, 781 .size = sizeof(uint32_t), 782 .info = &vmstate_cpsr, 783 .flags = VMS_SINGLE, 784 .offset = 0, 785 }, 786 VMSTATE_UINT32(env.spsr, ARMCPU), 787 VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 8), 788 VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 8), 789 VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 8), 790 VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5), 791 VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5), 792 VMSTATE_UINT64_ARRAY(env.elr_el, ARMCPU, 4), 793 VMSTATE_UINT64_ARRAY(env.sp_el, ARMCPU, 4), 794 /* The length-check must come before the arrays to avoid 795 * incoming data possibly overflowing the array. 796 */ 797 VMSTATE_INT32_POSITIVE_LE(cpreg_vmstate_array_len, ARMCPU), 798 VMSTATE_VARRAY_INT32(cpreg_vmstate_indexes, ARMCPU, 799 cpreg_vmstate_array_len, 800 0, vmstate_info_uint64, uint64_t), 801 VMSTATE_VARRAY_INT32(cpreg_vmstate_values, ARMCPU, 802 cpreg_vmstate_array_len, 803 0, vmstate_info_uint64, uint64_t), 804 VMSTATE_UINT64(env.exclusive_addr, ARMCPU), 805 VMSTATE_UINT64(env.exclusive_val, ARMCPU), 806 VMSTATE_UINT64(env.exclusive_high, ARMCPU), 807 VMSTATE_UINT64(env.features, ARMCPU), 808 VMSTATE_UINT32(env.exception.syndrome, ARMCPU), 809 VMSTATE_UINT32(env.exception.fsr, ARMCPU), 810 VMSTATE_UINT64(env.exception.vaddress, ARMCPU), 811 VMSTATE_TIMER_PTR(gt_timer[GTIMER_PHYS], ARMCPU), 812 VMSTATE_TIMER_PTR(gt_timer[GTIMER_VIRT], ARMCPU), 813 { 814 .name = "power_state", 815 .version_id = 0, 816 .size = sizeof(bool), 817 .info = &vmstate_powered_off, 818 .flags = VMS_SINGLE, 819 .offset = 0, 820 }, 821 VMSTATE_END_OF_LIST() 822 }, 823 .subsections = (const VMStateDescription*[]) { 824 &vmstate_vfp, 825 &vmstate_iwmmxt, 826 &vmstate_m, 827 &vmstate_thumb2ee, 828 /* pmsav7_rnr must come before pmsav7 so that we have the 829 * region number before we test it in the VMSTATE_VALIDATE 830 * in vmstate_pmsav7. 831 */ 832 &vmstate_pmsav7_rnr, 833 &vmstate_pmsav7, 834 &vmstate_pmsav8, 835 &vmstate_m_security, 836 #ifdef TARGET_AARCH64 837 &vmstate_sve, 838 #endif 839 &vmstate_serror, 840 &vmstate_irq_line_state, 841 NULL 842 } 843 }; 844