1 #include "qemu/osdep.h" 2 #include "qemu-common.h" 3 #include "cpu.h" 4 #include "hw/hw.h" 5 #include "hw/boards.h" 6 #include "qemu/error-report.h" 7 #include "sysemu/kvm.h" 8 #include "kvm_arm.h" 9 #include "internals.h" 10 #include "migration/cpu.h" 11 12 static bool vfp_needed(void *opaque) 13 { 14 ARMCPU *cpu = opaque; 15 CPUARMState *env = &cpu->env; 16 17 return arm_feature(env, ARM_FEATURE_VFP); 18 } 19 20 static int get_fpscr(QEMUFile *f, void *opaque, size_t size, 21 VMStateField *field) 22 { 23 ARMCPU *cpu = opaque; 24 CPUARMState *env = &cpu->env; 25 uint32_t val = qemu_get_be32(f); 26 27 vfp_set_fpscr(env, val); 28 return 0; 29 } 30 31 static int put_fpscr(QEMUFile *f, void *opaque, size_t size, 32 VMStateField *field, QJSON *vmdesc) 33 { 34 ARMCPU *cpu = opaque; 35 CPUARMState *env = &cpu->env; 36 37 qemu_put_be32(f, vfp_get_fpscr(env)); 38 return 0; 39 } 40 41 static const VMStateInfo vmstate_fpscr = { 42 .name = "fpscr", 43 .get = get_fpscr, 44 .put = put_fpscr, 45 }; 46 47 static const VMStateDescription vmstate_vfp = { 48 .name = "cpu/vfp", 49 .version_id = 3, 50 .minimum_version_id = 3, 51 .needed = vfp_needed, 52 .fields = (VMStateField[]) { 53 /* For compatibility, store Qn out of Zn here. */ 54 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[0].d, ARMCPU, 0, 2), 55 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[1].d, ARMCPU, 0, 2), 56 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[2].d, ARMCPU, 0, 2), 57 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[3].d, ARMCPU, 0, 2), 58 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[4].d, ARMCPU, 0, 2), 59 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[5].d, ARMCPU, 0, 2), 60 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[6].d, ARMCPU, 0, 2), 61 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[7].d, ARMCPU, 0, 2), 62 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[8].d, ARMCPU, 0, 2), 63 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[9].d, ARMCPU, 0, 2), 64 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[10].d, ARMCPU, 0, 2), 65 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[11].d, ARMCPU, 0, 2), 66 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[12].d, ARMCPU, 0, 2), 67 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[13].d, ARMCPU, 0, 2), 68 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[14].d, ARMCPU, 0, 2), 69 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[15].d, ARMCPU, 0, 2), 70 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[16].d, ARMCPU, 0, 2), 71 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[17].d, ARMCPU, 0, 2), 72 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[18].d, ARMCPU, 0, 2), 73 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[19].d, ARMCPU, 0, 2), 74 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[20].d, ARMCPU, 0, 2), 75 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[21].d, ARMCPU, 0, 2), 76 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[22].d, ARMCPU, 0, 2), 77 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[23].d, ARMCPU, 0, 2), 78 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[24].d, ARMCPU, 0, 2), 79 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[25].d, ARMCPU, 0, 2), 80 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[26].d, ARMCPU, 0, 2), 81 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[27].d, ARMCPU, 0, 2), 82 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[28].d, ARMCPU, 0, 2), 83 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[29].d, ARMCPU, 0, 2), 84 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[30].d, ARMCPU, 0, 2), 85 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[31].d, ARMCPU, 0, 2), 86 87 /* The xregs array is a little awkward because element 1 (FPSCR) 88 * requires a specific accessor, so we have to split it up in 89 * the vmstate: 90 */ 91 VMSTATE_UINT32(env.vfp.xregs[0], ARMCPU), 92 VMSTATE_UINT32_SUB_ARRAY(env.vfp.xregs, ARMCPU, 2, 14), 93 { 94 .name = "fpscr", 95 .version_id = 0, 96 .size = sizeof(uint32_t), 97 .info = &vmstate_fpscr, 98 .flags = VMS_SINGLE, 99 .offset = 0, 100 }, 101 VMSTATE_END_OF_LIST() 102 } 103 }; 104 105 static bool iwmmxt_needed(void *opaque) 106 { 107 ARMCPU *cpu = opaque; 108 CPUARMState *env = &cpu->env; 109 110 return arm_feature(env, ARM_FEATURE_IWMMXT); 111 } 112 113 static const VMStateDescription vmstate_iwmmxt = { 114 .name = "cpu/iwmmxt", 115 .version_id = 1, 116 .minimum_version_id = 1, 117 .needed = iwmmxt_needed, 118 .fields = (VMStateField[]) { 119 VMSTATE_UINT64_ARRAY(env.iwmmxt.regs, ARMCPU, 16), 120 VMSTATE_UINT32_ARRAY(env.iwmmxt.cregs, ARMCPU, 16), 121 VMSTATE_END_OF_LIST() 122 } 123 }; 124 125 #ifdef TARGET_AARCH64 126 /* The expression ARM_MAX_VQ - 2 is 0 for pure AArch32 build, 127 * and ARMPredicateReg is actively empty. This triggers errors 128 * in the expansion of the VMSTATE macros. 129 */ 130 131 static bool sve_needed(void *opaque) 132 { 133 ARMCPU *cpu = opaque; 134 CPUARMState *env = &cpu->env; 135 136 return arm_feature(env, ARM_FEATURE_SVE); 137 } 138 139 /* The first two words of each Zreg is stored in VFP state. */ 140 static const VMStateDescription vmstate_zreg_hi_reg = { 141 .name = "cpu/sve/zreg_hi", 142 .version_id = 1, 143 .minimum_version_id = 1, 144 .fields = (VMStateField[]) { 145 VMSTATE_UINT64_SUB_ARRAY(d, ARMVectorReg, 2, ARM_MAX_VQ - 2), 146 VMSTATE_END_OF_LIST() 147 } 148 }; 149 150 static const VMStateDescription vmstate_preg_reg = { 151 .name = "cpu/sve/preg", 152 .version_id = 1, 153 .minimum_version_id = 1, 154 .fields = (VMStateField[]) { 155 VMSTATE_UINT64_ARRAY(p, ARMPredicateReg, 2 * ARM_MAX_VQ / 8), 156 VMSTATE_END_OF_LIST() 157 } 158 }; 159 160 static const VMStateDescription vmstate_sve = { 161 .name = "cpu/sve", 162 .version_id = 1, 163 .minimum_version_id = 1, 164 .needed = sve_needed, 165 .fields = (VMStateField[]) { 166 VMSTATE_STRUCT_ARRAY(env.vfp.zregs, ARMCPU, 32, 0, 167 vmstate_zreg_hi_reg, ARMVectorReg), 168 VMSTATE_STRUCT_ARRAY(env.vfp.pregs, ARMCPU, 17, 0, 169 vmstate_preg_reg, ARMPredicateReg), 170 VMSTATE_END_OF_LIST() 171 } 172 }; 173 #endif /* AARCH64 */ 174 175 static bool m_needed(void *opaque) 176 { 177 ARMCPU *cpu = opaque; 178 CPUARMState *env = &cpu->env; 179 180 return arm_feature(env, ARM_FEATURE_M); 181 } 182 183 static const VMStateDescription vmstate_m_faultmask_primask = { 184 .name = "cpu/m/faultmask-primask", 185 .version_id = 1, 186 .minimum_version_id = 1, 187 .fields = (VMStateField[]) { 188 VMSTATE_UINT32(env.v7m.faultmask[M_REG_NS], ARMCPU), 189 VMSTATE_UINT32(env.v7m.primask[M_REG_NS], ARMCPU), 190 VMSTATE_END_OF_LIST() 191 } 192 }; 193 194 /* CSSELR is in a subsection because we didn't implement it previously. 195 * Migration from an old implementation will leave it at zero, which 196 * is OK since the only CPUs in the old implementation make the 197 * register RAZ/WI. 198 * Since there was no version of QEMU which implemented the CSSELR for 199 * just non-secure, we transfer both banks here rather than putting 200 * the secure banked version in the m-security subsection. 201 */ 202 static bool csselr_vmstate_validate(void *opaque, int version_id) 203 { 204 ARMCPU *cpu = opaque; 205 206 return cpu->env.v7m.csselr[M_REG_NS] <= R_V7M_CSSELR_INDEX_MASK 207 && cpu->env.v7m.csselr[M_REG_S] <= R_V7M_CSSELR_INDEX_MASK; 208 } 209 210 static bool m_csselr_needed(void *opaque) 211 { 212 ARMCPU *cpu = opaque; 213 214 return !arm_v7m_csselr_razwi(cpu); 215 } 216 217 static const VMStateDescription vmstate_m_csselr = { 218 .name = "cpu/m/csselr", 219 .version_id = 1, 220 .minimum_version_id = 1, 221 .needed = m_csselr_needed, 222 .fields = (VMStateField[]) { 223 VMSTATE_UINT32_ARRAY(env.v7m.csselr, ARMCPU, M_REG_NUM_BANKS), 224 VMSTATE_VALIDATE("CSSELR is valid", csselr_vmstate_validate), 225 VMSTATE_END_OF_LIST() 226 } 227 }; 228 229 static const VMStateDescription vmstate_m = { 230 .name = "cpu/m", 231 .version_id = 4, 232 .minimum_version_id = 4, 233 .needed = m_needed, 234 .fields = (VMStateField[]) { 235 VMSTATE_UINT32(env.v7m.vecbase[M_REG_NS], ARMCPU), 236 VMSTATE_UINT32(env.v7m.basepri[M_REG_NS], ARMCPU), 237 VMSTATE_UINT32(env.v7m.control[M_REG_NS], ARMCPU), 238 VMSTATE_UINT32(env.v7m.ccr[M_REG_NS], ARMCPU), 239 VMSTATE_UINT32(env.v7m.cfsr[M_REG_NS], ARMCPU), 240 VMSTATE_UINT32(env.v7m.hfsr, ARMCPU), 241 VMSTATE_UINT32(env.v7m.dfsr, ARMCPU), 242 VMSTATE_UINT32(env.v7m.mmfar[M_REG_NS], ARMCPU), 243 VMSTATE_UINT32(env.v7m.bfar, ARMCPU), 244 VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_NS], ARMCPU), 245 VMSTATE_INT32(env.v7m.exception, ARMCPU), 246 VMSTATE_END_OF_LIST() 247 }, 248 .subsections = (const VMStateDescription*[]) { 249 &vmstate_m_faultmask_primask, 250 &vmstate_m_csselr, 251 NULL 252 } 253 }; 254 255 static bool thumb2ee_needed(void *opaque) 256 { 257 ARMCPU *cpu = opaque; 258 CPUARMState *env = &cpu->env; 259 260 return arm_feature(env, ARM_FEATURE_THUMB2EE); 261 } 262 263 static const VMStateDescription vmstate_thumb2ee = { 264 .name = "cpu/thumb2ee", 265 .version_id = 1, 266 .minimum_version_id = 1, 267 .needed = thumb2ee_needed, 268 .fields = (VMStateField[]) { 269 VMSTATE_UINT32(env.teecr, ARMCPU), 270 VMSTATE_UINT32(env.teehbr, ARMCPU), 271 VMSTATE_END_OF_LIST() 272 } 273 }; 274 275 static bool pmsav7_needed(void *opaque) 276 { 277 ARMCPU *cpu = opaque; 278 CPUARMState *env = &cpu->env; 279 280 return arm_feature(env, ARM_FEATURE_PMSA) && 281 arm_feature(env, ARM_FEATURE_V7) && 282 !arm_feature(env, ARM_FEATURE_V8); 283 } 284 285 static bool pmsav7_rgnr_vmstate_validate(void *opaque, int version_id) 286 { 287 ARMCPU *cpu = opaque; 288 289 return cpu->env.pmsav7.rnr[M_REG_NS] < cpu->pmsav7_dregion; 290 } 291 292 static const VMStateDescription vmstate_pmsav7 = { 293 .name = "cpu/pmsav7", 294 .version_id = 1, 295 .minimum_version_id = 1, 296 .needed = pmsav7_needed, 297 .fields = (VMStateField[]) { 298 VMSTATE_VARRAY_UINT32(env.pmsav7.drbar, ARMCPU, pmsav7_dregion, 0, 299 vmstate_info_uint32, uint32_t), 300 VMSTATE_VARRAY_UINT32(env.pmsav7.drsr, ARMCPU, pmsav7_dregion, 0, 301 vmstate_info_uint32, uint32_t), 302 VMSTATE_VARRAY_UINT32(env.pmsav7.dracr, ARMCPU, pmsav7_dregion, 0, 303 vmstate_info_uint32, uint32_t), 304 VMSTATE_VALIDATE("rgnr is valid", pmsav7_rgnr_vmstate_validate), 305 VMSTATE_END_OF_LIST() 306 } 307 }; 308 309 static bool pmsav7_rnr_needed(void *opaque) 310 { 311 ARMCPU *cpu = opaque; 312 CPUARMState *env = &cpu->env; 313 314 /* For R profile cores pmsav7.rnr is migrated via the cpreg 315 * "RGNR" definition in helper.h. For M profile we have to 316 * migrate it separately. 317 */ 318 return arm_feature(env, ARM_FEATURE_M); 319 } 320 321 static const VMStateDescription vmstate_pmsav7_rnr = { 322 .name = "cpu/pmsav7-rnr", 323 .version_id = 1, 324 .minimum_version_id = 1, 325 .needed = pmsav7_rnr_needed, 326 .fields = (VMStateField[]) { 327 VMSTATE_UINT32(env.pmsav7.rnr[M_REG_NS], ARMCPU), 328 VMSTATE_END_OF_LIST() 329 } 330 }; 331 332 static bool pmsav8_needed(void *opaque) 333 { 334 ARMCPU *cpu = opaque; 335 CPUARMState *env = &cpu->env; 336 337 return arm_feature(env, ARM_FEATURE_PMSA) && 338 arm_feature(env, ARM_FEATURE_V8); 339 } 340 341 static const VMStateDescription vmstate_pmsav8 = { 342 .name = "cpu/pmsav8", 343 .version_id = 1, 344 .minimum_version_id = 1, 345 .needed = pmsav8_needed, 346 .fields = (VMStateField[]) { 347 VMSTATE_VARRAY_UINT32(env.pmsav8.rbar[M_REG_NS], ARMCPU, pmsav7_dregion, 348 0, vmstate_info_uint32, uint32_t), 349 VMSTATE_VARRAY_UINT32(env.pmsav8.rlar[M_REG_NS], ARMCPU, pmsav7_dregion, 350 0, vmstate_info_uint32, uint32_t), 351 VMSTATE_UINT32(env.pmsav8.mair0[M_REG_NS], ARMCPU), 352 VMSTATE_UINT32(env.pmsav8.mair1[M_REG_NS], ARMCPU), 353 VMSTATE_END_OF_LIST() 354 } 355 }; 356 357 static bool s_rnr_vmstate_validate(void *opaque, int version_id) 358 { 359 ARMCPU *cpu = opaque; 360 361 return cpu->env.pmsav7.rnr[M_REG_S] < cpu->pmsav7_dregion; 362 } 363 364 static bool sau_rnr_vmstate_validate(void *opaque, int version_id) 365 { 366 ARMCPU *cpu = opaque; 367 368 return cpu->env.sau.rnr < cpu->sau_sregion; 369 } 370 371 static bool m_security_needed(void *opaque) 372 { 373 ARMCPU *cpu = opaque; 374 CPUARMState *env = &cpu->env; 375 376 return arm_feature(env, ARM_FEATURE_M_SECURITY); 377 } 378 379 static const VMStateDescription vmstate_m_security = { 380 .name = "cpu/m-security", 381 .version_id = 1, 382 .minimum_version_id = 1, 383 .needed = m_security_needed, 384 .fields = (VMStateField[]) { 385 VMSTATE_UINT32(env.v7m.secure, ARMCPU), 386 VMSTATE_UINT32(env.v7m.other_ss_msp, ARMCPU), 387 VMSTATE_UINT32(env.v7m.other_ss_psp, ARMCPU), 388 VMSTATE_UINT32(env.v7m.basepri[M_REG_S], ARMCPU), 389 VMSTATE_UINT32(env.v7m.primask[M_REG_S], ARMCPU), 390 VMSTATE_UINT32(env.v7m.faultmask[M_REG_S], ARMCPU), 391 VMSTATE_UINT32(env.v7m.control[M_REG_S], ARMCPU), 392 VMSTATE_UINT32(env.v7m.vecbase[M_REG_S], ARMCPU), 393 VMSTATE_UINT32(env.pmsav8.mair0[M_REG_S], ARMCPU), 394 VMSTATE_UINT32(env.pmsav8.mair1[M_REG_S], ARMCPU), 395 VMSTATE_VARRAY_UINT32(env.pmsav8.rbar[M_REG_S], ARMCPU, pmsav7_dregion, 396 0, vmstate_info_uint32, uint32_t), 397 VMSTATE_VARRAY_UINT32(env.pmsav8.rlar[M_REG_S], ARMCPU, pmsav7_dregion, 398 0, vmstate_info_uint32, uint32_t), 399 VMSTATE_UINT32(env.pmsav7.rnr[M_REG_S], ARMCPU), 400 VMSTATE_VALIDATE("secure MPU_RNR is valid", s_rnr_vmstate_validate), 401 VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_S], ARMCPU), 402 VMSTATE_UINT32(env.v7m.ccr[M_REG_S], ARMCPU), 403 VMSTATE_UINT32(env.v7m.mmfar[M_REG_S], ARMCPU), 404 VMSTATE_UINT32(env.v7m.cfsr[M_REG_S], ARMCPU), 405 VMSTATE_UINT32(env.v7m.sfsr, ARMCPU), 406 VMSTATE_UINT32(env.v7m.sfar, ARMCPU), 407 VMSTATE_VARRAY_UINT32(env.sau.rbar, ARMCPU, sau_sregion, 0, 408 vmstate_info_uint32, uint32_t), 409 VMSTATE_VARRAY_UINT32(env.sau.rlar, ARMCPU, sau_sregion, 0, 410 vmstate_info_uint32, uint32_t), 411 VMSTATE_UINT32(env.sau.rnr, ARMCPU), 412 VMSTATE_VALIDATE("SAU_RNR is valid", sau_rnr_vmstate_validate), 413 VMSTATE_UINT32(env.sau.ctrl, ARMCPU), 414 VMSTATE_END_OF_LIST() 415 } 416 }; 417 418 static int get_cpsr(QEMUFile *f, void *opaque, size_t size, 419 VMStateField *field) 420 { 421 ARMCPU *cpu = opaque; 422 CPUARMState *env = &cpu->env; 423 uint32_t val = qemu_get_be32(f); 424 425 if (arm_feature(env, ARM_FEATURE_M)) { 426 if (val & XPSR_EXCP) { 427 /* This is a CPSR format value from an older QEMU. (We can tell 428 * because values transferred in XPSR format always have zero 429 * for the EXCP field, and CPSR format will always have bit 4 430 * set in CPSR_M.) Rearrange it into XPSR format. The significant 431 * differences are that the T bit is not in the same place, the 432 * primask/faultmask info may be in the CPSR I and F bits, and 433 * we do not want the mode bits. 434 * We know that this cleanup happened before v8M, so there 435 * is no complication with banked primask/faultmask. 436 */ 437 uint32_t newval = val; 438 439 assert(!arm_feature(env, ARM_FEATURE_M_SECURITY)); 440 441 newval &= (CPSR_NZCV | CPSR_Q | CPSR_IT | CPSR_GE); 442 if (val & CPSR_T) { 443 newval |= XPSR_T; 444 } 445 /* If the I or F bits are set then this is a migration from 446 * an old QEMU which still stored the M profile FAULTMASK 447 * and PRIMASK in env->daif. For a new QEMU, the data is 448 * transferred using the vmstate_m_faultmask_primask subsection. 449 */ 450 if (val & CPSR_F) { 451 env->v7m.faultmask[M_REG_NS] = 1; 452 } 453 if (val & CPSR_I) { 454 env->v7m.primask[M_REG_NS] = 1; 455 } 456 val = newval; 457 } 458 /* Ignore the low bits, they are handled by vmstate_m. */ 459 xpsr_write(env, val, ~XPSR_EXCP); 460 return 0; 461 } 462 463 env->aarch64 = ((val & PSTATE_nRW) == 0); 464 465 if (is_a64(env)) { 466 pstate_write(env, val); 467 return 0; 468 } 469 470 cpsr_write(env, val, 0xffffffff, CPSRWriteRaw); 471 return 0; 472 } 473 474 static int put_cpsr(QEMUFile *f, void *opaque, size_t size, 475 VMStateField *field, QJSON *vmdesc) 476 { 477 ARMCPU *cpu = opaque; 478 CPUARMState *env = &cpu->env; 479 uint32_t val; 480 481 if (arm_feature(env, ARM_FEATURE_M)) { 482 /* The low 9 bits are v7m.exception, which is handled by vmstate_m. */ 483 val = xpsr_read(env) & ~XPSR_EXCP; 484 } else if (is_a64(env)) { 485 val = pstate_read(env); 486 } else { 487 val = cpsr_read(env); 488 } 489 490 qemu_put_be32(f, val); 491 return 0; 492 } 493 494 static const VMStateInfo vmstate_cpsr = { 495 .name = "cpsr", 496 .get = get_cpsr, 497 .put = put_cpsr, 498 }; 499 500 static int get_power(QEMUFile *f, void *opaque, size_t size, 501 VMStateField *field) 502 { 503 ARMCPU *cpu = opaque; 504 bool powered_off = qemu_get_byte(f); 505 cpu->power_state = powered_off ? PSCI_OFF : PSCI_ON; 506 return 0; 507 } 508 509 static int put_power(QEMUFile *f, void *opaque, size_t size, 510 VMStateField *field, QJSON *vmdesc) 511 { 512 ARMCPU *cpu = opaque; 513 514 /* Migration should never happen while we transition power states */ 515 516 if (cpu->power_state == PSCI_ON || 517 cpu->power_state == PSCI_OFF) { 518 bool powered_off = (cpu->power_state == PSCI_OFF) ? true : false; 519 qemu_put_byte(f, powered_off); 520 return 0; 521 } else { 522 return 1; 523 } 524 } 525 526 static const VMStateInfo vmstate_powered_off = { 527 .name = "powered_off", 528 .get = get_power, 529 .put = put_power, 530 }; 531 532 static int cpu_pre_save(void *opaque) 533 { 534 ARMCPU *cpu = opaque; 535 536 if (kvm_enabled()) { 537 if (!write_kvmstate_to_list(cpu)) { 538 /* This should never fail */ 539 abort(); 540 } 541 } else { 542 if (!write_cpustate_to_list(cpu)) { 543 /* This should never fail. */ 544 abort(); 545 } 546 } 547 548 cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len; 549 memcpy(cpu->cpreg_vmstate_indexes, cpu->cpreg_indexes, 550 cpu->cpreg_array_len * sizeof(uint64_t)); 551 memcpy(cpu->cpreg_vmstate_values, cpu->cpreg_values, 552 cpu->cpreg_array_len * sizeof(uint64_t)); 553 554 return 0; 555 } 556 557 static int cpu_post_load(void *opaque, int version_id) 558 { 559 ARMCPU *cpu = opaque; 560 int i, v; 561 562 /* Update the values list from the incoming migration data. 563 * Anything in the incoming data which we don't know about is 564 * a migration failure; anything we know about but the incoming 565 * data doesn't specify retains its current (reset) value. 566 * The indexes list remains untouched -- we only inspect the 567 * incoming migration index list so we can match the values array 568 * entries with the right slots in our own values array. 569 */ 570 571 for (i = 0, v = 0; i < cpu->cpreg_array_len 572 && v < cpu->cpreg_vmstate_array_len; i++) { 573 if (cpu->cpreg_vmstate_indexes[v] > cpu->cpreg_indexes[i]) { 574 /* register in our list but not incoming : skip it */ 575 continue; 576 } 577 if (cpu->cpreg_vmstate_indexes[v] < cpu->cpreg_indexes[i]) { 578 /* register in their list but not ours: fail migration */ 579 return -1; 580 } 581 /* matching register, copy the value over */ 582 cpu->cpreg_values[i] = cpu->cpreg_vmstate_values[v]; 583 v++; 584 } 585 586 if (kvm_enabled()) { 587 if (!write_list_to_kvmstate(cpu, KVM_PUT_FULL_STATE)) { 588 return -1; 589 } 590 /* Note that it's OK for the TCG side not to know about 591 * every register in the list; KVM is authoritative if 592 * we're using it. 593 */ 594 write_list_to_cpustate(cpu); 595 } else { 596 if (!write_list_to_cpustate(cpu)) { 597 return -1; 598 } 599 } 600 601 hw_breakpoint_update_all(cpu); 602 hw_watchpoint_update_all(cpu); 603 604 return 0; 605 } 606 607 const VMStateDescription vmstate_arm_cpu = { 608 .name = "cpu", 609 .version_id = 22, 610 .minimum_version_id = 22, 611 .pre_save = cpu_pre_save, 612 .post_load = cpu_post_load, 613 .fields = (VMStateField[]) { 614 VMSTATE_UINT32_ARRAY(env.regs, ARMCPU, 16), 615 VMSTATE_UINT64_ARRAY(env.xregs, ARMCPU, 32), 616 VMSTATE_UINT64(env.pc, ARMCPU), 617 { 618 .name = "cpsr", 619 .version_id = 0, 620 .size = sizeof(uint32_t), 621 .info = &vmstate_cpsr, 622 .flags = VMS_SINGLE, 623 .offset = 0, 624 }, 625 VMSTATE_UINT32(env.spsr, ARMCPU), 626 VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 8), 627 VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 8), 628 VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 8), 629 VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5), 630 VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5), 631 VMSTATE_UINT64_ARRAY(env.elr_el, ARMCPU, 4), 632 VMSTATE_UINT64_ARRAY(env.sp_el, ARMCPU, 4), 633 /* The length-check must come before the arrays to avoid 634 * incoming data possibly overflowing the array. 635 */ 636 VMSTATE_INT32_POSITIVE_LE(cpreg_vmstate_array_len, ARMCPU), 637 VMSTATE_VARRAY_INT32(cpreg_vmstate_indexes, ARMCPU, 638 cpreg_vmstate_array_len, 639 0, vmstate_info_uint64, uint64_t), 640 VMSTATE_VARRAY_INT32(cpreg_vmstate_values, ARMCPU, 641 cpreg_vmstate_array_len, 642 0, vmstate_info_uint64, uint64_t), 643 VMSTATE_UINT64(env.exclusive_addr, ARMCPU), 644 VMSTATE_UINT64(env.exclusive_val, ARMCPU), 645 VMSTATE_UINT64(env.exclusive_high, ARMCPU), 646 VMSTATE_UINT64(env.features, ARMCPU), 647 VMSTATE_UINT32(env.exception.syndrome, ARMCPU), 648 VMSTATE_UINT32(env.exception.fsr, ARMCPU), 649 VMSTATE_UINT64(env.exception.vaddress, ARMCPU), 650 VMSTATE_TIMER_PTR(gt_timer[GTIMER_PHYS], ARMCPU), 651 VMSTATE_TIMER_PTR(gt_timer[GTIMER_VIRT], ARMCPU), 652 { 653 .name = "power_state", 654 .version_id = 0, 655 .size = sizeof(bool), 656 .info = &vmstate_powered_off, 657 .flags = VMS_SINGLE, 658 .offset = 0, 659 }, 660 VMSTATE_END_OF_LIST() 661 }, 662 .subsections = (const VMStateDescription*[]) { 663 &vmstate_vfp, 664 &vmstate_iwmmxt, 665 &vmstate_m, 666 &vmstate_thumb2ee, 667 /* pmsav7_rnr must come before pmsav7 so that we have the 668 * region number before we test it in the VMSTATE_VALIDATE 669 * in vmstate_pmsav7. 670 */ 671 &vmstate_pmsav7_rnr, 672 &vmstate_pmsav7, 673 &vmstate_pmsav8, 674 &vmstate_m_security, 675 #ifdef TARGET_AARCH64 676 &vmstate_sve, 677 #endif 678 NULL 679 } 680 }; 681