1 #include "qemu/osdep.h" 2 #include "qemu-common.h" 3 #include "cpu.h" 4 #include "hw/hw.h" 5 #include "hw/boards.h" 6 #include "qemu/error-report.h" 7 #include "sysemu/kvm.h" 8 #include "kvm_arm.h" 9 #include "internals.h" 10 #include "migration/cpu.h" 11 12 static bool vfp_needed(void *opaque) 13 { 14 ARMCPU *cpu = opaque; 15 CPUARMState *env = &cpu->env; 16 17 return arm_feature(env, ARM_FEATURE_VFP); 18 } 19 20 static int get_fpscr(QEMUFile *f, void *opaque, size_t size, 21 VMStateField *field) 22 { 23 ARMCPU *cpu = opaque; 24 CPUARMState *env = &cpu->env; 25 uint32_t val = qemu_get_be32(f); 26 27 vfp_set_fpscr(env, val); 28 return 0; 29 } 30 31 static int put_fpscr(QEMUFile *f, void *opaque, size_t size, 32 VMStateField *field, QJSON *vmdesc) 33 { 34 ARMCPU *cpu = opaque; 35 CPUARMState *env = &cpu->env; 36 37 qemu_put_be32(f, vfp_get_fpscr(env)); 38 return 0; 39 } 40 41 static const VMStateInfo vmstate_fpscr = { 42 .name = "fpscr", 43 .get = get_fpscr, 44 .put = put_fpscr, 45 }; 46 47 static const VMStateDescription vmstate_vfp = { 48 .name = "cpu/vfp", 49 .version_id = 3, 50 .minimum_version_id = 3, 51 .needed = vfp_needed, 52 .fields = (VMStateField[]) { 53 VMSTATE_FLOAT64_ARRAY(env.vfp.regs, ARMCPU, 64), 54 /* The xregs array is a little awkward because element 1 (FPSCR) 55 * requires a specific accessor, so we have to split it up in 56 * the vmstate: 57 */ 58 VMSTATE_UINT32(env.vfp.xregs[0], ARMCPU), 59 VMSTATE_UINT32_SUB_ARRAY(env.vfp.xregs, ARMCPU, 2, 14), 60 { 61 .name = "fpscr", 62 .version_id = 0, 63 .size = sizeof(uint32_t), 64 .info = &vmstate_fpscr, 65 .flags = VMS_SINGLE, 66 .offset = 0, 67 }, 68 VMSTATE_END_OF_LIST() 69 } 70 }; 71 72 static bool iwmmxt_needed(void *opaque) 73 { 74 ARMCPU *cpu = opaque; 75 CPUARMState *env = &cpu->env; 76 77 return arm_feature(env, ARM_FEATURE_IWMMXT); 78 } 79 80 static const VMStateDescription vmstate_iwmmxt = { 81 .name = "cpu/iwmmxt", 82 .version_id = 1, 83 .minimum_version_id = 1, 84 .needed = iwmmxt_needed, 85 .fields = (VMStateField[]) { 86 VMSTATE_UINT64_ARRAY(env.iwmmxt.regs, ARMCPU, 16), 87 VMSTATE_UINT32_ARRAY(env.iwmmxt.cregs, ARMCPU, 16), 88 VMSTATE_END_OF_LIST() 89 } 90 }; 91 92 static bool m_needed(void *opaque) 93 { 94 ARMCPU *cpu = opaque; 95 CPUARMState *env = &cpu->env; 96 97 return arm_feature(env, ARM_FEATURE_M); 98 } 99 100 static const VMStateDescription vmstate_m_faultmask_primask = { 101 .name = "cpu/m/faultmask-primask", 102 .version_id = 1, 103 .minimum_version_id = 1, 104 .fields = (VMStateField[]) { 105 VMSTATE_UINT32(env.v7m.faultmask[M_REG_NS], ARMCPU), 106 VMSTATE_UINT32(env.v7m.primask[M_REG_NS], ARMCPU), 107 VMSTATE_END_OF_LIST() 108 } 109 }; 110 111 static const VMStateDescription vmstate_m = { 112 .name = "cpu/m", 113 .version_id = 4, 114 .minimum_version_id = 4, 115 .needed = m_needed, 116 .fields = (VMStateField[]) { 117 VMSTATE_UINT32(env.v7m.vecbase[M_REG_NS], ARMCPU), 118 VMSTATE_UINT32(env.v7m.basepri[M_REG_NS], ARMCPU), 119 VMSTATE_UINT32(env.v7m.control[M_REG_NS], ARMCPU), 120 VMSTATE_UINT32(env.v7m.ccr, ARMCPU), 121 VMSTATE_UINT32(env.v7m.cfsr, ARMCPU), 122 VMSTATE_UINT32(env.v7m.hfsr, ARMCPU), 123 VMSTATE_UINT32(env.v7m.dfsr, ARMCPU), 124 VMSTATE_UINT32(env.v7m.mmfar, ARMCPU), 125 VMSTATE_UINT32(env.v7m.bfar, ARMCPU), 126 VMSTATE_UINT32(env.v7m.mpu_ctrl, ARMCPU), 127 VMSTATE_INT32(env.v7m.exception, ARMCPU), 128 VMSTATE_END_OF_LIST() 129 }, 130 .subsections = (const VMStateDescription*[]) { 131 &vmstate_m_faultmask_primask, 132 NULL 133 } 134 }; 135 136 static bool thumb2ee_needed(void *opaque) 137 { 138 ARMCPU *cpu = opaque; 139 CPUARMState *env = &cpu->env; 140 141 return arm_feature(env, ARM_FEATURE_THUMB2EE); 142 } 143 144 static const VMStateDescription vmstate_thumb2ee = { 145 .name = "cpu/thumb2ee", 146 .version_id = 1, 147 .minimum_version_id = 1, 148 .needed = thumb2ee_needed, 149 .fields = (VMStateField[]) { 150 VMSTATE_UINT32(env.teecr, ARMCPU), 151 VMSTATE_UINT32(env.teehbr, ARMCPU), 152 VMSTATE_END_OF_LIST() 153 } 154 }; 155 156 static bool pmsav7_needed(void *opaque) 157 { 158 ARMCPU *cpu = opaque; 159 CPUARMState *env = &cpu->env; 160 161 return arm_feature(env, ARM_FEATURE_PMSA) && 162 arm_feature(env, ARM_FEATURE_V7) && 163 !arm_feature(env, ARM_FEATURE_V8); 164 } 165 166 static bool pmsav7_rgnr_vmstate_validate(void *opaque, int version_id) 167 { 168 ARMCPU *cpu = opaque; 169 170 return cpu->env.pmsav7.rnr < cpu->pmsav7_dregion; 171 } 172 173 static const VMStateDescription vmstate_pmsav7 = { 174 .name = "cpu/pmsav7", 175 .version_id = 1, 176 .minimum_version_id = 1, 177 .needed = pmsav7_needed, 178 .fields = (VMStateField[]) { 179 VMSTATE_VARRAY_UINT32(env.pmsav7.drbar, ARMCPU, pmsav7_dregion, 0, 180 vmstate_info_uint32, uint32_t), 181 VMSTATE_VARRAY_UINT32(env.pmsav7.drsr, ARMCPU, pmsav7_dregion, 0, 182 vmstate_info_uint32, uint32_t), 183 VMSTATE_VARRAY_UINT32(env.pmsav7.dracr, ARMCPU, pmsav7_dregion, 0, 184 vmstate_info_uint32, uint32_t), 185 VMSTATE_VALIDATE("rgnr is valid", pmsav7_rgnr_vmstate_validate), 186 VMSTATE_END_OF_LIST() 187 } 188 }; 189 190 static bool pmsav7_rnr_needed(void *opaque) 191 { 192 ARMCPU *cpu = opaque; 193 CPUARMState *env = &cpu->env; 194 195 /* For R profile cores pmsav7.rnr is migrated via the cpreg 196 * "RGNR" definition in helper.h. For M profile we have to 197 * migrate it separately. 198 */ 199 return arm_feature(env, ARM_FEATURE_M); 200 } 201 202 static const VMStateDescription vmstate_pmsav7_rnr = { 203 .name = "cpu/pmsav7-rnr", 204 .version_id = 1, 205 .minimum_version_id = 1, 206 .needed = pmsav7_rnr_needed, 207 .fields = (VMStateField[]) { 208 VMSTATE_UINT32(env.pmsav7.rnr, ARMCPU), 209 VMSTATE_END_OF_LIST() 210 } 211 }; 212 213 static bool pmsav8_needed(void *opaque) 214 { 215 ARMCPU *cpu = opaque; 216 CPUARMState *env = &cpu->env; 217 218 return arm_feature(env, ARM_FEATURE_PMSA) && 219 arm_feature(env, ARM_FEATURE_V8); 220 } 221 222 static const VMStateDescription vmstate_pmsav8 = { 223 .name = "cpu/pmsav8", 224 .version_id = 1, 225 .minimum_version_id = 1, 226 .needed = pmsav8_needed, 227 .fields = (VMStateField[]) { 228 VMSTATE_VARRAY_UINT32(env.pmsav8.rbar, ARMCPU, pmsav7_dregion, 0, 229 vmstate_info_uint32, uint32_t), 230 VMSTATE_VARRAY_UINT32(env.pmsav8.rlar, ARMCPU, pmsav7_dregion, 0, 231 vmstate_info_uint32, uint32_t), 232 VMSTATE_UINT32(env.pmsav8.mair0[M_REG_NS], ARMCPU), 233 VMSTATE_UINT32(env.pmsav8.mair1[M_REG_NS], ARMCPU), 234 VMSTATE_END_OF_LIST() 235 } 236 }; 237 238 static bool m_security_needed(void *opaque) 239 { 240 ARMCPU *cpu = opaque; 241 CPUARMState *env = &cpu->env; 242 243 return arm_feature(env, ARM_FEATURE_M_SECURITY); 244 } 245 246 static const VMStateDescription vmstate_m_security = { 247 .name = "cpu/m-security", 248 .version_id = 1, 249 .minimum_version_id = 1, 250 .needed = m_security_needed, 251 .fields = (VMStateField[]) { 252 VMSTATE_UINT32(env.v7m.secure, ARMCPU), 253 VMSTATE_UINT32(env.v7m.basepri[M_REG_S], ARMCPU), 254 VMSTATE_UINT32(env.v7m.primask[M_REG_S], ARMCPU), 255 VMSTATE_UINT32(env.v7m.faultmask[M_REG_S], ARMCPU), 256 VMSTATE_UINT32(env.v7m.control[M_REG_S], ARMCPU), 257 VMSTATE_UINT32(env.v7m.vecbase[M_REG_S], ARMCPU), 258 VMSTATE_UINT32(env.pmsav8.mair0[M_REG_S], ARMCPU), 259 VMSTATE_UINT32(env.pmsav8.mair1[M_REG_S], ARMCPU), 260 VMSTATE_END_OF_LIST() 261 } 262 }; 263 264 static int get_cpsr(QEMUFile *f, void *opaque, size_t size, 265 VMStateField *field) 266 { 267 ARMCPU *cpu = opaque; 268 CPUARMState *env = &cpu->env; 269 uint32_t val = qemu_get_be32(f); 270 271 if (arm_feature(env, ARM_FEATURE_M)) { 272 if (val & XPSR_EXCP) { 273 /* This is a CPSR format value from an older QEMU. (We can tell 274 * because values transferred in XPSR format always have zero 275 * for the EXCP field, and CPSR format will always have bit 4 276 * set in CPSR_M.) Rearrange it into XPSR format. The significant 277 * differences are that the T bit is not in the same place, the 278 * primask/faultmask info may be in the CPSR I and F bits, and 279 * we do not want the mode bits. 280 * We know that this cleanup happened before v8M, so there 281 * is no complication with banked primask/faultmask. 282 */ 283 uint32_t newval = val; 284 285 assert(!arm_feature(env, ARM_FEATURE_M_SECURITY)); 286 287 newval &= (CPSR_NZCV | CPSR_Q | CPSR_IT | CPSR_GE); 288 if (val & CPSR_T) { 289 newval |= XPSR_T; 290 } 291 /* If the I or F bits are set then this is a migration from 292 * an old QEMU which still stored the M profile FAULTMASK 293 * and PRIMASK in env->daif. For a new QEMU, the data is 294 * transferred using the vmstate_m_faultmask_primask subsection. 295 */ 296 if (val & CPSR_F) { 297 env->v7m.faultmask[M_REG_NS] = 1; 298 } 299 if (val & CPSR_I) { 300 env->v7m.primask[M_REG_NS] = 1; 301 } 302 val = newval; 303 } 304 /* Ignore the low bits, they are handled by vmstate_m. */ 305 xpsr_write(env, val, ~XPSR_EXCP); 306 return 0; 307 } 308 309 env->aarch64 = ((val & PSTATE_nRW) == 0); 310 311 if (is_a64(env)) { 312 pstate_write(env, val); 313 return 0; 314 } 315 316 cpsr_write(env, val, 0xffffffff, CPSRWriteRaw); 317 return 0; 318 } 319 320 static int put_cpsr(QEMUFile *f, void *opaque, size_t size, 321 VMStateField *field, QJSON *vmdesc) 322 { 323 ARMCPU *cpu = opaque; 324 CPUARMState *env = &cpu->env; 325 uint32_t val; 326 327 if (arm_feature(env, ARM_FEATURE_M)) { 328 /* The low 9 bits are v7m.exception, which is handled by vmstate_m. */ 329 val = xpsr_read(env) & ~XPSR_EXCP; 330 } else if (is_a64(env)) { 331 val = pstate_read(env); 332 } else { 333 val = cpsr_read(env); 334 } 335 336 qemu_put_be32(f, val); 337 return 0; 338 } 339 340 static const VMStateInfo vmstate_cpsr = { 341 .name = "cpsr", 342 .get = get_cpsr, 343 .put = put_cpsr, 344 }; 345 346 static int get_power(QEMUFile *f, void *opaque, size_t size, 347 VMStateField *field) 348 { 349 ARMCPU *cpu = opaque; 350 bool powered_off = qemu_get_byte(f); 351 cpu->power_state = powered_off ? PSCI_OFF : PSCI_ON; 352 return 0; 353 } 354 355 static int put_power(QEMUFile *f, void *opaque, size_t size, 356 VMStateField *field, QJSON *vmdesc) 357 { 358 ARMCPU *cpu = opaque; 359 360 /* Migration should never happen while we transition power states */ 361 362 if (cpu->power_state == PSCI_ON || 363 cpu->power_state == PSCI_OFF) { 364 bool powered_off = (cpu->power_state == PSCI_OFF) ? true : false; 365 qemu_put_byte(f, powered_off); 366 return 0; 367 } else { 368 return 1; 369 } 370 } 371 372 static const VMStateInfo vmstate_powered_off = { 373 .name = "powered_off", 374 .get = get_power, 375 .put = put_power, 376 }; 377 378 static void cpu_pre_save(void *opaque) 379 { 380 ARMCPU *cpu = opaque; 381 382 if (kvm_enabled()) { 383 if (!write_kvmstate_to_list(cpu)) { 384 /* This should never fail */ 385 abort(); 386 } 387 } else { 388 if (!write_cpustate_to_list(cpu)) { 389 /* This should never fail. */ 390 abort(); 391 } 392 } 393 394 cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len; 395 memcpy(cpu->cpreg_vmstate_indexes, cpu->cpreg_indexes, 396 cpu->cpreg_array_len * sizeof(uint64_t)); 397 memcpy(cpu->cpreg_vmstate_values, cpu->cpreg_values, 398 cpu->cpreg_array_len * sizeof(uint64_t)); 399 } 400 401 static int cpu_post_load(void *opaque, int version_id) 402 { 403 ARMCPU *cpu = opaque; 404 int i, v; 405 406 /* Update the values list from the incoming migration data. 407 * Anything in the incoming data which we don't know about is 408 * a migration failure; anything we know about but the incoming 409 * data doesn't specify retains its current (reset) value. 410 * The indexes list remains untouched -- we only inspect the 411 * incoming migration index list so we can match the values array 412 * entries with the right slots in our own values array. 413 */ 414 415 for (i = 0, v = 0; i < cpu->cpreg_array_len 416 && v < cpu->cpreg_vmstate_array_len; i++) { 417 if (cpu->cpreg_vmstate_indexes[v] > cpu->cpreg_indexes[i]) { 418 /* register in our list but not incoming : skip it */ 419 continue; 420 } 421 if (cpu->cpreg_vmstate_indexes[v] < cpu->cpreg_indexes[i]) { 422 /* register in their list but not ours: fail migration */ 423 return -1; 424 } 425 /* matching register, copy the value over */ 426 cpu->cpreg_values[i] = cpu->cpreg_vmstate_values[v]; 427 v++; 428 } 429 430 if (kvm_enabled()) { 431 if (!write_list_to_kvmstate(cpu, KVM_PUT_FULL_STATE)) { 432 return -1; 433 } 434 /* Note that it's OK for the TCG side not to know about 435 * every register in the list; KVM is authoritative if 436 * we're using it. 437 */ 438 write_list_to_cpustate(cpu); 439 } else { 440 if (!write_list_to_cpustate(cpu)) { 441 return -1; 442 } 443 } 444 445 hw_breakpoint_update_all(cpu); 446 hw_watchpoint_update_all(cpu); 447 448 return 0; 449 } 450 451 const VMStateDescription vmstate_arm_cpu = { 452 .name = "cpu", 453 .version_id = 22, 454 .minimum_version_id = 22, 455 .pre_save = cpu_pre_save, 456 .post_load = cpu_post_load, 457 .fields = (VMStateField[]) { 458 VMSTATE_UINT32_ARRAY(env.regs, ARMCPU, 16), 459 VMSTATE_UINT64_ARRAY(env.xregs, ARMCPU, 32), 460 VMSTATE_UINT64(env.pc, ARMCPU), 461 { 462 .name = "cpsr", 463 .version_id = 0, 464 .size = sizeof(uint32_t), 465 .info = &vmstate_cpsr, 466 .flags = VMS_SINGLE, 467 .offset = 0, 468 }, 469 VMSTATE_UINT32(env.spsr, ARMCPU), 470 VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 8), 471 VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 8), 472 VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 8), 473 VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5), 474 VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5), 475 VMSTATE_UINT64_ARRAY(env.elr_el, ARMCPU, 4), 476 VMSTATE_UINT64_ARRAY(env.sp_el, ARMCPU, 4), 477 /* The length-check must come before the arrays to avoid 478 * incoming data possibly overflowing the array. 479 */ 480 VMSTATE_INT32_POSITIVE_LE(cpreg_vmstate_array_len, ARMCPU), 481 VMSTATE_VARRAY_INT32(cpreg_vmstate_indexes, ARMCPU, 482 cpreg_vmstate_array_len, 483 0, vmstate_info_uint64, uint64_t), 484 VMSTATE_VARRAY_INT32(cpreg_vmstate_values, ARMCPU, 485 cpreg_vmstate_array_len, 486 0, vmstate_info_uint64, uint64_t), 487 VMSTATE_UINT64(env.exclusive_addr, ARMCPU), 488 VMSTATE_UINT64(env.exclusive_val, ARMCPU), 489 VMSTATE_UINT64(env.exclusive_high, ARMCPU), 490 VMSTATE_UINT64(env.features, ARMCPU), 491 VMSTATE_UINT32(env.exception.syndrome, ARMCPU), 492 VMSTATE_UINT32(env.exception.fsr, ARMCPU), 493 VMSTATE_UINT64(env.exception.vaddress, ARMCPU), 494 VMSTATE_TIMER_PTR(gt_timer[GTIMER_PHYS], ARMCPU), 495 VMSTATE_TIMER_PTR(gt_timer[GTIMER_VIRT], ARMCPU), 496 { 497 .name = "power_state", 498 .version_id = 0, 499 .size = sizeof(bool), 500 .info = &vmstate_powered_off, 501 .flags = VMS_SINGLE, 502 .offset = 0, 503 }, 504 VMSTATE_END_OF_LIST() 505 }, 506 .subsections = (const VMStateDescription*[]) { 507 &vmstate_vfp, 508 &vmstate_iwmmxt, 509 &vmstate_m, 510 &vmstate_thumb2ee, 511 /* pmsav7_rnr must come before pmsav7 so that we have the 512 * region number before we test it in the VMSTATE_VALIDATE 513 * in vmstate_pmsav7. 514 */ 515 &vmstate_pmsav7_rnr, 516 &vmstate_pmsav7, 517 &vmstate_pmsav8, 518 &vmstate_m_security, 519 NULL 520 } 521 }; 522