1 #include "qemu/osdep.h" 2 #include "cpu.h" 3 #include "qemu/error-report.h" 4 #include "sysemu/kvm.h" 5 #include "kvm_arm.h" 6 #include "internals.h" 7 #include "migration/cpu.h" 8 9 static bool vfp_needed(void *opaque) 10 { 11 ARMCPU *cpu = opaque; 12 13 return (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) 14 ? cpu_isar_feature(aa64_fp_simd, cpu) 15 : cpu_isar_feature(aa32_vfp_simd, cpu)); 16 } 17 18 static int get_fpscr(QEMUFile *f, void *opaque, size_t size, 19 const VMStateField *field) 20 { 21 ARMCPU *cpu = opaque; 22 CPUARMState *env = &cpu->env; 23 uint32_t val = qemu_get_be32(f); 24 25 vfp_set_fpscr(env, val); 26 return 0; 27 } 28 29 static int put_fpscr(QEMUFile *f, void *opaque, size_t size, 30 const VMStateField *field, JSONWriter *vmdesc) 31 { 32 ARMCPU *cpu = opaque; 33 CPUARMState *env = &cpu->env; 34 35 qemu_put_be32(f, vfp_get_fpscr(env)); 36 return 0; 37 } 38 39 static const VMStateInfo vmstate_fpscr = { 40 .name = "fpscr", 41 .get = get_fpscr, 42 .put = put_fpscr, 43 }; 44 45 static const VMStateDescription vmstate_vfp = { 46 .name = "cpu/vfp", 47 .version_id = 3, 48 .minimum_version_id = 3, 49 .needed = vfp_needed, 50 .fields = (VMStateField[]) { 51 /* For compatibility, store Qn out of Zn here. */ 52 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[0].d, ARMCPU, 0, 2), 53 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[1].d, ARMCPU, 0, 2), 54 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[2].d, ARMCPU, 0, 2), 55 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[3].d, ARMCPU, 0, 2), 56 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[4].d, ARMCPU, 0, 2), 57 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[5].d, ARMCPU, 0, 2), 58 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[6].d, ARMCPU, 0, 2), 59 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[7].d, ARMCPU, 0, 2), 60 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[8].d, ARMCPU, 0, 2), 61 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[9].d, ARMCPU, 0, 2), 62 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[10].d, ARMCPU, 0, 2), 63 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[11].d, ARMCPU, 0, 2), 64 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[12].d, ARMCPU, 0, 2), 65 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[13].d, ARMCPU, 0, 2), 66 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[14].d, ARMCPU, 0, 2), 67 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[15].d, ARMCPU, 0, 2), 68 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[16].d, ARMCPU, 0, 2), 69 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[17].d, ARMCPU, 0, 2), 70 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[18].d, ARMCPU, 0, 2), 71 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[19].d, ARMCPU, 0, 2), 72 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[20].d, ARMCPU, 0, 2), 73 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[21].d, ARMCPU, 0, 2), 74 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[22].d, ARMCPU, 0, 2), 75 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[23].d, ARMCPU, 0, 2), 76 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[24].d, ARMCPU, 0, 2), 77 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[25].d, ARMCPU, 0, 2), 78 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[26].d, ARMCPU, 0, 2), 79 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[27].d, ARMCPU, 0, 2), 80 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[28].d, ARMCPU, 0, 2), 81 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[29].d, ARMCPU, 0, 2), 82 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[30].d, ARMCPU, 0, 2), 83 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[31].d, ARMCPU, 0, 2), 84 85 /* The xregs array is a little awkward because element 1 (FPSCR) 86 * requires a specific accessor, so we have to split it up in 87 * the vmstate: 88 */ 89 VMSTATE_UINT32(env.vfp.xregs[0], ARMCPU), 90 VMSTATE_UINT32_SUB_ARRAY(env.vfp.xregs, ARMCPU, 2, 14), 91 { 92 .name = "fpscr", 93 .version_id = 0, 94 .size = sizeof(uint32_t), 95 .info = &vmstate_fpscr, 96 .flags = VMS_SINGLE, 97 .offset = 0, 98 }, 99 VMSTATE_END_OF_LIST() 100 } 101 }; 102 103 static bool iwmmxt_needed(void *opaque) 104 { 105 ARMCPU *cpu = opaque; 106 CPUARMState *env = &cpu->env; 107 108 return arm_feature(env, ARM_FEATURE_IWMMXT); 109 } 110 111 static const VMStateDescription vmstate_iwmmxt = { 112 .name = "cpu/iwmmxt", 113 .version_id = 1, 114 .minimum_version_id = 1, 115 .needed = iwmmxt_needed, 116 .fields = (VMStateField[]) { 117 VMSTATE_UINT64_ARRAY(env.iwmmxt.regs, ARMCPU, 16), 118 VMSTATE_UINT32_ARRAY(env.iwmmxt.cregs, ARMCPU, 16), 119 VMSTATE_END_OF_LIST() 120 } 121 }; 122 123 #ifdef TARGET_AARCH64 124 /* The expression ARM_MAX_VQ - 2 is 0 for pure AArch32 build, 125 * and ARMPredicateReg is actively empty. This triggers errors 126 * in the expansion of the VMSTATE macros. 127 */ 128 129 static bool sve_needed(void *opaque) 130 { 131 ARMCPU *cpu = opaque; 132 133 return cpu_isar_feature(aa64_sve, cpu); 134 } 135 136 /* The first two words of each Zreg is stored in VFP state. */ 137 static const VMStateDescription vmstate_zreg_hi_reg = { 138 .name = "cpu/sve/zreg_hi", 139 .version_id = 1, 140 .minimum_version_id = 1, 141 .fields = (VMStateField[]) { 142 VMSTATE_UINT64_SUB_ARRAY(d, ARMVectorReg, 2, ARM_MAX_VQ - 2), 143 VMSTATE_END_OF_LIST() 144 } 145 }; 146 147 static const VMStateDescription vmstate_preg_reg = { 148 .name = "cpu/sve/preg", 149 .version_id = 1, 150 .minimum_version_id = 1, 151 .fields = (VMStateField[]) { 152 VMSTATE_UINT64_ARRAY(p, ARMPredicateReg, 2 * ARM_MAX_VQ / 8), 153 VMSTATE_END_OF_LIST() 154 } 155 }; 156 157 static const VMStateDescription vmstate_sve = { 158 .name = "cpu/sve", 159 .version_id = 1, 160 .minimum_version_id = 1, 161 .needed = sve_needed, 162 .fields = (VMStateField[]) { 163 VMSTATE_STRUCT_ARRAY(env.vfp.zregs, ARMCPU, 32, 0, 164 vmstate_zreg_hi_reg, ARMVectorReg), 165 VMSTATE_STRUCT_ARRAY(env.vfp.pregs, ARMCPU, 17, 0, 166 vmstate_preg_reg, ARMPredicateReg), 167 VMSTATE_END_OF_LIST() 168 } 169 }; 170 171 static const VMStateDescription vmstate_vreg = { 172 .name = "vreg", 173 .version_id = 1, 174 .minimum_version_id = 1, 175 .fields = (VMStateField[]) { 176 VMSTATE_UINT64_ARRAY(d, ARMVectorReg, ARM_MAX_VQ * 2), 177 VMSTATE_END_OF_LIST() 178 } 179 }; 180 181 static bool za_needed(void *opaque) 182 { 183 ARMCPU *cpu = opaque; 184 185 /* 186 * When ZA storage is disabled, its contents are discarded. 187 * It will be zeroed when ZA storage is re-enabled. 188 */ 189 return FIELD_EX64(cpu->env.svcr, SVCR, ZA); 190 } 191 192 static const VMStateDescription vmstate_za = { 193 .name = "cpu/sme", 194 .version_id = 1, 195 .minimum_version_id = 1, 196 .needed = za_needed, 197 .fields = (VMStateField[]) { 198 VMSTATE_STRUCT_ARRAY(env.zarray, ARMCPU, ARM_MAX_VQ * 16, 0, 199 vmstate_vreg, ARMVectorReg), 200 VMSTATE_END_OF_LIST() 201 } 202 }; 203 #endif /* AARCH64 */ 204 205 static bool serror_needed(void *opaque) 206 { 207 ARMCPU *cpu = opaque; 208 CPUARMState *env = &cpu->env; 209 210 return env->serror.pending != 0; 211 } 212 213 static const VMStateDescription vmstate_serror = { 214 .name = "cpu/serror", 215 .version_id = 1, 216 .minimum_version_id = 1, 217 .needed = serror_needed, 218 .fields = (VMStateField[]) { 219 VMSTATE_UINT8(env.serror.pending, ARMCPU), 220 VMSTATE_UINT8(env.serror.has_esr, ARMCPU), 221 VMSTATE_UINT64(env.serror.esr, ARMCPU), 222 VMSTATE_END_OF_LIST() 223 } 224 }; 225 226 static bool irq_line_state_needed(void *opaque) 227 { 228 return true; 229 } 230 231 static const VMStateDescription vmstate_irq_line_state = { 232 .name = "cpu/irq-line-state", 233 .version_id = 1, 234 .minimum_version_id = 1, 235 .needed = irq_line_state_needed, 236 .fields = (VMStateField[]) { 237 VMSTATE_UINT32(env.irq_line_state, ARMCPU), 238 VMSTATE_END_OF_LIST() 239 } 240 }; 241 242 static bool m_needed(void *opaque) 243 { 244 ARMCPU *cpu = opaque; 245 CPUARMState *env = &cpu->env; 246 247 return arm_feature(env, ARM_FEATURE_M); 248 } 249 250 static const VMStateDescription vmstate_m_faultmask_primask = { 251 .name = "cpu/m/faultmask-primask", 252 .version_id = 1, 253 .minimum_version_id = 1, 254 .needed = m_needed, 255 .fields = (VMStateField[]) { 256 VMSTATE_UINT32(env.v7m.faultmask[M_REG_NS], ARMCPU), 257 VMSTATE_UINT32(env.v7m.primask[M_REG_NS], ARMCPU), 258 VMSTATE_END_OF_LIST() 259 } 260 }; 261 262 /* CSSELR is in a subsection because we didn't implement it previously. 263 * Migration from an old implementation will leave it at zero, which 264 * is OK since the only CPUs in the old implementation make the 265 * register RAZ/WI. 266 * Since there was no version of QEMU which implemented the CSSELR for 267 * just non-secure, we transfer both banks here rather than putting 268 * the secure banked version in the m-security subsection. 269 */ 270 static bool csselr_vmstate_validate(void *opaque, int version_id) 271 { 272 ARMCPU *cpu = opaque; 273 274 return cpu->env.v7m.csselr[M_REG_NS] <= R_V7M_CSSELR_INDEX_MASK 275 && cpu->env.v7m.csselr[M_REG_S] <= R_V7M_CSSELR_INDEX_MASK; 276 } 277 278 static bool m_csselr_needed(void *opaque) 279 { 280 ARMCPU *cpu = opaque; 281 282 return !arm_v7m_csselr_razwi(cpu); 283 } 284 285 static const VMStateDescription vmstate_m_csselr = { 286 .name = "cpu/m/csselr", 287 .version_id = 1, 288 .minimum_version_id = 1, 289 .needed = m_csselr_needed, 290 .fields = (VMStateField[]) { 291 VMSTATE_UINT32_ARRAY(env.v7m.csselr, ARMCPU, M_REG_NUM_BANKS), 292 VMSTATE_VALIDATE("CSSELR is valid", csselr_vmstate_validate), 293 VMSTATE_END_OF_LIST() 294 } 295 }; 296 297 static const VMStateDescription vmstate_m_scr = { 298 .name = "cpu/m/scr", 299 .version_id = 1, 300 .minimum_version_id = 1, 301 .needed = m_needed, 302 .fields = (VMStateField[]) { 303 VMSTATE_UINT32(env.v7m.scr[M_REG_NS], ARMCPU), 304 VMSTATE_END_OF_LIST() 305 } 306 }; 307 308 static const VMStateDescription vmstate_m_other_sp = { 309 .name = "cpu/m/other-sp", 310 .version_id = 1, 311 .minimum_version_id = 1, 312 .needed = m_needed, 313 .fields = (VMStateField[]) { 314 VMSTATE_UINT32(env.v7m.other_sp, ARMCPU), 315 VMSTATE_END_OF_LIST() 316 } 317 }; 318 319 static bool m_v8m_needed(void *opaque) 320 { 321 ARMCPU *cpu = opaque; 322 CPUARMState *env = &cpu->env; 323 324 return arm_feature(env, ARM_FEATURE_M) && arm_feature(env, ARM_FEATURE_V8); 325 } 326 327 static const VMStateDescription vmstate_m_v8m = { 328 .name = "cpu/m/v8m", 329 .version_id = 1, 330 .minimum_version_id = 1, 331 .needed = m_v8m_needed, 332 .fields = (VMStateField[]) { 333 VMSTATE_UINT32_ARRAY(env.v7m.msplim, ARMCPU, M_REG_NUM_BANKS), 334 VMSTATE_UINT32_ARRAY(env.v7m.psplim, ARMCPU, M_REG_NUM_BANKS), 335 VMSTATE_END_OF_LIST() 336 } 337 }; 338 339 static const VMStateDescription vmstate_m_fp = { 340 .name = "cpu/m/fp", 341 .version_id = 1, 342 .minimum_version_id = 1, 343 .needed = vfp_needed, 344 .fields = (VMStateField[]) { 345 VMSTATE_UINT32_ARRAY(env.v7m.fpcar, ARMCPU, M_REG_NUM_BANKS), 346 VMSTATE_UINT32_ARRAY(env.v7m.fpccr, ARMCPU, M_REG_NUM_BANKS), 347 VMSTATE_UINT32_ARRAY(env.v7m.fpdscr, ARMCPU, M_REG_NUM_BANKS), 348 VMSTATE_UINT32_ARRAY(env.v7m.cpacr, ARMCPU, M_REG_NUM_BANKS), 349 VMSTATE_UINT32(env.v7m.nsacr, ARMCPU), 350 VMSTATE_END_OF_LIST() 351 } 352 }; 353 354 static bool mve_needed(void *opaque) 355 { 356 ARMCPU *cpu = opaque; 357 358 return cpu_isar_feature(aa32_mve, cpu); 359 } 360 361 static const VMStateDescription vmstate_m_mve = { 362 .name = "cpu/m/mve", 363 .version_id = 1, 364 .minimum_version_id = 1, 365 .needed = mve_needed, 366 .fields = (VMStateField[]) { 367 VMSTATE_UINT32(env.v7m.vpr, ARMCPU), 368 VMSTATE_UINT32(env.v7m.ltpsize, ARMCPU), 369 VMSTATE_END_OF_LIST() 370 }, 371 }; 372 373 static const VMStateDescription vmstate_m = { 374 .name = "cpu/m", 375 .version_id = 4, 376 .minimum_version_id = 4, 377 .needed = m_needed, 378 .fields = (VMStateField[]) { 379 VMSTATE_UINT32(env.v7m.vecbase[M_REG_NS], ARMCPU), 380 VMSTATE_UINT32(env.v7m.basepri[M_REG_NS], ARMCPU), 381 VMSTATE_UINT32(env.v7m.control[M_REG_NS], ARMCPU), 382 VMSTATE_UINT32(env.v7m.ccr[M_REG_NS], ARMCPU), 383 VMSTATE_UINT32(env.v7m.cfsr[M_REG_NS], ARMCPU), 384 VMSTATE_UINT32(env.v7m.hfsr, ARMCPU), 385 VMSTATE_UINT32(env.v7m.dfsr, ARMCPU), 386 VMSTATE_UINT32(env.v7m.mmfar[M_REG_NS], ARMCPU), 387 VMSTATE_UINT32(env.v7m.bfar, ARMCPU), 388 VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_NS], ARMCPU), 389 VMSTATE_INT32(env.v7m.exception, ARMCPU), 390 VMSTATE_END_OF_LIST() 391 }, 392 .subsections = (const VMStateDescription*[]) { 393 &vmstate_m_faultmask_primask, 394 &vmstate_m_csselr, 395 &vmstate_m_scr, 396 &vmstate_m_other_sp, 397 &vmstate_m_v8m, 398 &vmstate_m_fp, 399 &vmstate_m_mve, 400 NULL 401 } 402 }; 403 404 static bool thumb2ee_needed(void *opaque) 405 { 406 ARMCPU *cpu = opaque; 407 CPUARMState *env = &cpu->env; 408 409 return arm_feature(env, ARM_FEATURE_THUMB2EE); 410 } 411 412 static const VMStateDescription vmstate_thumb2ee = { 413 .name = "cpu/thumb2ee", 414 .version_id = 1, 415 .minimum_version_id = 1, 416 .needed = thumb2ee_needed, 417 .fields = (VMStateField[]) { 418 VMSTATE_UINT32(env.teecr, ARMCPU), 419 VMSTATE_UINT32(env.teehbr, ARMCPU), 420 VMSTATE_END_OF_LIST() 421 } 422 }; 423 424 static bool pmsav7_needed(void *opaque) 425 { 426 ARMCPU *cpu = opaque; 427 CPUARMState *env = &cpu->env; 428 429 return arm_feature(env, ARM_FEATURE_PMSA) && 430 arm_feature(env, ARM_FEATURE_V7) && 431 !arm_feature(env, ARM_FEATURE_V8); 432 } 433 434 static bool pmsav7_rgnr_vmstate_validate(void *opaque, int version_id) 435 { 436 ARMCPU *cpu = opaque; 437 438 return cpu->env.pmsav7.rnr[M_REG_NS] < cpu->pmsav7_dregion; 439 } 440 441 static const VMStateDescription vmstate_pmsav7 = { 442 .name = "cpu/pmsav7", 443 .version_id = 1, 444 .minimum_version_id = 1, 445 .needed = pmsav7_needed, 446 .fields = (VMStateField[]) { 447 VMSTATE_VARRAY_UINT32(env.pmsav7.drbar, ARMCPU, pmsav7_dregion, 0, 448 vmstate_info_uint32, uint32_t), 449 VMSTATE_VARRAY_UINT32(env.pmsav7.drsr, ARMCPU, pmsav7_dregion, 0, 450 vmstate_info_uint32, uint32_t), 451 VMSTATE_VARRAY_UINT32(env.pmsav7.dracr, ARMCPU, pmsav7_dregion, 0, 452 vmstate_info_uint32, uint32_t), 453 VMSTATE_VALIDATE("rgnr is valid", pmsav7_rgnr_vmstate_validate), 454 VMSTATE_END_OF_LIST() 455 } 456 }; 457 458 static bool pmsav7_rnr_needed(void *opaque) 459 { 460 ARMCPU *cpu = opaque; 461 CPUARMState *env = &cpu->env; 462 463 /* For R profile cores pmsav7.rnr is migrated via the cpreg 464 * "RGNR" definition in helper.h. For M profile we have to 465 * migrate it separately. 466 */ 467 return arm_feature(env, ARM_FEATURE_M); 468 } 469 470 static const VMStateDescription vmstate_pmsav7_rnr = { 471 .name = "cpu/pmsav7-rnr", 472 .version_id = 1, 473 .minimum_version_id = 1, 474 .needed = pmsav7_rnr_needed, 475 .fields = (VMStateField[]) { 476 VMSTATE_UINT32(env.pmsav7.rnr[M_REG_NS], ARMCPU), 477 VMSTATE_END_OF_LIST() 478 } 479 }; 480 481 static bool pmsav8_needed(void *opaque) 482 { 483 ARMCPU *cpu = opaque; 484 CPUARMState *env = &cpu->env; 485 486 return arm_feature(env, ARM_FEATURE_PMSA) && 487 arm_feature(env, ARM_FEATURE_V8); 488 } 489 490 static bool pmsav8r_needed(void *opaque) 491 { 492 ARMCPU *cpu = opaque; 493 CPUARMState *env = &cpu->env; 494 495 return arm_feature(env, ARM_FEATURE_PMSA) && 496 arm_feature(env, ARM_FEATURE_V8) && 497 !arm_feature(env, ARM_FEATURE_M); 498 } 499 500 static const VMStateDescription vmstate_pmsav8r = { 501 .name = "cpu/pmsav8/pmsav8r", 502 .version_id = 1, 503 .minimum_version_id = 1, 504 .needed = pmsav8r_needed, 505 .fields = (VMStateField[]) { 506 VMSTATE_VARRAY_UINT32(env.pmsav8.hprbar, ARMCPU, 507 pmsav8r_hdregion, 0, vmstate_info_uint32, uint32_t), 508 VMSTATE_VARRAY_UINT32(env.pmsav8.hprlar, ARMCPU, 509 pmsav8r_hdregion, 0, vmstate_info_uint32, uint32_t), 510 VMSTATE_END_OF_LIST() 511 }, 512 }; 513 514 static const VMStateDescription vmstate_pmsav8 = { 515 .name = "cpu/pmsav8", 516 .version_id = 1, 517 .minimum_version_id = 1, 518 .needed = pmsav8_needed, 519 .fields = (VMStateField[]) { 520 VMSTATE_VARRAY_UINT32(env.pmsav8.rbar[M_REG_NS], ARMCPU, pmsav7_dregion, 521 0, vmstate_info_uint32, uint32_t), 522 VMSTATE_VARRAY_UINT32(env.pmsav8.rlar[M_REG_NS], ARMCPU, pmsav7_dregion, 523 0, vmstate_info_uint32, uint32_t), 524 VMSTATE_UINT32(env.pmsav8.mair0[M_REG_NS], ARMCPU), 525 VMSTATE_UINT32(env.pmsav8.mair1[M_REG_NS], ARMCPU), 526 VMSTATE_END_OF_LIST() 527 }, 528 .subsections = (const VMStateDescription * []) { 529 &vmstate_pmsav8r, 530 NULL 531 } 532 }; 533 534 static bool s_rnr_vmstate_validate(void *opaque, int version_id) 535 { 536 ARMCPU *cpu = opaque; 537 538 return cpu->env.pmsav7.rnr[M_REG_S] < cpu->pmsav7_dregion; 539 } 540 541 static bool sau_rnr_vmstate_validate(void *opaque, int version_id) 542 { 543 ARMCPU *cpu = opaque; 544 545 return cpu->env.sau.rnr < cpu->sau_sregion; 546 } 547 548 static bool m_security_needed(void *opaque) 549 { 550 ARMCPU *cpu = opaque; 551 CPUARMState *env = &cpu->env; 552 553 return arm_feature(env, ARM_FEATURE_M_SECURITY); 554 } 555 556 static const VMStateDescription vmstate_m_security = { 557 .name = "cpu/m-security", 558 .version_id = 1, 559 .minimum_version_id = 1, 560 .needed = m_security_needed, 561 .fields = (VMStateField[]) { 562 VMSTATE_UINT32(env.v7m.secure, ARMCPU), 563 VMSTATE_UINT32(env.v7m.other_ss_msp, ARMCPU), 564 VMSTATE_UINT32(env.v7m.other_ss_psp, ARMCPU), 565 VMSTATE_UINT32(env.v7m.basepri[M_REG_S], ARMCPU), 566 VMSTATE_UINT32(env.v7m.primask[M_REG_S], ARMCPU), 567 VMSTATE_UINT32(env.v7m.faultmask[M_REG_S], ARMCPU), 568 VMSTATE_UINT32(env.v7m.control[M_REG_S], ARMCPU), 569 VMSTATE_UINT32(env.v7m.vecbase[M_REG_S], ARMCPU), 570 VMSTATE_UINT32(env.pmsav8.mair0[M_REG_S], ARMCPU), 571 VMSTATE_UINT32(env.pmsav8.mair1[M_REG_S], ARMCPU), 572 VMSTATE_VARRAY_UINT32(env.pmsav8.rbar[M_REG_S], ARMCPU, pmsav7_dregion, 573 0, vmstate_info_uint32, uint32_t), 574 VMSTATE_VARRAY_UINT32(env.pmsav8.rlar[M_REG_S], ARMCPU, pmsav7_dregion, 575 0, vmstate_info_uint32, uint32_t), 576 VMSTATE_UINT32(env.pmsav7.rnr[M_REG_S], ARMCPU), 577 VMSTATE_VALIDATE("secure MPU_RNR is valid", s_rnr_vmstate_validate), 578 VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_S], ARMCPU), 579 VMSTATE_UINT32(env.v7m.ccr[M_REG_S], ARMCPU), 580 VMSTATE_UINT32(env.v7m.mmfar[M_REG_S], ARMCPU), 581 VMSTATE_UINT32(env.v7m.cfsr[M_REG_S], ARMCPU), 582 VMSTATE_UINT32(env.v7m.sfsr, ARMCPU), 583 VMSTATE_UINT32(env.v7m.sfar, ARMCPU), 584 VMSTATE_VARRAY_UINT32(env.sau.rbar, ARMCPU, sau_sregion, 0, 585 vmstate_info_uint32, uint32_t), 586 VMSTATE_VARRAY_UINT32(env.sau.rlar, ARMCPU, sau_sregion, 0, 587 vmstate_info_uint32, uint32_t), 588 VMSTATE_UINT32(env.sau.rnr, ARMCPU), 589 VMSTATE_VALIDATE("SAU_RNR is valid", sau_rnr_vmstate_validate), 590 VMSTATE_UINT32(env.sau.ctrl, ARMCPU), 591 VMSTATE_UINT32(env.v7m.scr[M_REG_S], ARMCPU), 592 /* AIRCR is not secure-only, but our implementation is R/O if the 593 * security extension is unimplemented, so we migrate it here. 594 */ 595 VMSTATE_UINT32(env.v7m.aircr, ARMCPU), 596 VMSTATE_END_OF_LIST() 597 } 598 }; 599 600 static int get_cpsr(QEMUFile *f, void *opaque, size_t size, 601 const VMStateField *field) 602 { 603 ARMCPU *cpu = opaque; 604 CPUARMState *env = &cpu->env; 605 uint32_t val = qemu_get_be32(f); 606 607 if (arm_feature(env, ARM_FEATURE_M)) { 608 if (val & XPSR_EXCP) { 609 /* This is a CPSR format value from an older QEMU. (We can tell 610 * because values transferred in XPSR format always have zero 611 * for the EXCP field, and CPSR format will always have bit 4 612 * set in CPSR_M.) Rearrange it into XPSR format. The significant 613 * differences are that the T bit is not in the same place, the 614 * primask/faultmask info may be in the CPSR I and F bits, and 615 * we do not want the mode bits. 616 * We know that this cleanup happened before v8M, so there 617 * is no complication with banked primask/faultmask. 618 */ 619 uint32_t newval = val; 620 621 assert(!arm_feature(env, ARM_FEATURE_M_SECURITY)); 622 623 newval &= (CPSR_NZCV | CPSR_Q | CPSR_IT | CPSR_GE); 624 if (val & CPSR_T) { 625 newval |= XPSR_T; 626 } 627 /* If the I or F bits are set then this is a migration from 628 * an old QEMU which still stored the M profile FAULTMASK 629 * and PRIMASK in env->daif. For a new QEMU, the data is 630 * transferred using the vmstate_m_faultmask_primask subsection. 631 */ 632 if (val & CPSR_F) { 633 env->v7m.faultmask[M_REG_NS] = 1; 634 } 635 if (val & CPSR_I) { 636 env->v7m.primask[M_REG_NS] = 1; 637 } 638 val = newval; 639 } 640 /* Ignore the low bits, they are handled by vmstate_m. */ 641 xpsr_write(env, val, ~XPSR_EXCP); 642 return 0; 643 } 644 645 env->aarch64 = ((val & PSTATE_nRW) == 0); 646 647 if (is_a64(env)) { 648 pstate_write(env, val); 649 return 0; 650 } 651 652 cpsr_write(env, val, 0xffffffff, CPSRWriteRaw); 653 return 0; 654 } 655 656 static int put_cpsr(QEMUFile *f, void *opaque, size_t size, 657 const VMStateField *field, JSONWriter *vmdesc) 658 { 659 ARMCPU *cpu = opaque; 660 CPUARMState *env = &cpu->env; 661 uint32_t val; 662 663 if (arm_feature(env, ARM_FEATURE_M)) { 664 /* The low 9 bits are v7m.exception, which is handled by vmstate_m. */ 665 val = xpsr_read(env) & ~XPSR_EXCP; 666 } else if (is_a64(env)) { 667 val = pstate_read(env); 668 } else { 669 val = cpsr_read(env); 670 } 671 672 qemu_put_be32(f, val); 673 return 0; 674 } 675 676 static const VMStateInfo vmstate_cpsr = { 677 .name = "cpsr", 678 .get = get_cpsr, 679 .put = put_cpsr, 680 }; 681 682 static int get_power(QEMUFile *f, void *opaque, size_t size, 683 const VMStateField *field) 684 { 685 ARMCPU *cpu = opaque; 686 bool powered_off = qemu_get_byte(f); 687 cpu->power_state = powered_off ? PSCI_OFF : PSCI_ON; 688 return 0; 689 } 690 691 static int put_power(QEMUFile *f, void *opaque, size_t size, 692 const VMStateField *field, JSONWriter *vmdesc) 693 { 694 ARMCPU *cpu = opaque; 695 696 /* Migration should never happen while we transition power states */ 697 698 if (cpu->power_state == PSCI_ON || 699 cpu->power_state == PSCI_OFF) { 700 bool powered_off = (cpu->power_state == PSCI_OFF) ? true : false; 701 qemu_put_byte(f, powered_off); 702 return 0; 703 } else { 704 return 1; 705 } 706 } 707 708 static const VMStateInfo vmstate_powered_off = { 709 .name = "powered_off", 710 .get = get_power, 711 .put = put_power, 712 }; 713 714 static int cpu_pre_save(void *opaque) 715 { 716 ARMCPU *cpu = opaque; 717 718 if (!kvm_enabled()) { 719 pmu_op_start(&cpu->env); 720 } 721 722 if (kvm_enabled()) { 723 if (!write_kvmstate_to_list(cpu)) { 724 /* This should never fail */ 725 g_assert_not_reached(); 726 } 727 728 /* 729 * kvm_arm_cpu_pre_save() must be called after 730 * write_kvmstate_to_list() 731 */ 732 kvm_arm_cpu_pre_save(cpu); 733 } else { 734 if (!write_cpustate_to_list(cpu, false)) { 735 /* This should never fail. */ 736 g_assert_not_reached(); 737 } 738 } 739 740 cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len; 741 memcpy(cpu->cpreg_vmstate_indexes, cpu->cpreg_indexes, 742 cpu->cpreg_array_len * sizeof(uint64_t)); 743 memcpy(cpu->cpreg_vmstate_values, cpu->cpreg_values, 744 cpu->cpreg_array_len * sizeof(uint64_t)); 745 746 return 0; 747 } 748 749 static int cpu_post_save(void *opaque) 750 { 751 ARMCPU *cpu = opaque; 752 753 if (!kvm_enabled()) { 754 pmu_op_finish(&cpu->env); 755 } 756 757 return 0; 758 } 759 760 static int cpu_pre_load(void *opaque) 761 { 762 ARMCPU *cpu = opaque; 763 CPUARMState *env = &cpu->env; 764 765 /* 766 * Pre-initialize irq_line_state to a value that's never valid as 767 * real data, so cpu_post_load() can tell whether we've seen the 768 * irq-line-state subsection in the incoming migration state. 769 */ 770 env->irq_line_state = UINT32_MAX; 771 772 if (!kvm_enabled()) { 773 pmu_op_start(&cpu->env); 774 } 775 776 return 0; 777 } 778 779 static int cpu_post_load(void *opaque, int version_id) 780 { 781 ARMCPU *cpu = opaque; 782 CPUARMState *env = &cpu->env; 783 int i, v; 784 785 /* 786 * Handle migration compatibility from old QEMU which didn't 787 * send the irq-line-state subsection. A QEMU without it did not 788 * implement the HCR_EL2.{VI,VF} bits as generating interrupts, 789 * so for TCG the line state matches the bits set in cs->interrupt_request. 790 * For KVM the line state is not stored in cs->interrupt_request 791 * and so this will leave irq_line_state as 0, but this is OK because 792 * we only need to care about it for TCG. 793 */ 794 if (env->irq_line_state == UINT32_MAX) { 795 CPUState *cs = CPU(cpu); 796 797 env->irq_line_state = cs->interrupt_request & 798 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIQ | 799 CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VFIQ); 800 } 801 802 /* Update the values list from the incoming migration data. 803 * Anything in the incoming data which we don't know about is 804 * a migration failure; anything we know about but the incoming 805 * data doesn't specify retains its current (reset) value. 806 * The indexes list remains untouched -- we only inspect the 807 * incoming migration index list so we can match the values array 808 * entries with the right slots in our own values array. 809 */ 810 811 for (i = 0, v = 0; i < cpu->cpreg_array_len 812 && v < cpu->cpreg_vmstate_array_len; i++) { 813 if (cpu->cpreg_vmstate_indexes[v] > cpu->cpreg_indexes[i]) { 814 /* register in our list but not incoming : skip it */ 815 continue; 816 } 817 if (cpu->cpreg_vmstate_indexes[v] < cpu->cpreg_indexes[i]) { 818 /* register in their list but not ours: fail migration */ 819 return -1; 820 } 821 /* matching register, copy the value over */ 822 cpu->cpreg_values[i] = cpu->cpreg_vmstate_values[v]; 823 v++; 824 } 825 826 if (kvm_enabled()) { 827 if (!write_list_to_kvmstate(cpu, KVM_PUT_FULL_STATE)) { 828 return -1; 829 } 830 /* Note that it's OK for the TCG side not to know about 831 * every register in the list; KVM is authoritative if 832 * we're using it. 833 */ 834 write_list_to_cpustate(cpu); 835 kvm_arm_cpu_post_load(cpu); 836 } else { 837 if (!write_list_to_cpustate(cpu)) { 838 return -1; 839 } 840 } 841 842 /* 843 * Misaligned thumb pc is architecturally impossible. Fail the 844 * incoming migration. For TCG it would trigger the assert in 845 * thumb_tr_translate_insn(). 846 */ 847 if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) { 848 return -1; 849 } 850 851 hw_breakpoint_update_all(cpu); 852 hw_watchpoint_update_all(cpu); 853 854 /* 855 * TCG gen_update_fp_context() relies on the invariant that 856 * FPDSCR.LTPSIZE is constant 4 for M-profile with the LOB extension; 857 * forbid bogus incoming data with some other value. 858 */ 859 if (arm_feature(env, ARM_FEATURE_M) && cpu_isar_feature(aa32_lob, cpu)) { 860 if (extract32(env->v7m.fpdscr[M_REG_NS], 861 FPCR_LTPSIZE_SHIFT, FPCR_LTPSIZE_LENGTH) != 4 || 862 extract32(env->v7m.fpdscr[M_REG_S], 863 FPCR_LTPSIZE_SHIFT, FPCR_LTPSIZE_LENGTH) != 4) { 864 return -1; 865 } 866 } 867 868 if (!kvm_enabled()) { 869 pmu_op_finish(&cpu->env); 870 } 871 arm_rebuild_hflags(&cpu->env); 872 873 return 0; 874 } 875 876 const VMStateDescription vmstate_arm_cpu = { 877 .name = "cpu", 878 .version_id = 22, 879 .minimum_version_id = 22, 880 .pre_save = cpu_pre_save, 881 .post_save = cpu_post_save, 882 .pre_load = cpu_pre_load, 883 .post_load = cpu_post_load, 884 .fields = (VMStateField[]) { 885 VMSTATE_UINT32_ARRAY(env.regs, ARMCPU, 16), 886 VMSTATE_UINT64_ARRAY(env.xregs, ARMCPU, 32), 887 VMSTATE_UINT64(env.pc, ARMCPU), 888 { 889 .name = "cpsr", 890 .version_id = 0, 891 .size = sizeof(uint32_t), 892 .info = &vmstate_cpsr, 893 .flags = VMS_SINGLE, 894 .offset = 0, 895 }, 896 VMSTATE_UINT32(env.spsr, ARMCPU), 897 VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 8), 898 VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 8), 899 VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 8), 900 VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5), 901 VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5), 902 VMSTATE_UINT64_ARRAY(env.elr_el, ARMCPU, 4), 903 VMSTATE_UINT64_ARRAY(env.sp_el, ARMCPU, 4), 904 /* The length-check must come before the arrays to avoid 905 * incoming data possibly overflowing the array. 906 */ 907 VMSTATE_INT32_POSITIVE_LE(cpreg_vmstate_array_len, ARMCPU), 908 VMSTATE_VARRAY_INT32(cpreg_vmstate_indexes, ARMCPU, 909 cpreg_vmstate_array_len, 910 0, vmstate_info_uint64, uint64_t), 911 VMSTATE_VARRAY_INT32(cpreg_vmstate_values, ARMCPU, 912 cpreg_vmstate_array_len, 913 0, vmstate_info_uint64, uint64_t), 914 VMSTATE_UINT64(env.exclusive_addr, ARMCPU), 915 VMSTATE_UINT64(env.exclusive_val, ARMCPU), 916 VMSTATE_UINT64(env.exclusive_high, ARMCPU), 917 VMSTATE_UNUSED(sizeof(uint64_t)), 918 VMSTATE_UINT32(env.exception.syndrome, ARMCPU), 919 VMSTATE_UINT32(env.exception.fsr, ARMCPU), 920 VMSTATE_UINT64(env.exception.vaddress, ARMCPU), 921 VMSTATE_TIMER_PTR(gt_timer[GTIMER_PHYS], ARMCPU), 922 VMSTATE_TIMER_PTR(gt_timer[GTIMER_VIRT], ARMCPU), 923 { 924 .name = "power_state", 925 .version_id = 0, 926 .size = sizeof(bool), 927 .info = &vmstate_powered_off, 928 .flags = VMS_SINGLE, 929 .offset = 0, 930 }, 931 VMSTATE_END_OF_LIST() 932 }, 933 .subsections = (const VMStateDescription*[]) { 934 &vmstate_vfp, 935 &vmstate_iwmmxt, 936 &vmstate_m, 937 &vmstate_thumb2ee, 938 /* pmsav7_rnr must come before pmsav7 so that we have the 939 * region number before we test it in the VMSTATE_VALIDATE 940 * in vmstate_pmsav7. 941 */ 942 &vmstate_pmsav7_rnr, 943 &vmstate_pmsav7, 944 &vmstate_pmsav8, 945 &vmstate_m_security, 946 #ifdef TARGET_AARCH64 947 &vmstate_sve, 948 &vmstate_za, 949 #endif 950 &vmstate_serror, 951 &vmstate_irq_line_state, 952 NULL 953 } 954 }; 955