1 #include "qemu/osdep.h" 2 #include "qemu-common.h" 3 #include "cpu.h" 4 #include "hw/hw.h" 5 #include "hw/boards.h" 6 #include "qemu/error-report.h" 7 #include "sysemu/kvm.h" 8 #include "kvm_arm.h" 9 #include "internals.h" 10 #include "migration/cpu.h" 11 12 static bool vfp_needed(void *opaque) 13 { 14 ARMCPU *cpu = opaque; 15 CPUARMState *env = &cpu->env; 16 17 return arm_feature(env, ARM_FEATURE_VFP); 18 } 19 20 static int get_fpscr(QEMUFile *f, void *opaque, size_t size, 21 VMStateField *field) 22 { 23 ARMCPU *cpu = opaque; 24 CPUARMState *env = &cpu->env; 25 uint32_t val = qemu_get_be32(f); 26 27 vfp_set_fpscr(env, val); 28 return 0; 29 } 30 31 static int put_fpscr(QEMUFile *f, void *opaque, size_t size, 32 VMStateField *field, QJSON *vmdesc) 33 { 34 ARMCPU *cpu = opaque; 35 CPUARMState *env = &cpu->env; 36 37 qemu_put_be32(f, vfp_get_fpscr(env)); 38 return 0; 39 } 40 41 static const VMStateInfo vmstate_fpscr = { 42 .name = "fpscr", 43 .get = get_fpscr, 44 .put = put_fpscr, 45 }; 46 47 static const VMStateDescription vmstate_vfp = { 48 .name = "cpu/vfp", 49 .version_id = 3, 50 .minimum_version_id = 3, 51 .needed = vfp_needed, 52 .fields = (VMStateField[]) { 53 /* For compatibility, store Qn out of Zn here. */ 54 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[0].d, ARMCPU, 0, 2), 55 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[1].d, ARMCPU, 0, 2), 56 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[2].d, ARMCPU, 0, 2), 57 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[3].d, ARMCPU, 0, 2), 58 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[4].d, ARMCPU, 0, 2), 59 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[5].d, ARMCPU, 0, 2), 60 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[6].d, ARMCPU, 0, 2), 61 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[7].d, ARMCPU, 0, 2), 62 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[8].d, ARMCPU, 0, 2), 63 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[9].d, ARMCPU, 0, 2), 64 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[10].d, ARMCPU, 0, 2), 65 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[11].d, ARMCPU, 0, 2), 66 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[12].d, ARMCPU, 0, 2), 67 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[13].d, ARMCPU, 0, 2), 68 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[14].d, ARMCPU, 0, 2), 69 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[15].d, ARMCPU, 0, 2), 70 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[16].d, ARMCPU, 0, 2), 71 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[17].d, ARMCPU, 0, 2), 72 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[18].d, ARMCPU, 0, 2), 73 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[19].d, ARMCPU, 0, 2), 74 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[20].d, ARMCPU, 0, 2), 75 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[21].d, ARMCPU, 0, 2), 76 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[22].d, ARMCPU, 0, 2), 77 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[23].d, ARMCPU, 0, 2), 78 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[24].d, ARMCPU, 0, 2), 79 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[25].d, ARMCPU, 0, 2), 80 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[26].d, ARMCPU, 0, 2), 81 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[27].d, ARMCPU, 0, 2), 82 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[28].d, ARMCPU, 0, 2), 83 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[29].d, ARMCPU, 0, 2), 84 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[30].d, ARMCPU, 0, 2), 85 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[31].d, ARMCPU, 0, 2), 86 87 /* The xregs array is a little awkward because element 1 (FPSCR) 88 * requires a specific accessor, so we have to split it up in 89 * the vmstate: 90 */ 91 VMSTATE_UINT32(env.vfp.xregs[0], ARMCPU), 92 VMSTATE_UINT32_SUB_ARRAY(env.vfp.xregs, ARMCPU, 2, 14), 93 { 94 .name = "fpscr", 95 .version_id = 0, 96 .size = sizeof(uint32_t), 97 .info = &vmstate_fpscr, 98 .flags = VMS_SINGLE, 99 .offset = 0, 100 }, 101 VMSTATE_END_OF_LIST() 102 } 103 }; 104 105 static bool iwmmxt_needed(void *opaque) 106 { 107 ARMCPU *cpu = opaque; 108 CPUARMState *env = &cpu->env; 109 110 return arm_feature(env, ARM_FEATURE_IWMMXT); 111 } 112 113 static const VMStateDescription vmstate_iwmmxt = { 114 .name = "cpu/iwmmxt", 115 .version_id = 1, 116 .minimum_version_id = 1, 117 .needed = iwmmxt_needed, 118 .fields = (VMStateField[]) { 119 VMSTATE_UINT64_ARRAY(env.iwmmxt.regs, ARMCPU, 16), 120 VMSTATE_UINT32_ARRAY(env.iwmmxt.cregs, ARMCPU, 16), 121 VMSTATE_END_OF_LIST() 122 } 123 }; 124 125 #ifdef TARGET_AARCH64 126 /* The expression ARM_MAX_VQ - 2 is 0 for pure AArch32 build, 127 * and ARMPredicateReg is actively empty. This triggers errors 128 * in the expansion of the VMSTATE macros. 129 */ 130 131 static bool sve_needed(void *opaque) 132 { 133 ARMCPU *cpu = opaque; 134 CPUARMState *env = &cpu->env; 135 136 return arm_feature(env, ARM_FEATURE_SVE); 137 } 138 139 /* The first two words of each Zreg is stored in VFP state. */ 140 static const VMStateDescription vmstate_zreg_hi_reg = { 141 .name = "cpu/sve/zreg_hi", 142 .version_id = 1, 143 .minimum_version_id = 1, 144 .fields = (VMStateField[]) { 145 VMSTATE_UINT64_SUB_ARRAY(d, ARMVectorReg, 2, ARM_MAX_VQ - 2), 146 VMSTATE_END_OF_LIST() 147 } 148 }; 149 150 static const VMStateDescription vmstate_preg_reg = { 151 .name = "cpu/sve/preg", 152 .version_id = 1, 153 .minimum_version_id = 1, 154 .fields = (VMStateField[]) { 155 VMSTATE_UINT64_ARRAY(p, ARMPredicateReg, 2 * ARM_MAX_VQ / 8), 156 VMSTATE_END_OF_LIST() 157 } 158 }; 159 160 static const VMStateDescription vmstate_sve = { 161 .name = "cpu/sve", 162 .version_id = 1, 163 .minimum_version_id = 1, 164 .needed = sve_needed, 165 .fields = (VMStateField[]) { 166 VMSTATE_STRUCT_ARRAY(env.vfp.zregs, ARMCPU, 32, 0, 167 vmstate_zreg_hi_reg, ARMVectorReg), 168 VMSTATE_STRUCT_ARRAY(env.vfp.pregs, ARMCPU, 17, 0, 169 vmstate_preg_reg, ARMPredicateReg), 170 VMSTATE_END_OF_LIST() 171 } 172 }; 173 #endif /* AARCH64 */ 174 175 static bool m_needed(void *opaque) 176 { 177 ARMCPU *cpu = opaque; 178 CPUARMState *env = &cpu->env; 179 180 return arm_feature(env, ARM_FEATURE_M); 181 } 182 183 static const VMStateDescription vmstate_m_faultmask_primask = { 184 .name = "cpu/m/faultmask-primask", 185 .version_id = 1, 186 .minimum_version_id = 1, 187 .fields = (VMStateField[]) { 188 VMSTATE_UINT32(env.v7m.faultmask[M_REG_NS], ARMCPU), 189 VMSTATE_UINT32(env.v7m.primask[M_REG_NS], ARMCPU), 190 VMSTATE_END_OF_LIST() 191 } 192 }; 193 194 /* CSSELR is in a subsection because we didn't implement it previously. 195 * Migration from an old implementation will leave it at zero, which 196 * is OK since the only CPUs in the old implementation make the 197 * register RAZ/WI. 198 * Since there was no version of QEMU which implemented the CSSELR for 199 * just non-secure, we transfer both banks here rather than putting 200 * the secure banked version in the m-security subsection. 201 */ 202 static bool csselr_vmstate_validate(void *opaque, int version_id) 203 { 204 ARMCPU *cpu = opaque; 205 206 return cpu->env.v7m.csselr[M_REG_NS] <= R_V7M_CSSELR_INDEX_MASK 207 && cpu->env.v7m.csselr[M_REG_S] <= R_V7M_CSSELR_INDEX_MASK; 208 } 209 210 static bool m_csselr_needed(void *opaque) 211 { 212 ARMCPU *cpu = opaque; 213 214 return !arm_v7m_csselr_razwi(cpu); 215 } 216 217 static const VMStateDescription vmstate_m_csselr = { 218 .name = "cpu/m/csselr", 219 .version_id = 1, 220 .minimum_version_id = 1, 221 .needed = m_csselr_needed, 222 .fields = (VMStateField[]) { 223 VMSTATE_UINT32_ARRAY(env.v7m.csselr, ARMCPU, M_REG_NUM_BANKS), 224 VMSTATE_VALIDATE("CSSELR is valid", csselr_vmstate_validate), 225 VMSTATE_END_OF_LIST() 226 } 227 }; 228 229 static const VMStateDescription vmstate_m_scr = { 230 .name = "cpu/m/scr", 231 .version_id = 1, 232 .minimum_version_id = 1, 233 .fields = (VMStateField[]) { 234 VMSTATE_UINT32(env.v7m.scr[M_REG_NS], ARMCPU), 235 VMSTATE_END_OF_LIST() 236 } 237 }; 238 239 static const VMStateDescription vmstate_m = { 240 .name = "cpu/m", 241 .version_id = 4, 242 .minimum_version_id = 4, 243 .needed = m_needed, 244 .fields = (VMStateField[]) { 245 VMSTATE_UINT32(env.v7m.vecbase[M_REG_NS], ARMCPU), 246 VMSTATE_UINT32(env.v7m.basepri[M_REG_NS], ARMCPU), 247 VMSTATE_UINT32(env.v7m.control[M_REG_NS], ARMCPU), 248 VMSTATE_UINT32(env.v7m.ccr[M_REG_NS], ARMCPU), 249 VMSTATE_UINT32(env.v7m.cfsr[M_REG_NS], ARMCPU), 250 VMSTATE_UINT32(env.v7m.hfsr, ARMCPU), 251 VMSTATE_UINT32(env.v7m.dfsr, ARMCPU), 252 VMSTATE_UINT32(env.v7m.mmfar[M_REG_NS], ARMCPU), 253 VMSTATE_UINT32(env.v7m.bfar, ARMCPU), 254 VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_NS], ARMCPU), 255 VMSTATE_INT32(env.v7m.exception, ARMCPU), 256 VMSTATE_END_OF_LIST() 257 }, 258 .subsections = (const VMStateDescription*[]) { 259 &vmstate_m_faultmask_primask, 260 &vmstate_m_csselr, 261 &vmstate_m_scr, 262 NULL 263 } 264 }; 265 266 static bool thumb2ee_needed(void *opaque) 267 { 268 ARMCPU *cpu = opaque; 269 CPUARMState *env = &cpu->env; 270 271 return arm_feature(env, ARM_FEATURE_THUMB2EE); 272 } 273 274 static const VMStateDescription vmstate_thumb2ee = { 275 .name = "cpu/thumb2ee", 276 .version_id = 1, 277 .minimum_version_id = 1, 278 .needed = thumb2ee_needed, 279 .fields = (VMStateField[]) { 280 VMSTATE_UINT32(env.teecr, ARMCPU), 281 VMSTATE_UINT32(env.teehbr, ARMCPU), 282 VMSTATE_END_OF_LIST() 283 } 284 }; 285 286 static bool pmsav7_needed(void *opaque) 287 { 288 ARMCPU *cpu = opaque; 289 CPUARMState *env = &cpu->env; 290 291 return arm_feature(env, ARM_FEATURE_PMSA) && 292 arm_feature(env, ARM_FEATURE_V7) && 293 !arm_feature(env, ARM_FEATURE_V8); 294 } 295 296 static bool pmsav7_rgnr_vmstate_validate(void *opaque, int version_id) 297 { 298 ARMCPU *cpu = opaque; 299 300 return cpu->env.pmsav7.rnr[M_REG_NS] < cpu->pmsav7_dregion; 301 } 302 303 static const VMStateDescription vmstate_pmsav7 = { 304 .name = "cpu/pmsav7", 305 .version_id = 1, 306 .minimum_version_id = 1, 307 .needed = pmsav7_needed, 308 .fields = (VMStateField[]) { 309 VMSTATE_VARRAY_UINT32(env.pmsav7.drbar, ARMCPU, pmsav7_dregion, 0, 310 vmstate_info_uint32, uint32_t), 311 VMSTATE_VARRAY_UINT32(env.pmsav7.drsr, ARMCPU, pmsav7_dregion, 0, 312 vmstate_info_uint32, uint32_t), 313 VMSTATE_VARRAY_UINT32(env.pmsav7.dracr, ARMCPU, pmsav7_dregion, 0, 314 vmstate_info_uint32, uint32_t), 315 VMSTATE_VALIDATE("rgnr is valid", pmsav7_rgnr_vmstate_validate), 316 VMSTATE_END_OF_LIST() 317 } 318 }; 319 320 static bool pmsav7_rnr_needed(void *opaque) 321 { 322 ARMCPU *cpu = opaque; 323 CPUARMState *env = &cpu->env; 324 325 /* For R profile cores pmsav7.rnr is migrated via the cpreg 326 * "RGNR" definition in helper.h. For M profile we have to 327 * migrate it separately. 328 */ 329 return arm_feature(env, ARM_FEATURE_M); 330 } 331 332 static const VMStateDescription vmstate_pmsav7_rnr = { 333 .name = "cpu/pmsav7-rnr", 334 .version_id = 1, 335 .minimum_version_id = 1, 336 .needed = pmsav7_rnr_needed, 337 .fields = (VMStateField[]) { 338 VMSTATE_UINT32(env.pmsav7.rnr[M_REG_NS], ARMCPU), 339 VMSTATE_END_OF_LIST() 340 } 341 }; 342 343 static bool pmsav8_needed(void *opaque) 344 { 345 ARMCPU *cpu = opaque; 346 CPUARMState *env = &cpu->env; 347 348 return arm_feature(env, ARM_FEATURE_PMSA) && 349 arm_feature(env, ARM_FEATURE_V8); 350 } 351 352 static const VMStateDescription vmstate_pmsav8 = { 353 .name = "cpu/pmsav8", 354 .version_id = 1, 355 .minimum_version_id = 1, 356 .needed = pmsav8_needed, 357 .fields = (VMStateField[]) { 358 VMSTATE_VARRAY_UINT32(env.pmsav8.rbar[M_REG_NS], ARMCPU, pmsav7_dregion, 359 0, vmstate_info_uint32, uint32_t), 360 VMSTATE_VARRAY_UINT32(env.pmsav8.rlar[M_REG_NS], ARMCPU, pmsav7_dregion, 361 0, vmstate_info_uint32, uint32_t), 362 VMSTATE_UINT32(env.pmsav8.mair0[M_REG_NS], ARMCPU), 363 VMSTATE_UINT32(env.pmsav8.mair1[M_REG_NS], ARMCPU), 364 VMSTATE_END_OF_LIST() 365 } 366 }; 367 368 static bool s_rnr_vmstate_validate(void *opaque, int version_id) 369 { 370 ARMCPU *cpu = opaque; 371 372 return cpu->env.pmsav7.rnr[M_REG_S] < cpu->pmsav7_dregion; 373 } 374 375 static bool sau_rnr_vmstate_validate(void *opaque, int version_id) 376 { 377 ARMCPU *cpu = opaque; 378 379 return cpu->env.sau.rnr < cpu->sau_sregion; 380 } 381 382 static bool m_security_needed(void *opaque) 383 { 384 ARMCPU *cpu = opaque; 385 CPUARMState *env = &cpu->env; 386 387 return arm_feature(env, ARM_FEATURE_M_SECURITY); 388 } 389 390 static const VMStateDescription vmstate_m_security = { 391 .name = "cpu/m-security", 392 .version_id = 1, 393 .minimum_version_id = 1, 394 .needed = m_security_needed, 395 .fields = (VMStateField[]) { 396 VMSTATE_UINT32(env.v7m.secure, ARMCPU), 397 VMSTATE_UINT32(env.v7m.other_ss_msp, ARMCPU), 398 VMSTATE_UINT32(env.v7m.other_ss_psp, ARMCPU), 399 VMSTATE_UINT32(env.v7m.basepri[M_REG_S], ARMCPU), 400 VMSTATE_UINT32(env.v7m.primask[M_REG_S], ARMCPU), 401 VMSTATE_UINT32(env.v7m.faultmask[M_REG_S], ARMCPU), 402 VMSTATE_UINT32(env.v7m.control[M_REG_S], ARMCPU), 403 VMSTATE_UINT32(env.v7m.vecbase[M_REG_S], ARMCPU), 404 VMSTATE_UINT32(env.pmsav8.mair0[M_REG_S], ARMCPU), 405 VMSTATE_UINT32(env.pmsav8.mair1[M_REG_S], ARMCPU), 406 VMSTATE_VARRAY_UINT32(env.pmsav8.rbar[M_REG_S], ARMCPU, pmsav7_dregion, 407 0, vmstate_info_uint32, uint32_t), 408 VMSTATE_VARRAY_UINT32(env.pmsav8.rlar[M_REG_S], ARMCPU, pmsav7_dregion, 409 0, vmstate_info_uint32, uint32_t), 410 VMSTATE_UINT32(env.pmsav7.rnr[M_REG_S], ARMCPU), 411 VMSTATE_VALIDATE("secure MPU_RNR is valid", s_rnr_vmstate_validate), 412 VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_S], ARMCPU), 413 VMSTATE_UINT32(env.v7m.ccr[M_REG_S], ARMCPU), 414 VMSTATE_UINT32(env.v7m.mmfar[M_REG_S], ARMCPU), 415 VMSTATE_UINT32(env.v7m.cfsr[M_REG_S], ARMCPU), 416 VMSTATE_UINT32(env.v7m.sfsr, ARMCPU), 417 VMSTATE_UINT32(env.v7m.sfar, ARMCPU), 418 VMSTATE_VARRAY_UINT32(env.sau.rbar, ARMCPU, sau_sregion, 0, 419 vmstate_info_uint32, uint32_t), 420 VMSTATE_VARRAY_UINT32(env.sau.rlar, ARMCPU, sau_sregion, 0, 421 vmstate_info_uint32, uint32_t), 422 VMSTATE_UINT32(env.sau.rnr, ARMCPU), 423 VMSTATE_VALIDATE("SAU_RNR is valid", sau_rnr_vmstate_validate), 424 VMSTATE_UINT32(env.sau.ctrl, ARMCPU), 425 VMSTATE_UINT32(env.v7m.scr[M_REG_S], ARMCPU), 426 VMSTATE_END_OF_LIST() 427 } 428 }; 429 430 static int get_cpsr(QEMUFile *f, void *opaque, size_t size, 431 VMStateField *field) 432 { 433 ARMCPU *cpu = opaque; 434 CPUARMState *env = &cpu->env; 435 uint32_t val = qemu_get_be32(f); 436 437 if (arm_feature(env, ARM_FEATURE_M)) { 438 if (val & XPSR_EXCP) { 439 /* This is a CPSR format value from an older QEMU. (We can tell 440 * because values transferred in XPSR format always have zero 441 * for the EXCP field, and CPSR format will always have bit 4 442 * set in CPSR_M.) Rearrange it into XPSR format. The significant 443 * differences are that the T bit is not in the same place, the 444 * primask/faultmask info may be in the CPSR I and F bits, and 445 * we do not want the mode bits. 446 * We know that this cleanup happened before v8M, so there 447 * is no complication with banked primask/faultmask. 448 */ 449 uint32_t newval = val; 450 451 assert(!arm_feature(env, ARM_FEATURE_M_SECURITY)); 452 453 newval &= (CPSR_NZCV | CPSR_Q | CPSR_IT | CPSR_GE); 454 if (val & CPSR_T) { 455 newval |= XPSR_T; 456 } 457 /* If the I or F bits are set then this is a migration from 458 * an old QEMU which still stored the M profile FAULTMASK 459 * and PRIMASK in env->daif. For a new QEMU, the data is 460 * transferred using the vmstate_m_faultmask_primask subsection. 461 */ 462 if (val & CPSR_F) { 463 env->v7m.faultmask[M_REG_NS] = 1; 464 } 465 if (val & CPSR_I) { 466 env->v7m.primask[M_REG_NS] = 1; 467 } 468 val = newval; 469 } 470 /* Ignore the low bits, they are handled by vmstate_m. */ 471 xpsr_write(env, val, ~XPSR_EXCP); 472 return 0; 473 } 474 475 env->aarch64 = ((val & PSTATE_nRW) == 0); 476 477 if (is_a64(env)) { 478 pstate_write(env, val); 479 return 0; 480 } 481 482 cpsr_write(env, val, 0xffffffff, CPSRWriteRaw); 483 return 0; 484 } 485 486 static int put_cpsr(QEMUFile *f, void *opaque, size_t size, 487 VMStateField *field, QJSON *vmdesc) 488 { 489 ARMCPU *cpu = opaque; 490 CPUARMState *env = &cpu->env; 491 uint32_t val; 492 493 if (arm_feature(env, ARM_FEATURE_M)) { 494 /* The low 9 bits are v7m.exception, which is handled by vmstate_m. */ 495 val = xpsr_read(env) & ~XPSR_EXCP; 496 } else if (is_a64(env)) { 497 val = pstate_read(env); 498 } else { 499 val = cpsr_read(env); 500 } 501 502 qemu_put_be32(f, val); 503 return 0; 504 } 505 506 static const VMStateInfo vmstate_cpsr = { 507 .name = "cpsr", 508 .get = get_cpsr, 509 .put = put_cpsr, 510 }; 511 512 static int get_power(QEMUFile *f, void *opaque, size_t size, 513 VMStateField *field) 514 { 515 ARMCPU *cpu = opaque; 516 bool powered_off = qemu_get_byte(f); 517 cpu->power_state = powered_off ? PSCI_OFF : PSCI_ON; 518 return 0; 519 } 520 521 static int put_power(QEMUFile *f, void *opaque, size_t size, 522 VMStateField *field, QJSON *vmdesc) 523 { 524 ARMCPU *cpu = opaque; 525 526 /* Migration should never happen while we transition power states */ 527 528 if (cpu->power_state == PSCI_ON || 529 cpu->power_state == PSCI_OFF) { 530 bool powered_off = (cpu->power_state == PSCI_OFF) ? true : false; 531 qemu_put_byte(f, powered_off); 532 return 0; 533 } else { 534 return 1; 535 } 536 } 537 538 static const VMStateInfo vmstate_powered_off = { 539 .name = "powered_off", 540 .get = get_power, 541 .put = put_power, 542 }; 543 544 static int cpu_pre_save(void *opaque) 545 { 546 ARMCPU *cpu = opaque; 547 548 if (kvm_enabled()) { 549 if (!write_kvmstate_to_list(cpu)) { 550 /* This should never fail */ 551 abort(); 552 } 553 } else { 554 if (!write_cpustate_to_list(cpu)) { 555 /* This should never fail. */ 556 abort(); 557 } 558 } 559 560 cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len; 561 memcpy(cpu->cpreg_vmstate_indexes, cpu->cpreg_indexes, 562 cpu->cpreg_array_len * sizeof(uint64_t)); 563 memcpy(cpu->cpreg_vmstate_values, cpu->cpreg_values, 564 cpu->cpreg_array_len * sizeof(uint64_t)); 565 566 return 0; 567 } 568 569 static int cpu_post_load(void *opaque, int version_id) 570 { 571 ARMCPU *cpu = opaque; 572 int i, v; 573 574 /* Update the values list from the incoming migration data. 575 * Anything in the incoming data which we don't know about is 576 * a migration failure; anything we know about but the incoming 577 * data doesn't specify retains its current (reset) value. 578 * The indexes list remains untouched -- we only inspect the 579 * incoming migration index list so we can match the values array 580 * entries with the right slots in our own values array. 581 */ 582 583 for (i = 0, v = 0; i < cpu->cpreg_array_len 584 && v < cpu->cpreg_vmstate_array_len; i++) { 585 if (cpu->cpreg_vmstate_indexes[v] > cpu->cpreg_indexes[i]) { 586 /* register in our list but not incoming : skip it */ 587 continue; 588 } 589 if (cpu->cpreg_vmstate_indexes[v] < cpu->cpreg_indexes[i]) { 590 /* register in their list but not ours: fail migration */ 591 return -1; 592 } 593 /* matching register, copy the value over */ 594 cpu->cpreg_values[i] = cpu->cpreg_vmstate_values[v]; 595 v++; 596 } 597 598 if (kvm_enabled()) { 599 if (!write_list_to_kvmstate(cpu, KVM_PUT_FULL_STATE)) { 600 return -1; 601 } 602 /* Note that it's OK for the TCG side not to know about 603 * every register in the list; KVM is authoritative if 604 * we're using it. 605 */ 606 write_list_to_cpustate(cpu); 607 } else { 608 if (!write_list_to_cpustate(cpu)) { 609 return -1; 610 } 611 } 612 613 hw_breakpoint_update_all(cpu); 614 hw_watchpoint_update_all(cpu); 615 616 return 0; 617 } 618 619 const VMStateDescription vmstate_arm_cpu = { 620 .name = "cpu", 621 .version_id = 22, 622 .minimum_version_id = 22, 623 .pre_save = cpu_pre_save, 624 .post_load = cpu_post_load, 625 .fields = (VMStateField[]) { 626 VMSTATE_UINT32_ARRAY(env.regs, ARMCPU, 16), 627 VMSTATE_UINT64_ARRAY(env.xregs, ARMCPU, 32), 628 VMSTATE_UINT64(env.pc, ARMCPU), 629 { 630 .name = "cpsr", 631 .version_id = 0, 632 .size = sizeof(uint32_t), 633 .info = &vmstate_cpsr, 634 .flags = VMS_SINGLE, 635 .offset = 0, 636 }, 637 VMSTATE_UINT32(env.spsr, ARMCPU), 638 VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 8), 639 VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 8), 640 VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 8), 641 VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5), 642 VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5), 643 VMSTATE_UINT64_ARRAY(env.elr_el, ARMCPU, 4), 644 VMSTATE_UINT64_ARRAY(env.sp_el, ARMCPU, 4), 645 /* The length-check must come before the arrays to avoid 646 * incoming data possibly overflowing the array. 647 */ 648 VMSTATE_INT32_POSITIVE_LE(cpreg_vmstate_array_len, ARMCPU), 649 VMSTATE_VARRAY_INT32(cpreg_vmstate_indexes, ARMCPU, 650 cpreg_vmstate_array_len, 651 0, vmstate_info_uint64, uint64_t), 652 VMSTATE_VARRAY_INT32(cpreg_vmstate_values, ARMCPU, 653 cpreg_vmstate_array_len, 654 0, vmstate_info_uint64, uint64_t), 655 VMSTATE_UINT64(env.exclusive_addr, ARMCPU), 656 VMSTATE_UINT64(env.exclusive_val, ARMCPU), 657 VMSTATE_UINT64(env.exclusive_high, ARMCPU), 658 VMSTATE_UINT64(env.features, ARMCPU), 659 VMSTATE_UINT32(env.exception.syndrome, ARMCPU), 660 VMSTATE_UINT32(env.exception.fsr, ARMCPU), 661 VMSTATE_UINT64(env.exception.vaddress, ARMCPU), 662 VMSTATE_TIMER_PTR(gt_timer[GTIMER_PHYS], ARMCPU), 663 VMSTATE_TIMER_PTR(gt_timer[GTIMER_VIRT], ARMCPU), 664 { 665 .name = "power_state", 666 .version_id = 0, 667 .size = sizeof(bool), 668 .info = &vmstate_powered_off, 669 .flags = VMS_SINGLE, 670 .offset = 0, 671 }, 672 VMSTATE_END_OF_LIST() 673 }, 674 .subsections = (const VMStateDescription*[]) { 675 &vmstate_vfp, 676 &vmstate_iwmmxt, 677 &vmstate_m, 678 &vmstate_thumb2ee, 679 /* pmsav7_rnr must come before pmsav7 so that we have the 680 * region number before we test it in the VMSTATE_VALIDATE 681 * in vmstate_pmsav7. 682 */ 683 &vmstate_pmsav7_rnr, 684 &vmstate_pmsav7, 685 &vmstate_pmsav8, 686 &vmstate_m_security, 687 #ifdef TARGET_AARCH64 688 &vmstate_sve, 689 #endif 690 NULL 691 } 692 }; 693