1 #include "qemu/osdep.h" 2 #include "qemu-common.h" 3 #include "cpu.h" 4 #include "hw/hw.h" 5 #include "hw/boards.h" 6 #include "qemu/error-report.h" 7 #include "sysemu/kvm.h" 8 #include "kvm_arm.h" 9 #include "internals.h" 10 #include "migration/cpu.h" 11 12 static bool vfp_needed(void *opaque) 13 { 14 ARMCPU *cpu = opaque; 15 CPUARMState *env = &cpu->env; 16 17 return arm_feature(env, ARM_FEATURE_VFP); 18 } 19 20 static int get_fpscr(QEMUFile *f, void *opaque, size_t size, 21 VMStateField *field) 22 { 23 ARMCPU *cpu = opaque; 24 CPUARMState *env = &cpu->env; 25 uint32_t val = qemu_get_be32(f); 26 27 vfp_set_fpscr(env, val); 28 return 0; 29 } 30 31 static int put_fpscr(QEMUFile *f, void *opaque, size_t size, 32 VMStateField *field, QJSON *vmdesc) 33 { 34 ARMCPU *cpu = opaque; 35 CPUARMState *env = &cpu->env; 36 37 qemu_put_be32(f, vfp_get_fpscr(env)); 38 return 0; 39 } 40 41 static const VMStateInfo vmstate_fpscr = { 42 .name = "fpscr", 43 .get = get_fpscr, 44 .put = put_fpscr, 45 }; 46 47 static const VMStateDescription vmstate_vfp = { 48 .name = "cpu/vfp", 49 .version_id = 3, 50 .minimum_version_id = 3, 51 .needed = vfp_needed, 52 .fields = (VMStateField[]) { 53 VMSTATE_FLOAT64_ARRAY(env.vfp.regs, ARMCPU, 64), 54 /* The xregs array is a little awkward because element 1 (FPSCR) 55 * requires a specific accessor, so we have to split it up in 56 * the vmstate: 57 */ 58 VMSTATE_UINT32(env.vfp.xregs[0], ARMCPU), 59 VMSTATE_UINT32_SUB_ARRAY(env.vfp.xregs, ARMCPU, 2, 14), 60 { 61 .name = "fpscr", 62 .version_id = 0, 63 .size = sizeof(uint32_t), 64 .info = &vmstate_fpscr, 65 .flags = VMS_SINGLE, 66 .offset = 0, 67 }, 68 VMSTATE_END_OF_LIST() 69 } 70 }; 71 72 static bool iwmmxt_needed(void *opaque) 73 { 74 ARMCPU *cpu = opaque; 75 CPUARMState *env = &cpu->env; 76 77 return arm_feature(env, ARM_FEATURE_IWMMXT); 78 } 79 80 static const VMStateDescription vmstate_iwmmxt = { 81 .name = "cpu/iwmmxt", 82 .version_id = 1, 83 .minimum_version_id = 1, 84 .needed = iwmmxt_needed, 85 .fields = (VMStateField[]) { 86 VMSTATE_UINT64_ARRAY(env.iwmmxt.regs, ARMCPU, 16), 87 VMSTATE_UINT32_ARRAY(env.iwmmxt.cregs, ARMCPU, 16), 88 VMSTATE_END_OF_LIST() 89 } 90 }; 91 92 static bool m_needed(void *opaque) 93 { 94 ARMCPU *cpu = opaque; 95 CPUARMState *env = &cpu->env; 96 97 return arm_feature(env, ARM_FEATURE_M); 98 } 99 100 static const VMStateDescription vmstate_m_faultmask_primask = { 101 .name = "cpu/m/faultmask-primask", 102 .version_id = 1, 103 .minimum_version_id = 1, 104 .fields = (VMStateField[]) { 105 VMSTATE_UINT32(env.v7m.faultmask, ARMCPU), 106 VMSTATE_UINT32(env.v7m.primask, ARMCPU), 107 VMSTATE_END_OF_LIST() 108 } 109 }; 110 111 static const VMStateDescription vmstate_m = { 112 .name = "cpu/m", 113 .version_id = 4, 114 .minimum_version_id = 4, 115 .needed = m_needed, 116 .fields = (VMStateField[]) { 117 VMSTATE_UINT32(env.v7m.vecbase, ARMCPU), 118 VMSTATE_UINT32(env.v7m.basepri, ARMCPU), 119 VMSTATE_UINT32(env.v7m.control, ARMCPU), 120 VMSTATE_UINT32(env.v7m.ccr, ARMCPU), 121 VMSTATE_UINT32(env.v7m.cfsr, ARMCPU), 122 VMSTATE_UINT32(env.v7m.hfsr, ARMCPU), 123 VMSTATE_UINT32(env.v7m.dfsr, ARMCPU), 124 VMSTATE_UINT32(env.v7m.mmfar, ARMCPU), 125 VMSTATE_UINT32(env.v7m.bfar, ARMCPU), 126 VMSTATE_UINT32(env.v7m.mpu_ctrl, ARMCPU), 127 VMSTATE_INT32(env.v7m.exception, ARMCPU), 128 VMSTATE_END_OF_LIST() 129 }, 130 .subsections = (const VMStateDescription*[]) { 131 &vmstate_m_faultmask_primask, 132 NULL 133 } 134 }; 135 136 static bool thumb2ee_needed(void *opaque) 137 { 138 ARMCPU *cpu = opaque; 139 CPUARMState *env = &cpu->env; 140 141 return arm_feature(env, ARM_FEATURE_THUMB2EE); 142 } 143 144 static const VMStateDescription vmstate_thumb2ee = { 145 .name = "cpu/thumb2ee", 146 .version_id = 1, 147 .minimum_version_id = 1, 148 .needed = thumb2ee_needed, 149 .fields = (VMStateField[]) { 150 VMSTATE_UINT32(env.teecr, ARMCPU), 151 VMSTATE_UINT32(env.teehbr, ARMCPU), 152 VMSTATE_END_OF_LIST() 153 } 154 }; 155 156 static bool pmsav7_needed(void *opaque) 157 { 158 ARMCPU *cpu = opaque; 159 CPUARMState *env = &cpu->env; 160 161 return arm_feature(env, ARM_FEATURE_PMSA) && 162 arm_feature(env, ARM_FEATURE_V7); 163 } 164 165 static bool pmsav7_rgnr_vmstate_validate(void *opaque, int version_id) 166 { 167 ARMCPU *cpu = opaque; 168 169 return cpu->env.pmsav7.rnr < cpu->pmsav7_dregion; 170 } 171 172 static const VMStateDescription vmstate_pmsav7 = { 173 .name = "cpu/pmsav7", 174 .version_id = 1, 175 .minimum_version_id = 1, 176 .needed = pmsav7_needed, 177 .fields = (VMStateField[]) { 178 VMSTATE_VARRAY_UINT32(env.pmsav7.drbar, ARMCPU, pmsav7_dregion, 0, 179 vmstate_info_uint32, uint32_t), 180 VMSTATE_VARRAY_UINT32(env.pmsav7.drsr, ARMCPU, pmsav7_dregion, 0, 181 vmstate_info_uint32, uint32_t), 182 VMSTATE_VARRAY_UINT32(env.pmsav7.dracr, ARMCPU, pmsav7_dregion, 0, 183 vmstate_info_uint32, uint32_t), 184 VMSTATE_VALIDATE("rgnr is valid", pmsav7_rgnr_vmstate_validate), 185 VMSTATE_END_OF_LIST() 186 } 187 }; 188 189 static bool pmsav7_rnr_needed(void *opaque) 190 { 191 ARMCPU *cpu = opaque; 192 CPUARMState *env = &cpu->env; 193 194 /* For R profile cores pmsav7.rnr is migrated via the cpreg 195 * "RGNR" definition in helper.h. For M profile we have to 196 * migrate it separately. 197 */ 198 return arm_feature(env, ARM_FEATURE_M); 199 } 200 201 static const VMStateDescription vmstate_pmsav7_rnr = { 202 .name = "cpu/pmsav7-rnr", 203 .version_id = 1, 204 .minimum_version_id = 1, 205 .needed = pmsav7_rnr_needed, 206 .fields = (VMStateField[]) { 207 VMSTATE_UINT32(env.pmsav7.rnr, ARMCPU), 208 VMSTATE_END_OF_LIST() 209 } 210 }; 211 212 static int get_cpsr(QEMUFile *f, void *opaque, size_t size, 213 VMStateField *field) 214 { 215 ARMCPU *cpu = opaque; 216 CPUARMState *env = &cpu->env; 217 uint32_t val = qemu_get_be32(f); 218 219 if (arm_feature(env, ARM_FEATURE_M)) { 220 if (val & XPSR_EXCP) { 221 /* This is a CPSR format value from an older QEMU. (We can tell 222 * because values transferred in XPSR format always have zero 223 * for the EXCP field, and CPSR format will always have bit 4 224 * set in CPSR_M.) Rearrange it into XPSR format. The significant 225 * differences are that the T bit is not in the same place, the 226 * primask/faultmask info may be in the CPSR I and F bits, and 227 * we do not want the mode bits. 228 */ 229 uint32_t newval = val; 230 231 newval &= (CPSR_NZCV | CPSR_Q | CPSR_IT | CPSR_GE); 232 if (val & CPSR_T) { 233 newval |= XPSR_T; 234 } 235 /* If the I or F bits are set then this is a migration from 236 * an old QEMU which still stored the M profile FAULTMASK 237 * and PRIMASK in env->daif. For a new QEMU, the data is 238 * transferred using the vmstate_m_faultmask_primask subsection. 239 */ 240 if (val & CPSR_F) { 241 env->v7m.faultmask = 1; 242 } 243 if (val & CPSR_I) { 244 env->v7m.primask = 1; 245 } 246 val = newval; 247 } 248 /* Ignore the low bits, they are handled by vmstate_m. */ 249 xpsr_write(env, val, ~XPSR_EXCP); 250 return 0; 251 } 252 253 env->aarch64 = ((val & PSTATE_nRW) == 0); 254 255 if (is_a64(env)) { 256 pstate_write(env, val); 257 return 0; 258 } 259 260 cpsr_write(env, val, 0xffffffff, CPSRWriteRaw); 261 return 0; 262 } 263 264 static int put_cpsr(QEMUFile *f, void *opaque, size_t size, 265 VMStateField *field, QJSON *vmdesc) 266 { 267 ARMCPU *cpu = opaque; 268 CPUARMState *env = &cpu->env; 269 uint32_t val; 270 271 if (arm_feature(env, ARM_FEATURE_M)) { 272 /* The low 9 bits are v7m.exception, which is handled by vmstate_m. */ 273 val = xpsr_read(env) & ~XPSR_EXCP; 274 } else if (is_a64(env)) { 275 val = pstate_read(env); 276 } else { 277 val = cpsr_read(env); 278 } 279 280 qemu_put_be32(f, val); 281 return 0; 282 } 283 284 static const VMStateInfo vmstate_cpsr = { 285 .name = "cpsr", 286 .get = get_cpsr, 287 .put = put_cpsr, 288 }; 289 290 static int get_power(QEMUFile *f, void *opaque, size_t size, 291 VMStateField *field) 292 { 293 ARMCPU *cpu = opaque; 294 bool powered_off = qemu_get_byte(f); 295 cpu->power_state = powered_off ? PSCI_OFF : PSCI_ON; 296 return 0; 297 } 298 299 static int put_power(QEMUFile *f, void *opaque, size_t size, 300 VMStateField *field, QJSON *vmdesc) 301 { 302 ARMCPU *cpu = opaque; 303 304 /* Migration should never happen while we transition power states */ 305 306 if (cpu->power_state == PSCI_ON || 307 cpu->power_state == PSCI_OFF) { 308 bool powered_off = (cpu->power_state == PSCI_OFF) ? true : false; 309 qemu_put_byte(f, powered_off); 310 return 0; 311 } else { 312 return 1; 313 } 314 } 315 316 static const VMStateInfo vmstate_powered_off = { 317 .name = "powered_off", 318 .get = get_power, 319 .put = put_power, 320 }; 321 322 static void cpu_pre_save(void *opaque) 323 { 324 ARMCPU *cpu = opaque; 325 326 if (kvm_enabled()) { 327 if (!write_kvmstate_to_list(cpu)) { 328 /* This should never fail */ 329 abort(); 330 } 331 } else { 332 if (!write_cpustate_to_list(cpu)) { 333 /* This should never fail. */ 334 abort(); 335 } 336 } 337 338 cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len; 339 memcpy(cpu->cpreg_vmstate_indexes, cpu->cpreg_indexes, 340 cpu->cpreg_array_len * sizeof(uint64_t)); 341 memcpy(cpu->cpreg_vmstate_values, cpu->cpreg_values, 342 cpu->cpreg_array_len * sizeof(uint64_t)); 343 } 344 345 static int cpu_post_load(void *opaque, int version_id) 346 { 347 ARMCPU *cpu = opaque; 348 int i, v; 349 350 /* Update the values list from the incoming migration data. 351 * Anything in the incoming data which we don't know about is 352 * a migration failure; anything we know about but the incoming 353 * data doesn't specify retains its current (reset) value. 354 * The indexes list remains untouched -- we only inspect the 355 * incoming migration index list so we can match the values array 356 * entries with the right slots in our own values array. 357 */ 358 359 for (i = 0, v = 0; i < cpu->cpreg_array_len 360 && v < cpu->cpreg_vmstate_array_len; i++) { 361 if (cpu->cpreg_vmstate_indexes[v] > cpu->cpreg_indexes[i]) { 362 /* register in our list but not incoming : skip it */ 363 continue; 364 } 365 if (cpu->cpreg_vmstate_indexes[v] < cpu->cpreg_indexes[i]) { 366 /* register in their list but not ours: fail migration */ 367 return -1; 368 } 369 /* matching register, copy the value over */ 370 cpu->cpreg_values[i] = cpu->cpreg_vmstate_values[v]; 371 v++; 372 } 373 374 if (kvm_enabled()) { 375 if (!write_list_to_kvmstate(cpu, KVM_PUT_FULL_STATE)) { 376 return -1; 377 } 378 /* Note that it's OK for the TCG side not to know about 379 * every register in the list; KVM is authoritative if 380 * we're using it. 381 */ 382 write_list_to_cpustate(cpu); 383 } else { 384 if (!write_list_to_cpustate(cpu)) { 385 return -1; 386 } 387 } 388 389 hw_breakpoint_update_all(cpu); 390 hw_watchpoint_update_all(cpu); 391 392 return 0; 393 } 394 395 const VMStateDescription vmstate_arm_cpu = { 396 .name = "cpu", 397 .version_id = 22, 398 .minimum_version_id = 22, 399 .pre_save = cpu_pre_save, 400 .post_load = cpu_post_load, 401 .fields = (VMStateField[]) { 402 VMSTATE_UINT32_ARRAY(env.regs, ARMCPU, 16), 403 VMSTATE_UINT64_ARRAY(env.xregs, ARMCPU, 32), 404 VMSTATE_UINT64(env.pc, ARMCPU), 405 { 406 .name = "cpsr", 407 .version_id = 0, 408 .size = sizeof(uint32_t), 409 .info = &vmstate_cpsr, 410 .flags = VMS_SINGLE, 411 .offset = 0, 412 }, 413 VMSTATE_UINT32(env.spsr, ARMCPU), 414 VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 8), 415 VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 8), 416 VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 8), 417 VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5), 418 VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5), 419 VMSTATE_UINT64_ARRAY(env.elr_el, ARMCPU, 4), 420 VMSTATE_UINT64_ARRAY(env.sp_el, ARMCPU, 4), 421 /* The length-check must come before the arrays to avoid 422 * incoming data possibly overflowing the array. 423 */ 424 VMSTATE_INT32_POSITIVE_LE(cpreg_vmstate_array_len, ARMCPU), 425 VMSTATE_VARRAY_INT32(cpreg_vmstate_indexes, ARMCPU, 426 cpreg_vmstate_array_len, 427 0, vmstate_info_uint64, uint64_t), 428 VMSTATE_VARRAY_INT32(cpreg_vmstate_values, ARMCPU, 429 cpreg_vmstate_array_len, 430 0, vmstate_info_uint64, uint64_t), 431 VMSTATE_UINT64(env.exclusive_addr, ARMCPU), 432 VMSTATE_UINT64(env.exclusive_val, ARMCPU), 433 VMSTATE_UINT64(env.exclusive_high, ARMCPU), 434 VMSTATE_UINT64(env.features, ARMCPU), 435 VMSTATE_UINT32(env.exception.syndrome, ARMCPU), 436 VMSTATE_UINT32(env.exception.fsr, ARMCPU), 437 VMSTATE_UINT64(env.exception.vaddress, ARMCPU), 438 VMSTATE_TIMER_PTR(gt_timer[GTIMER_PHYS], ARMCPU), 439 VMSTATE_TIMER_PTR(gt_timer[GTIMER_VIRT], ARMCPU), 440 { 441 .name = "power_state", 442 .version_id = 0, 443 .size = sizeof(bool), 444 .info = &vmstate_powered_off, 445 .flags = VMS_SINGLE, 446 .offset = 0, 447 }, 448 VMSTATE_END_OF_LIST() 449 }, 450 .subsections = (const VMStateDescription*[]) { 451 &vmstate_vfp, 452 &vmstate_iwmmxt, 453 &vmstate_m, 454 &vmstate_thumb2ee, 455 /* pmsav7_rnr must come before pmsav7 so that we have the 456 * region number before we test it in the VMSTATE_VALIDATE 457 * in vmstate_pmsav7. 458 */ 459 &vmstate_pmsav7_rnr, 460 &vmstate_pmsav7, 461 NULL 462 } 463 }; 464