1 /* 2 * ARM implementation of KVM hooks 3 * 4 * Copyright Christoffer Dall 2009-2010 5 * Copyright Mian-M. Hamayun 2013, Virtual Open Systems 6 * Copyright Alex Bennée 2014, Linaro 7 * 8 * This work is licensed under the terms of the GNU GPL, version 2 or later. 9 * See the COPYING file in the top-level directory. 10 * 11 */ 12 13 #include "qemu/osdep.h" 14 #include <sys/ioctl.h> 15 16 #include <linux/kvm.h> 17 18 #include "qemu/timer.h" 19 #include "qemu/error-report.h" 20 #include "qemu/main-loop.h" 21 #include "qom/object.h" 22 #include "qapi/error.h" 23 #include "system/system.h" 24 #include "system/runstate.h" 25 #include "system/kvm.h" 26 #include "system/kvm_int.h" 27 #include "kvm_arm.h" 28 #include "cpu.h" 29 #include "cpu-sysregs.h" 30 #include "trace.h" 31 #include "internals.h" 32 #include "hw/pci/pci.h" 33 #include "exec/memattrs.h" 34 #include "system/address-spaces.h" 35 #include "gdbstub/enums.h" 36 #include "hw/boards.h" 37 #include "hw/irq.h" 38 #include "qapi/visitor.h" 39 #include "qemu/log.h" 40 #include "hw/acpi/acpi.h" 41 #include "hw/acpi/ghes.h" 42 #include "target/arm/gtimer.h" 43 #include "migration/blocker.h" 44 45 const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 46 KVM_CAP_INFO(DEVICE_CTRL), 47 KVM_CAP_LAST_INFO 48 }; 49 50 static bool cap_has_mp_state; 51 static bool cap_has_inject_serror_esr; 52 static bool cap_has_inject_ext_dabt; 53 54 /** 55 * ARMHostCPUFeatures: information about the host CPU (identified 56 * by asking the host kernel) 57 */ 58 typedef struct ARMHostCPUFeatures { 59 ARMISARegisters isar; 60 uint64_t features; 61 uint32_t target; 62 const char *dtb_compatible; 63 } ARMHostCPUFeatures; 64 65 static ARMHostCPUFeatures arm_host_cpu_features; 66 67 /** 68 * kvm_arm_vcpu_init: 69 * @cpu: ARMCPU 70 * 71 * Initialize (or reinitialize) the VCPU by invoking the 72 * KVM_ARM_VCPU_INIT ioctl with the CPU type and feature 73 * bitmask specified in the CPUState. 74 * 75 * Returns: 0 if success else < 0 error code 76 */ 77 static int kvm_arm_vcpu_init(ARMCPU *cpu) 78 { 79 struct kvm_vcpu_init init; 80 81 init.target = cpu->kvm_target; 82 memcpy(init.features, cpu->kvm_init_features, sizeof(init.features)); 83 84 return kvm_vcpu_ioctl(CPU(cpu), KVM_ARM_VCPU_INIT, &init); 85 } 86 87 /** 88 * kvm_arm_vcpu_finalize: 89 * @cpu: ARMCPU 90 * @feature: feature to finalize 91 * 92 * Finalizes the configuration of the specified VCPU feature by 93 * invoking the KVM_ARM_VCPU_FINALIZE ioctl. Features requiring 94 * this are documented in the "KVM_ARM_VCPU_FINALIZE" section of 95 * KVM's API documentation. 96 * 97 * Returns: 0 if success else < 0 error code 98 */ 99 static int kvm_arm_vcpu_finalize(ARMCPU *cpu, int feature) 100 { 101 return kvm_vcpu_ioctl(CPU(cpu), KVM_ARM_VCPU_FINALIZE, &feature); 102 } 103 104 bool kvm_arm_create_scratch_host_vcpu(int *fdarray, 105 struct kvm_vcpu_init *init) 106 { 107 int ret = 0, kvmfd = -1, vmfd = -1, cpufd = -1; 108 int max_vm_pa_size; 109 110 kvmfd = qemu_open_old("/dev/kvm", O_RDWR); 111 if (kvmfd < 0) { 112 goto err; 113 } 114 max_vm_pa_size = ioctl(kvmfd, KVM_CHECK_EXTENSION, KVM_CAP_ARM_VM_IPA_SIZE); 115 if (max_vm_pa_size < 0) { 116 max_vm_pa_size = 0; 117 } 118 do { 119 vmfd = ioctl(kvmfd, KVM_CREATE_VM, max_vm_pa_size); 120 } while (vmfd == -1 && errno == EINTR); 121 if (vmfd < 0) { 122 goto err; 123 } 124 125 /* 126 * The MTE capability must be enabled by the VMM before creating 127 * any VCPUs in order to allow the MTE bits of the ID_AA64PFR1 128 * register to be probed correctly, as they are masked if MTE 129 * is not enabled. 130 */ 131 if (kvm_arm_mte_supported()) { 132 KVMState kvm_state; 133 134 kvm_state.fd = kvmfd; 135 kvm_state.vmfd = vmfd; 136 kvm_vm_enable_cap(&kvm_state, KVM_CAP_ARM_MTE, 0); 137 } 138 139 cpufd = ioctl(vmfd, KVM_CREATE_VCPU, 0); 140 if (cpufd < 0) { 141 goto err; 142 } 143 144 if (!init) { 145 /* Caller doesn't want the VCPU to be initialized, so skip it */ 146 goto finish; 147 } 148 149 if (init->target == -1) { 150 struct kvm_vcpu_init preferred; 151 152 ret = ioctl(vmfd, KVM_ARM_PREFERRED_TARGET, &preferred); 153 if (ret < 0) { 154 goto err; 155 } 156 init->target = preferred.target; 157 } 158 ret = ioctl(cpufd, KVM_ARM_VCPU_INIT, init); 159 if (ret < 0) { 160 goto err; 161 } 162 163 finish: 164 fdarray[0] = kvmfd; 165 fdarray[1] = vmfd; 166 fdarray[2] = cpufd; 167 168 return true; 169 170 err: 171 if (cpufd >= 0) { 172 close(cpufd); 173 } 174 if (vmfd >= 0) { 175 close(vmfd); 176 } 177 if (kvmfd >= 0) { 178 close(kvmfd); 179 } 180 181 return false; 182 } 183 184 void kvm_arm_destroy_scratch_host_vcpu(int *fdarray) 185 { 186 int i; 187 188 for (i = 2; i >= 0; i--) { 189 close(fdarray[i]); 190 } 191 } 192 193 static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id) 194 { 195 uint64_t ret; 196 struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)&ret }; 197 int err; 198 199 assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64); 200 err = ioctl(fd, KVM_GET_ONE_REG, &idreg); 201 if (err < 0) { 202 return -1; 203 } 204 *pret = ret; 205 return 0; 206 } 207 208 static int read_sys_reg64(int fd, uint64_t *pret, uint64_t id) 209 { 210 struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)pret }; 211 212 assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64); 213 return ioctl(fd, KVM_GET_ONE_REG, &idreg); 214 } 215 216 static bool kvm_arm_pauth_supported(void) 217 { 218 return (kvm_check_extension(kvm_state, KVM_CAP_ARM_PTRAUTH_ADDRESS) && 219 kvm_check_extension(kvm_state, KVM_CAP_ARM_PTRAUTH_GENERIC)); 220 } 221 222 223 static uint64_t idregs_sysreg_to_kvm_reg(ARMSysRegs sysreg) 224 { 225 return ARM64_SYS_REG((sysreg & CP_REG_ARM64_SYSREG_OP0_MASK) >> CP_REG_ARM64_SYSREG_OP0_SHIFT, 226 (sysreg & CP_REG_ARM64_SYSREG_OP1_MASK) >> CP_REG_ARM64_SYSREG_OP1_SHIFT, 227 (sysreg & CP_REG_ARM64_SYSREG_CRN_MASK) >> CP_REG_ARM64_SYSREG_CRN_SHIFT, 228 (sysreg & CP_REG_ARM64_SYSREG_CRM_MASK) >> CP_REG_ARM64_SYSREG_CRM_SHIFT, 229 (sysreg & CP_REG_ARM64_SYSREG_OP2_MASK) >> CP_REG_ARM64_SYSREG_OP2_SHIFT); 230 } 231 232 /* read a sysreg value and store it in the idregs */ 233 static int get_host_cpu_reg(int fd, ARMHostCPUFeatures *ahcf, 234 ARMIDRegisterIdx index) 235 { 236 uint64_t *reg; 237 int ret; 238 239 reg = &ahcf->isar.idregs[index]; 240 ret = read_sys_reg64(fd, reg, 241 idregs_sysreg_to_kvm_reg(id_register_sysreg[index])); 242 return ret; 243 } 244 245 static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) 246 { 247 /* Identify the feature bits corresponding to the host CPU, and 248 * fill out the ARMHostCPUClass fields accordingly. To do this 249 * we have to create a scratch VM, create a single CPU inside it, 250 * and then query that CPU for the relevant ID registers. 251 */ 252 int fdarray[3]; 253 bool sve_supported; 254 bool el2_supported; 255 bool pmu_supported = false; 256 uint64_t features = 0; 257 int err; 258 259 /* 260 * target = -1 informs kvm_arm_create_scratch_host_vcpu() 261 * to use the preferred target 262 */ 263 struct kvm_vcpu_init init = { .target = -1, }; 264 265 /* 266 * Ask for SVE if supported, so that we can query ID_AA64ZFR0, 267 * which is otherwise RAZ. 268 */ 269 sve_supported = kvm_arm_sve_supported(); 270 if (sve_supported) { 271 init.features[0] |= 1 << KVM_ARM_VCPU_SVE; 272 } 273 274 /* 275 * Ask for EL2 if supported. 276 */ 277 el2_supported = kvm_arm_el2_supported(); 278 if (el2_supported) { 279 init.features[0] |= 1 << KVM_ARM_VCPU_HAS_EL2; 280 } 281 282 /* 283 * Ask for Pointer Authentication if supported, so that we get 284 * the unsanitized field values for AA64ISAR1_EL1. 285 */ 286 if (kvm_arm_pauth_supported()) { 287 init.features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS | 288 1 << KVM_ARM_VCPU_PTRAUTH_GENERIC); 289 } 290 291 if (kvm_arm_pmu_supported()) { 292 init.features[0] |= 1 << KVM_ARM_VCPU_PMU_V3; 293 pmu_supported = true; 294 features |= 1ULL << ARM_FEATURE_PMU; 295 } 296 297 if (!kvm_arm_create_scratch_host_vcpu(fdarray, &init)) { 298 return false; 299 } 300 301 ahcf->target = init.target; 302 ahcf->dtb_compatible = "arm,armv8"; 303 int fd = fdarray[2]; 304 305 err = get_host_cpu_reg(fd, ahcf, ID_AA64PFR0_EL1_IDX); 306 if (unlikely(err < 0)) { 307 /* 308 * Before v4.15, the kernel only exposed a limited number of system 309 * registers, not including any of the interesting AArch64 ID regs. 310 * For the most part we could leave these fields as zero with minimal 311 * effect, since this does not affect the values seen by the guest. 312 * 313 * However, it could cause problems down the line for QEMU, 314 * so provide a minimal v8.0 default. 315 * 316 * ??? Could read MIDR and use knowledge from cpu64.c. 317 * ??? Could map a page of memory into our temp guest and 318 * run the tiniest of hand-crafted kernels to extract 319 * the values seen by the guest. 320 * ??? Either of these sounds like too much effort just 321 * to work around running a modern host kernel. 322 */ 323 SET_IDREG(&ahcf->isar, ID_AA64PFR0, 0x00000011); /* EL1&0, AArch64 only */ 324 err = 0; 325 } else { 326 err |= get_host_cpu_reg(fd, ahcf, ID_AA64PFR1_EL1_IDX); 327 err |= get_host_cpu_reg(fd, ahcf, ID_AA64SMFR0_EL1_IDX); 328 err |= get_host_cpu_reg(fd, ahcf, ID_AA64DFR0_EL1_IDX); 329 err |= get_host_cpu_reg(fd, ahcf, ID_AA64DFR1_EL1_IDX); 330 err |= get_host_cpu_reg(fd, ahcf, ID_AA64ISAR0_EL1_IDX); 331 err |= get_host_cpu_reg(fd, ahcf, ID_AA64ISAR1_EL1_IDX); 332 err |= get_host_cpu_reg(fd, ahcf, ID_AA64ISAR2_EL1_IDX); 333 err |= get_host_cpu_reg(fd, ahcf, ID_AA64MMFR0_EL1_IDX); 334 err |= get_host_cpu_reg(fd, ahcf, ID_AA64MMFR1_EL1_IDX); 335 err |= get_host_cpu_reg(fd, ahcf, ID_AA64MMFR2_EL1_IDX); 336 err |= get_host_cpu_reg(fd, ahcf, ID_AA64MMFR3_EL1_IDX); 337 338 /* 339 * Note that if AArch32 support is not present in the host, 340 * the AArch32 sysregs are present to be read, but will 341 * return UNKNOWN values. This is neither better nor worse 342 * than skipping the reads and leaving 0, as we must avoid 343 * considering the values in every case. 344 */ 345 err |= get_host_cpu_reg(fd, ahcf, ID_PFR0_EL1_IDX); 346 err |= get_host_cpu_reg(fd, ahcf, ID_PFR1_EL1_IDX); 347 err |= get_host_cpu_reg(fd, ahcf, ID_DFR0_EL1_IDX); 348 err |= get_host_cpu_reg(fd, ahcf, ID_MMFR0_EL1_IDX); 349 err |= get_host_cpu_reg(fd, ahcf, ID_MMFR1_EL1_IDX); 350 err |= get_host_cpu_reg(fd, ahcf, ID_MMFR2_EL1_IDX); 351 err |= get_host_cpu_reg(fd, ahcf, ID_MMFR3_EL1_IDX); 352 err |= get_host_cpu_reg(fd, ahcf, ID_ISAR0_EL1_IDX); 353 err |= get_host_cpu_reg(fd, ahcf, ID_ISAR1_EL1_IDX); 354 err |= get_host_cpu_reg(fd, ahcf, ID_ISAR2_EL1_IDX); 355 err |= get_host_cpu_reg(fd, ahcf, ID_ISAR3_EL1_IDX); 356 err |= get_host_cpu_reg(fd, ahcf, ID_ISAR4_EL1_IDX); 357 err |= get_host_cpu_reg(fd, ahcf, ID_ISAR5_EL1_IDX); 358 err |= get_host_cpu_reg(fd, ahcf, ID_ISAR6_EL1_IDX); 359 err |= get_host_cpu_reg(fd, ahcf, ID_MMFR4_EL1_IDX); 360 361 err |= read_sys_reg32(fd, &ahcf->isar.mvfr0, 362 ARM64_SYS_REG(3, 0, 0, 3, 0)); 363 err |= read_sys_reg32(fd, &ahcf->isar.mvfr1, 364 ARM64_SYS_REG(3, 0, 0, 3, 1)); 365 err |= read_sys_reg32(fd, &ahcf->isar.mvfr2, 366 ARM64_SYS_REG(3, 0, 0, 3, 2)); 367 err |= get_host_cpu_reg(fd, ahcf, ID_PFR2_EL1_IDX); 368 err |= get_host_cpu_reg(fd, ahcf, ID_DFR1_EL1_IDX); 369 err |= get_host_cpu_reg(fd, ahcf, ID_MMFR5_EL1_IDX); 370 371 /* 372 * DBGDIDR is a bit complicated because the kernel doesn't 373 * provide an accessor for it in 64-bit mode, which is what this 374 * scratch VM is in, and there's no architected "64-bit sysreg 375 * which reads the same as the 32-bit register" the way there is 376 * for other ID registers. Instead we synthesize a value from the 377 * AArch64 ID_AA64DFR0, the same way the kernel code in 378 * arch/arm64/kvm/sys_regs.c:trap_dbgidr() does. 379 * We only do this if the CPU supports AArch32 at EL1. 380 */ 381 if (FIELD_EX32_IDREG(&ahcf->isar, ID_AA64PFR0, EL1) >= 2) { 382 int wrps = FIELD_EX64_IDREG(&ahcf->isar, ID_AA64DFR0, WRPS); 383 int brps = FIELD_EX64_IDREG(&ahcf->isar, ID_AA64DFR0, BRPS); 384 int ctx_cmps = 385 FIELD_EX64_IDREG(&ahcf->isar, ID_AA64DFR0, CTX_CMPS); 386 int version = 6; /* ARMv8 debug architecture */ 387 bool has_el3 = 388 !!FIELD_EX32_IDREG(&ahcf->isar, ID_AA64PFR0, EL3); 389 uint32_t dbgdidr = 0; 390 391 dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, WRPS, wrps); 392 dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, BRPS, brps); 393 dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, CTX_CMPS, ctx_cmps); 394 dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, VERSION, version); 395 dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, NSUHD_IMP, has_el3); 396 dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, SE_IMP, has_el3); 397 dbgdidr |= (1 << 15); /* RES1 bit */ 398 ahcf->isar.dbgdidr = dbgdidr; 399 } 400 401 if (pmu_supported) { 402 /* PMCR_EL0 is only accessible if the vCPU has feature PMU_V3 */ 403 err |= read_sys_reg64(fd, &ahcf->isar.reset_pmcr_el0, 404 ARM64_SYS_REG(3, 3, 9, 12, 0)); 405 } 406 407 if (sve_supported) { 408 /* 409 * There is a range of kernels between kernel commit 73433762fcae 410 * and f81cb2c3ad41 which have a bug where the kernel doesn't 411 * expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has 412 * enabled SVE support, which resulted in an error rather than RAZ. 413 * So only read the register if we set KVM_ARM_VCPU_SVE above. 414 */ 415 err |= get_host_cpu_reg(fd, ahcf, ID_AA64ZFR0_EL1_IDX); 416 } 417 } 418 419 kvm_arm_destroy_scratch_host_vcpu(fdarray); 420 421 if (err < 0) { 422 return false; 423 } 424 425 /* 426 * We can assume any KVM supporting CPU is at least a v8 427 * with VFPv4+Neon; this in turn implies most of the other 428 * feature bits. 429 */ 430 features |= 1ULL << ARM_FEATURE_V8; 431 features |= 1ULL << ARM_FEATURE_NEON; 432 features |= 1ULL << ARM_FEATURE_AARCH64; 433 features |= 1ULL << ARM_FEATURE_GENERIC_TIMER; 434 435 if (el2_supported) { 436 features |= 1ULL << ARM_FEATURE_EL2; 437 } 438 439 ahcf->features = features; 440 441 return true; 442 } 443 444 void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) 445 { 446 CPUARMState *env = &cpu->env; 447 448 if (!arm_host_cpu_features.dtb_compatible) { 449 if (!kvm_enabled() || 450 !kvm_arm_get_host_cpu_features(&arm_host_cpu_features)) { 451 /* We can't report this error yet, so flag that we need to 452 * in arm_cpu_realizefn(). 453 */ 454 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 455 cpu->host_cpu_probe_failed = true; 456 return; 457 } 458 } 459 460 cpu->kvm_target = arm_host_cpu_features.target; 461 cpu->dtb_compatible = arm_host_cpu_features.dtb_compatible; 462 cpu->isar = arm_host_cpu_features.isar; 463 env->features = arm_host_cpu_features.features; 464 } 465 466 static bool kvm_no_adjvtime_get(Object *obj, Error **errp) 467 { 468 return !ARM_CPU(obj)->kvm_adjvtime; 469 } 470 471 static void kvm_no_adjvtime_set(Object *obj, bool value, Error **errp) 472 { 473 ARM_CPU(obj)->kvm_adjvtime = !value; 474 } 475 476 static bool kvm_steal_time_get(Object *obj, Error **errp) 477 { 478 return ARM_CPU(obj)->kvm_steal_time != ON_OFF_AUTO_OFF; 479 } 480 481 static void kvm_steal_time_set(Object *obj, bool value, Error **errp) 482 { 483 ARM_CPU(obj)->kvm_steal_time = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; 484 } 485 486 /* KVM VCPU properties should be prefixed with "kvm-". */ 487 void kvm_arm_add_vcpu_properties(ARMCPU *cpu) 488 { 489 CPUARMState *env = &cpu->env; 490 Object *obj = OBJECT(cpu); 491 492 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { 493 cpu->kvm_adjvtime = true; 494 object_property_add_bool(obj, "kvm-no-adjvtime", kvm_no_adjvtime_get, 495 kvm_no_adjvtime_set); 496 object_property_set_description(obj, "kvm-no-adjvtime", 497 "Set on to disable the adjustment of " 498 "the virtual counter. VM stopped time " 499 "will be counted."); 500 } 501 502 cpu->kvm_steal_time = ON_OFF_AUTO_AUTO; 503 object_property_add_bool(obj, "kvm-steal-time", kvm_steal_time_get, 504 kvm_steal_time_set); 505 object_property_set_description(obj, "kvm-steal-time", 506 "Set off to disable KVM steal time."); 507 } 508 509 bool kvm_arm_pmu_supported(void) 510 { 511 return kvm_check_extension(kvm_state, KVM_CAP_ARM_PMU_V3); 512 } 513 514 int kvm_arm_get_max_vm_ipa_size(MachineState *ms, bool *fixed_ipa) 515 { 516 KVMState *s = KVM_STATE(ms->accelerator); 517 int ret; 518 519 ret = kvm_check_extension(s, KVM_CAP_ARM_VM_IPA_SIZE); 520 *fixed_ipa = ret <= 0; 521 522 return ret > 0 ? ret : 40; 523 } 524 525 int kvm_arch_get_default_type(MachineState *ms) 526 { 527 bool fixed_ipa; 528 int size = kvm_arm_get_max_vm_ipa_size(ms, &fixed_ipa); 529 return fixed_ipa ? 0 : size; 530 } 531 532 int kvm_arch_init(MachineState *ms, KVMState *s) 533 { 534 int ret = 0; 535 /* For ARM interrupt delivery is always asynchronous, 536 * whether we are using an in-kernel VGIC or not. 537 */ 538 kvm_async_interrupts_allowed = true; 539 540 /* 541 * PSCI wakes up secondary cores, so we always need to 542 * have vCPUs waiting in kernel space 543 */ 544 kvm_halt_in_kernel_allowed = true; 545 546 cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE); 547 548 /* Check whether user space can specify guest syndrome value */ 549 cap_has_inject_serror_esr = 550 kvm_check_extension(s, KVM_CAP_ARM_INJECT_SERROR_ESR); 551 552 if (ms->smp.cpus > 256 && 553 !kvm_check_extension(s, KVM_CAP_ARM_IRQ_LINE_LAYOUT_2)) { 554 error_report("Using more than 256 vcpus requires a host kernel " 555 "with KVM_CAP_ARM_IRQ_LINE_LAYOUT_2"); 556 ret = -EINVAL; 557 } 558 559 if (kvm_check_extension(s, KVM_CAP_ARM_NISV_TO_USER)) { 560 if (kvm_vm_enable_cap(s, KVM_CAP_ARM_NISV_TO_USER, 0)) { 561 error_report("Failed to enable KVM_CAP_ARM_NISV_TO_USER cap"); 562 } else { 563 /* Set status for supporting the external dabt injection */ 564 cap_has_inject_ext_dabt = kvm_check_extension(s, 565 KVM_CAP_ARM_INJECT_EXT_DABT); 566 } 567 } 568 569 if (s->kvm_eager_split_size) { 570 uint32_t sizes; 571 572 sizes = kvm_vm_check_extension(s, KVM_CAP_ARM_SUPPORTED_BLOCK_SIZES); 573 if (!sizes) { 574 s->kvm_eager_split_size = 0; 575 warn_report("Eager Page Split support not available"); 576 } else if (!(s->kvm_eager_split_size & sizes)) { 577 error_report("Eager Page Split requested chunk size not valid"); 578 ret = -EINVAL; 579 } else { 580 ret = kvm_vm_enable_cap(s, KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE, 0, 581 s->kvm_eager_split_size); 582 if (ret < 0) { 583 error_report("Enabling of Eager Page Split failed: %s", 584 strerror(-ret)); 585 } 586 } 587 } 588 589 max_hw_wps = kvm_check_extension(s, KVM_CAP_GUEST_DEBUG_HW_WPS); 590 hw_watchpoints = g_array_sized_new(true, true, 591 sizeof(HWWatchpoint), max_hw_wps); 592 593 max_hw_bps = kvm_check_extension(s, KVM_CAP_GUEST_DEBUG_HW_BPS); 594 hw_breakpoints = g_array_sized_new(true, true, 595 sizeof(HWBreakpoint), max_hw_bps); 596 597 return ret; 598 } 599 600 unsigned long kvm_arch_vcpu_id(CPUState *cpu) 601 { 602 return cpu->cpu_index; 603 } 604 605 /* We track all the KVM devices which need their memory addresses 606 * passing to the kernel in a list of these structures. 607 * When board init is complete we run through the list and 608 * tell the kernel the base addresses of the memory regions. 609 * We use a MemoryListener to track mapping and unmapping of 610 * the regions during board creation, so the board models don't 611 * need to do anything special for the KVM case. 612 * 613 * Sometimes the address must be OR'ed with some other fields 614 * (for example for KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION). 615 * @kda_addr_ormask aims at storing the value of those fields. 616 */ 617 typedef struct KVMDevice { 618 struct kvm_arm_device_addr kda; 619 struct kvm_device_attr kdattr; 620 uint64_t kda_addr_ormask; 621 MemoryRegion *mr; 622 QSLIST_ENTRY(KVMDevice) entries; 623 int dev_fd; 624 } KVMDevice; 625 626 static QSLIST_HEAD(, KVMDevice) kvm_devices_head; 627 628 static void kvm_arm_devlistener_add(MemoryListener *listener, 629 MemoryRegionSection *section) 630 { 631 KVMDevice *kd; 632 633 QSLIST_FOREACH(kd, &kvm_devices_head, entries) { 634 if (section->mr == kd->mr) { 635 kd->kda.addr = section->offset_within_address_space; 636 } 637 } 638 } 639 640 static void kvm_arm_devlistener_del(MemoryListener *listener, 641 MemoryRegionSection *section) 642 { 643 KVMDevice *kd; 644 645 QSLIST_FOREACH(kd, &kvm_devices_head, entries) { 646 if (section->mr == kd->mr) { 647 kd->kda.addr = -1; 648 } 649 } 650 } 651 652 static MemoryListener devlistener = { 653 .name = "kvm-arm", 654 .region_add = kvm_arm_devlistener_add, 655 .region_del = kvm_arm_devlistener_del, 656 .priority = MEMORY_LISTENER_PRIORITY_MIN, 657 }; 658 659 static void kvm_arm_set_device_addr(KVMDevice *kd) 660 { 661 struct kvm_device_attr *attr = &kd->kdattr; 662 int ret; 663 uint64_t addr = kd->kda.addr; 664 665 addr |= kd->kda_addr_ormask; 666 attr->addr = (uintptr_t)&addr; 667 ret = kvm_device_ioctl(kd->dev_fd, KVM_SET_DEVICE_ATTR, attr); 668 669 if (ret < 0) { 670 fprintf(stderr, "Failed to set device address: %s\n", 671 strerror(-ret)); 672 abort(); 673 } 674 } 675 676 static void kvm_arm_machine_init_done(Notifier *notifier, void *data) 677 { 678 KVMDevice *kd, *tkd; 679 680 QSLIST_FOREACH_SAFE(kd, &kvm_devices_head, entries, tkd) { 681 if (kd->kda.addr != -1) { 682 kvm_arm_set_device_addr(kd); 683 } 684 memory_region_unref(kd->mr); 685 QSLIST_REMOVE_HEAD(&kvm_devices_head, entries); 686 g_free(kd); 687 } 688 memory_listener_unregister(&devlistener); 689 } 690 691 static Notifier notify = { 692 .notify = kvm_arm_machine_init_done, 693 }; 694 695 void kvm_arm_register_device(MemoryRegion *mr, uint64_t devid, uint64_t group, 696 uint64_t attr, int dev_fd, uint64_t addr_ormask) 697 { 698 KVMDevice *kd; 699 700 if (!kvm_irqchip_in_kernel()) { 701 return; 702 } 703 704 if (QSLIST_EMPTY(&kvm_devices_head)) { 705 memory_listener_register(&devlistener, &address_space_memory); 706 qemu_add_machine_init_done_notifier(¬ify); 707 } 708 kd = g_new0(KVMDevice, 1); 709 kd->mr = mr; 710 kd->kda.id = devid; 711 kd->kda.addr = -1; 712 kd->kdattr.flags = 0; 713 kd->kdattr.group = group; 714 kd->kdattr.attr = attr; 715 kd->dev_fd = dev_fd; 716 kd->kda_addr_ormask = addr_ormask; 717 QSLIST_INSERT_HEAD(&kvm_devices_head, kd, entries); 718 memory_region_ref(kd->mr); 719 } 720 721 static int compare_u64(const void *a, const void *b) 722 { 723 if (*(uint64_t *)a > *(uint64_t *)b) { 724 return 1; 725 } 726 if (*(uint64_t *)a < *(uint64_t *)b) { 727 return -1; 728 } 729 return 0; 730 } 731 732 /* 733 * cpreg_values are sorted in ascending order by KVM register ID 734 * (see kvm_arm_init_cpreg_list). This allows us to cheaply find 735 * the storage for a KVM register by ID with a binary search. 736 */ 737 static uint64_t *kvm_arm_get_cpreg_ptr(ARMCPU *cpu, uint64_t regidx) 738 { 739 uint64_t *res; 740 741 res = bsearch(®idx, cpu->cpreg_indexes, cpu->cpreg_array_len, 742 sizeof(uint64_t), compare_u64); 743 assert(res); 744 745 return &cpu->cpreg_values[res - cpu->cpreg_indexes]; 746 } 747 748 /** 749 * kvm_arm_reg_syncs_via_cpreg_list: 750 * @regidx: KVM register index 751 * 752 * Return true if this KVM register should be synchronized via the 753 * cpreg list of arbitrary system registers, false if it is synchronized 754 * by hand using code in kvm_arch_get/put_registers(). 755 */ 756 static bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx) 757 { 758 switch (regidx & KVM_REG_ARM_COPROC_MASK) { 759 case KVM_REG_ARM_CORE: 760 case KVM_REG_ARM64_SVE: 761 return false; 762 default: 763 return true; 764 } 765 } 766 767 /** 768 * kvm_arm_init_cpreg_list: 769 * @cpu: ARMCPU 770 * 771 * Initialize the ARMCPU cpreg list according to the kernel's 772 * definition of what CPU registers it knows about (and throw away 773 * the previous TCG-created cpreg list). 774 * 775 * Returns: 0 if success, else < 0 error code 776 */ 777 static int kvm_arm_init_cpreg_list(ARMCPU *cpu) 778 { 779 struct kvm_reg_list rl; 780 struct kvm_reg_list *rlp; 781 int i, ret, arraylen; 782 CPUState *cs = CPU(cpu); 783 784 rl.n = 0; 785 ret = kvm_vcpu_ioctl(cs, KVM_GET_REG_LIST, &rl); 786 if (ret != -E2BIG) { 787 return ret; 788 } 789 rlp = g_malloc(sizeof(struct kvm_reg_list) + rl.n * sizeof(uint64_t)); 790 rlp->n = rl.n; 791 ret = kvm_vcpu_ioctl(cs, KVM_GET_REG_LIST, rlp); 792 if (ret) { 793 goto out; 794 } 795 /* Sort the list we get back from the kernel, since cpreg_tuples 796 * must be in strictly ascending order. 797 */ 798 qsort(&rlp->reg, rlp->n, sizeof(rlp->reg[0]), compare_u64); 799 800 for (i = 0, arraylen = 0; i < rlp->n; i++) { 801 if (!kvm_arm_reg_syncs_via_cpreg_list(rlp->reg[i])) { 802 continue; 803 } 804 switch (rlp->reg[i] & KVM_REG_SIZE_MASK) { 805 case KVM_REG_SIZE_U32: 806 case KVM_REG_SIZE_U64: 807 break; 808 default: 809 fprintf(stderr, "Can't handle size of register in kernel list\n"); 810 ret = -EINVAL; 811 goto out; 812 } 813 814 arraylen++; 815 } 816 817 cpu->cpreg_indexes = g_renew(uint64_t, cpu->cpreg_indexes, arraylen); 818 cpu->cpreg_values = g_renew(uint64_t, cpu->cpreg_values, arraylen); 819 cpu->cpreg_vmstate_indexes = g_renew(uint64_t, cpu->cpreg_vmstate_indexes, 820 arraylen); 821 cpu->cpreg_vmstate_values = g_renew(uint64_t, cpu->cpreg_vmstate_values, 822 arraylen); 823 cpu->cpreg_array_len = arraylen; 824 cpu->cpreg_vmstate_array_len = arraylen; 825 826 for (i = 0, arraylen = 0; i < rlp->n; i++) { 827 uint64_t regidx = rlp->reg[i]; 828 if (!kvm_arm_reg_syncs_via_cpreg_list(regidx)) { 829 continue; 830 } 831 cpu->cpreg_indexes[arraylen] = regidx; 832 arraylen++; 833 } 834 assert(cpu->cpreg_array_len == arraylen); 835 836 if (!write_kvmstate_to_list(cpu)) { 837 /* Shouldn't happen unless kernel is inconsistent about 838 * what registers exist. 839 */ 840 fprintf(stderr, "Initial read of kernel register state failed\n"); 841 ret = -EINVAL; 842 goto out; 843 } 844 845 out: 846 g_free(rlp); 847 return ret; 848 } 849 850 /** 851 * kvm_arm_cpreg_level: 852 * @regidx: KVM register index 853 * 854 * Return the level of this coprocessor/system register. Return value is 855 * either KVM_PUT_RUNTIME_STATE, KVM_PUT_RESET_STATE, or KVM_PUT_FULL_STATE. 856 */ 857 static int kvm_arm_cpreg_level(uint64_t regidx) 858 { 859 /* 860 * All system registers are assumed to be level KVM_PUT_RUNTIME_STATE. 861 * If a register should be written less often, you must add it here 862 * with a state of either KVM_PUT_RESET_STATE or KVM_PUT_FULL_STATE. 863 */ 864 switch (regidx) { 865 case KVM_REG_ARM_TIMER_CNT: 866 case KVM_REG_ARM_PTIMER_CNT: 867 return KVM_PUT_FULL_STATE; 868 } 869 return KVM_PUT_RUNTIME_STATE; 870 } 871 872 bool write_kvmstate_to_list(ARMCPU *cpu) 873 { 874 CPUState *cs = CPU(cpu); 875 int i; 876 bool ok = true; 877 878 for (i = 0; i < cpu->cpreg_array_len; i++) { 879 uint64_t regidx = cpu->cpreg_indexes[i]; 880 uint32_t v32; 881 int ret; 882 883 switch (regidx & KVM_REG_SIZE_MASK) { 884 case KVM_REG_SIZE_U32: 885 ret = kvm_get_one_reg(cs, regidx, &v32); 886 if (!ret) { 887 cpu->cpreg_values[i] = v32; 888 } 889 break; 890 case KVM_REG_SIZE_U64: 891 ret = kvm_get_one_reg(cs, regidx, cpu->cpreg_values + i); 892 break; 893 default: 894 g_assert_not_reached(); 895 } 896 if (ret) { 897 ok = false; 898 } 899 } 900 return ok; 901 } 902 903 bool write_list_to_kvmstate(ARMCPU *cpu, int level) 904 { 905 CPUState *cs = CPU(cpu); 906 int i; 907 bool ok = true; 908 909 for (i = 0; i < cpu->cpreg_array_len; i++) { 910 uint64_t regidx = cpu->cpreg_indexes[i]; 911 uint32_t v32; 912 int ret; 913 914 if (kvm_arm_cpreg_level(regidx) > level) { 915 continue; 916 } 917 918 switch (regidx & KVM_REG_SIZE_MASK) { 919 case KVM_REG_SIZE_U32: 920 v32 = cpu->cpreg_values[i]; 921 ret = kvm_set_one_reg(cs, regidx, &v32); 922 break; 923 case KVM_REG_SIZE_U64: 924 ret = kvm_set_one_reg(cs, regidx, cpu->cpreg_values + i); 925 break; 926 default: 927 g_assert_not_reached(); 928 } 929 if (ret) { 930 /* We might fail for "unknown register" and also for 931 * "you tried to set a register which is constant with 932 * a different value from what it actually contains". 933 */ 934 ok = false; 935 } 936 } 937 return ok; 938 } 939 940 void kvm_arm_cpu_pre_save(ARMCPU *cpu) 941 { 942 /* KVM virtual time adjustment */ 943 if (cpu->kvm_vtime_dirty) { 944 *kvm_arm_get_cpreg_ptr(cpu, KVM_REG_ARM_TIMER_CNT) = cpu->kvm_vtime; 945 } 946 } 947 948 bool kvm_arm_cpu_post_load(ARMCPU *cpu) 949 { 950 if (!write_list_to_kvmstate(cpu, KVM_PUT_FULL_STATE)) { 951 return false; 952 } 953 /* Note that it's OK for the TCG side not to know about 954 * every register in the list; KVM is authoritative if 955 * we're using it. 956 */ 957 write_list_to_cpustate(cpu); 958 959 /* KVM virtual time adjustment */ 960 if (cpu->kvm_adjvtime) { 961 cpu->kvm_vtime = *kvm_arm_get_cpreg_ptr(cpu, KVM_REG_ARM_TIMER_CNT); 962 cpu->kvm_vtime_dirty = true; 963 } 964 965 return true; 966 } 967 968 void kvm_arm_reset_vcpu(ARMCPU *cpu) 969 { 970 int ret; 971 972 /* Re-init VCPU so that all registers are set to 973 * their respective reset values. 974 */ 975 ret = kvm_arm_vcpu_init(cpu); 976 if (ret < 0) { 977 fprintf(stderr, "kvm_arm_vcpu_init failed: %s\n", strerror(-ret)); 978 abort(); 979 } 980 if (!write_kvmstate_to_list(cpu)) { 981 fprintf(stderr, "write_kvmstate_to_list failed\n"); 982 abort(); 983 } 984 /* 985 * Sync the reset values also into the CPUState. This is necessary 986 * because the next thing we do will be a kvm_arch_put_registers() 987 * which will update the list values from the CPUState before copying 988 * the list values back to KVM. It's OK to ignore failure returns here 989 * for the same reason we do so in kvm_arch_get_registers(). 990 */ 991 write_list_to_cpustate(cpu); 992 } 993 994 /* 995 * Update KVM's MP_STATE based on what QEMU thinks it is 996 */ 997 static int kvm_arm_sync_mpstate_to_kvm(ARMCPU *cpu) 998 { 999 if (cap_has_mp_state) { 1000 struct kvm_mp_state mp_state = { 1001 .mp_state = (cpu->power_state == PSCI_OFF) ? 1002 KVM_MP_STATE_STOPPED : KVM_MP_STATE_RUNNABLE 1003 }; 1004 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state); 1005 } 1006 return 0; 1007 } 1008 1009 /* 1010 * Sync the KVM MP_STATE into QEMU 1011 */ 1012 static int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu) 1013 { 1014 if (cap_has_mp_state) { 1015 struct kvm_mp_state mp_state; 1016 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MP_STATE, &mp_state); 1017 if (ret) { 1018 return ret; 1019 } 1020 cpu->power_state = (mp_state.mp_state == KVM_MP_STATE_STOPPED) ? 1021 PSCI_OFF : PSCI_ON; 1022 } 1023 return 0; 1024 } 1025 1026 /** 1027 * kvm_arm_get_virtual_time: 1028 * @cpu: ARMCPU 1029 * 1030 * Gets the VCPU's virtual counter and stores it in the KVM CPU state. 1031 */ 1032 static void kvm_arm_get_virtual_time(ARMCPU *cpu) 1033 { 1034 int ret; 1035 1036 if (cpu->kvm_vtime_dirty) { 1037 return; 1038 } 1039 1040 ret = kvm_get_one_reg(CPU(cpu), KVM_REG_ARM_TIMER_CNT, &cpu->kvm_vtime); 1041 if (ret) { 1042 error_report("Failed to get KVM_REG_ARM_TIMER_CNT"); 1043 abort(); 1044 } 1045 1046 cpu->kvm_vtime_dirty = true; 1047 } 1048 1049 /** 1050 * kvm_arm_put_virtual_time: 1051 * @cpu: ARMCPU 1052 * 1053 * Sets the VCPU's virtual counter to the value stored in the KVM CPU state. 1054 */ 1055 static void kvm_arm_put_virtual_time(ARMCPU *cpu) 1056 { 1057 int ret; 1058 1059 if (!cpu->kvm_vtime_dirty) { 1060 return; 1061 } 1062 1063 ret = kvm_set_one_reg(CPU(cpu), KVM_REG_ARM_TIMER_CNT, &cpu->kvm_vtime); 1064 if (ret) { 1065 error_report("Failed to set KVM_REG_ARM_TIMER_CNT"); 1066 abort(); 1067 } 1068 1069 cpu->kvm_vtime_dirty = false; 1070 } 1071 1072 /** 1073 * kvm_put_vcpu_events: 1074 * @cpu: ARMCPU 1075 * 1076 * Put VCPU related state to kvm. 1077 * 1078 * Returns: 0 if success else < 0 error code 1079 */ 1080 static int kvm_put_vcpu_events(ARMCPU *cpu) 1081 { 1082 CPUARMState *env = &cpu->env; 1083 struct kvm_vcpu_events events; 1084 int ret; 1085 1086 if (!kvm_has_vcpu_events()) { 1087 return 0; 1088 } 1089 1090 memset(&events, 0, sizeof(events)); 1091 events.exception.serror_pending = env->serror.pending; 1092 1093 /* Inject SError to guest with specified syndrome if host kernel 1094 * supports it, otherwise inject SError without syndrome. 1095 */ 1096 if (cap_has_inject_serror_esr) { 1097 events.exception.serror_has_esr = env->serror.has_esr; 1098 events.exception.serror_esr = env->serror.esr; 1099 } 1100 1101 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events); 1102 if (ret) { 1103 error_report("failed to put vcpu events"); 1104 } 1105 1106 return ret; 1107 } 1108 1109 /** 1110 * kvm_get_vcpu_events: 1111 * @cpu: ARMCPU 1112 * 1113 * Get VCPU related state from kvm. 1114 * 1115 * Returns: 0 if success else < 0 error code 1116 */ 1117 static int kvm_get_vcpu_events(ARMCPU *cpu) 1118 { 1119 CPUARMState *env = &cpu->env; 1120 struct kvm_vcpu_events events; 1121 int ret; 1122 1123 if (!kvm_has_vcpu_events()) { 1124 return 0; 1125 } 1126 1127 memset(&events, 0, sizeof(events)); 1128 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events); 1129 if (ret) { 1130 error_report("failed to get vcpu events"); 1131 return ret; 1132 } 1133 1134 env->serror.pending = events.exception.serror_pending; 1135 env->serror.has_esr = events.exception.serror_has_esr; 1136 env->serror.esr = events.exception.serror_esr; 1137 1138 return 0; 1139 } 1140 1141 #define ARM64_REG_ESR_EL1 ARM64_SYS_REG(3, 0, 5, 2, 0) 1142 #define ARM64_REG_TCR_EL1 ARM64_SYS_REG(3, 0, 2, 0, 2) 1143 1144 /* 1145 * ESR_EL1 1146 * ISS encoding 1147 * AARCH64: DFSC, bits [5:0] 1148 * AARCH32: 1149 * TTBCR.EAE == 0 1150 * FS[4] - DFSR[10] 1151 * FS[3:0] - DFSR[3:0] 1152 * TTBCR.EAE == 1 1153 * FS, bits [5:0] 1154 */ 1155 #define ESR_DFSC(aarch64, lpae, v) \ 1156 ((aarch64 || (lpae)) ? ((v) & 0x3F) \ 1157 : (((v) >> 6) | ((v) & 0x1F))) 1158 1159 #define ESR_DFSC_EXTABT(aarch64, lpae) \ 1160 ((aarch64) ? 0x10 : (lpae) ? 0x10 : 0x8) 1161 1162 /** 1163 * kvm_arm_verify_ext_dabt_pending: 1164 * @cpu: ARMCPU 1165 * 1166 * Verify the fault status code wrt the Ext DABT injection 1167 * 1168 * Returns: true if the fault status code is as expected, false otherwise 1169 */ 1170 static bool kvm_arm_verify_ext_dabt_pending(ARMCPU *cpu) 1171 { 1172 CPUState *cs = CPU(cpu); 1173 uint64_t dfsr_val; 1174 1175 if (!kvm_get_one_reg(cs, ARM64_REG_ESR_EL1, &dfsr_val)) { 1176 CPUARMState *env = &cpu->env; 1177 int aarch64_mode = arm_feature(env, ARM_FEATURE_AARCH64); 1178 int lpae = 0; 1179 1180 if (!aarch64_mode) { 1181 uint64_t ttbcr; 1182 1183 if (!kvm_get_one_reg(cs, ARM64_REG_TCR_EL1, &ttbcr)) { 1184 lpae = arm_feature(env, ARM_FEATURE_LPAE) 1185 && (ttbcr & TTBCR_EAE); 1186 } 1187 } 1188 /* 1189 * The verification here is based on the DFSC bits 1190 * of the ESR_EL1 reg only 1191 */ 1192 return (ESR_DFSC(aarch64_mode, lpae, dfsr_val) == 1193 ESR_DFSC_EXTABT(aarch64_mode, lpae)); 1194 } 1195 return false; 1196 } 1197 1198 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) 1199 { 1200 ARMCPU *cpu = ARM_CPU(cs); 1201 CPUARMState *env = &cpu->env; 1202 1203 if (unlikely(env->ext_dabt_raised)) { 1204 /* 1205 * Verifying that the ext DABT has been properly injected, 1206 * otherwise risking indefinitely re-running the faulting instruction 1207 * Covering a very narrow case for kernels 5.5..5.5.4 1208 * when injected abort was misconfigured to be 1209 * an IMPLEMENTATION DEFINED exception (for 32-bit EL1) 1210 */ 1211 if (!arm_feature(env, ARM_FEATURE_AARCH64) && 1212 unlikely(!kvm_arm_verify_ext_dabt_pending(cpu))) { 1213 1214 error_report("Data abort exception with no valid ISS generated by " 1215 "guest memory access. KVM unable to emulate faulting " 1216 "instruction. Failed to inject an external data abort " 1217 "into the guest."); 1218 abort(); 1219 } 1220 /* Clear the status */ 1221 env->ext_dabt_raised = 0; 1222 } 1223 } 1224 1225 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) 1226 { 1227 ARMCPU *cpu; 1228 uint32_t switched_level; 1229 1230 if (kvm_irqchip_in_kernel()) { 1231 /* 1232 * We only need to sync timer states with user-space interrupt 1233 * controllers, so return early and save cycles if we don't. 1234 */ 1235 return MEMTXATTRS_UNSPECIFIED; 1236 } 1237 1238 cpu = ARM_CPU(cs); 1239 1240 /* Synchronize our shadowed in-kernel device irq lines with the kvm ones */ 1241 if (run->s.regs.device_irq_level != cpu->device_irq_level) { 1242 switched_level = cpu->device_irq_level ^ run->s.regs.device_irq_level; 1243 1244 bql_lock(); 1245 1246 if (switched_level & KVM_ARM_DEV_EL1_VTIMER) { 1247 qemu_set_irq(cpu->gt_timer_outputs[GTIMER_VIRT], 1248 !!(run->s.regs.device_irq_level & 1249 KVM_ARM_DEV_EL1_VTIMER)); 1250 switched_level &= ~KVM_ARM_DEV_EL1_VTIMER; 1251 } 1252 1253 if (switched_level & KVM_ARM_DEV_EL1_PTIMER) { 1254 qemu_set_irq(cpu->gt_timer_outputs[GTIMER_PHYS], 1255 !!(run->s.regs.device_irq_level & 1256 KVM_ARM_DEV_EL1_PTIMER)); 1257 switched_level &= ~KVM_ARM_DEV_EL1_PTIMER; 1258 } 1259 1260 if (switched_level & KVM_ARM_DEV_PMU) { 1261 qemu_set_irq(cpu->pmu_interrupt, 1262 !!(run->s.regs.device_irq_level & KVM_ARM_DEV_PMU)); 1263 switched_level &= ~KVM_ARM_DEV_PMU; 1264 } 1265 1266 if (switched_level) { 1267 qemu_log_mask(LOG_UNIMP, "%s: unhandled in-kernel device IRQ %x\n", 1268 __func__, switched_level); 1269 } 1270 1271 /* We also mark unknown levels as processed to not waste cycles */ 1272 cpu->device_irq_level = run->s.regs.device_irq_level; 1273 bql_unlock(); 1274 } 1275 1276 return MEMTXATTRS_UNSPECIFIED; 1277 } 1278 1279 static void kvm_arm_vm_state_change(void *opaque, bool running, RunState state) 1280 { 1281 ARMCPU *cpu = opaque; 1282 1283 if (running) { 1284 if (cpu->kvm_adjvtime) { 1285 kvm_arm_put_virtual_time(cpu); 1286 } 1287 } else { 1288 if (cpu->kvm_adjvtime) { 1289 kvm_arm_get_virtual_time(cpu); 1290 } 1291 } 1292 } 1293 1294 /** 1295 * kvm_arm_handle_dabt_nisv: 1296 * @cpu: ARMCPU 1297 * @esr_iss: ISS encoding (limited) for the exception from Data Abort 1298 * ISV bit set to '0b0' -> no valid instruction syndrome 1299 * @fault_ipa: faulting address for the synchronous data abort 1300 * 1301 * Returns: 0 if the exception has been handled, < 0 otherwise 1302 */ 1303 static int kvm_arm_handle_dabt_nisv(ARMCPU *cpu, uint64_t esr_iss, 1304 uint64_t fault_ipa) 1305 { 1306 CPUARMState *env = &cpu->env; 1307 /* 1308 * Request KVM to inject the external data abort into the guest 1309 */ 1310 if (cap_has_inject_ext_dabt) { 1311 struct kvm_vcpu_events events = { }; 1312 /* 1313 * The external data abort event will be handled immediately by KVM 1314 * using the address fault that triggered the exit on given VCPU. 1315 * Requesting injection of the external data abort does not rely 1316 * on any other VCPU state. Therefore, in this particular case, the VCPU 1317 * synchronization can be exceptionally skipped. 1318 */ 1319 events.exception.ext_dabt_pending = 1; 1320 /* KVM_CAP_ARM_INJECT_EXT_DABT implies KVM_CAP_VCPU_EVENTS */ 1321 if (!kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events)) { 1322 env->ext_dabt_raised = 1; 1323 return 0; 1324 } 1325 } else { 1326 error_report("Data abort exception triggered by guest memory access " 1327 "at physical address: 0x" TARGET_FMT_lx, 1328 (target_ulong)fault_ipa); 1329 error_printf("KVM unable to emulate faulting instruction.\n"); 1330 } 1331 return -1; 1332 } 1333 1334 /** 1335 * kvm_arm_handle_debug: 1336 * @cpu: ARMCPU 1337 * @debug_exit: debug part of the KVM exit structure 1338 * 1339 * Returns: TRUE if the debug exception was handled. 1340 * 1341 * See v8 ARM ARM D7.2.27 ESR_ELx, Exception Syndrome Register 1342 * 1343 * To minimise translating between kernel and user-space the kernel 1344 * ABI just provides user-space with the full exception syndrome 1345 * register value to be decoded in QEMU. 1346 */ 1347 static bool kvm_arm_handle_debug(ARMCPU *cpu, 1348 struct kvm_debug_exit_arch *debug_exit) 1349 { 1350 int hsr_ec = syn_get_ec(debug_exit->hsr); 1351 CPUState *cs = CPU(cpu); 1352 CPUARMState *env = &cpu->env; 1353 1354 /* Ensure PC is synchronised */ 1355 kvm_cpu_synchronize_state(cs); 1356 1357 switch (hsr_ec) { 1358 case EC_SOFTWARESTEP: 1359 if (cs->singlestep_enabled) { 1360 return true; 1361 } else { 1362 /* 1363 * The kernel should have suppressed the guest's ability to 1364 * single step at this point so something has gone wrong. 1365 */ 1366 error_report("%s: guest single-step while debugging unsupported" 1367 " (%"PRIx64", %"PRIx32")", 1368 __func__, env->pc, debug_exit->hsr); 1369 return false; 1370 } 1371 break; 1372 case EC_AA64_BKPT: 1373 if (kvm_find_sw_breakpoint(cs, env->pc)) { 1374 return true; 1375 } 1376 break; 1377 case EC_BREAKPOINT: 1378 if (find_hw_breakpoint(cs, env->pc)) { 1379 return true; 1380 } 1381 break; 1382 case EC_WATCHPOINT: 1383 { 1384 CPUWatchpoint *wp = find_hw_watchpoint(cs, debug_exit->far); 1385 if (wp) { 1386 cs->watchpoint_hit = wp; 1387 return true; 1388 } 1389 break; 1390 } 1391 default: 1392 error_report("%s: unhandled debug exit (%"PRIx32", %"PRIx64")", 1393 __func__, debug_exit->hsr, env->pc); 1394 } 1395 1396 /* If we are not handling the debug exception it must belong to 1397 * the guest. Let's re-use the existing TCG interrupt code to set 1398 * everything up properly. 1399 */ 1400 cs->exception_index = EXCP_BKPT; 1401 env->exception.syndrome = debug_exit->hsr; 1402 env->exception.vaddress = debug_exit->far; 1403 env->exception.target_el = 1; 1404 bql_lock(); 1405 arm_cpu_do_interrupt(cs); 1406 bql_unlock(); 1407 1408 return false; 1409 } 1410 1411 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) 1412 { 1413 ARMCPU *cpu = ARM_CPU(cs); 1414 int ret = 0; 1415 1416 switch (run->exit_reason) { 1417 case KVM_EXIT_DEBUG: 1418 if (kvm_arm_handle_debug(cpu, &run->debug.arch)) { 1419 ret = EXCP_DEBUG; 1420 } /* otherwise return to guest */ 1421 break; 1422 case KVM_EXIT_ARM_NISV: 1423 /* External DABT with no valid iss to decode */ 1424 ret = kvm_arm_handle_dabt_nisv(cpu, run->arm_nisv.esr_iss, 1425 run->arm_nisv.fault_ipa); 1426 break; 1427 default: 1428 qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n", 1429 __func__, run->exit_reason); 1430 break; 1431 } 1432 return ret; 1433 } 1434 1435 bool kvm_arch_stop_on_emulation_error(CPUState *cs) 1436 { 1437 return true; 1438 } 1439 1440 int kvm_arch_process_async_events(CPUState *cs) 1441 { 1442 return 0; 1443 } 1444 1445 /** 1446 * kvm_arm_hw_debug_active: 1447 * @cpu: ARMCPU 1448 * 1449 * Return: TRUE if any hardware breakpoints in use. 1450 */ 1451 static bool kvm_arm_hw_debug_active(ARMCPU *cpu) 1452 { 1453 return ((cur_hw_wps > 0) || (cur_hw_bps > 0)); 1454 } 1455 1456 /** 1457 * kvm_arm_copy_hw_debug_data: 1458 * @ptr: kvm_guest_debug_arch structure 1459 * 1460 * Copy the architecture specific debug registers into the 1461 * kvm_guest_debug ioctl structure. 1462 */ 1463 static void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr) 1464 { 1465 int i; 1466 memset(ptr, 0, sizeof(struct kvm_guest_debug_arch)); 1467 1468 for (i = 0; i < max_hw_wps; i++) { 1469 HWWatchpoint *wp = get_hw_wp(i); 1470 ptr->dbg_wcr[i] = wp->wcr; 1471 ptr->dbg_wvr[i] = wp->wvr; 1472 } 1473 for (i = 0; i < max_hw_bps; i++) { 1474 HWBreakpoint *bp = get_hw_bp(i); 1475 ptr->dbg_bcr[i] = bp->bcr; 1476 ptr->dbg_bvr[i] = bp->bvr; 1477 } 1478 } 1479 1480 void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg) 1481 { 1482 if (kvm_sw_breakpoints_active(cs)) { 1483 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP; 1484 } 1485 if (kvm_arm_hw_debug_active(ARM_CPU(cs))) { 1486 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW; 1487 kvm_arm_copy_hw_debug_data(&dbg->arch); 1488 } 1489 } 1490 1491 void kvm_arch_init_irq_routing(KVMState *s) 1492 { 1493 } 1494 1495 int kvm_arch_irqchip_create(KVMState *s) 1496 { 1497 if (kvm_kernel_irqchip_split()) { 1498 error_report("-machine kernel_irqchip=split is not supported on ARM."); 1499 exit(1); 1500 } 1501 1502 /* If we can create the VGIC using the newer device control API, we 1503 * let the device do this when it initializes itself, otherwise we 1504 * fall back to the old API */ 1505 return kvm_check_extension(s, KVM_CAP_DEVICE_CTRL); 1506 } 1507 1508 int kvm_arm_vgic_probe(void) 1509 { 1510 int val = 0; 1511 1512 if (kvm_create_device(kvm_state, 1513 KVM_DEV_TYPE_ARM_VGIC_V3, true) == 0) { 1514 val |= KVM_ARM_VGIC_V3; 1515 } 1516 if (kvm_create_device(kvm_state, 1517 KVM_DEV_TYPE_ARM_VGIC_V2, true) == 0) { 1518 val |= KVM_ARM_VGIC_V2; 1519 } 1520 return val; 1521 } 1522 1523 int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level) 1524 { 1525 int kvm_irq = (irqtype << KVM_ARM_IRQ_TYPE_SHIFT) | irq; 1526 int cpu_idx1 = cpu % 256; 1527 int cpu_idx2 = cpu / 256; 1528 1529 kvm_irq |= (cpu_idx1 << KVM_ARM_IRQ_VCPU_SHIFT) | 1530 (cpu_idx2 << KVM_ARM_IRQ_VCPU2_SHIFT); 1531 1532 return kvm_set_irq(kvm_state, kvm_irq, !!level); 1533 } 1534 1535 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, 1536 uint64_t address, uint32_t data, PCIDevice *dev) 1537 { 1538 AddressSpace *as = pci_device_iommu_address_space(dev); 1539 hwaddr xlat, len, doorbell_gpa; 1540 MemoryRegionSection mrs; 1541 MemoryRegion *mr; 1542 1543 if (as == &address_space_memory) { 1544 return 0; 1545 } 1546 1547 /* MSI doorbell address is translated by an IOMMU */ 1548 1549 RCU_READ_LOCK_GUARD(); 1550 1551 mr = address_space_translate(as, address, &xlat, &len, true, 1552 MEMTXATTRS_UNSPECIFIED); 1553 1554 if (!mr) { 1555 return 1; 1556 } 1557 1558 mrs = memory_region_find(mr, xlat, 1); 1559 1560 if (!mrs.mr) { 1561 return 1; 1562 } 1563 1564 doorbell_gpa = mrs.offset_within_address_space; 1565 memory_region_unref(mrs.mr); 1566 1567 route->u.msi.address_lo = doorbell_gpa; 1568 route->u.msi.address_hi = doorbell_gpa >> 32; 1569 1570 trace_kvm_arm_fixup_msi_route(address, doorbell_gpa); 1571 1572 return 0; 1573 } 1574 1575 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, 1576 int vector, PCIDevice *dev) 1577 { 1578 return 0; 1579 } 1580 1581 int kvm_arch_release_virq_post(int virq) 1582 { 1583 return 0; 1584 } 1585 1586 int kvm_arch_msi_data_to_gsi(uint32_t data) 1587 { 1588 return (data - 32) & 0xffff; 1589 } 1590 1591 static void kvm_arch_get_eager_split_size(Object *obj, Visitor *v, 1592 const char *name, void *opaque, 1593 Error **errp) 1594 { 1595 KVMState *s = KVM_STATE(obj); 1596 uint64_t value = s->kvm_eager_split_size; 1597 1598 visit_type_size(v, name, &value, errp); 1599 } 1600 1601 static void kvm_arch_set_eager_split_size(Object *obj, Visitor *v, 1602 const char *name, void *opaque, 1603 Error **errp) 1604 { 1605 KVMState *s = KVM_STATE(obj); 1606 uint64_t value; 1607 1608 if (s->fd != -1) { 1609 error_setg(errp, "Unable to set early-split-size after KVM has been initialized"); 1610 return; 1611 } 1612 1613 if (!visit_type_size(v, name, &value, errp)) { 1614 return; 1615 } 1616 1617 if (value && !is_power_of_2(value)) { 1618 error_setg(errp, "early-split-size must be a power of two"); 1619 return; 1620 } 1621 1622 s->kvm_eager_split_size = value; 1623 } 1624 1625 void kvm_arch_accel_class_init(ObjectClass *oc) 1626 { 1627 object_class_property_add(oc, "eager-split-size", "size", 1628 kvm_arch_get_eager_split_size, 1629 kvm_arch_set_eager_split_size, NULL, NULL); 1630 1631 object_class_property_set_description(oc, "eager-split-size", 1632 "Eager Page Split chunk size for hugepages. (default: 0, disabled)"); 1633 } 1634 1635 int kvm_arch_insert_hw_breakpoint(vaddr addr, vaddr len, int type) 1636 { 1637 switch (type) { 1638 case GDB_BREAKPOINT_HW: 1639 return insert_hw_breakpoint(addr); 1640 break; 1641 case GDB_WATCHPOINT_READ: 1642 case GDB_WATCHPOINT_WRITE: 1643 case GDB_WATCHPOINT_ACCESS: 1644 return insert_hw_watchpoint(addr, len, type); 1645 default: 1646 return -ENOSYS; 1647 } 1648 } 1649 1650 int kvm_arch_remove_hw_breakpoint(vaddr addr, vaddr len, int type) 1651 { 1652 switch (type) { 1653 case GDB_BREAKPOINT_HW: 1654 return delete_hw_breakpoint(addr); 1655 case GDB_WATCHPOINT_READ: 1656 case GDB_WATCHPOINT_WRITE: 1657 case GDB_WATCHPOINT_ACCESS: 1658 return delete_hw_watchpoint(addr, len, type); 1659 default: 1660 return -ENOSYS; 1661 } 1662 } 1663 1664 void kvm_arch_remove_all_hw_breakpoints(void) 1665 { 1666 if (cur_hw_wps > 0) { 1667 g_array_remove_range(hw_watchpoints, 0, cur_hw_wps); 1668 } 1669 if (cur_hw_bps > 0) { 1670 g_array_remove_range(hw_breakpoints, 0, cur_hw_bps); 1671 } 1672 } 1673 1674 static bool kvm_arm_set_device_attr(ARMCPU *cpu, struct kvm_device_attr *attr, 1675 const char *name) 1676 { 1677 int err; 1678 1679 err = kvm_vcpu_ioctl(CPU(cpu), KVM_HAS_DEVICE_ATTR, attr); 1680 if (err != 0) { 1681 error_report("%s: KVM_HAS_DEVICE_ATTR: %s", name, strerror(-err)); 1682 return false; 1683 } 1684 1685 err = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEVICE_ATTR, attr); 1686 if (err != 0) { 1687 error_report("%s: KVM_SET_DEVICE_ATTR: %s", name, strerror(-err)); 1688 return false; 1689 } 1690 1691 return true; 1692 } 1693 1694 void kvm_arm_pmu_init(ARMCPU *cpu) 1695 { 1696 struct kvm_device_attr attr = { 1697 .group = KVM_ARM_VCPU_PMU_V3_CTRL, 1698 .attr = KVM_ARM_VCPU_PMU_V3_INIT, 1699 }; 1700 1701 if (!cpu->has_pmu) { 1702 return; 1703 } 1704 if (!kvm_arm_set_device_attr(cpu, &attr, "PMU")) { 1705 error_report("failed to init PMU"); 1706 abort(); 1707 } 1708 } 1709 1710 void kvm_arm_pmu_set_irq(ARMCPU *cpu, int irq) 1711 { 1712 struct kvm_device_attr attr = { 1713 .group = KVM_ARM_VCPU_PMU_V3_CTRL, 1714 .addr = (intptr_t)&irq, 1715 .attr = KVM_ARM_VCPU_PMU_V3_IRQ, 1716 }; 1717 1718 if (!cpu->has_pmu) { 1719 return; 1720 } 1721 if (!kvm_arm_set_device_attr(cpu, &attr, "PMU")) { 1722 error_report("failed to set irq for PMU"); 1723 abort(); 1724 } 1725 } 1726 1727 void kvm_arm_pvtime_init(ARMCPU *cpu, uint64_t ipa) 1728 { 1729 struct kvm_device_attr attr = { 1730 .group = KVM_ARM_VCPU_PVTIME_CTRL, 1731 .attr = KVM_ARM_VCPU_PVTIME_IPA, 1732 .addr = (uint64_t)&ipa, 1733 }; 1734 1735 if (cpu->kvm_steal_time == ON_OFF_AUTO_OFF) { 1736 return; 1737 } 1738 if (!kvm_arm_set_device_attr(cpu, &attr, "PVTIME IPA")) { 1739 error_report("failed to init PVTIME IPA"); 1740 abort(); 1741 } 1742 } 1743 1744 void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp) 1745 { 1746 bool has_steal_time = kvm_check_extension(kvm_state, KVM_CAP_STEAL_TIME); 1747 1748 if (cpu->kvm_steal_time == ON_OFF_AUTO_AUTO) { 1749 if (!has_steal_time || !arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1750 cpu->kvm_steal_time = ON_OFF_AUTO_OFF; 1751 } else { 1752 cpu->kvm_steal_time = ON_OFF_AUTO_ON; 1753 } 1754 } else if (cpu->kvm_steal_time == ON_OFF_AUTO_ON) { 1755 if (!has_steal_time) { 1756 error_setg(errp, "'kvm-steal-time' cannot be enabled " 1757 "on this host"); 1758 return; 1759 } else if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1760 /* 1761 * DEN0057A chapter 2 says "This specification only covers 1762 * systems in which the Execution state of the hypervisor 1763 * as well as EL1 of virtual machines is AArch64.". And, 1764 * to ensure that, the smc/hvc calls are only specified as 1765 * smc64/hvc64. 1766 */ 1767 error_setg(errp, "'kvm-steal-time' cannot be enabled " 1768 "for AArch32 guests"); 1769 return; 1770 } 1771 } 1772 } 1773 1774 bool kvm_arm_aarch32_supported(void) 1775 { 1776 return kvm_check_extension(kvm_state, KVM_CAP_ARM_EL1_32BIT); 1777 } 1778 1779 bool kvm_arm_el2_supported(void) 1780 { 1781 return kvm_check_extension(kvm_state, KVM_CAP_ARM_EL2); 1782 } 1783 1784 bool kvm_arm_sve_supported(void) 1785 { 1786 return kvm_check_extension(kvm_state, KVM_CAP_ARM_SVE); 1787 } 1788 1789 bool kvm_arm_mte_supported(void) 1790 { 1791 return kvm_check_extension(kvm_state, KVM_CAP_ARM_MTE); 1792 } 1793 1794 QEMU_BUILD_BUG_ON(KVM_ARM64_SVE_VQ_MIN != 1); 1795 1796 uint32_t kvm_arm_sve_get_vls(ARMCPU *cpu) 1797 { 1798 /* Only call this function if kvm_arm_sve_supported() returns true. */ 1799 static uint64_t vls[KVM_ARM64_SVE_VLS_WORDS]; 1800 static bool probed; 1801 uint32_t vq = 0; 1802 int i; 1803 1804 /* 1805 * KVM ensures all host CPUs support the same set of vector lengths. 1806 * So we only need to create the scratch VCPUs once and then cache 1807 * the results. 1808 */ 1809 if (!probed) { 1810 struct kvm_vcpu_init init = { 1811 .target = -1, 1812 .features[0] = (1 << KVM_ARM_VCPU_SVE), 1813 }; 1814 struct kvm_one_reg reg = { 1815 .id = KVM_REG_ARM64_SVE_VLS, 1816 .addr = (uint64_t)&vls[0], 1817 }; 1818 int fdarray[3], ret; 1819 1820 probed = true; 1821 1822 if (!kvm_arm_create_scratch_host_vcpu(fdarray, &init)) { 1823 error_report("failed to create scratch VCPU with SVE enabled"); 1824 abort(); 1825 } 1826 ret = ioctl(fdarray[2], KVM_GET_ONE_REG, ®); 1827 kvm_arm_destroy_scratch_host_vcpu(fdarray); 1828 if (ret) { 1829 error_report("failed to get KVM_REG_ARM64_SVE_VLS: %s", 1830 strerror(errno)); 1831 abort(); 1832 } 1833 1834 for (i = KVM_ARM64_SVE_VLS_WORDS - 1; i >= 0; --i) { 1835 if (vls[i]) { 1836 vq = 64 - clz64(vls[i]) + i * 64; 1837 break; 1838 } 1839 } 1840 if (vq > ARM_MAX_VQ) { 1841 warn_report("KVM supports vector lengths larger than " 1842 "QEMU can enable"); 1843 vls[0] &= MAKE_64BIT_MASK(0, ARM_MAX_VQ); 1844 } 1845 } 1846 1847 return vls[0]; 1848 } 1849 1850 static int kvm_arm_sve_set_vls(ARMCPU *cpu) 1851 { 1852 uint64_t vls[KVM_ARM64_SVE_VLS_WORDS] = { cpu->sve_vq.map }; 1853 1854 assert(cpu->sve_max_vq <= KVM_ARM64_SVE_VQ_MAX); 1855 1856 return kvm_set_one_reg(CPU(cpu), KVM_REG_ARM64_SVE_VLS, &vls[0]); 1857 } 1858 1859 #define ARM_CPU_ID_MPIDR 3, 0, 0, 0, 5 1860 1861 int kvm_arch_pre_create_vcpu(CPUState *cpu, Error **errp) 1862 { 1863 return 0; 1864 } 1865 1866 int kvm_arch_init_vcpu(CPUState *cs) 1867 { 1868 int ret; 1869 uint64_t mpidr; 1870 ARMCPU *cpu = ARM_CPU(cs); 1871 CPUARMState *env = &cpu->env; 1872 uint64_t psciver; 1873 1874 if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE) { 1875 error_report("KVM is not supported for this guest CPU type"); 1876 return -EINVAL; 1877 } 1878 1879 qemu_add_vm_change_state_handler(kvm_arm_vm_state_change, cpu); 1880 1881 /* Determine init features for this CPU */ 1882 memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features)); 1883 if (cs->start_powered_off) { 1884 cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_POWER_OFF; 1885 } 1886 if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PSCI_0_2)) { 1887 cpu->psci_version = QEMU_PSCI_VERSION_0_2; 1888 cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PSCI_0_2; 1889 } 1890 if (!arm_feature(env, ARM_FEATURE_AARCH64)) { 1891 cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_EL1_32BIT; 1892 } 1893 if (cpu->has_pmu) { 1894 cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PMU_V3; 1895 } 1896 if (cpu_isar_feature(aa64_sve, cpu)) { 1897 assert(kvm_arm_sve_supported()); 1898 cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_SVE; 1899 } 1900 if (cpu_isar_feature(aa64_pauth, cpu)) { 1901 cpu->kvm_init_features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS | 1902 1 << KVM_ARM_VCPU_PTRAUTH_GENERIC); 1903 } 1904 if (cpu->has_el2 && kvm_arm_el2_supported()) { 1905 cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_HAS_EL2; 1906 } 1907 1908 /* Do KVM_ARM_VCPU_INIT ioctl */ 1909 ret = kvm_arm_vcpu_init(cpu); 1910 if (ret) { 1911 return ret; 1912 } 1913 1914 if (cpu_isar_feature(aa64_sve, cpu)) { 1915 ret = kvm_arm_sve_set_vls(cpu); 1916 if (ret) { 1917 return ret; 1918 } 1919 ret = kvm_arm_vcpu_finalize(cpu, KVM_ARM_VCPU_SVE); 1920 if (ret) { 1921 return ret; 1922 } 1923 } 1924 1925 /* 1926 * KVM reports the exact PSCI version it is implementing via a 1927 * special sysreg. If it is present, use its contents to determine 1928 * what to report to the guest in the dtb (it is the PSCI version, 1929 * in the same 15-bits major 16-bits minor format that PSCI_VERSION 1930 * returns). 1931 */ 1932 if (!kvm_get_one_reg(cs, KVM_REG_ARM_PSCI_VERSION, &psciver)) { 1933 cpu->psci_version = psciver; 1934 } 1935 1936 /* 1937 * When KVM is in use, PSCI is emulated in-kernel and not by qemu. 1938 * Currently KVM has its own idea about MPIDR assignment, so we 1939 * override our defaults with what we get from KVM. 1940 */ 1941 ret = kvm_get_one_reg(cs, ARM64_SYS_REG(ARM_CPU_ID_MPIDR), &mpidr); 1942 if (ret) { 1943 return ret; 1944 } 1945 cpu->mp_affinity = mpidr & ARM64_AFFINITY_MASK; 1946 1947 return kvm_arm_init_cpreg_list(cpu); 1948 } 1949 1950 int kvm_arch_destroy_vcpu(CPUState *cs) 1951 { 1952 return 0; 1953 } 1954 1955 /* Callers must hold the iothread mutex lock */ 1956 static void kvm_inject_arm_sea(CPUState *c) 1957 { 1958 ARMCPU *cpu = ARM_CPU(c); 1959 CPUARMState *env = &cpu->env; 1960 uint32_t esr; 1961 bool same_el; 1962 1963 c->exception_index = EXCP_DATA_ABORT; 1964 env->exception.target_el = 1; 1965 1966 /* 1967 * Set the DFSC to synchronous external abort and set FnV to not valid, 1968 * this will tell guest the FAR_ELx is UNKNOWN for this abort. 1969 */ 1970 same_el = arm_current_el(env) == env->exception.target_el; 1971 esr = syn_data_abort_no_iss(same_el, 1, 0, 0, 0, 0, 0x10); 1972 1973 env->exception.syndrome = esr; 1974 1975 arm_cpu_do_interrupt(c); 1976 } 1977 1978 #define AARCH64_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \ 1979 KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x)) 1980 1981 #define AARCH64_SIMD_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U128 | \ 1982 KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x)) 1983 1984 #define AARCH64_SIMD_CTRL_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U32 | \ 1985 KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x)) 1986 1987 static int kvm_arch_put_fpsimd(CPUState *cs) 1988 { 1989 CPUARMState *env = &ARM_CPU(cs)->env; 1990 int i, ret; 1991 1992 for (i = 0; i < 32; i++) { 1993 uint64_t *q = aa64_vfp_qreg(env, i); 1994 #if HOST_BIG_ENDIAN 1995 uint64_t fp_val[2] = { q[1], q[0] }; 1996 ret = kvm_set_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]), 1997 fp_val); 1998 #else 1999 ret = kvm_set_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]), q); 2000 #endif 2001 if (ret) { 2002 return ret; 2003 } 2004 } 2005 2006 return 0; 2007 } 2008 2009 /* 2010 * KVM SVE registers come in slices where ZREGs have a slice size of 2048 bits 2011 * and PREGS and the FFR have a slice size of 256 bits. However we simply hard 2012 * code the slice index to zero for now as it's unlikely we'll need more than 2013 * one slice for quite some time. 2014 */ 2015 static int kvm_arch_put_sve(CPUState *cs) 2016 { 2017 ARMCPU *cpu = ARM_CPU(cs); 2018 CPUARMState *env = &cpu->env; 2019 uint64_t tmp[ARM_MAX_VQ * 2]; 2020 uint64_t *r; 2021 int n, ret; 2022 2023 for (n = 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) { 2024 r = sve_bswap64(tmp, &env->vfp.zregs[n].d[0], cpu->sve_max_vq * 2); 2025 ret = kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_ZREG(n, 0), r); 2026 if (ret) { 2027 return ret; 2028 } 2029 } 2030 2031 for (n = 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) { 2032 r = sve_bswap64(tmp, r = &env->vfp.pregs[n].p[0], 2033 DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); 2034 ret = kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_PREG(n, 0), r); 2035 if (ret) { 2036 return ret; 2037 } 2038 } 2039 2040 r = sve_bswap64(tmp, &env->vfp.pregs[FFR_PRED_NUM].p[0], 2041 DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); 2042 ret = kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_FFR(0), r); 2043 if (ret) { 2044 return ret; 2045 } 2046 2047 return 0; 2048 } 2049 2050 int kvm_arch_put_registers(CPUState *cs, int level, Error **errp) 2051 { 2052 uint64_t val; 2053 uint32_t fpr; 2054 int i, ret; 2055 unsigned int el; 2056 2057 ARMCPU *cpu = ARM_CPU(cs); 2058 CPUARMState *env = &cpu->env; 2059 2060 /* If we are in AArch32 mode then we need to copy the AArch32 regs to the 2061 * AArch64 registers before pushing them out to 64-bit KVM. 2062 */ 2063 if (!is_a64(env)) { 2064 aarch64_sync_32_to_64(env); 2065 } 2066 2067 for (i = 0; i < 31; i++) { 2068 ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.regs[i]), 2069 &env->xregs[i]); 2070 if (ret) { 2071 return ret; 2072 } 2073 } 2074 2075 /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the 2076 * QEMU side we keep the current SP in xregs[31] as well. 2077 */ 2078 aarch64_save_sp(env, 1); 2079 2080 ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.sp), &env->sp_el[0]); 2081 if (ret) { 2082 return ret; 2083 } 2084 2085 ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(sp_el1), &env->sp_el[1]); 2086 if (ret) { 2087 return ret; 2088 } 2089 2090 /* Note that KVM thinks pstate is 64 bit but we use a uint32_t */ 2091 if (is_a64(env)) { 2092 val = pstate_read(env); 2093 } else { 2094 val = cpsr_read(env); 2095 } 2096 ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.pstate), &val); 2097 if (ret) { 2098 return ret; 2099 } 2100 2101 ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.pc), &env->pc); 2102 if (ret) { 2103 return ret; 2104 } 2105 2106 ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(elr_el1), &env->elr_el[1]); 2107 if (ret) { 2108 return ret; 2109 } 2110 2111 /* Saved Program State Registers 2112 * 2113 * Before we restore from the banked_spsr[] array we need to 2114 * ensure that any modifications to env->spsr are correctly 2115 * reflected in the banks. 2116 */ 2117 el = arm_current_el(env); 2118 if (el > 0 && !is_a64(env)) { 2119 i = bank_number(env->uncached_cpsr & CPSR_M); 2120 env->banked_spsr[i] = env->spsr; 2121 } 2122 2123 /* KVM 0-4 map to QEMU banks 1-5 */ 2124 for (i = 0; i < KVM_NR_SPSR; i++) { 2125 ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(spsr[i]), 2126 &env->banked_spsr[i + 1]); 2127 if (ret) { 2128 return ret; 2129 } 2130 } 2131 2132 if (cpu_isar_feature(aa64_sve, cpu)) { 2133 ret = kvm_arch_put_sve(cs); 2134 } else { 2135 ret = kvm_arch_put_fpsimd(cs); 2136 } 2137 if (ret) { 2138 return ret; 2139 } 2140 2141 fpr = vfp_get_fpsr(env); 2142 ret = kvm_set_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpsr), &fpr); 2143 if (ret) { 2144 return ret; 2145 } 2146 2147 fpr = vfp_get_fpcr(env); 2148 ret = kvm_set_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpcr), &fpr); 2149 if (ret) { 2150 return ret; 2151 } 2152 2153 write_cpustate_to_list(cpu, true); 2154 2155 if (!write_list_to_kvmstate(cpu, level)) { 2156 return -EINVAL; 2157 } 2158 2159 /* 2160 * Setting VCPU events should be triggered after syncing the registers 2161 * to avoid overwriting potential changes made by KVM upon calling 2162 * KVM_SET_VCPU_EVENTS ioctl 2163 */ 2164 ret = kvm_put_vcpu_events(cpu); 2165 if (ret) { 2166 return ret; 2167 } 2168 2169 return kvm_arm_sync_mpstate_to_kvm(cpu); 2170 } 2171 2172 static int kvm_arch_get_fpsimd(CPUState *cs) 2173 { 2174 CPUARMState *env = &ARM_CPU(cs)->env; 2175 int i, ret; 2176 2177 for (i = 0; i < 32; i++) { 2178 uint64_t *q = aa64_vfp_qreg(env, i); 2179 ret = kvm_get_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]), q); 2180 if (ret) { 2181 return ret; 2182 } else { 2183 #if HOST_BIG_ENDIAN 2184 uint64_t t; 2185 t = q[0], q[0] = q[1], q[1] = t; 2186 #endif 2187 } 2188 } 2189 2190 return 0; 2191 } 2192 2193 /* 2194 * KVM SVE registers come in slices where ZREGs have a slice size of 2048 bits 2195 * and PREGS and the FFR have a slice size of 256 bits. However we simply hard 2196 * code the slice index to zero for now as it's unlikely we'll need more than 2197 * one slice for quite some time. 2198 */ 2199 static int kvm_arch_get_sve(CPUState *cs) 2200 { 2201 ARMCPU *cpu = ARM_CPU(cs); 2202 CPUARMState *env = &cpu->env; 2203 uint64_t *r; 2204 int n, ret; 2205 2206 for (n = 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) { 2207 r = &env->vfp.zregs[n].d[0]; 2208 ret = kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_ZREG(n, 0), r); 2209 if (ret) { 2210 return ret; 2211 } 2212 sve_bswap64(r, r, cpu->sve_max_vq * 2); 2213 } 2214 2215 for (n = 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) { 2216 r = &env->vfp.pregs[n].p[0]; 2217 ret = kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_PREG(n, 0), r); 2218 if (ret) { 2219 return ret; 2220 } 2221 sve_bswap64(r, r, DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); 2222 } 2223 2224 r = &env->vfp.pregs[FFR_PRED_NUM].p[0]; 2225 ret = kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_FFR(0), r); 2226 if (ret) { 2227 return ret; 2228 } 2229 sve_bswap64(r, r, DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); 2230 2231 return 0; 2232 } 2233 2234 int kvm_arch_get_registers(CPUState *cs, Error **errp) 2235 { 2236 uint64_t val; 2237 unsigned int el; 2238 uint32_t fpr; 2239 int i, ret; 2240 2241 ARMCPU *cpu = ARM_CPU(cs); 2242 CPUARMState *env = &cpu->env; 2243 2244 for (i = 0; i < 31; i++) { 2245 ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.regs[i]), 2246 &env->xregs[i]); 2247 if (ret) { 2248 return ret; 2249 } 2250 } 2251 2252 ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.sp), &env->sp_el[0]); 2253 if (ret) { 2254 return ret; 2255 } 2256 2257 ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(sp_el1), &env->sp_el[1]); 2258 if (ret) { 2259 return ret; 2260 } 2261 2262 ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.pstate), &val); 2263 if (ret) { 2264 return ret; 2265 } 2266 2267 env->aarch64 = ((val & PSTATE_nRW) == 0); 2268 if (is_a64(env)) { 2269 pstate_write(env, val); 2270 } else { 2271 cpsr_write(env, val, 0xffffffff, CPSRWriteRaw); 2272 } 2273 2274 /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the 2275 * QEMU side we keep the current SP in xregs[31] as well. 2276 */ 2277 aarch64_restore_sp(env, 1); 2278 2279 ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.pc), &env->pc); 2280 if (ret) { 2281 return ret; 2282 } 2283 2284 /* If we are in AArch32 mode then we need to sync the AArch32 regs with the 2285 * incoming AArch64 regs received from 64-bit KVM. 2286 * We must perform this after all of the registers have been acquired from 2287 * the kernel. 2288 */ 2289 if (!is_a64(env)) { 2290 aarch64_sync_64_to_32(env); 2291 } 2292 2293 ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(elr_el1), &env->elr_el[1]); 2294 if (ret) { 2295 return ret; 2296 } 2297 2298 /* Fetch the SPSR registers 2299 * 2300 * KVM SPSRs 0-4 map to QEMU banks 1-5 2301 */ 2302 for (i = 0; i < KVM_NR_SPSR; i++) { 2303 ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(spsr[i]), 2304 &env->banked_spsr[i + 1]); 2305 if (ret) { 2306 return ret; 2307 } 2308 } 2309 2310 el = arm_current_el(env); 2311 if (el > 0 && !is_a64(env)) { 2312 i = bank_number(env->uncached_cpsr & CPSR_M); 2313 env->spsr = env->banked_spsr[i]; 2314 } 2315 2316 if (cpu_isar_feature(aa64_sve, cpu)) { 2317 ret = kvm_arch_get_sve(cs); 2318 } else { 2319 ret = kvm_arch_get_fpsimd(cs); 2320 } 2321 if (ret) { 2322 return ret; 2323 } 2324 2325 ret = kvm_get_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpsr), &fpr); 2326 if (ret) { 2327 return ret; 2328 } 2329 vfp_set_fpsr(env, fpr); 2330 2331 ret = kvm_get_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpcr), &fpr); 2332 if (ret) { 2333 return ret; 2334 } 2335 vfp_set_fpcr(env, fpr); 2336 2337 ret = kvm_get_vcpu_events(cpu); 2338 if (ret) { 2339 return ret; 2340 } 2341 2342 if (!write_kvmstate_to_list(cpu)) { 2343 return -EINVAL; 2344 } 2345 /* Note that it's OK to have registers which aren't in CPUState, 2346 * so we can ignore a failure return here. 2347 */ 2348 write_list_to_cpustate(cpu); 2349 2350 ret = kvm_arm_sync_mpstate_to_qemu(cpu); 2351 2352 /* TODO: other registers */ 2353 return ret; 2354 } 2355 2356 void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr) 2357 { 2358 ram_addr_t ram_addr; 2359 hwaddr paddr; 2360 2361 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO); 2362 2363 if (acpi_ghes_present() && addr) { 2364 ram_addr = qemu_ram_addr_from_host(addr); 2365 if (ram_addr != RAM_ADDR_INVALID && 2366 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) { 2367 kvm_hwpoison_page_add(ram_addr); 2368 /* 2369 * If this is a BUS_MCEERR_AR, we know we have been called 2370 * synchronously from the vCPU thread, so we can easily 2371 * synchronize the state and inject an error. 2372 * 2373 * TODO: we currently don't tell the guest at all about 2374 * BUS_MCEERR_AO. In that case we might either be being 2375 * called synchronously from the vCPU thread, or a bit 2376 * later from the main thread, so doing the injection of 2377 * the error would be more complicated. 2378 */ 2379 if (code == BUS_MCEERR_AR) { 2380 kvm_cpu_synchronize_state(c); 2381 if (!acpi_ghes_memory_errors(ACPI_HEST_SRC_ID_SEA, paddr)) { 2382 kvm_inject_arm_sea(c); 2383 } else { 2384 error_report("failed to record the error"); 2385 abort(); 2386 } 2387 } 2388 return; 2389 } 2390 if (code == BUS_MCEERR_AO) { 2391 error_report("Hardware memory error at addr %p for memory used by " 2392 "QEMU itself instead of guest system!", addr); 2393 } 2394 } 2395 2396 if (code == BUS_MCEERR_AR) { 2397 error_report("Hardware memory error!"); 2398 exit(1); 2399 } 2400 } 2401 2402 /* C6.6.29 BRK instruction */ 2403 static const uint32_t brk_insn = 0xd4200000; 2404 2405 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 2406 { 2407 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 0) || 2408 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&brk_insn, 4, 1)) { 2409 return -EINVAL; 2410 } 2411 return 0; 2412 } 2413 2414 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 2415 { 2416 static uint32_t brk; 2417 2418 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&brk, 4, 0) || 2419 brk != brk_insn || 2420 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 1)) { 2421 return -EINVAL; 2422 } 2423 return 0; 2424 } 2425 2426 void kvm_arm_enable_mte(Object *cpuobj, Error **errp) 2427 { 2428 static bool tried_to_enable; 2429 static bool succeeded_to_enable; 2430 Error *mte_migration_blocker = NULL; 2431 ARMCPU *cpu = ARM_CPU(cpuobj); 2432 int ret; 2433 2434 if (!tried_to_enable) { 2435 /* 2436 * MTE on KVM is enabled on a per-VM basis (and retrying doesn't make 2437 * sense), and we only want a single migration blocker as well. 2438 */ 2439 tried_to_enable = true; 2440 2441 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_ARM_MTE, 0); 2442 if (ret) { 2443 error_setg_errno(errp, -ret, "Failed to enable KVM_CAP_ARM_MTE"); 2444 return; 2445 } 2446 2447 /* TODO: Add migration support with MTE enabled */ 2448 error_setg(&mte_migration_blocker, 2449 "Live migration disabled due to MTE enabled"); 2450 if (migrate_add_blocker(&mte_migration_blocker, errp)) { 2451 error_free(mte_migration_blocker); 2452 return; 2453 } 2454 2455 succeeded_to_enable = true; 2456 } 2457 2458 if (succeeded_to_enable) { 2459 cpu->kvm_mte = true; 2460 } 2461 } 2462 2463 void arm_cpu_kvm_set_irq(void *arm_cpu, int irq, int level) 2464 { 2465 ARMCPU *cpu = arm_cpu; 2466 CPUARMState *env = &cpu->env; 2467 CPUState *cs = CPU(cpu); 2468 uint32_t linestate_bit; 2469 int irq_id; 2470 2471 switch (irq) { 2472 case ARM_CPU_IRQ: 2473 irq_id = KVM_ARM_IRQ_CPU_IRQ; 2474 linestate_bit = CPU_INTERRUPT_HARD; 2475 break; 2476 case ARM_CPU_FIQ: 2477 irq_id = KVM_ARM_IRQ_CPU_FIQ; 2478 linestate_bit = CPU_INTERRUPT_FIQ; 2479 break; 2480 default: 2481 g_assert_not_reached(); 2482 } 2483 2484 if (level) { 2485 env->irq_line_state |= linestate_bit; 2486 } else { 2487 env->irq_line_state &= ~linestate_bit; 2488 } 2489 kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); 2490 } 2491