1 /* 2 * QEMU ARM CPU -- internal functions and types 3 * 4 * Copyright (c) 2014 Linaro Ltd 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 * 20 * This header defines functions, types, etc which need to be shared 21 * between different source files within target/arm/ but which are 22 * private to it and not required by the rest of QEMU. 23 */ 24 25 #ifndef TARGET_ARM_INTERNALS_H 26 #define TARGET_ARM_INTERNALS_H 27 28 #include "hw/registerfields.h" 29 #include "tcg/tcg-gvec-desc.h" 30 #include "syndrome.h" 31 32 /* register banks for CPU modes */ 33 #define BANK_USRSYS 0 34 #define BANK_SVC 1 35 #define BANK_ABT 2 36 #define BANK_UND 3 37 #define BANK_IRQ 4 38 #define BANK_FIQ 5 39 #define BANK_HYP 6 40 #define BANK_MON 7 41 42 static inline bool excp_is_internal(int excp) 43 { 44 /* Return true if this exception number represents a QEMU-internal 45 * exception that will not be passed to the guest. 46 */ 47 return excp == EXCP_INTERRUPT 48 || excp == EXCP_HLT 49 || excp == EXCP_DEBUG 50 || excp == EXCP_HALTED 51 || excp == EXCP_EXCEPTION_EXIT 52 || excp == EXCP_KERNEL_TRAP 53 || excp == EXCP_SEMIHOST; 54 } 55 56 /* Scale factor for generic timers, ie number of ns per tick. 57 * This gives a 62.5MHz timer. 58 */ 59 #define GTIMER_SCALE 16 60 61 /* Bit definitions for the v7M CONTROL register */ 62 FIELD(V7M_CONTROL, NPRIV, 0, 1) 63 FIELD(V7M_CONTROL, SPSEL, 1, 1) 64 FIELD(V7M_CONTROL, FPCA, 2, 1) 65 FIELD(V7M_CONTROL, SFPA, 3, 1) 66 67 /* Bit definitions for v7M exception return payload */ 68 FIELD(V7M_EXCRET, ES, 0, 1) 69 FIELD(V7M_EXCRET, RES0, 1, 1) 70 FIELD(V7M_EXCRET, SPSEL, 2, 1) 71 FIELD(V7M_EXCRET, MODE, 3, 1) 72 FIELD(V7M_EXCRET, FTYPE, 4, 1) 73 FIELD(V7M_EXCRET, DCRS, 5, 1) 74 FIELD(V7M_EXCRET, S, 6, 1) 75 FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */ 76 77 /* Minimum value which is a magic number for exception return */ 78 #define EXC_RETURN_MIN_MAGIC 0xff000000 79 /* Minimum number which is a magic number for function or exception return 80 * when using v8M security extension 81 */ 82 #define FNC_RETURN_MIN_MAGIC 0xfefffffe 83 84 /* We use a few fake FSR values for internal purposes in M profile. 85 * M profile cores don't have A/R format FSRs, but currently our 86 * get_phys_addr() code assumes A/R profile and reports failures via 87 * an A/R format FSR value. We then translate that into the proper 88 * M profile exception and FSR status bit in arm_v7m_cpu_do_interrupt(). 89 * Mostly the FSR values we use for this are those defined for v7PMSA, 90 * since we share some of that codepath. A few kinds of fault are 91 * only for M profile and have no A/R equivalent, though, so we have 92 * to pick a value from the reserved range (which we never otherwise 93 * generate) to use for these. 94 * These values will never be visible to the guest. 95 */ 96 #define M_FAKE_FSR_NSC_EXEC 0xf /* NS executing in S&NSC memory */ 97 #define M_FAKE_FSR_SFAULT 0xe /* SecureFault INVTRAN, INVEP or AUVIOL */ 98 99 /** 100 * raise_exception: Raise the specified exception. 101 * Raise a guest exception with the specified value, syndrome register 102 * and target exception level. This should be called from helper functions, 103 * and never returns because we will longjump back up to the CPU main loop. 104 */ 105 void QEMU_NORETURN raise_exception(CPUARMState *env, uint32_t excp, 106 uint32_t syndrome, uint32_t target_el); 107 108 /* 109 * Similarly, but also use unwinding to restore cpu state. 110 */ 111 void QEMU_NORETURN raise_exception_ra(CPUARMState *env, uint32_t excp, 112 uint32_t syndrome, uint32_t target_el, 113 uintptr_t ra); 114 115 /* 116 * For AArch64, map a given EL to an index in the banked_spsr array. 117 * Note that this mapping and the AArch32 mapping defined in bank_number() 118 * must agree such that the AArch64<->AArch32 SPSRs have the architecturally 119 * mandated mapping between each other. 120 */ 121 static inline unsigned int aarch64_banked_spsr_index(unsigned int el) 122 { 123 static const unsigned int map[4] = { 124 [1] = BANK_SVC, /* EL1. */ 125 [2] = BANK_HYP, /* EL2. */ 126 [3] = BANK_MON, /* EL3. */ 127 }; 128 assert(el >= 1 && el <= 3); 129 return map[el]; 130 } 131 132 /* Map CPU modes onto saved register banks. */ 133 static inline int bank_number(int mode) 134 { 135 switch (mode) { 136 case ARM_CPU_MODE_USR: 137 case ARM_CPU_MODE_SYS: 138 return BANK_USRSYS; 139 case ARM_CPU_MODE_SVC: 140 return BANK_SVC; 141 case ARM_CPU_MODE_ABT: 142 return BANK_ABT; 143 case ARM_CPU_MODE_UND: 144 return BANK_UND; 145 case ARM_CPU_MODE_IRQ: 146 return BANK_IRQ; 147 case ARM_CPU_MODE_FIQ: 148 return BANK_FIQ; 149 case ARM_CPU_MODE_HYP: 150 return BANK_HYP; 151 case ARM_CPU_MODE_MON: 152 return BANK_MON; 153 } 154 g_assert_not_reached(); 155 } 156 157 /** 158 * r14_bank_number: Map CPU mode onto register bank for r14 159 * 160 * Given an AArch32 CPU mode, return the index into the saved register 161 * banks to use for the R14 (LR) in that mode. This is the same as 162 * bank_number(), except for the special case of Hyp mode, where 163 * R14 is shared with USR and SYS, unlike its R13 and SPSR. 164 * This should be used as the index into env->banked_r14[], and 165 * bank_number() used for the index into env->banked_r13[] and 166 * env->banked_spsr[]. 167 */ 168 static inline int r14_bank_number(int mode) 169 { 170 return (mode == ARM_CPU_MODE_HYP) ? BANK_USRSYS : bank_number(mode); 171 } 172 173 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu); 174 void arm_translate_init(void); 175 176 #ifdef CONFIG_TCG 177 void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb); 178 #endif /* CONFIG_TCG */ 179 180 /** 181 * aarch64_sve_zcr_get_valid_len: 182 * @cpu: cpu context 183 * @start_len: maximum len to consider 184 * 185 * Return the maximum supported sve vector length <= @start_len. 186 * Note that both @start_len and the return value are in units 187 * of ZCR_ELx.LEN, so the vector bit length is (x + 1) * 128. 188 */ 189 uint32_t aarch64_sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len); 190 191 enum arm_fprounding { 192 FPROUNDING_TIEEVEN, 193 FPROUNDING_POSINF, 194 FPROUNDING_NEGINF, 195 FPROUNDING_ZERO, 196 FPROUNDING_TIEAWAY, 197 FPROUNDING_ODD 198 }; 199 200 int arm_rmode_to_sf(int rmode); 201 202 static inline void aarch64_save_sp(CPUARMState *env, int el) 203 { 204 if (env->pstate & PSTATE_SP) { 205 env->sp_el[el] = env->xregs[31]; 206 } else { 207 env->sp_el[0] = env->xregs[31]; 208 } 209 } 210 211 static inline void aarch64_restore_sp(CPUARMState *env, int el) 212 { 213 if (env->pstate & PSTATE_SP) { 214 env->xregs[31] = env->sp_el[el]; 215 } else { 216 env->xregs[31] = env->sp_el[0]; 217 } 218 } 219 220 static inline void update_spsel(CPUARMState *env, uint32_t imm) 221 { 222 unsigned int cur_el = arm_current_el(env); 223 /* Update PSTATE SPSel bit; this requires us to update the 224 * working stack pointer in xregs[31]. 225 */ 226 if (!((imm ^ env->pstate) & PSTATE_SP)) { 227 return; 228 } 229 aarch64_save_sp(env, cur_el); 230 env->pstate = deposit32(env->pstate, 0, 1, imm); 231 232 /* We rely on illegal updates to SPsel from EL0 to get trapped 233 * at translation time. 234 */ 235 assert(cur_el >= 1 && cur_el <= 3); 236 aarch64_restore_sp(env, cur_el); 237 } 238 239 /* 240 * arm_pamax 241 * @cpu: ARMCPU 242 * 243 * Returns the implementation defined bit-width of physical addresses. 244 * The ARMv8 reference manuals refer to this as PAMax(). 245 */ 246 static inline unsigned int arm_pamax(ARMCPU *cpu) 247 { 248 static const unsigned int pamax_map[] = { 249 [0] = 32, 250 [1] = 36, 251 [2] = 40, 252 [3] = 42, 253 [4] = 44, 254 [5] = 48, 255 }; 256 unsigned int parange = 257 FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE); 258 259 /* id_aa64mmfr0 is a read-only register so values outside of the 260 * supported mappings can be considered an implementation error. */ 261 assert(parange < ARRAY_SIZE(pamax_map)); 262 return pamax_map[parange]; 263 } 264 265 /* Return true if extended addresses are enabled. 266 * This is always the case if our translation regime is 64 bit, 267 * but depends on TTBCR.EAE for 32 bit. 268 */ 269 static inline bool extended_addresses_enabled(CPUARMState *env) 270 { 271 TCR *tcr = &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1]; 272 return arm_el_is_aa64(env, 1) || 273 (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE)); 274 } 275 276 /* Update a QEMU watchpoint based on the information the guest has set in the 277 * DBGWCR<n>_EL1 and DBGWVR<n>_EL1 registers. 278 */ 279 void hw_watchpoint_update(ARMCPU *cpu, int n); 280 /* Update the QEMU watchpoints for every guest watchpoint. This does a 281 * complete delete-and-reinstate of the QEMU watchpoint list and so is 282 * suitable for use after migration or on reset. 283 */ 284 void hw_watchpoint_update_all(ARMCPU *cpu); 285 /* Update a QEMU breakpoint based on the information the guest has set in the 286 * DBGBCR<n>_EL1 and DBGBVR<n>_EL1 registers. 287 */ 288 void hw_breakpoint_update(ARMCPU *cpu, int n); 289 /* Update the QEMU breakpoints for every guest breakpoint. This does a 290 * complete delete-and-reinstate of the QEMU breakpoint list and so is 291 * suitable for use after migration or on reset. 292 */ 293 void hw_breakpoint_update_all(ARMCPU *cpu); 294 295 /* Callback function for checking if a breakpoint should trigger. */ 296 bool arm_debug_check_breakpoint(CPUState *cs); 297 298 /* Callback function for checking if a watchpoint should trigger. */ 299 bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); 300 301 /* Adjust addresses (in BE32 mode) before testing against watchpoint 302 * addresses. 303 */ 304 vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len); 305 306 /* Callback function for when a watchpoint or breakpoint triggers. */ 307 void arm_debug_excp_handler(CPUState *cs); 308 309 #if defined(CONFIG_USER_ONLY) || !defined(CONFIG_TCG) 310 static inline bool arm_is_psci_call(ARMCPU *cpu, int excp_type) 311 { 312 return false; 313 } 314 static inline void arm_handle_psci_call(ARMCPU *cpu) 315 { 316 g_assert_not_reached(); 317 } 318 #else 319 /* Return true if the r0/x0 value indicates that this SMC/HVC is a PSCI call. */ 320 bool arm_is_psci_call(ARMCPU *cpu, int excp_type); 321 /* Actually handle a PSCI call */ 322 void arm_handle_psci_call(ARMCPU *cpu); 323 #endif 324 325 /** 326 * arm_clear_exclusive: clear the exclusive monitor 327 * @env: CPU env 328 * Clear the CPU's exclusive monitor, like the guest CLREX instruction. 329 */ 330 static inline void arm_clear_exclusive(CPUARMState *env) 331 { 332 env->exclusive_addr = -1; 333 } 334 335 /** 336 * ARMFaultType: type of an ARM MMU fault 337 * This corresponds to the v8A pseudocode's Fault enumeration, 338 * with extensions for QEMU internal conditions. 339 */ 340 typedef enum ARMFaultType { 341 ARMFault_None, 342 ARMFault_AccessFlag, 343 ARMFault_Alignment, 344 ARMFault_Background, 345 ARMFault_Domain, 346 ARMFault_Permission, 347 ARMFault_Translation, 348 ARMFault_AddressSize, 349 ARMFault_SyncExternal, 350 ARMFault_SyncExternalOnWalk, 351 ARMFault_SyncParity, 352 ARMFault_SyncParityOnWalk, 353 ARMFault_AsyncParity, 354 ARMFault_AsyncExternal, 355 ARMFault_Debug, 356 ARMFault_TLBConflict, 357 ARMFault_Lockdown, 358 ARMFault_Exclusive, 359 ARMFault_ICacheMaint, 360 ARMFault_QEMU_NSCExec, /* v8M: NS executing in S&NSC memory */ 361 ARMFault_QEMU_SFault, /* v8M: SecureFault INVTRAN, INVEP or AUVIOL */ 362 } ARMFaultType; 363 364 /** 365 * ARMMMUFaultInfo: Information describing an ARM MMU Fault 366 * @type: Type of fault 367 * @level: Table walk level (for translation, access flag and permission faults) 368 * @domain: Domain of the fault address (for non-LPAE CPUs only) 369 * @s2addr: Address that caused a fault at stage 2 370 * @stage2: True if we faulted at stage 2 371 * @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table walk 372 * @s1ns: True if we faulted on a non-secure IPA while in secure state 373 * @ea: True if we should set the EA (external abort type) bit in syndrome 374 */ 375 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; 376 struct ARMMMUFaultInfo { 377 ARMFaultType type; 378 target_ulong s2addr; 379 int level; 380 int domain; 381 bool stage2; 382 bool s1ptw; 383 bool s1ns; 384 bool ea; 385 }; 386 387 /** 388 * arm_fi_to_sfsc: Convert fault info struct to short-format FSC 389 * Compare pseudocode EncodeSDFSC(), though unlike that function 390 * we set up a whole FSR-format code including domain field and 391 * putting the high bit of the FSC into bit 10. 392 */ 393 static inline uint32_t arm_fi_to_sfsc(ARMMMUFaultInfo *fi) 394 { 395 uint32_t fsc; 396 397 switch (fi->type) { 398 case ARMFault_None: 399 return 0; 400 case ARMFault_AccessFlag: 401 fsc = fi->level == 1 ? 0x3 : 0x6; 402 break; 403 case ARMFault_Alignment: 404 fsc = 0x1; 405 break; 406 case ARMFault_Permission: 407 fsc = fi->level == 1 ? 0xd : 0xf; 408 break; 409 case ARMFault_Domain: 410 fsc = fi->level == 1 ? 0x9 : 0xb; 411 break; 412 case ARMFault_Translation: 413 fsc = fi->level == 1 ? 0x5 : 0x7; 414 break; 415 case ARMFault_SyncExternal: 416 fsc = 0x8 | (fi->ea << 12); 417 break; 418 case ARMFault_SyncExternalOnWalk: 419 fsc = fi->level == 1 ? 0xc : 0xe; 420 fsc |= (fi->ea << 12); 421 break; 422 case ARMFault_SyncParity: 423 fsc = 0x409; 424 break; 425 case ARMFault_SyncParityOnWalk: 426 fsc = fi->level == 1 ? 0x40c : 0x40e; 427 break; 428 case ARMFault_AsyncParity: 429 fsc = 0x408; 430 break; 431 case ARMFault_AsyncExternal: 432 fsc = 0x406 | (fi->ea << 12); 433 break; 434 case ARMFault_Debug: 435 fsc = 0x2; 436 break; 437 case ARMFault_TLBConflict: 438 fsc = 0x400; 439 break; 440 case ARMFault_Lockdown: 441 fsc = 0x404; 442 break; 443 case ARMFault_Exclusive: 444 fsc = 0x405; 445 break; 446 case ARMFault_ICacheMaint: 447 fsc = 0x4; 448 break; 449 case ARMFault_Background: 450 fsc = 0x0; 451 break; 452 case ARMFault_QEMU_NSCExec: 453 fsc = M_FAKE_FSR_NSC_EXEC; 454 break; 455 case ARMFault_QEMU_SFault: 456 fsc = M_FAKE_FSR_SFAULT; 457 break; 458 default: 459 /* Other faults can't occur in a context that requires a 460 * short-format status code. 461 */ 462 g_assert_not_reached(); 463 } 464 465 fsc |= (fi->domain << 4); 466 return fsc; 467 } 468 469 /** 470 * arm_fi_to_lfsc: Convert fault info struct to long-format FSC 471 * Compare pseudocode EncodeLDFSC(), though unlike that function 472 * we fill in also the LPAE bit 9 of a DFSR format. 473 */ 474 static inline uint32_t arm_fi_to_lfsc(ARMMMUFaultInfo *fi) 475 { 476 uint32_t fsc; 477 478 switch (fi->type) { 479 case ARMFault_None: 480 return 0; 481 case ARMFault_AddressSize: 482 fsc = fi->level & 3; 483 break; 484 case ARMFault_AccessFlag: 485 fsc = (fi->level & 3) | (0x2 << 2); 486 break; 487 case ARMFault_Permission: 488 fsc = (fi->level & 3) | (0x3 << 2); 489 break; 490 case ARMFault_Translation: 491 fsc = (fi->level & 3) | (0x1 << 2); 492 break; 493 case ARMFault_SyncExternal: 494 fsc = 0x10 | (fi->ea << 12); 495 break; 496 case ARMFault_SyncExternalOnWalk: 497 fsc = (fi->level & 3) | (0x5 << 2) | (fi->ea << 12); 498 break; 499 case ARMFault_SyncParity: 500 fsc = 0x18; 501 break; 502 case ARMFault_SyncParityOnWalk: 503 fsc = (fi->level & 3) | (0x7 << 2); 504 break; 505 case ARMFault_AsyncParity: 506 fsc = 0x19; 507 break; 508 case ARMFault_AsyncExternal: 509 fsc = 0x11 | (fi->ea << 12); 510 break; 511 case ARMFault_Alignment: 512 fsc = 0x21; 513 break; 514 case ARMFault_Debug: 515 fsc = 0x22; 516 break; 517 case ARMFault_TLBConflict: 518 fsc = 0x30; 519 break; 520 case ARMFault_Lockdown: 521 fsc = 0x34; 522 break; 523 case ARMFault_Exclusive: 524 fsc = 0x35; 525 break; 526 default: 527 /* Other faults can't occur in a context that requires a 528 * long-format status code. 529 */ 530 g_assert_not_reached(); 531 } 532 533 fsc |= 1 << 9; 534 return fsc; 535 } 536 537 static inline bool arm_extabort_type(MemTxResult result) 538 { 539 /* The EA bit in syndromes and fault status registers is an 540 * IMPDEF classification of external aborts. ARM implementations 541 * usually use this to indicate AXI bus Decode error (0) or 542 * Slave error (1); in QEMU we follow that. 543 */ 544 return result != MEMTX_DECODE_ERROR; 545 } 546 547 bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 548 MMUAccessType access_type, int mmu_idx, 549 bool probe, uintptr_t retaddr); 550 551 static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) 552 { 553 return mmu_idx & ARM_MMU_IDX_COREIDX_MASK; 554 } 555 556 static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx) 557 { 558 if (arm_feature(env, ARM_FEATURE_M)) { 559 return mmu_idx | ARM_MMU_IDX_M; 560 } else { 561 return mmu_idx | ARM_MMU_IDX_A; 562 } 563 } 564 565 static inline ARMMMUIdx core_to_aa64_mmu_idx(int mmu_idx) 566 { 567 /* AArch64 is always a-profile. */ 568 return mmu_idx | ARM_MMU_IDX_A; 569 } 570 571 int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx); 572 573 /* 574 * Return the MMU index for a v7M CPU with all relevant information 575 * manually specified. 576 */ 577 ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, 578 bool secstate, bool priv, bool negpri); 579 580 /* 581 * Return the MMU index for a v7M CPU in the specified security and 582 * privilege state. 583 */ 584 ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, 585 bool secstate, bool priv); 586 587 /* Return the MMU index for a v7M CPU in the specified security state */ 588 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); 589 590 /* Return true if the stage 1 translation regime is using LPAE format page 591 * tables */ 592 bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx); 593 594 /* Raise a data fault alignment exception for the specified virtual address */ 595 void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, 596 MMUAccessType access_type, 597 int mmu_idx, uintptr_t retaddr) QEMU_NORETURN; 598 599 /* arm_cpu_do_transaction_failed: handle a memory system error response 600 * (eg "no device/memory present at address") by raising an external abort 601 * exception 602 */ 603 void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 604 vaddr addr, unsigned size, 605 MMUAccessType access_type, 606 int mmu_idx, MemTxAttrs attrs, 607 MemTxResult response, uintptr_t retaddr); 608 609 /* Call any registered EL change hooks */ 610 static inline void arm_call_pre_el_change_hook(ARMCPU *cpu) 611 { 612 ARMELChangeHook *hook, *next; 613 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 614 hook->hook(cpu, hook->opaque); 615 } 616 } 617 static inline void arm_call_el_change_hook(ARMCPU *cpu) 618 { 619 ARMELChangeHook *hook, *next; 620 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 621 hook->hook(cpu, hook->opaque); 622 } 623 } 624 625 /* Return true if this address translation regime has two ranges. */ 626 static inline bool regime_has_2_ranges(ARMMMUIdx mmu_idx) 627 { 628 switch (mmu_idx) { 629 case ARMMMUIdx_Stage1_E0: 630 case ARMMMUIdx_Stage1_E1: 631 case ARMMMUIdx_Stage1_E1_PAN: 632 case ARMMMUIdx_Stage1_SE0: 633 case ARMMMUIdx_Stage1_SE1: 634 case ARMMMUIdx_Stage1_SE1_PAN: 635 case ARMMMUIdx_E10_0: 636 case ARMMMUIdx_E10_1: 637 case ARMMMUIdx_E10_1_PAN: 638 case ARMMMUIdx_E20_0: 639 case ARMMMUIdx_E20_2: 640 case ARMMMUIdx_E20_2_PAN: 641 case ARMMMUIdx_SE10_0: 642 case ARMMMUIdx_SE10_1: 643 case ARMMMUIdx_SE10_1_PAN: 644 case ARMMMUIdx_SE20_0: 645 case ARMMMUIdx_SE20_2: 646 case ARMMMUIdx_SE20_2_PAN: 647 return true; 648 default: 649 return false; 650 } 651 } 652 653 /* Return true if this address translation regime is secure */ 654 static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) 655 { 656 switch (mmu_idx) { 657 case ARMMMUIdx_E10_0: 658 case ARMMMUIdx_E10_1: 659 case ARMMMUIdx_E10_1_PAN: 660 case ARMMMUIdx_E20_0: 661 case ARMMMUIdx_E20_2: 662 case ARMMMUIdx_E20_2_PAN: 663 case ARMMMUIdx_Stage1_E0: 664 case ARMMMUIdx_Stage1_E1: 665 case ARMMMUIdx_Stage1_E1_PAN: 666 case ARMMMUIdx_E2: 667 case ARMMMUIdx_Stage2: 668 case ARMMMUIdx_MPrivNegPri: 669 case ARMMMUIdx_MUserNegPri: 670 case ARMMMUIdx_MPriv: 671 case ARMMMUIdx_MUser: 672 return false; 673 case ARMMMUIdx_SE3: 674 case ARMMMUIdx_SE10_0: 675 case ARMMMUIdx_SE10_1: 676 case ARMMMUIdx_SE10_1_PAN: 677 case ARMMMUIdx_SE20_0: 678 case ARMMMUIdx_SE20_2: 679 case ARMMMUIdx_SE20_2_PAN: 680 case ARMMMUIdx_Stage1_SE0: 681 case ARMMMUIdx_Stage1_SE1: 682 case ARMMMUIdx_Stage1_SE1_PAN: 683 case ARMMMUIdx_SE2: 684 case ARMMMUIdx_Stage2_S: 685 case ARMMMUIdx_MSPrivNegPri: 686 case ARMMMUIdx_MSUserNegPri: 687 case ARMMMUIdx_MSPriv: 688 case ARMMMUIdx_MSUser: 689 return true; 690 default: 691 g_assert_not_reached(); 692 } 693 } 694 695 static inline bool regime_is_pan(CPUARMState *env, ARMMMUIdx mmu_idx) 696 { 697 switch (mmu_idx) { 698 case ARMMMUIdx_Stage1_E1_PAN: 699 case ARMMMUIdx_Stage1_SE1_PAN: 700 case ARMMMUIdx_E10_1_PAN: 701 case ARMMMUIdx_E20_2_PAN: 702 case ARMMMUIdx_SE10_1_PAN: 703 case ARMMMUIdx_SE20_2_PAN: 704 return true; 705 default: 706 return false; 707 } 708 } 709 710 /* Return the exception level which controls this address translation regime */ 711 static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) 712 { 713 switch (mmu_idx) { 714 case ARMMMUIdx_SE20_0: 715 case ARMMMUIdx_SE20_2: 716 case ARMMMUIdx_SE20_2_PAN: 717 case ARMMMUIdx_E20_0: 718 case ARMMMUIdx_E20_2: 719 case ARMMMUIdx_E20_2_PAN: 720 case ARMMMUIdx_Stage2: 721 case ARMMMUIdx_Stage2_S: 722 case ARMMMUIdx_SE2: 723 case ARMMMUIdx_E2: 724 return 2; 725 case ARMMMUIdx_SE3: 726 return 3; 727 case ARMMMUIdx_SE10_0: 728 case ARMMMUIdx_Stage1_SE0: 729 return arm_el_is_aa64(env, 3) ? 1 : 3; 730 case ARMMMUIdx_SE10_1: 731 case ARMMMUIdx_SE10_1_PAN: 732 case ARMMMUIdx_Stage1_E0: 733 case ARMMMUIdx_Stage1_E1: 734 case ARMMMUIdx_Stage1_E1_PAN: 735 case ARMMMUIdx_Stage1_SE1: 736 case ARMMMUIdx_Stage1_SE1_PAN: 737 case ARMMMUIdx_E10_0: 738 case ARMMMUIdx_E10_1: 739 case ARMMMUIdx_E10_1_PAN: 740 case ARMMMUIdx_MPrivNegPri: 741 case ARMMMUIdx_MUserNegPri: 742 case ARMMMUIdx_MPriv: 743 case ARMMMUIdx_MUser: 744 case ARMMMUIdx_MSPrivNegPri: 745 case ARMMMUIdx_MSUserNegPri: 746 case ARMMMUIdx_MSPriv: 747 case ARMMMUIdx_MSUser: 748 return 1; 749 default: 750 g_assert_not_reached(); 751 } 752 } 753 754 /* Return the TCR controlling this translation regime */ 755 static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) 756 { 757 if (mmu_idx == ARMMMUIdx_Stage2) { 758 return &env->cp15.vtcr_el2; 759 } 760 if (mmu_idx == ARMMMUIdx_Stage2_S) { 761 /* 762 * Note: Secure stage 2 nominally shares fields from VTCR_EL2, but 763 * those are not currently used by QEMU, so just return VSTCR_EL2. 764 */ 765 return &env->cp15.vstcr_el2; 766 } 767 return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; 768 } 769 770 /* Return the FSR value for a debug exception (watchpoint, hardware 771 * breakpoint or BKPT insn) targeting the specified exception level. 772 */ 773 static inline uint32_t arm_debug_exception_fsr(CPUARMState *env) 774 { 775 ARMMMUFaultInfo fi = { .type = ARMFault_Debug }; 776 int target_el = arm_debug_target_el(env); 777 bool using_lpae = false; 778 779 if (target_el == 2 || arm_el_is_aa64(env, target_el)) { 780 using_lpae = true; 781 } else { 782 if (arm_feature(env, ARM_FEATURE_LPAE) && 783 (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) { 784 using_lpae = true; 785 } 786 } 787 788 if (using_lpae) { 789 return arm_fi_to_lfsc(&fi); 790 } else { 791 return arm_fi_to_sfsc(&fi); 792 } 793 } 794 795 /** 796 * arm_num_brps: Return number of implemented breakpoints. 797 * Note that the ID register BRPS field is "number of bps - 1", 798 * and we return the actual number of breakpoints. 799 */ 800 static inline int arm_num_brps(ARMCPU *cpu) 801 { 802 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 803 return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, BRPS) + 1; 804 } else { 805 return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, BRPS) + 1; 806 } 807 } 808 809 /** 810 * arm_num_wrps: Return number of implemented watchpoints. 811 * Note that the ID register WRPS field is "number of wps - 1", 812 * and we return the actual number of watchpoints. 813 */ 814 static inline int arm_num_wrps(ARMCPU *cpu) 815 { 816 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 817 return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, WRPS) + 1; 818 } else { 819 return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, WRPS) + 1; 820 } 821 } 822 823 /** 824 * arm_num_ctx_cmps: Return number of implemented context comparators. 825 * Note that the ID register CTX_CMPS field is "number of cmps - 1", 826 * and we return the actual number of comparators. 827 */ 828 static inline int arm_num_ctx_cmps(ARMCPU *cpu) 829 { 830 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 831 return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS) + 1; 832 } else { 833 return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, CTX_CMPS) + 1; 834 } 835 } 836 837 /** 838 * v7m_using_psp: Return true if using process stack pointer 839 * Return true if the CPU is currently using the process stack 840 * pointer, or false if it is using the main stack pointer. 841 */ 842 static inline bool v7m_using_psp(CPUARMState *env) 843 { 844 /* Handler mode always uses the main stack; for thread mode 845 * the CONTROL.SPSEL bit determines the answer. 846 * Note that in v7M it is not possible to be in Handler mode with 847 * CONTROL.SPSEL non-zero, but in v8M it is, so we must check both. 848 */ 849 return !arm_v7m_is_handler_mode(env) && 850 env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK; 851 } 852 853 /** 854 * v7m_sp_limit: Return SP limit for current CPU state 855 * Return the SP limit value for the current CPU security state 856 * and stack pointer. 857 */ 858 static inline uint32_t v7m_sp_limit(CPUARMState *env) 859 { 860 if (v7m_using_psp(env)) { 861 return env->v7m.psplim[env->v7m.secure]; 862 } else { 863 return env->v7m.msplim[env->v7m.secure]; 864 } 865 } 866 867 /** 868 * v7m_cpacr_pass: 869 * Return true if the v7M CPACR permits access to the FPU for the specified 870 * security state and privilege level. 871 */ 872 static inline bool v7m_cpacr_pass(CPUARMState *env, 873 bool is_secure, bool is_priv) 874 { 875 switch (extract32(env->v7m.cpacr[is_secure], 20, 2)) { 876 case 0: 877 case 2: /* UNPREDICTABLE: we treat like 0 */ 878 return false; 879 case 1: 880 return is_priv; 881 case 3: 882 return true; 883 default: 884 g_assert_not_reached(); 885 } 886 } 887 888 /** 889 * aarch32_mode_name(): Return name of the AArch32 CPU mode 890 * @psr: Program Status Register indicating CPU mode 891 * 892 * Returns, for debug logging purposes, a printable representation 893 * of the AArch32 CPU mode ("svc", "usr", etc) as indicated by 894 * the low bits of the specified PSR. 895 */ 896 static inline const char *aarch32_mode_name(uint32_t psr) 897 { 898 static const char cpu_mode_names[16][4] = { 899 "usr", "fiq", "irq", "svc", "???", "???", "mon", "abt", 900 "???", "???", "hyp", "und", "???", "???", "???", "sys" 901 }; 902 903 return cpu_mode_names[psr & 0xf]; 904 } 905 906 /** 907 * arm_cpu_update_virq: Update CPU_INTERRUPT_VIRQ bit in cs->interrupt_request 908 * 909 * Update the CPU_INTERRUPT_VIRQ bit in cs->interrupt_request, following 910 * a change to either the input VIRQ line from the GIC or the HCR_EL2.VI bit. 911 * Must be called with the iothread lock held. 912 */ 913 void arm_cpu_update_virq(ARMCPU *cpu); 914 915 /** 916 * arm_cpu_update_vfiq: Update CPU_INTERRUPT_VFIQ bit in cs->interrupt_request 917 * 918 * Update the CPU_INTERRUPT_VFIQ bit in cs->interrupt_request, following 919 * a change to either the input VFIQ line from the GIC or the HCR_EL2.VF bit. 920 * Must be called with the iothread lock held. 921 */ 922 void arm_cpu_update_vfiq(ARMCPU *cpu); 923 924 /** 925 * arm_mmu_idx_el: 926 * @env: The cpu environment 927 * @el: The EL to use. 928 * 929 * Return the full ARMMMUIdx for the translation regime for EL. 930 */ 931 ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el); 932 933 /** 934 * arm_mmu_idx: 935 * @env: The cpu environment 936 * 937 * Return the full ARMMMUIdx for the current translation regime. 938 */ 939 ARMMMUIdx arm_mmu_idx(CPUARMState *env); 940 941 /** 942 * arm_stage1_mmu_idx: 943 * @env: The cpu environment 944 * 945 * Return the ARMMMUIdx for the stage1 traversal for the current regime. 946 */ 947 #ifdef CONFIG_USER_ONLY 948 static inline ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) 949 { 950 return ARMMMUIdx_Stage1_E0; 951 } 952 #else 953 ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env); 954 #endif 955 956 /** 957 * arm_mmu_idx_is_stage1_of_2: 958 * @mmu_idx: The ARMMMUIdx to test 959 * 960 * Return true if @mmu_idx is a NOTLB mmu_idx that is the 961 * first stage of a two stage regime. 962 */ 963 static inline bool arm_mmu_idx_is_stage1_of_2(ARMMMUIdx mmu_idx) 964 { 965 switch (mmu_idx) { 966 case ARMMMUIdx_Stage1_E0: 967 case ARMMMUIdx_Stage1_E1: 968 case ARMMMUIdx_Stage1_E1_PAN: 969 case ARMMMUIdx_Stage1_SE0: 970 case ARMMMUIdx_Stage1_SE1: 971 case ARMMMUIdx_Stage1_SE1_PAN: 972 return true; 973 default: 974 return false; 975 } 976 } 977 978 static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features, 979 const ARMISARegisters *id) 980 { 981 uint32_t valid = CPSR_M | CPSR_AIF | CPSR_IL | CPSR_NZCV; 982 983 if ((features >> ARM_FEATURE_V4T) & 1) { 984 valid |= CPSR_T; 985 } 986 if ((features >> ARM_FEATURE_V5) & 1) { 987 valid |= CPSR_Q; /* V5TE in reality*/ 988 } 989 if ((features >> ARM_FEATURE_V6) & 1) { 990 valid |= CPSR_E | CPSR_GE; 991 } 992 if ((features >> ARM_FEATURE_THUMB2) & 1) { 993 valid |= CPSR_IT; 994 } 995 if (isar_feature_aa32_jazelle(id)) { 996 valid |= CPSR_J; 997 } 998 if (isar_feature_aa32_pan(id)) { 999 valid |= CPSR_PAN; 1000 } 1001 if (isar_feature_aa32_dit(id)) { 1002 valid |= CPSR_DIT; 1003 } 1004 if (isar_feature_aa32_ssbs(id)) { 1005 valid |= CPSR_SSBS; 1006 } 1007 1008 return valid; 1009 } 1010 1011 static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id) 1012 { 1013 uint32_t valid; 1014 1015 valid = PSTATE_M | PSTATE_DAIF | PSTATE_IL | PSTATE_SS | PSTATE_NZCV; 1016 if (isar_feature_aa64_bti(id)) { 1017 valid |= PSTATE_BTYPE; 1018 } 1019 if (isar_feature_aa64_pan(id)) { 1020 valid |= PSTATE_PAN; 1021 } 1022 if (isar_feature_aa64_uao(id)) { 1023 valid |= PSTATE_UAO; 1024 } 1025 if (isar_feature_aa64_dit(id)) { 1026 valid |= PSTATE_DIT; 1027 } 1028 if (isar_feature_aa64_ssbs(id)) { 1029 valid |= PSTATE_SSBS; 1030 } 1031 if (isar_feature_aa64_mte(id)) { 1032 valid |= PSTATE_TCO; 1033 } 1034 1035 return valid; 1036 } 1037 1038 /* 1039 * Parameters of a given virtual address, as extracted from the 1040 * translation control register (TCR) for a given regime. 1041 */ 1042 typedef struct ARMVAParameters { 1043 unsigned tsz : 8; 1044 unsigned select : 1; 1045 bool tbi : 1; 1046 bool epd : 1; 1047 bool hpd : 1; 1048 bool using16k : 1; 1049 bool using64k : 1; 1050 } ARMVAParameters; 1051 1052 ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, 1053 ARMMMUIdx mmu_idx, bool data); 1054 1055 static inline int exception_target_el(CPUARMState *env) 1056 { 1057 int target_el = MAX(1, arm_current_el(env)); 1058 1059 /* 1060 * No such thing as secure EL1 if EL3 is aarch32, 1061 * so update the target EL to EL3 in this case. 1062 */ 1063 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el == 1) { 1064 target_el = 3; 1065 } 1066 1067 return target_el; 1068 } 1069 1070 /* Determine if allocation tags are available. */ 1071 static inline bool allocation_tag_access_enabled(CPUARMState *env, int el, 1072 uint64_t sctlr) 1073 { 1074 if (el < 3 1075 && arm_feature(env, ARM_FEATURE_EL3) 1076 && !(env->cp15.scr_el3 & SCR_ATA)) { 1077 return false; 1078 } 1079 if (el < 2 && arm_feature(env, ARM_FEATURE_EL2)) { 1080 uint64_t hcr = arm_hcr_el2_eff(env); 1081 if (!(hcr & HCR_ATA) && (!(hcr & HCR_E2H) || !(hcr & HCR_TGE))) { 1082 return false; 1083 } 1084 } 1085 sctlr &= (el == 0 ? SCTLR_ATA0 : SCTLR_ATA); 1086 return sctlr != 0; 1087 } 1088 1089 #ifndef CONFIG_USER_ONLY 1090 1091 /* Security attributes for an address, as returned by v8m_security_lookup. */ 1092 typedef struct V8M_SAttributes { 1093 bool subpage; /* true if these attrs don't cover the whole TARGET_PAGE */ 1094 bool ns; 1095 bool nsc; 1096 uint8_t sregion; 1097 bool srvalid; 1098 uint8_t iregion; 1099 bool irvalid; 1100 } V8M_SAttributes; 1101 1102 void v8m_security_lookup(CPUARMState *env, uint32_t address, 1103 MMUAccessType access_type, ARMMMUIdx mmu_idx, 1104 V8M_SAttributes *sattrs); 1105 1106 bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, 1107 MMUAccessType access_type, ARMMMUIdx mmu_idx, 1108 hwaddr *phys_ptr, MemTxAttrs *txattrs, 1109 int *prot, bool *is_subpage, 1110 ARMMMUFaultInfo *fi, uint32_t *mregion); 1111 1112 /* Cacheability and shareability attributes for a memory access */ 1113 typedef struct ARMCacheAttrs { 1114 unsigned int attrs:8; /* as in the MAIR register encoding */ 1115 unsigned int shareability:2; /* as in the SH field of the VMSAv8-64 PTEs */ 1116 } ARMCacheAttrs; 1117 1118 bool get_phys_addr(CPUARMState *env, target_ulong address, 1119 MMUAccessType access_type, ARMMMUIdx mmu_idx, 1120 hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, 1121 target_ulong *page_size, 1122 ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) 1123 __attribute__((nonnull)); 1124 1125 void arm_log_exception(int idx); 1126 1127 #endif /* !CONFIG_USER_ONLY */ 1128 1129 /* 1130 * The log2 of the words in the tag block, for GMID_EL1.BS. 1131 * The is the maximum, 256 bytes, which manipulates 64-bits of tags. 1132 */ 1133 #define GMID_EL1_BS 6 1134 1135 /* We associate one allocation tag per 16 bytes, the minimum. */ 1136 #define LOG2_TAG_GRANULE 4 1137 #define TAG_GRANULE (1 << LOG2_TAG_GRANULE) 1138 1139 /* 1140 * SVE predicates are 1/8 the size of SVE vectors, and cannot use 1141 * the same simd_desc() encoding due to restrictions on size. 1142 * Use these instead. 1143 */ 1144 FIELD(PREDDESC, OPRSZ, 0, 6) 1145 FIELD(PREDDESC, ESZ, 6, 2) 1146 FIELD(PREDDESC, DATA, 8, 24) 1147 1148 /* 1149 * The SVE simd_data field, for memory ops, contains either 1150 * rd (5 bits) or a shift count (2 bits). 1151 */ 1152 #define SVE_MTEDESC_SHIFT 5 1153 1154 /* Bits within a descriptor passed to the helper_mte_check* functions. */ 1155 FIELD(MTEDESC, MIDX, 0, 4) 1156 FIELD(MTEDESC, TBI, 4, 2) 1157 FIELD(MTEDESC, TCMA, 6, 2) 1158 FIELD(MTEDESC, WRITE, 8, 1) 1159 FIELD(MTEDESC, SIZEM1, 9, SIMD_DATA_BITS - 9) /* size - 1 */ 1160 1161 bool mte_probe(CPUARMState *env, uint32_t desc, uint64_t ptr); 1162 uint64_t mte_check(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_t ra); 1163 1164 static inline int allocation_tag_from_addr(uint64_t ptr) 1165 { 1166 return extract64(ptr, 56, 4); 1167 } 1168 1169 static inline uint64_t address_with_allocation_tag(uint64_t ptr, int rtag) 1170 { 1171 return deposit64(ptr, 56, 4, rtag); 1172 } 1173 1174 /* Return true if tbi bits mean that the access is checked. */ 1175 static inline bool tbi_check(uint32_t desc, int bit55) 1176 { 1177 return (desc >> (R_MTEDESC_TBI_SHIFT + bit55)) & 1; 1178 } 1179 1180 /* Return true if tcma bits mean that the access is unchecked. */ 1181 static inline bool tcma_check(uint32_t desc, int bit55, int ptr_tag) 1182 { 1183 /* 1184 * We had extracted bit55 and ptr_tag for other reasons, so fold 1185 * (ptr<59:55> == 00000 || ptr<59:55> == 11111) into a single test. 1186 */ 1187 bool match = ((ptr_tag + bit55) & 0xf) == 0; 1188 bool tcma = (desc >> (R_MTEDESC_TCMA_SHIFT + bit55)) & 1; 1189 return tcma && match; 1190 } 1191 1192 /* 1193 * For TBI, ideally, we would do nothing. Proper behaviour on fault is 1194 * for the tag to be present in the FAR_ELx register. But for user-only 1195 * mode, we do not have a TLB with which to implement this, so we must 1196 * remove the top byte. 1197 */ 1198 static inline uint64_t useronly_clean_ptr(uint64_t ptr) 1199 { 1200 #ifdef CONFIG_USER_ONLY 1201 /* TBI0 is known to be enabled, while TBI1 is disabled. */ 1202 ptr &= sextract64(ptr, 0, 56); 1203 #endif 1204 return ptr; 1205 } 1206 1207 static inline uint64_t useronly_maybe_clean_ptr(uint32_t desc, uint64_t ptr) 1208 { 1209 #ifdef CONFIG_USER_ONLY 1210 int64_t clean_ptr = sextract64(ptr, 0, 56); 1211 if (tbi_check(desc, clean_ptr < 0)) { 1212 ptr = clean_ptr; 1213 } 1214 #endif 1215 return ptr; 1216 } 1217 1218 /* Values for M-profile PSR.ECI for MVE insns */ 1219 enum MVEECIState { 1220 ECI_NONE = 0, /* No completed beats */ 1221 ECI_A0 = 1, /* Completed: A0 */ 1222 ECI_A0A1 = 2, /* Completed: A0, A1 */ 1223 /* 3 is reserved */ 1224 ECI_A0A1A2 = 4, /* Completed: A0, A1, A2 */ 1225 ECI_A0A1A2B0 = 5, /* Completed: A0, A1, A2, B0 */ 1226 /* All other values reserved */ 1227 }; 1228 1229 /* Definitions for the PMU registers */ 1230 #define PMCRN_MASK 0xf800 1231 #define PMCRN_SHIFT 11 1232 #define PMCRLC 0x40 1233 #define PMCRDP 0x20 1234 #define PMCRX 0x10 1235 #define PMCRD 0x8 1236 #define PMCRC 0x4 1237 #define PMCRP 0x2 1238 #define PMCRE 0x1 1239 /* 1240 * Mask of PMCR bits writeable by guest (not including WO bits like C, P, 1241 * which can be written as 1 to trigger behaviour but which stay RAZ). 1242 */ 1243 #define PMCR_WRITEABLE_MASK (PMCRLC | PMCRDP | PMCRX | PMCRD | PMCRE) 1244 1245 #define PMXEVTYPER_P 0x80000000 1246 #define PMXEVTYPER_U 0x40000000 1247 #define PMXEVTYPER_NSK 0x20000000 1248 #define PMXEVTYPER_NSU 0x10000000 1249 #define PMXEVTYPER_NSH 0x08000000 1250 #define PMXEVTYPER_M 0x04000000 1251 #define PMXEVTYPER_MT 0x02000000 1252 #define PMXEVTYPER_EVTCOUNT 0x0000ffff 1253 #define PMXEVTYPER_MASK (PMXEVTYPER_P | PMXEVTYPER_U | PMXEVTYPER_NSK | \ 1254 PMXEVTYPER_NSU | PMXEVTYPER_NSH | \ 1255 PMXEVTYPER_M | PMXEVTYPER_MT | \ 1256 PMXEVTYPER_EVTCOUNT) 1257 1258 #define PMCCFILTR 0xf8000000 1259 #define PMCCFILTR_M PMXEVTYPER_M 1260 #define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M) 1261 1262 static inline uint32_t pmu_num_counters(CPUARMState *env) 1263 { 1264 return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT; 1265 } 1266 1267 /* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */ 1268 static inline uint64_t pmu_counter_mask(CPUARMState *env) 1269 { 1270 return (1 << 31) | ((1 << pmu_num_counters(env)) - 1); 1271 } 1272 1273 #ifdef TARGET_AARCH64 1274 int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg); 1275 int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg); 1276 int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg); 1277 int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg); 1278 #endif 1279 1280 #endif 1281