1 /* 2 * QEMU ARM CPU -- internal functions and types 3 * 4 * Copyright (c) 2014 Linaro Ltd 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 * 20 * This header defines functions, types, etc which need to be shared 21 * between different source files within target/arm/ but which are 22 * private to it and not required by the rest of QEMU. 23 */ 24 25 #ifndef TARGET_ARM_INTERNALS_H 26 #define TARGET_ARM_INTERNALS_H 27 28 #include "hw/registerfields.h" 29 30 /* register banks for CPU modes */ 31 #define BANK_USRSYS 0 32 #define BANK_SVC 1 33 #define BANK_ABT 2 34 #define BANK_UND 3 35 #define BANK_IRQ 4 36 #define BANK_FIQ 5 37 #define BANK_HYP 6 38 #define BANK_MON 7 39 40 static inline bool excp_is_internal(int excp) 41 { 42 /* Return true if this exception number represents a QEMU-internal 43 * exception that will not be passed to the guest. 44 */ 45 return excp == EXCP_INTERRUPT 46 || excp == EXCP_HLT 47 || excp == EXCP_DEBUG 48 || excp == EXCP_HALTED 49 || excp == EXCP_EXCEPTION_EXIT 50 || excp == EXCP_KERNEL_TRAP 51 || excp == EXCP_SEMIHOST; 52 } 53 54 /* Scale factor for generic timers, ie number of ns per tick. 55 * This gives a 62.5MHz timer. 56 */ 57 #define GTIMER_SCALE 16 58 59 /* Bit definitions for the v7M CONTROL register */ 60 FIELD(V7M_CONTROL, NPRIV, 0, 1) 61 FIELD(V7M_CONTROL, SPSEL, 1, 1) 62 FIELD(V7M_CONTROL, FPCA, 2, 1) 63 FIELD(V7M_CONTROL, SFPA, 3, 1) 64 65 /* Bit definitions for v7M exception return payload */ 66 FIELD(V7M_EXCRET, ES, 0, 1) 67 FIELD(V7M_EXCRET, RES0, 1, 1) 68 FIELD(V7M_EXCRET, SPSEL, 2, 1) 69 FIELD(V7M_EXCRET, MODE, 3, 1) 70 FIELD(V7M_EXCRET, FTYPE, 4, 1) 71 FIELD(V7M_EXCRET, DCRS, 5, 1) 72 FIELD(V7M_EXCRET, S, 6, 1) 73 FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */ 74 75 /* Minimum value which is a magic number for exception return */ 76 #define EXC_RETURN_MIN_MAGIC 0xff000000 77 /* Minimum number which is a magic number for function or exception return 78 * when using v8M security extension 79 */ 80 #define FNC_RETURN_MIN_MAGIC 0xfefffffe 81 82 /* We use a few fake FSR values for internal purposes in M profile. 83 * M profile cores don't have A/R format FSRs, but currently our 84 * get_phys_addr() code assumes A/R profile and reports failures via 85 * an A/R format FSR value. We then translate that into the proper 86 * M profile exception and FSR status bit in arm_v7m_cpu_do_interrupt(). 87 * Mostly the FSR values we use for this are those defined for v7PMSA, 88 * since we share some of that codepath. A few kinds of fault are 89 * only for M profile and have no A/R equivalent, though, so we have 90 * to pick a value from the reserved range (which we never otherwise 91 * generate) to use for these. 92 * These values will never be visible to the guest. 93 */ 94 #define M_FAKE_FSR_NSC_EXEC 0xf /* NS executing in S&NSC memory */ 95 #define M_FAKE_FSR_SFAULT 0xe /* SecureFault INVTRAN, INVEP or AUVIOL */ 96 97 /** 98 * raise_exception: Raise the specified exception. 99 * Raise a guest exception with the specified value, syndrome register 100 * and target exception level. This should be called from helper functions, 101 * and never returns because we will longjump back up to the CPU main loop. 102 */ 103 void QEMU_NORETURN raise_exception(CPUARMState *env, uint32_t excp, 104 uint32_t syndrome, uint32_t target_el); 105 106 /* 107 * For AArch64, map a given EL to an index in the banked_spsr array. 108 * Note that this mapping and the AArch32 mapping defined in bank_number() 109 * must agree such that the AArch64<->AArch32 SPSRs have the architecturally 110 * mandated mapping between each other. 111 */ 112 static inline unsigned int aarch64_banked_spsr_index(unsigned int el) 113 { 114 static const unsigned int map[4] = { 115 [1] = BANK_SVC, /* EL1. */ 116 [2] = BANK_HYP, /* EL2. */ 117 [3] = BANK_MON, /* EL3. */ 118 }; 119 assert(el >= 1 && el <= 3); 120 return map[el]; 121 } 122 123 /* Map CPU modes onto saved register banks. */ 124 static inline int bank_number(int mode) 125 { 126 switch (mode) { 127 case ARM_CPU_MODE_USR: 128 case ARM_CPU_MODE_SYS: 129 return BANK_USRSYS; 130 case ARM_CPU_MODE_SVC: 131 return BANK_SVC; 132 case ARM_CPU_MODE_ABT: 133 return BANK_ABT; 134 case ARM_CPU_MODE_UND: 135 return BANK_UND; 136 case ARM_CPU_MODE_IRQ: 137 return BANK_IRQ; 138 case ARM_CPU_MODE_FIQ: 139 return BANK_FIQ; 140 case ARM_CPU_MODE_HYP: 141 return BANK_HYP; 142 case ARM_CPU_MODE_MON: 143 return BANK_MON; 144 } 145 g_assert_not_reached(); 146 } 147 148 void switch_mode(CPUARMState *, int); 149 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu); 150 void arm_translate_init(void); 151 152 enum arm_fprounding { 153 FPROUNDING_TIEEVEN, 154 FPROUNDING_POSINF, 155 FPROUNDING_NEGINF, 156 FPROUNDING_ZERO, 157 FPROUNDING_TIEAWAY, 158 FPROUNDING_ODD 159 }; 160 161 int arm_rmode_to_sf(int rmode); 162 163 static inline void aarch64_save_sp(CPUARMState *env, int el) 164 { 165 if (env->pstate & PSTATE_SP) { 166 env->sp_el[el] = env->xregs[31]; 167 } else { 168 env->sp_el[0] = env->xregs[31]; 169 } 170 } 171 172 static inline void aarch64_restore_sp(CPUARMState *env, int el) 173 { 174 if (env->pstate & PSTATE_SP) { 175 env->xregs[31] = env->sp_el[el]; 176 } else { 177 env->xregs[31] = env->sp_el[0]; 178 } 179 } 180 181 static inline void update_spsel(CPUARMState *env, uint32_t imm) 182 { 183 unsigned int cur_el = arm_current_el(env); 184 /* Update PSTATE SPSel bit; this requires us to update the 185 * working stack pointer in xregs[31]. 186 */ 187 if (!((imm ^ env->pstate) & PSTATE_SP)) { 188 return; 189 } 190 aarch64_save_sp(env, cur_el); 191 env->pstate = deposit32(env->pstate, 0, 1, imm); 192 193 /* We rely on illegal updates to SPsel from EL0 to get trapped 194 * at translation time. 195 */ 196 assert(cur_el >= 1 && cur_el <= 3); 197 aarch64_restore_sp(env, cur_el); 198 } 199 200 /* 201 * arm_pamax 202 * @cpu: ARMCPU 203 * 204 * Returns the implementation defined bit-width of physical addresses. 205 * The ARMv8 reference manuals refer to this as PAMax(). 206 */ 207 static inline unsigned int arm_pamax(ARMCPU *cpu) 208 { 209 static const unsigned int pamax_map[] = { 210 [0] = 32, 211 [1] = 36, 212 [2] = 40, 213 [3] = 42, 214 [4] = 44, 215 [5] = 48, 216 }; 217 unsigned int parange = extract32(cpu->id_aa64mmfr0, 0, 4); 218 219 /* id_aa64mmfr0 is a read-only register so values outside of the 220 * supported mappings can be considered an implementation error. */ 221 assert(parange < ARRAY_SIZE(pamax_map)); 222 return pamax_map[parange]; 223 } 224 225 /* Return true if extended addresses are enabled. 226 * This is always the case if our translation regime is 64 bit, 227 * but depends on TTBCR.EAE for 32 bit. 228 */ 229 static inline bool extended_addresses_enabled(CPUARMState *env) 230 { 231 TCR *tcr = &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1]; 232 return arm_el_is_aa64(env, 1) || 233 (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE)); 234 } 235 236 /* Valid Syndrome Register EC field values */ 237 enum arm_exception_class { 238 EC_UNCATEGORIZED = 0x00, 239 EC_WFX_TRAP = 0x01, 240 EC_CP15RTTRAP = 0x03, 241 EC_CP15RRTTRAP = 0x04, 242 EC_CP14RTTRAP = 0x05, 243 EC_CP14DTTRAP = 0x06, 244 EC_ADVSIMDFPACCESSTRAP = 0x07, 245 EC_FPIDTRAP = 0x08, 246 EC_CP14RRTTRAP = 0x0c, 247 EC_ILLEGALSTATE = 0x0e, 248 EC_AA32_SVC = 0x11, 249 EC_AA32_HVC = 0x12, 250 EC_AA32_SMC = 0x13, 251 EC_AA64_SVC = 0x15, 252 EC_AA64_HVC = 0x16, 253 EC_AA64_SMC = 0x17, 254 EC_SYSTEMREGISTERTRAP = 0x18, 255 EC_SVEACCESSTRAP = 0x19, 256 EC_INSNABORT = 0x20, 257 EC_INSNABORT_SAME_EL = 0x21, 258 EC_PCALIGNMENT = 0x22, 259 EC_DATAABORT = 0x24, 260 EC_DATAABORT_SAME_EL = 0x25, 261 EC_SPALIGNMENT = 0x26, 262 EC_AA32_FPTRAP = 0x28, 263 EC_AA64_FPTRAP = 0x2c, 264 EC_SERROR = 0x2f, 265 EC_BREAKPOINT = 0x30, 266 EC_BREAKPOINT_SAME_EL = 0x31, 267 EC_SOFTWARESTEP = 0x32, 268 EC_SOFTWARESTEP_SAME_EL = 0x33, 269 EC_WATCHPOINT = 0x34, 270 EC_WATCHPOINT_SAME_EL = 0x35, 271 EC_AA32_BKPT = 0x38, 272 EC_VECTORCATCH = 0x3a, 273 EC_AA64_BKPT = 0x3c, 274 }; 275 276 #define ARM_EL_EC_SHIFT 26 277 #define ARM_EL_IL_SHIFT 25 278 #define ARM_EL_ISV_SHIFT 24 279 #define ARM_EL_IL (1 << ARM_EL_IL_SHIFT) 280 #define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT) 281 282 /* Utility functions for constructing various kinds of syndrome value. 283 * Note that in general we follow the AArch64 syndrome values; in a 284 * few cases the value in HSR for exceptions taken to AArch32 Hyp 285 * mode differs slightly, so if we ever implemented Hyp mode then the 286 * syndrome value would need some massaging on exception entry. 287 * (One example of this is that AArch64 defaults to IL bit set for 288 * exceptions which don't specifically indicate information about the 289 * trapping instruction, whereas AArch32 defaults to IL bit clear.) 290 */ 291 static inline uint32_t syn_uncategorized(void) 292 { 293 return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL; 294 } 295 296 static inline uint32_t syn_aa64_svc(uint32_t imm16) 297 { 298 return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 299 } 300 301 static inline uint32_t syn_aa64_hvc(uint32_t imm16) 302 { 303 return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 304 } 305 306 static inline uint32_t syn_aa64_smc(uint32_t imm16) 307 { 308 return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 309 } 310 311 static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit) 312 { 313 return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) 314 | (is_16bit ? 0 : ARM_EL_IL); 315 } 316 317 static inline uint32_t syn_aa32_hvc(uint32_t imm16) 318 { 319 return (EC_AA32_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 320 } 321 322 static inline uint32_t syn_aa32_smc(void) 323 { 324 return (EC_AA32_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL; 325 } 326 327 static inline uint32_t syn_aa64_bkpt(uint32_t imm16) 328 { 329 return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 330 } 331 332 static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit) 333 { 334 return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) 335 | (is_16bit ? 0 : ARM_EL_IL); 336 } 337 338 static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2, 339 int crn, int crm, int rt, 340 int isread) 341 { 342 return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL 343 | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5) 344 | (crm << 1) | isread; 345 } 346 347 static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2, 348 int crn, int crm, int rt, int isread, 349 bool is_16bit) 350 { 351 return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT) 352 | (is_16bit ? 0 : ARM_EL_IL) 353 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) 354 | (crn << 10) | (rt << 5) | (crm << 1) | isread; 355 } 356 357 static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2, 358 int crn, int crm, int rt, int isread, 359 bool is_16bit) 360 { 361 return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT) 362 | (is_16bit ? 0 : ARM_EL_IL) 363 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) 364 | (crn << 10) | (rt << 5) | (crm << 1) | isread; 365 } 366 367 static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm, 368 int rt, int rt2, int isread, 369 bool is_16bit) 370 { 371 return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT) 372 | (is_16bit ? 0 : ARM_EL_IL) 373 | (cv << 24) | (cond << 20) | (opc1 << 16) 374 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; 375 } 376 377 static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm, 378 int rt, int rt2, int isread, 379 bool is_16bit) 380 { 381 return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT) 382 | (is_16bit ? 0 : ARM_EL_IL) 383 | (cv << 24) | (cond << 20) | (opc1 << 16) 384 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; 385 } 386 387 static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit) 388 { 389 return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) 390 | (is_16bit ? 0 : ARM_EL_IL) 391 | (cv << 24) | (cond << 20); 392 } 393 394 static inline uint32_t syn_sve_access_trap(void) 395 { 396 return EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT; 397 } 398 399 static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc) 400 { 401 return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 402 | ARM_EL_IL | (ea << 9) | (s1ptw << 7) | fsc; 403 } 404 405 static inline uint32_t syn_data_abort_no_iss(int same_el, 406 int ea, int cm, int s1ptw, 407 int wnr, int fsc) 408 { 409 return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 410 | ARM_EL_IL 411 | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc; 412 } 413 414 static inline uint32_t syn_data_abort_with_iss(int same_el, 415 int sas, int sse, int srt, 416 int sf, int ar, 417 int ea, int cm, int s1ptw, 418 int wnr, int fsc, 419 bool is_16bit) 420 { 421 return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 422 | (is_16bit ? 0 : ARM_EL_IL) 423 | ARM_EL_ISV | (sas << 22) | (sse << 21) | (srt << 16) 424 | (sf << 15) | (ar << 14) 425 | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc; 426 } 427 428 static inline uint32_t syn_swstep(int same_el, int isv, int ex) 429 { 430 return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 431 | ARM_EL_IL | (isv << 24) | (ex << 6) | 0x22; 432 } 433 434 static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr) 435 { 436 return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 437 | ARM_EL_IL | (cm << 8) | (wnr << 6) | 0x22; 438 } 439 440 static inline uint32_t syn_breakpoint(int same_el) 441 { 442 return (EC_BREAKPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 443 | ARM_EL_IL | 0x22; 444 } 445 446 static inline uint32_t syn_wfx(int cv, int cond, int ti, bool is_16bit) 447 { 448 return (EC_WFX_TRAP << ARM_EL_EC_SHIFT) | 449 (is_16bit ? 0 : (1 << ARM_EL_IL_SHIFT)) | 450 (cv << 24) | (cond << 20) | ti; 451 } 452 453 /* Update a QEMU watchpoint based on the information the guest has set in the 454 * DBGWCR<n>_EL1 and DBGWVR<n>_EL1 registers. 455 */ 456 void hw_watchpoint_update(ARMCPU *cpu, int n); 457 /* Update the QEMU watchpoints for every guest watchpoint. This does a 458 * complete delete-and-reinstate of the QEMU watchpoint list and so is 459 * suitable for use after migration or on reset. 460 */ 461 void hw_watchpoint_update_all(ARMCPU *cpu); 462 /* Update a QEMU breakpoint based on the information the guest has set in the 463 * DBGBCR<n>_EL1 and DBGBVR<n>_EL1 registers. 464 */ 465 void hw_breakpoint_update(ARMCPU *cpu, int n); 466 /* Update the QEMU breakpoints for every guest breakpoint. This does a 467 * complete delete-and-reinstate of the QEMU breakpoint list and so is 468 * suitable for use after migration or on reset. 469 */ 470 void hw_breakpoint_update_all(ARMCPU *cpu); 471 472 /* Callback function for checking if a watchpoint should trigger. */ 473 bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); 474 475 /* Adjust addresses (in BE32 mode) before testing against watchpoint 476 * addresses. 477 */ 478 vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len); 479 480 /* Callback function for when a watchpoint or breakpoint triggers. */ 481 void arm_debug_excp_handler(CPUState *cs); 482 483 #ifdef CONFIG_USER_ONLY 484 static inline bool arm_is_psci_call(ARMCPU *cpu, int excp_type) 485 { 486 return false; 487 } 488 #else 489 /* Return true if the r0/x0 value indicates that this SMC/HVC is a PSCI call. */ 490 bool arm_is_psci_call(ARMCPU *cpu, int excp_type); 491 /* Actually handle a PSCI call */ 492 void arm_handle_psci_call(ARMCPU *cpu); 493 #endif 494 495 /** 496 * arm_clear_exclusive: clear the exclusive monitor 497 * @env: CPU env 498 * Clear the CPU's exclusive monitor, like the guest CLREX instruction. 499 */ 500 static inline void arm_clear_exclusive(CPUARMState *env) 501 { 502 env->exclusive_addr = -1; 503 } 504 505 /** 506 * ARMFaultType: type of an ARM MMU fault 507 * This corresponds to the v8A pseudocode's Fault enumeration, 508 * with extensions for QEMU internal conditions. 509 */ 510 typedef enum ARMFaultType { 511 ARMFault_None, 512 ARMFault_AccessFlag, 513 ARMFault_Alignment, 514 ARMFault_Background, 515 ARMFault_Domain, 516 ARMFault_Permission, 517 ARMFault_Translation, 518 ARMFault_AddressSize, 519 ARMFault_SyncExternal, 520 ARMFault_SyncExternalOnWalk, 521 ARMFault_SyncParity, 522 ARMFault_SyncParityOnWalk, 523 ARMFault_AsyncParity, 524 ARMFault_AsyncExternal, 525 ARMFault_Debug, 526 ARMFault_TLBConflict, 527 ARMFault_Lockdown, 528 ARMFault_Exclusive, 529 ARMFault_ICacheMaint, 530 ARMFault_QEMU_NSCExec, /* v8M: NS executing in S&NSC memory */ 531 ARMFault_QEMU_SFault, /* v8M: SecureFault INVTRAN, INVEP or AUVIOL */ 532 } ARMFaultType; 533 534 /** 535 * ARMMMUFaultInfo: Information describing an ARM MMU Fault 536 * @type: Type of fault 537 * @level: Table walk level (for translation, access flag and permission faults) 538 * @domain: Domain of the fault address (for non-LPAE CPUs only) 539 * @s2addr: Address that caused a fault at stage 2 540 * @stage2: True if we faulted at stage 2 541 * @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table walk 542 * @ea: True if we should set the EA (external abort type) bit in syndrome 543 */ 544 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; 545 struct ARMMMUFaultInfo { 546 ARMFaultType type; 547 target_ulong s2addr; 548 int level; 549 int domain; 550 bool stage2; 551 bool s1ptw; 552 bool ea; 553 }; 554 555 /** 556 * arm_fi_to_sfsc: Convert fault info struct to short-format FSC 557 * Compare pseudocode EncodeSDFSC(), though unlike that function 558 * we set up a whole FSR-format code including domain field and 559 * putting the high bit of the FSC into bit 10. 560 */ 561 static inline uint32_t arm_fi_to_sfsc(ARMMMUFaultInfo *fi) 562 { 563 uint32_t fsc; 564 565 switch (fi->type) { 566 case ARMFault_None: 567 return 0; 568 case ARMFault_AccessFlag: 569 fsc = fi->level == 1 ? 0x3 : 0x6; 570 break; 571 case ARMFault_Alignment: 572 fsc = 0x1; 573 break; 574 case ARMFault_Permission: 575 fsc = fi->level == 1 ? 0xd : 0xf; 576 break; 577 case ARMFault_Domain: 578 fsc = fi->level == 1 ? 0x9 : 0xb; 579 break; 580 case ARMFault_Translation: 581 fsc = fi->level == 1 ? 0x5 : 0x7; 582 break; 583 case ARMFault_SyncExternal: 584 fsc = 0x8 | (fi->ea << 12); 585 break; 586 case ARMFault_SyncExternalOnWalk: 587 fsc = fi->level == 1 ? 0xc : 0xe; 588 fsc |= (fi->ea << 12); 589 break; 590 case ARMFault_SyncParity: 591 fsc = 0x409; 592 break; 593 case ARMFault_SyncParityOnWalk: 594 fsc = fi->level == 1 ? 0x40c : 0x40e; 595 break; 596 case ARMFault_AsyncParity: 597 fsc = 0x408; 598 break; 599 case ARMFault_AsyncExternal: 600 fsc = 0x406 | (fi->ea << 12); 601 break; 602 case ARMFault_Debug: 603 fsc = 0x2; 604 break; 605 case ARMFault_TLBConflict: 606 fsc = 0x400; 607 break; 608 case ARMFault_Lockdown: 609 fsc = 0x404; 610 break; 611 case ARMFault_Exclusive: 612 fsc = 0x405; 613 break; 614 case ARMFault_ICacheMaint: 615 fsc = 0x4; 616 break; 617 case ARMFault_Background: 618 fsc = 0x0; 619 break; 620 case ARMFault_QEMU_NSCExec: 621 fsc = M_FAKE_FSR_NSC_EXEC; 622 break; 623 case ARMFault_QEMU_SFault: 624 fsc = M_FAKE_FSR_SFAULT; 625 break; 626 default: 627 /* Other faults can't occur in a context that requires a 628 * short-format status code. 629 */ 630 g_assert_not_reached(); 631 } 632 633 fsc |= (fi->domain << 4); 634 return fsc; 635 } 636 637 /** 638 * arm_fi_to_lfsc: Convert fault info struct to long-format FSC 639 * Compare pseudocode EncodeLDFSC(), though unlike that function 640 * we fill in also the LPAE bit 9 of a DFSR format. 641 */ 642 static inline uint32_t arm_fi_to_lfsc(ARMMMUFaultInfo *fi) 643 { 644 uint32_t fsc; 645 646 switch (fi->type) { 647 case ARMFault_None: 648 return 0; 649 case ARMFault_AddressSize: 650 fsc = fi->level & 3; 651 break; 652 case ARMFault_AccessFlag: 653 fsc = (fi->level & 3) | (0x2 << 2); 654 break; 655 case ARMFault_Permission: 656 fsc = (fi->level & 3) | (0x3 << 2); 657 break; 658 case ARMFault_Translation: 659 fsc = (fi->level & 3) | (0x1 << 2); 660 break; 661 case ARMFault_SyncExternal: 662 fsc = 0x10 | (fi->ea << 12); 663 break; 664 case ARMFault_SyncExternalOnWalk: 665 fsc = (fi->level & 3) | (0x5 << 2) | (fi->ea << 12); 666 break; 667 case ARMFault_SyncParity: 668 fsc = 0x18; 669 break; 670 case ARMFault_SyncParityOnWalk: 671 fsc = (fi->level & 3) | (0x7 << 2); 672 break; 673 case ARMFault_AsyncParity: 674 fsc = 0x19; 675 break; 676 case ARMFault_AsyncExternal: 677 fsc = 0x11 | (fi->ea << 12); 678 break; 679 case ARMFault_Alignment: 680 fsc = 0x21; 681 break; 682 case ARMFault_Debug: 683 fsc = 0x22; 684 break; 685 case ARMFault_TLBConflict: 686 fsc = 0x30; 687 break; 688 case ARMFault_Lockdown: 689 fsc = 0x34; 690 break; 691 case ARMFault_Exclusive: 692 fsc = 0x35; 693 break; 694 default: 695 /* Other faults can't occur in a context that requires a 696 * long-format status code. 697 */ 698 g_assert_not_reached(); 699 } 700 701 fsc |= 1 << 9; 702 return fsc; 703 } 704 705 static inline bool arm_extabort_type(MemTxResult result) 706 { 707 /* The EA bit in syndromes and fault status registers is an 708 * IMPDEF classification of external aborts. ARM implementations 709 * usually use this to indicate AXI bus Decode error (0) or 710 * Slave error (1); in QEMU we follow that. 711 */ 712 return result != MEMTX_DECODE_ERROR; 713 } 714 715 /* Do a page table walk and add page to TLB if possible */ 716 bool arm_tlb_fill(CPUState *cpu, vaddr address, 717 MMUAccessType access_type, int mmu_idx, 718 ARMMMUFaultInfo *fi); 719 720 /* Return true if the stage 1 translation regime is using LPAE format page 721 * tables */ 722 bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx); 723 724 /* Raise a data fault alignment exception for the specified virtual address */ 725 void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, 726 MMUAccessType access_type, 727 int mmu_idx, uintptr_t retaddr); 728 729 /* arm_cpu_do_transaction_failed: handle a memory system error response 730 * (eg "no device/memory present at address") by raising an external abort 731 * exception 732 */ 733 void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 734 vaddr addr, unsigned size, 735 MMUAccessType access_type, 736 int mmu_idx, MemTxAttrs attrs, 737 MemTxResult response, uintptr_t retaddr); 738 739 /* Call any registered EL change hooks */ 740 static inline void arm_call_pre_el_change_hook(ARMCPU *cpu) 741 { 742 ARMELChangeHook *hook, *next; 743 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 744 hook->hook(cpu, hook->opaque); 745 } 746 } 747 static inline void arm_call_el_change_hook(ARMCPU *cpu) 748 { 749 ARMELChangeHook *hook, *next; 750 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 751 hook->hook(cpu, hook->opaque); 752 } 753 } 754 755 /* Return true if this address translation regime is secure */ 756 static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) 757 { 758 switch (mmu_idx) { 759 case ARMMMUIdx_S12NSE0: 760 case ARMMMUIdx_S12NSE1: 761 case ARMMMUIdx_S1NSE0: 762 case ARMMMUIdx_S1NSE1: 763 case ARMMMUIdx_S1E2: 764 case ARMMMUIdx_S2NS: 765 case ARMMMUIdx_MPrivNegPri: 766 case ARMMMUIdx_MUserNegPri: 767 case ARMMMUIdx_MPriv: 768 case ARMMMUIdx_MUser: 769 return false; 770 case ARMMMUIdx_S1E3: 771 case ARMMMUIdx_S1SE0: 772 case ARMMMUIdx_S1SE1: 773 case ARMMMUIdx_MSPrivNegPri: 774 case ARMMMUIdx_MSUserNegPri: 775 case ARMMMUIdx_MSPriv: 776 case ARMMMUIdx_MSUser: 777 return true; 778 default: 779 g_assert_not_reached(); 780 } 781 } 782 783 /* Return the FSR value for a debug exception (watchpoint, hardware 784 * breakpoint or BKPT insn) targeting the specified exception level. 785 */ 786 static inline uint32_t arm_debug_exception_fsr(CPUARMState *env) 787 { 788 ARMMMUFaultInfo fi = { .type = ARMFault_Debug }; 789 int target_el = arm_debug_target_el(env); 790 bool using_lpae = false; 791 792 if (target_el == 2 || arm_el_is_aa64(env, target_el)) { 793 using_lpae = true; 794 } else { 795 if (arm_feature(env, ARM_FEATURE_LPAE) && 796 (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) { 797 using_lpae = true; 798 } 799 } 800 801 if (using_lpae) { 802 return arm_fi_to_lfsc(&fi); 803 } else { 804 return arm_fi_to_sfsc(&fi); 805 } 806 } 807 808 /* Note make_memop_idx reserves 4 bits for mmu_idx, and MO_BSWAP is bit 3. 809 * Thus a TCGMemOpIdx, without any MO_ALIGN bits, fits in 8 bits. 810 */ 811 #define MEMOPIDX_SHIFT 8 812 813 /** 814 * v7m_using_psp: Return true if using process stack pointer 815 * Return true if the CPU is currently using the process stack 816 * pointer, or false if it is using the main stack pointer. 817 */ 818 static inline bool v7m_using_psp(CPUARMState *env) 819 { 820 /* Handler mode always uses the main stack; for thread mode 821 * the CONTROL.SPSEL bit determines the answer. 822 * Note that in v7M it is not possible to be in Handler mode with 823 * CONTROL.SPSEL non-zero, but in v8M it is, so we must check both. 824 */ 825 return !arm_v7m_is_handler_mode(env) && 826 env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK; 827 } 828 829 /** 830 * v7m_sp_limit: Return SP limit for current CPU state 831 * Return the SP limit value for the current CPU security state 832 * and stack pointer. 833 */ 834 static inline uint32_t v7m_sp_limit(CPUARMState *env) 835 { 836 if (v7m_using_psp(env)) { 837 return env->v7m.psplim[env->v7m.secure]; 838 } else { 839 return env->v7m.msplim[env->v7m.secure]; 840 } 841 } 842 843 #endif 844