1 /* 2 * QEMU ARM CPU -- internal functions and types 3 * 4 * Copyright (c) 2014 Linaro Ltd 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 * 20 * This header defines functions, types, etc which need to be shared 21 * between different source files within target/arm/ but which are 22 * private to it and not required by the rest of QEMU. 23 */ 24 25 #ifndef TARGET_ARM_INTERNALS_H 26 #define TARGET_ARM_INTERNALS_H 27 28 #include "hw/registerfields.h" 29 30 /* register banks for CPU modes */ 31 #define BANK_USRSYS 0 32 #define BANK_SVC 1 33 #define BANK_ABT 2 34 #define BANK_UND 3 35 #define BANK_IRQ 4 36 #define BANK_FIQ 5 37 #define BANK_HYP 6 38 #define BANK_MON 7 39 40 static inline bool excp_is_internal(int excp) 41 { 42 /* Return true if this exception number represents a QEMU-internal 43 * exception that will not be passed to the guest. 44 */ 45 return excp == EXCP_INTERRUPT 46 || excp == EXCP_HLT 47 || excp == EXCP_DEBUG 48 || excp == EXCP_HALTED 49 || excp == EXCP_EXCEPTION_EXIT 50 || excp == EXCP_KERNEL_TRAP 51 || excp == EXCP_SEMIHOST; 52 } 53 54 /* Scale factor for generic timers, ie number of ns per tick. 55 * This gives a 62.5MHz timer. 56 */ 57 #define GTIMER_SCALE 16 58 59 /* Bit definitions for the v7M CONTROL register */ 60 FIELD(V7M_CONTROL, NPRIV, 0, 1) 61 FIELD(V7M_CONTROL, SPSEL, 1, 1) 62 FIELD(V7M_CONTROL, FPCA, 2, 1) 63 FIELD(V7M_CONTROL, SFPA, 3, 1) 64 65 /* Bit definitions for v7M exception return payload */ 66 FIELD(V7M_EXCRET, ES, 0, 1) 67 FIELD(V7M_EXCRET, RES0, 1, 1) 68 FIELD(V7M_EXCRET, SPSEL, 2, 1) 69 FIELD(V7M_EXCRET, MODE, 3, 1) 70 FIELD(V7M_EXCRET, FTYPE, 4, 1) 71 FIELD(V7M_EXCRET, DCRS, 5, 1) 72 FIELD(V7M_EXCRET, S, 6, 1) 73 FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */ 74 75 /* Minimum value which is a magic number for exception return */ 76 #define EXC_RETURN_MIN_MAGIC 0xff000000 77 /* Minimum number which is a magic number for function or exception return 78 * when using v8M security extension 79 */ 80 #define FNC_RETURN_MIN_MAGIC 0xfefffffe 81 82 /* We use a few fake FSR values for internal purposes in M profile. 83 * M profile cores don't have A/R format FSRs, but currently our 84 * get_phys_addr() code assumes A/R profile and reports failures via 85 * an A/R format FSR value. We then translate that into the proper 86 * M profile exception and FSR status bit in arm_v7m_cpu_do_interrupt(). 87 * Mostly the FSR values we use for this are those defined for v7PMSA, 88 * since we share some of that codepath. A few kinds of fault are 89 * only for M profile and have no A/R equivalent, though, so we have 90 * to pick a value from the reserved range (which we never otherwise 91 * generate) to use for these. 92 * These values will never be visible to the guest. 93 */ 94 #define M_FAKE_FSR_NSC_EXEC 0xf /* NS executing in S&NSC memory */ 95 #define M_FAKE_FSR_SFAULT 0xe /* SecureFault INVTRAN, INVEP or AUVIOL */ 96 97 /** 98 * raise_exception: Raise the specified exception. 99 * Raise a guest exception with the specified value, syndrome register 100 * and target exception level. This should be called from helper functions, 101 * and never returns because we will longjump back up to the CPU main loop. 102 */ 103 void QEMU_NORETURN raise_exception(CPUARMState *env, uint32_t excp, 104 uint32_t syndrome, uint32_t target_el); 105 106 /* 107 * For AArch64, map a given EL to an index in the banked_spsr array. 108 * Note that this mapping and the AArch32 mapping defined in bank_number() 109 * must agree such that the AArch64<->AArch32 SPSRs have the architecturally 110 * mandated mapping between each other. 111 */ 112 static inline unsigned int aarch64_banked_spsr_index(unsigned int el) 113 { 114 static const unsigned int map[4] = { 115 [1] = BANK_SVC, /* EL1. */ 116 [2] = BANK_HYP, /* EL2. */ 117 [3] = BANK_MON, /* EL3. */ 118 }; 119 assert(el >= 1 && el <= 3); 120 return map[el]; 121 } 122 123 /* Map CPU modes onto saved register banks. */ 124 static inline int bank_number(int mode) 125 { 126 switch (mode) { 127 case ARM_CPU_MODE_USR: 128 case ARM_CPU_MODE_SYS: 129 return BANK_USRSYS; 130 case ARM_CPU_MODE_SVC: 131 return BANK_SVC; 132 case ARM_CPU_MODE_ABT: 133 return BANK_ABT; 134 case ARM_CPU_MODE_UND: 135 return BANK_UND; 136 case ARM_CPU_MODE_IRQ: 137 return BANK_IRQ; 138 case ARM_CPU_MODE_FIQ: 139 return BANK_FIQ; 140 case ARM_CPU_MODE_HYP: 141 return BANK_HYP; 142 case ARM_CPU_MODE_MON: 143 return BANK_MON; 144 } 145 g_assert_not_reached(); 146 } 147 148 /** 149 * r14_bank_number: Map CPU mode onto register bank for r14 150 * 151 * Given an AArch32 CPU mode, return the index into the saved register 152 * banks to use for the R14 (LR) in that mode. This is the same as 153 * bank_number(), except for the special case of Hyp mode, where 154 * R14 is shared with USR and SYS, unlike its R13 and SPSR. 155 * This should be used as the index into env->banked_r14[], and 156 * bank_number() used for the index into env->banked_r13[] and 157 * env->banked_spsr[]. 158 */ 159 static inline int r14_bank_number(int mode) 160 { 161 return (mode == ARM_CPU_MODE_HYP) ? BANK_USRSYS : bank_number(mode); 162 } 163 164 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu); 165 void arm_translate_init(void); 166 167 enum arm_fprounding { 168 FPROUNDING_TIEEVEN, 169 FPROUNDING_POSINF, 170 FPROUNDING_NEGINF, 171 FPROUNDING_ZERO, 172 FPROUNDING_TIEAWAY, 173 FPROUNDING_ODD 174 }; 175 176 int arm_rmode_to_sf(int rmode); 177 178 static inline void aarch64_save_sp(CPUARMState *env, int el) 179 { 180 if (env->pstate & PSTATE_SP) { 181 env->sp_el[el] = env->xregs[31]; 182 } else { 183 env->sp_el[0] = env->xregs[31]; 184 } 185 } 186 187 static inline void aarch64_restore_sp(CPUARMState *env, int el) 188 { 189 if (env->pstate & PSTATE_SP) { 190 env->xregs[31] = env->sp_el[el]; 191 } else { 192 env->xregs[31] = env->sp_el[0]; 193 } 194 } 195 196 static inline void update_spsel(CPUARMState *env, uint32_t imm) 197 { 198 unsigned int cur_el = arm_current_el(env); 199 /* Update PSTATE SPSel bit; this requires us to update the 200 * working stack pointer in xregs[31]. 201 */ 202 if (!((imm ^ env->pstate) & PSTATE_SP)) { 203 return; 204 } 205 aarch64_save_sp(env, cur_el); 206 env->pstate = deposit32(env->pstate, 0, 1, imm); 207 208 /* We rely on illegal updates to SPsel from EL0 to get trapped 209 * at translation time. 210 */ 211 assert(cur_el >= 1 && cur_el <= 3); 212 aarch64_restore_sp(env, cur_el); 213 } 214 215 /* 216 * arm_pamax 217 * @cpu: ARMCPU 218 * 219 * Returns the implementation defined bit-width of physical addresses. 220 * The ARMv8 reference manuals refer to this as PAMax(). 221 */ 222 static inline unsigned int arm_pamax(ARMCPU *cpu) 223 { 224 static const unsigned int pamax_map[] = { 225 [0] = 32, 226 [1] = 36, 227 [2] = 40, 228 [3] = 42, 229 [4] = 44, 230 [5] = 48, 231 }; 232 unsigned int parange = 233 FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE); 234 235 /* id_aa64mmfr0 is a read-only register so values outside of the 236 * supported mappings can be considered an implementation error. */ 237 assert(parange < ARRAY_SIZE(pamax_map)); 238 return pamax_map[parange]; 239 } 240 241 /* Return true if extended addresses are enabled. 242 * This is always the case if our translation regime is 64 bit, 243 * but depends on TTBCR.EAE for 32 bit. 244 */ 245 static inline bool extended_addresses_enabled(CPUARMState *env) 246 { 247 TCR *tcr = &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1]; 248 return arm_el_is_aa64(env, 1) || 249 (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE)); 250 } 251 252 /* Valid Syndrome Register EC field values */ 253 enum arm_exception_class { 254 EC_UNCATEGORIZED = 0x00, 255 EC_WFX_TRAP = 0x01, 256 EC_CP15RTTRAP = 0x03, 257 EC_CP15RRTTRAP = 0x04, 258 EC_CP14RTTRAP = 0x05, 259 EC_CP14DTTRAP = 0x06, 260 EC_ADVSIMDFPACCESSTRAP = 0x07, 261 EC_FPIDTRAP = 0x08, 262 EC_CP14RRTTRAP = 0x0c, 263 EC_ILLEGALSTATE = 0x0e, 264 EC_AA32_SVC = 0x11, 265 EC_AA32_HVC = 0x12, 266 EC_AA32_SMC = 0x13, 267 EC_AA64_SVC = 0x15, 268 EC_AA64_HVC = 0x16, 269 EC_AA64_SMC = 0x17, 270 EC_SYSTEMREGISTERTRAP = 0x18, 271 EC_SVEACCESSTRAP = 0x19, 272 EC_INSNABORT = 0x20, 273 EC_INSNABORT_SAME_EL = 0x21, 274 EC_PCALIGNMENT = 0x22, 275 EC_DATAABORT = 0x24, 276 EC_DATAABORT_SAME_EL = 0x25, 277 EC_SPALIGNMENT = 0x26, 278 EC_AA32_FPTRAP = 0x28, 279 EC_AA64_FPTRAP = 0x2c, 280 EC_SERROR = 0x2f, 281 EC_BREAKPOINT = 0x30, 282 EC_BREAKPOINT_SAME_EL = 0x31, 283 EC_SOFTWARESTEP = 0x32, 284 EC_SOFTWARESTEP_SAME_EL = 0x33, 285 EC_WATCHPOINT = 0x34, 286 EC_WATCHPOINT_SAME_EL = 0x35, 287 EC_AA32_BKPT = 0x38, 288 EC_VECTORCATCH = 0x3a, 289 EC_AA64_BKPT = 0x3c, 290 }; 291 292 #define ARM_EL_EC_SHIFT 26 293 #define ARM_EL_IL_SHIFT 25 294 #define ARM_EL_ISV_SHIFT 24 295 #define ARM_EL_IL (1 << ARM_EL_IL_SHIFT) 296 #define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT) 297 298 static inline uint32_t syn_get_ec(uint32_t syn) 299 { 300 return syn >> ARM_EL_EC_SHIFT; 301 } 302 303 /* Utility functions for constructing various kinds of syndrome value. 304 * Note that in general we follow the AArch64 syndrome values; in a 305 * few cases the value in HSR for exceptions taken to AArch32 Hyp 306 * mode differs slightly, and we fix this up when populating HSR in 307 * arm_cpu_do_interrupt_aarch32_hyp(). 308 * The exception is FP/SIMD access traps -- these report extra information 309 * when taking an exception to AArch32. For those we include the extra coproc 310 * and TA fields, and mask them out when taking the exception to AArch64. 311 */ 312 static inline uint32_t syn_uncategorized(void) 313 { 314 return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL; 315 } 316 317 static inline uint32_t syn_aa64_svc(uint32_t imm16) 318 { 319 return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 320 } 321 322 static inline uint32_t syn_aa64_hvc(uint32_t imm16) 323 { 324 return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 325 } 326 327 static inline uint32_t syn_aa64_smc(uint32_t imm16) 328 { 329 return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 330 } 331 332 static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit) 333 { 334 return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) 335 | (is_16bit ? 0 : ARM_EL_IL); 336 } 337 338 static inline uint32_t syn_aa32_hvc(uint32_t imm16) 339 { 340 return (EC_AA32_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 341 } 342 343 static inline uint32_t syn_aa32_smc(void) 344 { 345 return (EC_AA32_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL; 346 } 347 348 static inline uint32_t syn_aa64_bkpt(uint32_t imm16) 349 { 350 return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 351 } 352 353 static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit) 354 { 355 return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) 356 | (is_16bit ? 0 : ARM_EL_IL); 357 } 358 359 static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2, 360 int crn, int crm, int rt, 361 int isread) 362 { 363 return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL 364 | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5) 365 | (crm << 1) | isread; 366 } 367 368 static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2, 369 int crn, int crm, int rt, int isread, 370 bool is_16bit) 371 { 372 return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT) 373 | (is_16bit ? 0 : ARM_EL_IL) 374 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) 375 | (crn << 10) | (rt << 5) | (crm << 1) | isread; 376 } 377 378 static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2, 379 int crn, int crm, int rt, int isread, 380 bool is_16bit) 381 { 382 return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT) 383 | (is_16bit ? 0 : ARM_EL_IL) 384 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) 385 | (crn << 10) | (rt << 5) | (crm << 1) | isread; 386 } 387 388 static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm, 389 int rt, int rt2, int isread, 390 bool is_16bit) 391 { 392 return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT) 393 | (is_16bit ? 0 : ARM_EL_IL) 394 | (cv << 24) | (cond << 20) | (opc1 << 16) 395 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; 396 } 397 398 static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm, 399 int rt, int rt2, int isread, 400 bool is_16bit) 401 { 402 return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT) 403 | (is_16bit ? 0 : ARM_EL_IL) 404 | (cv << 24) | (cond << 20) | (opc1 << 16) 405 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; 406 } 407 408 static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit) 409 { 410 /* AArch32 FP trap or any AArch64 FP/SIMD trap: TA == 0 coproc == 0xa */ 411 return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) 412 | (is_16bit ? 0 : ARM_EL_IL) 413 | (cv << 24) | (cond << 20) | 0xa; 414 } 415 416 static inline uint32_t syn_simd_access_trap(int cv, int cond, bool is_16bit) 417 { 418 /* AArch32 SIMD trap: TA == 1 coproc == 0 */ 419 return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) 420 | (is_16bit ? 0 : ARM_EL_IL) 421 | (cv << 24) | (cond << 20) | (1 << 5); 422 } 423 424 static inline uint32_t syn_sve_access_trap(void) 425 { 426 return EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT; 427 } 428 429 static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc) 430 { 431 return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 432 | ARM_EL_IL | (ea << 9) | (s1ptw << 7) | fsc; 433 } 434 435 static inline uint32_t syn_data_abort_no_iss(int same_el, 436 int ea, int cm, int s1ptw, 437 int wnr, int fsc) 438 { 439 return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 440 | ARM_EL_IL 441 | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc; 442 } 443 444 static inline uint32_t syn_data_abort_with_iss(int same_el, 445 int sas, int sse, int srt, 446 int sf, int ar, 447 int ea, int cm, int s1ptw, 448 int wnr, int fsc, 449 bool is_16bit) 450 { 451 return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 452 | (is_16bit ? 0 : ARM_EL_IL) 453 | ARM_EL_ISV | (sas << 22) | (sse << 21) | (srt << 16) 454 | (sf << 15) | (ar << 14) 455 | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc; 456 } 457 458 static inline uint32_t syn_swstep(int same_el, int isv, int ex) 459 { 460 return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 461 | ARM_EL_IL | (isv << 24) | (ex << 6) | 0x22; 462 } 463 464 static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr) 465 { 466 return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 467 | ARM_EL_IL | (cm << 8) | (wnr << 6) | 0x22; 468 } 469 470 static inline uint32_t syn_breakpoint(int same_el) 471 { 472 return (EC_BREAKPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 473 | ARM_EL_IL | 0x22; 474 } 475 476 static inline uint32_t syn_wfx(int cv, int cond, int ti, bool is_16bit) 477 { 478 return (EC_WFX_TRAP << ARM_EL_EC_SHIFT) | 479 (is_16bit ? 0 : (1 << ARM_EL_IL_SHIFT)) | 480 (cv << 24) | (cond << 20) | ti; 481 } 482 483 /* Update a QEMU watchpoint based on the information the guest has set in the 484 * DBGWCR<n>_EL1 and DBGWVR<n>_EL1 registers. 485 */ 486 void hw_watchpoint_update(ARMCPU *cpu, int n); 487 /* Update the QEMU watchpoints for every guest watchpoint. This does a 488 * complete delete-and-reinstate of the QEMU watchpoint list and so is 489 * suitable for use after migration or on reset. 490 */ 491 void hw_watchpoint_update_all(ARMCPU *cpu); 492 /* Update a QEMU breakpoint based on the information the guest has set in the 493 * DBGBCR<n>_EL1 and DBGBVR<n>_EL1 registers. 494 */ 495 void hw_breakpoint_update(ARMCPU *cpu, int n); 496 /* Update the QEMU breakpoints for every guest breakpoint. This does a 497 * complete delete-and-reinstate of the QEMU breakpoint list and so is 498 * suitable for use after migration or on reset. 499 */ 500 void hw_breakpoint_update_all(ARMCPU *cpu); 501 502 /* Callback function for checking if a watchpoint should trigger. */ 503 bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); 504 505 /* Adjust addresses (in BE32 mode) before testing against watchpoint 506 * addresses. 507 */ 508 vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len); 509 510 /* Callback function for when a watchpoint or breakpoint triggers. */ 511 void arm_debug_excp_handler(CPUState *cs); 512 513 #ifdef CONFIG_USER_ONLY 514 static inline bool arm_is_psci_call(ARMCPU *cpu, int excp_type) 515 { 516 return false; 517 } 518 #else 519 /* Return true if the r0/x0 value indicates that this SMC/HVC is a PSCI call. */ 520 bool arm_is_psci_call(ARMCPU *cpu, int excp_type); 521 /* Actually handle a PSCI call */ 522 void arm_handle_psci_call(ARMCPU *cpu); 523 #endif 524 525 /** 526 * arm_clear_exclusive: clear the exclusive monitor 527 * @env: CPU env 528 * Clear the CPU's exclusive monitor, like the guest CLREX instruction. 529 */ 530 static inline void arm_clear_exclusive(CPUARMState *env) 531 { 532 env->exclusive_addr = -1; 533 } 534 535 /** 536 * ARMFaultType: type of an ARM MMU fault 537 * This corresponds to the v8A pseudocode's Fault enumeration, 538 * with extensions for QEMU internal conditions. 539 */ 540 typedef enum ARMFaultType { 541 ARMFault_None, 542 ARMFault_AccessFlag, 543 ARMFault_Alignment, 544 ARMFault_Background, 545 ARMFault_Domain, 546 ARMFault_Permission, 547 ARMFault_Translation, 548 ARMFault_AddressSize, 549 ARMFault_SyncExternal, 550 ARMFault_SyncExternalOnWalk, 551 ARMFault_SyncParity, 552 ARMFault_SyncParityOnWalk, 553 ARMFault_AsyncParity, 554 ARMFault_AsyncExternal, 555 ARMFault_Debug, 556 ARMFault_TLBConflict, 557 ARMFault_Lockdown, 558 ARMFault_Exclusive, 559 ARMFault_ICacheMaint, 560 ARMFault_QEMU_NSCExec, /* v8M: NS executing in S&NSC memory */ 561 ARMFault_QEMU_SFault, /* v8M: SecureFault INVTRAN, INVEP or AUVIOL */ 562 } ARMFaultType; 563 564 /** 565 * ARMMMUFaultInfo: Information describing an ARM MMU Fault 566 * @type: Type of fault 567 * @level: Table walk level (for translation, access flag and permission faults) 568 * @domain: Domain of the fault address (for non-LPAE CPUs only) 569 * @s2addr: Address that caused a fault at stage 2 570 * @stage2: True if we faulted at stage 2 571 * @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table walk 572 * @ea: True if we should set the EA (external abort type) bit in syndrome 573 */ 574 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; 575 struct ARMMMUFaultInfo { 576 ARMFaultType type; 577 target_ulong s2addr; 578 int level; 579 int domain; 580 bool stage2; 581 bool s1ptw; 582 bool ea; 583 }; 584 585 /** 586 * arm_fi_to_sfsc: Convert fault info struct to short-format FSC 587 * Compare pseudocode EncodeSDFSC(), though unlike that function 588 * we set up a whole FSR-format code including domain field and 589 * putting the high bit of the FSC into bit 10. 590 */ 591 static inline uint32_t arm_fi_to_sfsc(ARMMMUFaultInfo *fi) 592 { 593 uint32_t fsc; 594 595 switch (fi->type) { 596 case ARMFault_None: 597 return 0; 598 case ARMFault_AccessFlag: 599 fsc = fi->level == 1 ? 0x3 : 0x6; 600 break; 601 case ARMFault_Alignment: 602 fsc = 0x1; 603 break; 604 case ARMFault_Permission: 605 fsc = fi->level == 1 ? 0xd : 0xf; 606 break; 607 case ARMFault_Domain: 608 fsc = fi->level == 1 ? 0x9 : 0xb; 609 break; 610 case ARMFault_Translation: 611 fsc = fi->level == 1 ? 0x5 : 0x7; 612 break; 613 case ARMFault_SyncExternal: 614 fsc = 0x8 | (fi->ea << 12); 615 break; 616 case ARMFault_SyncExternalOnWalk: 617 fsc = fi->level == 1 ? 0xc : 0xe; 618 fsc |= (fi->ea << 12); 619 break; 620 case ARMFault_SyncParity: 621 fsc = 0x409; 622 break; 623 case ARMFault_SyncParityOnWalk: 624 fsc = fi->level == 1 ? 0x40c : 0x40e; 625 break; 626 case ARMFault_AsyncParity: 627 fsc = 0x408; 628 break; 629 case ARMFault_AsyncExternal: 630 fsc = 0x406 | (fi->ea << 12); 631 break; 632 case ARMFault_Debug: 633 fsc = 0x2; 634 break; 635 case ARMFault_TLBConflict: 636 fsc = 0x400; 637 break; 638 case ARMFault_Lockdown: 639 fsc = 0x404; 640 break; 641 case ARMFault_Exclusive: 642 fsc = 0x405; 643 break; 644 case ARMFault_ICacheMaint: 645 fsc = 0x4; 646 break; 647 case ARMFault_Background: 648 fsc = 0x0; 649 break; 650 case ARMFault_QEMU_NSCExec: 651 fsc = M_FAKE_FSR_NSC_EXEC; 652 break; 653 case ARMFault_QEMU_SFault: 654 fsc = M_FAKE_FSR_SFAULT; 655 break; 656 default: 657 /* Other faults can't occur in a context that requires a 658 * short-format status code. 659 */ 660 g_assert_not_reached(); 661 } 662 663 fsc |= (fi->domain << 4); 664 return fsc; 665 } 666 667 /** 668 * arm_fi_to_lfsc: Convert fault info struct to long-format FSC 669 * Compare pseudocode EncodeLDFSC(), though unlike that function 670 * we fill in also the LPAE bit 9 of a DFSR format. 671 */ 672 static inline uint32_t arm_fi_to_lfsc(ARMMMUFaultInfo *fi) 673 { 674 uint32_t fsc; 675 676 switch (fi->type) { 677 case ARMFault_None: 678 return 0; 679 case ARMFault_AddressSize: 680 fsc = fi->level & 3; 681 break; 682 case ARMFault_AccessFlag: 683 fsc = (fi->level & 3) | (0x2 << 2); 684 break; 685 case ARMFault_Permission: 686 fsc = (fi->level & 3) | (0x3 << 2); 687 break; 688 case ARMFault_Translation: 689 fsc = (fi->level & 3) | (0x1 << 2); 690 break; 691 case ARMFault_SyncExternal: 692 fsc = 0x10 | (fi->ea << 12); 693 break; 694 case ARMFault_SyncExternalOnWalk: 695 fsc = (fi->level & 3) | (0x5 << 2) | (fi->ea << 12); 696 break; 697 case ARMFault_SyncParity: 698 fsc = 0x18; 699 break; 700 case ARMFault_SyncParityOnWalk: 701 fsc = (fi->level & 3) | (0x7 << 2); 702 break; 703 case ARMFault_AsyncParity: 704 fsc = 0x19; 705 break; 706 case ARMFault_AsyncExternal: 707 fsc = 0x11 | (fi->ea << 12); 708 break; 709 case ARMFault_Alignment: 710 fsc = 0x21; 711 break; 712 case ARMFault_Debug: 713 fsc = 0x22; 714 break; 715 case ARMFault_TLBConflict: 716 fsc = 0x30; 717 break; 718 case ARMFault_Lockdown: 719 fsc = 0x34; 720 break; 721 case ARMFault_Exclusive: 722 fsc = 0x35; 723 break; 724 default: 725 /* Other faults can't occur in a context that requires a 726 * long-format status code. 727 */ 728 g_assert_not_reached(); 729 } 730 731 fsc |= 1 << 9; 732 return fsc; 733 } 734 735 static inline bool arm_extabort_type(MemTxResult result) 736 { 737 /* The EA bit in syndromes and fault status registers is an 738 * IMPDEF classification of external aborts. ARM implementations 739 * usually use this to indicate AXI bus Decode error (0) or 740 * Slave error (1); in QEMU we follow that. 741 */ 742 return result != MEMTX_DECODE_ERROR; 743 } 744 745 /* Do a page table walk and add page to TLB if possible */ 746 bool arm_tlb_fill(CPUState *cpu, vaddr address, 747 MMUAccessType access_type, int mmu_idx, 748 ARMMMUFaultInfo *fi); 749 750 /* Return true if the stage 1 translation regime is using LPAE format page 751 * tables */ 752 bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx); 753 754 /* Raise a data fault alignment exception for the specified virtual address */ 755 void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, 756 MMUAccessType access_type, 757 int mmu_idx, uintptr_t retaddr); 758 759 /* arm_cpu_do_transaction_failed: handle a memory system error response 760 * (eg "no device/memory present at address") by raising an external abort 761 * exception 762 */ 763 void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 764 vaddr addr, unsigned size, 765 MMUAccessType access_type, 766 int mmu_idx, MemTxAttrs attrs, 767 MemTxResult response, uintptr_t retaddr); 768 769 /* Call any registered EL change hooks */ 770 static inline void arm_call_pre_el_change_hook(ARMCPU *cpu) 771 { 772 ARMELChangeHook *hook, *next; 773 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 774 hook->hook(cpu, hook->opaque); 775 } 776 } 777 static inline void arm_call_el_change_hook(ARMCPU *cpu) 778 { 779 ARMELChangeHook *hook, *next; 780 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 781 hook->hook(cpu, hook->opaque); 782 } 783 } 784 785 /* Return true if this address translation regime is secure */ 786 static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) 787 { 788 switch (mmu_idx) { 789 case ARMMMUIdx_S12NSE0: 790 case ARMMMUIdx_S12NSE1: 791 case ARMMMUIdx_S1NSE0: 792 case ARMMMUIdx_S1NSE1: 793 case ARMMMUIdx_S1E2: 794 case ARMMMUIdx_S2NS: 795 case ARMMMUIdx_MPrivNegPri: 796 case ARMMMUIdx_MUserNegPri: 797 case ARMMMUIdx_MPriv: 798 case ARMMMUIdx_MUser: 799 return false; 800 case ARMMMUIdx_S1E3: 801 case ARMMMUIdx_S1SE0: 802 case ARMMMUIdx_S1SE1: 803 case ARMMMUIdx_MSPrivNegPri: 804 case ARMMMUIdx_MSUserNegPri: 805 case ARMMMUIdx_MSPriv: 806 case ARMMMUIdx_MSUser: 807 return true; 808 default: 809 g_assert_not_reached(); 810 } 811 } 812 813 /* Return the FSR value for a debug exception (watchpoint, hardware 814 * breakpoint or BKPT insn) targeting the specified exception level. 815 */ 816 static inline uint32_t arm_debug_exception_fsr(CPUARMState *env) 817 { 818 ARMMMUFaultInfo fi = { .type = ARMFault_Debug }; 819 int target_el = arm_debug_target_el(env); 820 bool using_lpae = false; 821 822 if (target_el == 2 || arm_el_is_aa64(env, target_el)) { 823 using_lpae = true; 824 } else { 825 if (arm_feature(env, ARM_FEATURE_LPAE) && 826 (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) { 827 using_lpae = true; 828 } 829 } 830 831 if (using_lpae) { 832 return arm_fi_to_lfsc(&fi); 833 } else { 834 return arm_fi_to_sfsc(&fi); 835 } 836 } 837 838 /* Note make_memop_idx reserves 4 bits for mmu_idx, and MO_BSWAP is bit 3. 839 * Thus a TCGMemOpIdx, without any MO_ALIGN bits, fits in 8 bits. 840 */ 841 #define MEMOPIDX_SHIFT 8 842 843 /** 844 * v7m_using_psp: Return true if using process stack pointer 845 * Return true if the CPU is currently using the process stack 846 * pointer, or false if it is using the main stack pointer. 847 */ 848 static inline bool v7m_using_psp(CPUARMState *env) 849 { 850 /* Handler mode always uses the main stack; for thread mode 851 * the CONTROL.SPSEL bit determines the answer. 852 * Note that in v7M it is not possible to be in Handler mode with 853 * CONTROL.SPSEL non-zero, but in v8M it is, so we must check both. 854 */ 855 return !arm_v7m_is_handler_mode(env) && 856 env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK; 857 } 858 859 /** 860 * v7m_sp_limit: Return SP limit for current CPU state 861 * Return the SP limit value for the current CPU security state 862 * and stack pointer. 863 */ 864 static inline uint32_t v7m_sp_limit(CPUARMState *env) 865 { 866 if (v7m_using_psp(env)) { 867 return env->v7m.psplim[env->v7m.secure]; 868 } else { 869 return env->v7m.msplim[env->v7m.secure]; 870 } 871 } 872 873 /** 874 * aarch32_mode_name(): Return name of the AArch32 CPU mode 875 * @psr: Program Status Register indicating CPU mode 876 * 877 * Returns, for debug logging purposes, a printable representation 878 * of the AArch32 CPU mode ("svc", "usr", etc) as indicated by 879 * the low bits of the specified PSR. 880 */ 881 static inline const char *aarch32_mode_name(uint32_t psr) 882 { 883 static const char cpu_mode_names[16][4] = { 884 "usr", "fiq", "irq", "svc", "???", "???", "mon", "abt", 885 "???", "???", "hyp", "und", "???", "???", "???", "sys" 886 }; 887 888 return cpu_mode_names[psr & 0xf]; 889 } 890 891 /** 892 * arm_cpu_update_virq: Update CPU_INTERRUPT_VIRQ bit in cs->interrupt_request 893 * 894 * Update the CPU_INTERRUPT_VIRQ bit in cs->interrupt_request, following 895 * a change to either the input VIRQ line from the GIC or the HCR_EL2.VI bit. 896 * Must be called with the iothread lock held. 897 */ 898 void arm_cpu_update_virq(ARMCPU *cpu); 899 900 /** 901 * arm_cpu_update_vfiq: Update CPU_INTERRUPT_VFIQ bit in cs->interrupt_request 902 * 903 * Update the CPU_INTERRUPT_VFIQ bit in cs->interrupt_request, following 904 * a change to either the input VFIQ line from the GIC or the HCR_EL2.VF bit. 905 * Must be called with the iothread lock held. 906 */ 907 void arm_cpu_update_vfiq(ARMCPU *cpu); 908 909 #endif 910