1 /* 2 * QEMU ARM CPU -- internal functions and types 3 * 4 * Copyright (c) 2014 Linaro Ltd 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 * 20 * This header defines functions, types, etc which need to be shared 21 * between different source files within target/arm/ but which are 22 * private to it and not required by the rest of QEMU. 23 */ 24 25 #ifndef TARGET_ARM_INTERNALS_H 26 #define TARGET_ARM_INTERNALS_H 27 28 #include "hw/registerfields.h" 29 30 /* register banks for CPU modes */ 31 #define BANK_USRSYS 0 32 #define BANK_SVC 1 33 #define BANK_ABT 2 34 #define BANK_UND 3 35 #define BANK_IRQ 4 36 #define BANK_FIQ 5 37 #define BANK_HYP 6 38 #define BANK_MON 7 39 40 static inline bool excp_is_internal(int excp) 41 { 42 /* Return true if this exception number represents a QEMU-internal 43 * exception that will not be passed to the guest. 44 */ 45 return excp == EXCP_INTERRUPT 46 || excp == EXCP_HLT 47 || excp == EXCP_DEBUG 48 || excp == EXCP_HALTED 49 || excp == EXCP_EXCEPTION_EXIT 50 || excp == EXCP_KERNEL_TRAP 51 || excp == EXCP_SEMIHOST; 52 } 53 54 /* Scale factor for generic timers, ie number of ns per tick. 55 * This gives a 62.5MHz timer. 56 */ 57 #define GTIMER_SCALE 16 58 59 /* Bit definitions for the v7M CONTROL register */ 60 FIELD(V7M_CONTROL, NPRIV, 0, 1) 61 FIELD(V7M_CONTROL, SPSEL, 1, 1) 62 FIELD(V7M_CONTROL, FPCA, 2, 1) 63 FIELD(V7M_CONTROL, SFPA, 3, 1) 64 65 /* Bit definitions for v7M exception return payload */ 66 FIELD(V7M_EXCRET, ES, 0, 1) 67 FIELD(V7M_EXCRET, RES0, 1, 1) 68 FIELD(V7M_EXCRET, SPSEL, 2, 1) 69 FIELD(V7M_EXCRET, MODE, 3, 1) 70 FIELD(V7M_EXCRET, FTYPE, 4, 1) 71 FIELD(V7M_EXCRET, DCRS, 5, 1) 72 FIELD(V7M_EXCRET, S, 6, 1) 73 FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */ 74 75 /* Minimum value which is a magic number for exception return */ 76 #define EXC_RETURN_MIN_MAGIC 0xff000000 77 /* Minimum number which is a magic number for function or exception return 78 * when using v8M security extension 79 */ 80 #define FNC_RETURN_MIN_MAGIC 0xfefffffe 81 82 /* We use a few fake FSR values for internal purposes in M profile. 83 * M profile cores don't have A/R format FSRs, but currently our 84 * get_phys_addr() code assumes A/R profile and reports failures via 85 * an A/R format FSR value. We then translate that into the proper 86 * M profile exception and FSR status bit in arm_v7m_cpu_do_interrupt(). 87 * Mostly the FSR values we use for this are those defined for v7PMSA, 88 * since we share some of that codepath. A few kinds of fault are 89 * only for M profile and have no A/R equivalent, though, so we have 90 * to pick a value from the reserved range (which we never otherwise 91 * generate) to use for these. 92 * These values will never be visible to the guest. 93 */ 94 #define M_FAKE_FSR_NSC_EXEC 0xf /* NS executing in S&NSC memory */ 95 #define M_FAKE_FSR_SFAULT 0xe /* SecureFault INVTRAN, INVEP or AUVIOL */ 96 97 /** 98 * raise_exception: Raise the specified exception. 99 * Raise a guest exception with the specified value, syndrome register 100 * and target exception level. This should be called from helper functions, 101 * and never returns because we will longjump back up to the CPU main loop. 102 */ 103 void QEMU_NORETURN raise_exception(CPUARMState *env, uint32_t excp, 104 uint32_t syndrome, uint32_t target_el); 105 106 /* 107 * Similarly, but also use unwinding to restore cpu state. 108 */ 109 void QEMU_NORETURN raise_exception_ra(CPUARMState *env, uint32_t excp, 110 uint32_t syndrome, uint32_t target_el, 111 uintptr_t ra); 112 113 /* 114 * For AArch64, map a given EL to an index in the banked_spsr array. 115 * Note that this mapping and the AArch32 mapping defined in bank_number() 116 * must agree such that the AArch64<->AArch32 SPSRs have the architecturally 117 * mandated mapping between each other. 118 */ 119 static inline unsigned int aarch64_banked_spsr_index(unsigned int el) 120 { 121 static const unsigned int map[4] = { 122 [1] = BANK_SVC, /* EL1. */ 123 [2] = BANK_HYP, /* EL2. */ 124 [3] = BANK_MON, /* EL3. */ 125 }; 126 assert(el >= 1 && el <= 3); 127 return map[el]; 128 } 129 130 /* Map CPU modes onto saved register banks. */ 131 static inline int bank_number(int mode) 132 { 133 switch (mode) { 134 case ARM_CPU_MODE_USR: 135 case ARM_CPU_MODE_SYS: 136 return BANK_USRSYS; 137 case ARM_CPU_MODE_SVC: 138 return BANK_SVC; 139 case ARM_CPU_MODE_ABT: 140 return BANK_ABT; 141 case ARM_CPU_MODE_UND: 142 return BANK_UND; 143 case ARM_CPU_MODE_IRQ: 144 return BANK_IRQ; 145 case ARM_CPU_MODE_FIQ: 146 return BANK_FIQ; 147 case ARM_CPU_MODE_HYP: 148 return BANK_HYP; 149 case ARM_CPU_MODE_MON: 150 return BANK_MON; 151 } 152 g_assert_not_reached(); 153 } 154 155 /** 156 * r14_bank_number: Map CPU mode onto register bank for r14 157 * 158 * Given an AArch32 CPU mode, return the index into the saved register 159 * banks to use for the R14 (LR) in that mode. This is the same as 160 * bank_number(), except for the special case of Hyp mode, where 161 * R14 is shared with USR and SYS, unlike its R13 and SPSR. 162 * This should be used as the index into env->banked_r14[], and 163 * bank_number() used for the index into env->banked_r13[] and 164 * env->banked_spsr[]. 165 */ 166 static inline int r14_bank_number(int mode) 167 { 168 return (mode == ARM_CPU_MODE_HYP) ? BANK_USRSYS : bank_number(mode); 169 } 170 171 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu); 172 void arm_translate_init(void); 173 174 enum arm_fprounding { 175 FPROUNDING_TIEEVEN, 176 FPROUNDING_POSINF, 177 FPROUNDING_NEGINF, 178 FPROUNDING_ZERO, 179 FPROUNDING_TIEAWAY, 180 FPROUNDING_ODD 181 }; 182 183 int arm_rmode_to_sf(int rmode); 184 185 static inline void aarch64_save_sp(CPUARMState *env, int el) 186 { 187 if (env->pstate & PSTATE_SP) { 188 env->sp_el[el] = env->xregs[31]; 189 } else { 190 env->sp_el[0] = env->xregs[31]; 191 } 192 } 193 194 static inline void aarch64_restore_sp(CPUARMState *env, int el) 195 { 196 if (env->pstate & PSTATE_SP) { 197 env->xregs[31] = env->sp_el[el]; 198 } else { 199 env->xregs[31] = env->sp_el[0]; 200 } 201 } 202 203 static inline void update_spsel(CPUARMState *env, uint32_t imm) 204 { 205 unsigned int cur_el = arm_current_el(env); 206 /* Update PSTATE SPSel bit; this requires us to update the 207 * working stack pointer in xregs[31]. 208 */ 209 if (!((imm ^ env->pstate) & PSTATE_SP)) { 210 return; 211 } 212 aarch64_save_sp(env, cur_el); 213 env->pstate = deposit32(env->pstate, 0, 1, imm); 214 215 /* We rely on illegal updates to SPsel from EL0 to get trapped 216 * at translation time. 217 */ 218 assert(cur_el >= 1 && cur_el <= 3); 219 aarch64_restore_sp(env, cur_el); 220 } 221 222 /* 223 * arm_pamax 224 * @cpu: ARMCPU 225 * 226 * Returns the implementation defined bit-width of physical addresses. 227 * The ARMv8 reference manuals refer to this as PAMax(). 228 */ 229 static inline unsigned int arm_pamax(ARMCPU *cpu) 230 { 231 static const unsigned int pamax_map[] = { 232 [0] = 32, 233 [1] = 36, 234 [2] = 40, 235 [3] = 42, 236 [4] = 44, 237 [5] = 48, 238 }; 239 unsigned int parange = 240 FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE); 241 242 /* id_aa64mmfr0 is a read-only register so values outside of the 243 * supported mappings can be considered an implementation error. */ 244 assert(parange < ARRAY_SIZE(pamax_map)); 245 return pamax_map[parange]; 246 } 247 248 /* Return true if extended addresses are enabled. 249 * This is always the case if our translation regime is 64 bit, 250 * but depends on TTBCR.EAE for 32 bit. 251 */ 252 static inline bool extended_addresses_enabled(CPUARMState *env) 253 { 254 TCR *tcr = &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1]; 255 return arm_el_is_aa64(env, 1) || 256 (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE)); 257 } 258 259 /* Valid Syndrome Register EC field values */ 260 enum arm_exception_class { 261 EC_UNCATEGORIZED = 0x00, 262 EC_WFX_TRAP = 0x01, 263 EC_CP15RTTRAP = 0x03, 264 EC_CP15RRTTRAP = 0x04, 265 EC_CP14RTTRAP = 0x05, 266 EC_CP14DTTRAP = 0x06, 267 EC_ADVSIMDFPACCESSTRAP = 0x07, 268 EC_FPIDTRAP = 0x08, 269 EC_PACTRAP = 0x09, 270 EC_CP14RRTTRAP = 0x0c, 271 EC_ILLEGALSTATE = 0x0e, 272 EC_AA32_SVC = 0x11, 273 EC_AA32_HVC = 0x12, 274 EC_AA32_SMC = 0x13, 275 EC_AA64_SVC = 0x15, 276 EC_AA64_HVC = 0x16, 277 EC_AA64_SMC = 0x17, 278 EC_SYSTEMREGISTERTRAP = 0x18, 279 EC_SVEACCESSTRAP = 0x19, 280 EC_INSNABORT = 0x20, 281 EC_INSNABORT_SAME_EL = 0x21, 282 EC_PCALIGNMENT = 0x22, 283 EC_DATAABORT = 0x24, 284 EC_DATAABORT_SAME_EL = 0x25, 285 EC_SPALIGNMENT = 0x26, 286 EC_AA32_FPTRAP = 0x28, 287 EC_AA64_FPTRAP = 0x2c, 288 EC_SERROR = 0x2f, 289 EC_BREAKPOINT = 0x30, 290 EC_BREAKPOINT_SAME_EL = 0x31, 291 EC_SOFTWARESTEP = 0x32, 292 EC_SOFTWARESTEP_SAME_EL = 0x33, 293 EC_WATCHPOINT = 0x34, 294 EC_WATCHPOINT_SAME_EL = 0x35, 295 EC_AA32_BKPT = 0x38, 296 EC_VECTORCATCH = 0x3a, 297 EC_AA64_BKPT = 0x3c, 298 }; 299 300 #define ARM_EL_EC_SHIFT 26 301 #define ARM_EL_IL_SHIFT 25 302 #define ARM_EL_ISV_SHIFT 24 303 #define ARM_EL_IL (1 << ARM_EL_IL_SHIFT) 304 #define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT) 305 306 static inline uint32_t syn_get_ec(uint32_t syn) 307 { 308 return syn >> ARM_EL_EC_SHIFT; 309 } 310 311 /* Utility functions for constructing various kinds of syndrome value. 312 * Note that in general we follow the AArch64 syndrome values; in a 313 * few cases the value in HSR for exceptions taken to AArch32 Hyp 314 * mode differs slightly, and we fix this up when populating HSR in 315 * arm_cpu_do_interrupt_aarch32_hyp(). 316 * The exception is FP/SIMD access traps -- these report extra information 317 * when taking an exception to AArch32. For those we include the extra coproc 318 * and TA fields, and mask them out when taking the exception to AArch64. 319 */ 320 static inline uint32_t syn_uncategorized(void) 321 { 322 return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL; 323 } 324 325 static inline uint32_t syn_aa64_svc(uint32_t imm16) 326 { 327 return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 328 } 329 330 static inline uint32_t syn_aa64_hvc(uint32_t imm16) 331 { 332 return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 333 } 334 335 static inline uint32_t syn_aa64_smc(uint32_t imm16) 336 { 337 return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 338 } 339 340 static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit) 341 { 342 return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) 343 | (is_16bit ? 0 : ARM_EL_IL); 344 } 345 346 static inline uint32_t syn_aa32_hvc(uint32_t imm16) 347 { 348 return (EC_AA32_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 349 } 350 351 static inline uint32_t syn_aa32_smc(void) 352 { 353 return (EC_AA32_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL; 354 } 355 356 static inline uint32_t syn_aa64_bkpt(uint32_t imm16) 357 { 358 return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 359 } 360 361 static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit) 362 { 363 return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) 364 | (is_16bit ? 0 : ARM_EL_IL); 365 } 366 367 static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2, 368 int crn, int crm, int rt, 369 int isread) 370 { 371 return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL 372 | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5) 373 | (crm << 1) | isread; 374 } 375 376 static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2, 377 int crn, int crm, int rt, int isread, 378 bool is_16bit) 379 { 380 return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT) 381 | (is_16bit ? 0 : ARM_EL_IL) 382 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) 383 | (crn << 10) | (rt << 5) | (crm << 1) | isread; 384 } 385 386 static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2, 387 int crn, int crm, int rt, int isread, 388 bool is_16bit) 389 { 390 return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT) 391 | (is_16bit ? 0 : ARM_EL_IL) 392 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) 393 | (crn << 10) | (rt << 5) | (crm << 1) | isread; 394 } 395 396 static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm, 397 int rt, int rt2, int isread, 398 bool is_16bit) 399 { 400 return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT) 401 | (is_16bit ? 0 : ARM_EL_IL) 402 | (cv << 24) | (cond << 20) | (opc1 << 16) 403 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; 404 } 405 406 static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm, 407 int rt, int rt2, int isread, 408 bool is_16bit) 409 { 410 return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT) 411 | (is_16bit ? 0 : ARM_EL_IL) 412 | (cv << 24) | (cond << 20) | (opc1 << 16) 413 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; 414 } 415 416 static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit) 417 { 418 /* AArch32 FP trap or any AArch64 FP/SIMD trap: TA == 0 coproc == 0xa */ 419 return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) 420 | (is_16bit ? 0 : ARM_EL_IL) 421 | (cv << 24) | (cond << 20) | 0xa; 422 } 423 424 static inline uint32_t syn_simd_access_trap(int cv, int cond, bool is_16bit) 425 { 426 /* AArch32 SIMD trap: TA == 1 coproc == 0 */ 427 return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) 428 | (is_16bit ? 0 : ARM_EL_IL) 429 | (cv << 24) | (cond << 20) | (1 << 5); 430 } 431 432 static inline uint32_t syn_sve_access_trap(void) 433 { 434 return EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT; 435 } 436 437 static inline uint32_t syn_pactrap(void) 438 { 439 return EC_PACTRAP << ARM_EL_EC_SHIFT; 440 } 441 442 static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc) 443 { 444 return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 445 | ARM_EL_IL | (ea << 9) | (s1ptw << 7) | fsc; 446 } 447 448 static inline uint32_t syn_data_abort_no_iss(int same_el, 449 int ea, int cm, int s1ptw, 450 int wnr, int fsc) 451 { 452 return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 453 | ARM_EL_IL 454 | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc; 455 } 456 457 static inline uint32_t syn_data_abort_with_iss(int same_el, 458 int sas, int sse, int srt, 459 int sf, int ar, 460 int ea, int cm, int s1ptw, 461 int wnr, int fsc, 462 bool is_16bit) 463 { 464 return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 465 | (is_16bit ? 0 : ARM_EL_IL) 466 | ARM_EL_ISV | (sas << 22) | (sse << 21) | (srt << 16) 467 | (sf << 15) | (ar << 14) 468 | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc; 469 } 470 471 static inline uint32_t syn_swstep(int same_el, int isv, int ex) 472 { 473 return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 474 | ARM_EL_IL | (isv << 24) | (ex << 6) | 0x22; 475 } 476 477 static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr) 478 { 479 return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 480 | ARM_EL_IL | (cm << 8) | (wnr << 6) | 0x22; 481 } 482 483 static inline uint32_t syn_breakpoint(int same_el) 484 { 485 return (EC_BREAKPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 486 | ARM_EL_IL | 0x22; 487 } 488 489 static inline uint32_t syn_wfx(int cv, int cond, int ti, bool is_16bit) 490 { 491 return (EC_WFX_TRAP << ARM_EL_EC_SHIFT) | 492 (is_16bit ? 0 : (1 << ARM_EL_IL_SHIFT)) | 493 (cv << 24) | (cond << 20) | ti; 494 } 495 496 /* Update a QEMU watchpoint based on the information the guest has set in the 497 * DBGWCR<n>_EL1 and DBGWVR<n>_EL1 registers. 498 */ 499 void hw_watchpoint_update(ARMCPU *cpu, int n); 500 /* Update the QEMU watchpoints for every guest watchpoint. This does a 501 * complete delete-and-reinstate of the QEMU watchpoint list and so is 502 * suitable for use after migration or on reset. 503 */ 504 void hw_watchpoint_update_all(ARMCPU *cpu); 505 /* Update a QEMU breakpoint based on the information the guest has set in the 506 * DBGBCR<n>_EL1 and DBGBVR<n>_EL1 registers. 507 */ 508 void hw_breakpoint_update(ARMCPU *cpu, int n); 509 /* Update the QEMU breakpoints for every guest breakpoint. This does a 510 * complete delete-and-reinstate of the QEMU breakpoint list and so is 511 * suitable for use after migration or on reset. 512 */ 513 void hw_breakpoint_update_all(ARMCPU *cpu); 514 515 /* Callback function for checking if a watchpoint should trigger. */ 516 bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); 517 518 /* Adjust addresses (in BE32 mode) before testing against watchpoint 519 * addresses. 520 */ 521 vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len); 522 523 /* Callback function for when a watchpoint or breakpoint triggers. */ 524 void arm_debug_excp_handler(CPUState *cs); 525 526 #ifdef CONFIG_USER_ONLY 527 static inline bool arm_is_psci_call(ARMCPU *cpu, int excp_type) 528 { 529 return false; 530 } 531 #else 532 /* Return true if the r0/x0 value indicates that this SMC/HVC is a PSCI call. */ 533 bool arm_is_psci_call(ARMCPU *cpu, int excp_type); 534 /* Actually handle a PSCI call */ 535 void arm_handle_psci_call(ARMCPU *cpu); 536 #endif 537 538 /** 539 * arm_clear_exclusive: clear the exclusive monitor 540 * @env: CPU env 541 * Clear the CPU's exclusive monitor, like the guest CLREX instruction. 542 */ 543 static inline void arm_clear_exclusive(CPUARMState *env) 544 { 545 env->exclusive_addr = -1; 546 } 547 548 /** 549 * ARMFaultType: type of an ARM MMU fault 550 * This corresponds to the v8A pseudocode's Fault enumeration, 551 * with extensions for QEMU internal conditions. 552 */ 553 typedef enum ARMFaultType { 554 ARMFault_None, 555 ARMFault_AccessFlag, 556 ARMFault_Alignment, 557 ARMFault_Background, 558 ARMFault_Domain, 559 ARMFault_Permission, 560 ARMFault_Translation, 561 ARMFault_AddressSize, 562 ARMFault_SyncExternal, 563 ARMFault_SyncExternalOnWalk, 564 ARMFault_SyncParity, 565 ARMFault_SyncParityOnWalk, 566 ARMFault_AsyncParity, 567 ARMFault_AsyncExternal, 568 ARMFault_Debug, 569 ARMFault_TLBConflict, 570 ARMFault_Lockdown, 571 ARMFault_Exclusive, 572 ARMFault_ICacheMaint, 573 ARMFault_QEMU_NSCExec, /* v8M: NS executing in S&NSC memory */ 574 ARMFault_QEMU_SFault, /* v8M: SecureFault INVTRAN, INVEP or AUVIOL */ 575 } ARMFaultType; 576 577 /** 578 * ARMMMUFaultInfo: Information describing an ARM MMU Fault 579 * @type: Type of fault 580 * @level: Table walk level (for translation, access flag and permission faults) 581 * @domain: Domain of the fault address (for non-LPAE CPUs only) 582 * @s2addr: Address that caused a fault at stage 2 583 * @stage2: True if we faulted at stage 2 584 * @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table walk 585 * @ea: True if we should set the EA (external abort type) bit in syndrome 586 */ 587 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; 588 struct ARMMMUFaultInfo { 589 ARMFaultType type; 590 target_ulong s2addr; 591 int level; 592 int domain; 593 bool stage2; 594 bool s1ptw; 595 bool ea; 596 }; 597 598 /** 599 * arm_fi_to_sfsc: Convert fault info struct to short-format FSC 600 * Compare pseudocode EncodeSDFSC(), though unlike that function 601 * we set up a whole FSR-format code including domain field and 602 * putting the high bit of the FSC into bit 10. 603 */ 604 static inline uint32_t arm_fi_to_sfsc(ARMMMUFaultInfo *fi) 605 { 606 uint32_t fsc; 607 608 switch (fi->type) { 609 case ARMFault_None: 610 return 0; 611 case ARMFault_AccessFlag: 612 fsc = fi->level == 1 ? 0x3 : 0x6; 613 break; 614 case ARMFault_Alignment: 615 fsc = 0x1; 616 break; 617 case ARMFault_Permission: 618 fsc = fi->level == 1 ? 0xd : 0xf; 619 break; 620 case ARMFault_Domain: 621 fsc = fi->level == 1 ? 0x9 : 0xb; 622 break; 623 case ARMFault_Translation: 624 fsc = fi->level == 1 ? 0x5 : 0x7; 625 break; 626 case ARMFault_SyncExternal: 627 fsc = 0x8 | (fi->ea << 12); 628 break; 629 case ARMFault_SyncExternalOnWalk: 630 fsc = fi->level == 1 ? 0xc : 0xe; 631 fsc |= (fi->ea << 12); 632 break; 633 case ARMFault_SyncParity: 634 fsc = 0x409; 635 break; 636 case ARMFault_SyncParityOnWalk: 637 fsc = fi->level == 1 ? 0x40c : 0x40e; 638 break; 639 case ARMFault_AsyncParity: 640 fsc = 0x408; 641 break; 642 case ARMFault_AsyncExternal: 643 fsc = 0x406 | (fi->ea << 12); 644 break; 645 case ARMFault_Debug: 646 fsc = 0x2; 647 break; 648 case ARMFault_TLBConflict: 649 fsc = 0x400; 650 break; 651 case ARMFault_Lockdown: 652 fsc = 0x404; 653 break; 654 case ARMFault_Exclusive: 655 fsc = 0x405; 656 break; 657 case ARMFault_ICacheMaint: 658 fsc = 0x4; 659 break; 660 case ARMFault_Background: 661 fsc = 0x0; 662 break; 663 case ARMFault_QEMU_NSCExec: 664 fsc = M_FAKE_FSR_NSC_EXEC; 665 break; 666 case ARMFault_QEMU_SFault: 667 fsc = M_FAKE_FSR_SFAULT; 668 break; 669 default: 670 /* Other faults can't occur in a context that requires a 671 * short-format status code. 672 */ 673 g_assert_not_reached(); 674 } 675 676 fsc |= (fi->domain << 4); 677 return fsc; 678 } 679 680 /** 681 * arm_fi_to_lfsc: Convert fault info struct to long-format FSC 682 * Compare pseudocode EncodeLDFSC(), though unlike that function 683 * we fill in also the LPAE bit 9 of a DFSR format. 684 */ 685 static inline uint32_t arm_fi_to_lfsc(ARMMMUFaultInfo *fi) 686 { 687 uint32_t fsc; 688 689 switch (fi->type) { 690 case ARMFault_None: 691 return 0; 692 case ARMFault_AddressSize: 693 fsc = fi->level & 3; 694 break; 695 case ARMFault_AccessFlag: 696 fsc = (fi->level & 3) | (0x2 << 2); 697 break; 698 case ARMFault_Permission: 699 fsc = (fi->level & 3) | (0x3 << 2); 700 break; 701 case ARMFault_Translation: 702 fsc = (fi->level & 3) | (0x1 << 2); 703 break; 704 case ARMFault_SyncExternal: 705 fsc = 0x10 | (fi->ea << 12); 706 break; 707 case ARMFault_SyncExternalOnWalk: 708 fsc = (fi->level & 3) | (0x5 << 2) | (fi->ea << 12); 709 break; 710 case ARMFault_SyncParity: 711 fsc = 0x18; 712 break; 713 case ARMFault_SyncParityOnWalk: 714 fsc = (fi->level & 3) | (0x7 << 2); 715 break; 716 case ARMFault_AsyncParity: 717 fsc = 0x19; 718 break; 719 case ARMFault_AsyncExternal: 720 fsc = 0x11 | (fi->ea << 12); 721 break; 722 case ARMFault_Alignment: 723 fsc = 0x21; 724 break; 725 case ARMFault_Debug: 726 fsc = 0x22; 727 break; 728 case ARMFault_TLBConflict: 729 fsc = 0x30; 730 break; 731 case ARMFault_Lockdown: 732 fsc = 0x34; 733 break; 734 case ARMFault_Exclusive: 735 fsc = 0x35; 736 break; 737 default: 738 /* Other faults can't occur in a context that requires a 739 * long-format status code. 740 */ 741 g_assert_not_reached(); 742 } 743 744 fsc |= 1 << 9; 745 return fsc; 746 } 747 748 static inline bool arm_extabort_type(MemTxResult result) 749 { 750 /* The EA bit in syndromes and fault status registers is an 751 * IMPDEF classification of external aborts. ARM implementations 752 * usually use this to indicate AXI bus Decode error (0) or 753 * Slave error (1); in QEMU we follow that. 754 */ 755 return result != MEMTX_DECODE_ERROR; 756 } 757 758 /* Do a page table walk and add page to TLB if possible */ 759 bool arm_tlb_fill(CPUState *cpu, vaddr address, 760 MMUAccessType access_type, int mmu_idx, 761 ARMMMUFaultInfo *fi); 762 763 /* Return true if the stage 1 translation regime is using LPAE format page 764 * tables */ 765 bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx); 766 767 /* Raise a data fault alignment exception for the specified virtual address */ 768 void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, 769 MMUAccessType access_type, 770 int mmu_idx, uintptr_t retaddr); 771 772 /* arm_cpu_do_transaction_failed: handle a memory system error response 773 * (eg "no device/memory present at address") by raising an external abort 774 * exception 775 */ 776 void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 777 vaddr addr, unsigned size, 778 MMUAccessType access_type, 779 int mmu_idx, MemTxAttrs attrs, 780 MemTxResult response, uintptr_t retaddr); 781 782 /* Call any registered EL change hooks */ 783 static inline void arm_call_pre_el_change_hook(ARMCPU *cpu) 784 { 785 ARMELChangeHook *hook, *next; 786 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 787 hook->hook(cpu, hook->opaque); 788 } 789 } 790 static inline void arm_call_el_change_hook(ARMCPU *cpu) 791 { 792 ARMELChangeHook *hook, *next; 793 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 794 hook->hook(cpu, hook->opaque); 795 } 796 } 797 798 /* Return true if this address translation regime is secure */ 799 static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) 800 { 801 switch (mmu_idx) { 802 case ARMMMUIdx_S12NSE0: 803 case ARMMMUIdx_S12NSE1: 804 case ARMMMUIdx_S1NSE0: 805 case ARMMMUIdx_S1NSE1: 806 case ARMMMUIdx_S1E2: 807 case ARMMMUIdx_S2NS: 808 case ARMMMUIdx_MPrivNegPri: 809 case ARMMMUIdx_MUserNegPri: 810 case ARMMMUIdx_MPriv: 811 case ARMMMUIdx_MUser: 812 return false; 813 case ARMMMUIdx_S1E3: 814 case ARMMMUIdx_S1SE0: 815 case ARMMMUIdx_S1SE1: 816 case ARMMMUIdx_MSPrivNegPri: 817 case ARMMMUIdx_MSUserNegPri: 818 case ARMMMUIdx_MSPriv: 819 case ARMMMUIdx_MSUser: 820 return true; 821 default: 822 g_assert_not_reached(); 823 } 824 } 825 826 /* Return the FSR value for a debug exception (watchpoint, hardware 827 * breakpoint or BKPT insn) targeting the specified exception level. 828 */ 829 static inline uint32_t arm_debug_exception_fsr(CPUARMState *env) 830 { 831 ARMMMUFaultInfo fi = { .type = ARMFault_Debug }; 832 int target_el = arm_debug_target_el(env); 833 bool using_lpae = false; 834 835 if (target_el == 2 || arm_el_is_aa64(env, target_el)) { 836 using_lpae = true; 837 } else { 838 if (arm_feature(env, ARM_FEATURE_LPAE) && 839 (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) { 840 using_lpae = true; 841 } 842 } 843 844 if (using_lpae) { 845 return arm_fi_to_lfsc(&fi); 846 } else { 847 return arm_fi_to_sfsc(&fi); 848 } 849 } 850 851 /* Note make_memop_idx reserves 4 bits for mmu_idx, and MO_BSWAP is bit 3. 852 * Thus a TCGMemOpIdx, without any MO_ALIGN bits, fits in 8 bits. 853 */ 854 #define MEMOPIDX_SHIFT 8 855 856 /** 857 * v7m_using_psp: Return true if using process stack pointer 858 * Return true if the CPU is currently using the process stack 859 * pointer, or false if it is using the main stack pointer. 860 */ 861 static inline bool v7m_using_psp(CPUARMState *env) 862 { 863 /* Handler mode always uses the main stack; for thread mode 864 * the CONTROL.SPSEL bit determines the answer. 865 * Note that in v7M it is not possible to be in Handler mode with 866 * CONTROL.SPSEL non-zero, but in v8M it is, so we must check both. 867 */ 868 return !arm_v7m_is_handler_mode(env) && 869 env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK; 870 } 871 872 /** 873 * v7m_sp_limit: Return SP limit for current CPU state 874 * Return the SP limit value for the current CPU security state 875 * and stack pointer. 876 */ 877 static inline uint32_t v7m_sp_limit(CPUARMState *env) 878 { 879 if (v7m_using_psp(env)) { 880 return env->v7m.psplim[env->v7m.secure]; 881 } else { 882 return env->v7m.msplim[env->v7m.secure]; 883 } 884 } 885 886 /** 887 * aarch32_mode_name(): Return name of the AArch32 CPU mode 888 * @psr: Program Status Register indicating CPU mode 889 * 890 * Returns, for debug logging purposes, a printable representation 891 * of the AArch32 CPU mode ("svc", "usr", etc) as indicated by 892 * the low bits of the specified PSR. 893 */ 894 static inline const char *aarch32_mode_name(uint32_t psr) 895 { 896 static const char cpu_mode_names[16][4] = { 897 "usr", "fiq", "irq", "svc", "???", "???", "mon", "abt", 898 "???", "???", "hyp", "und", "???", "???", "???", "sys" 899 }; 900 901 return cpu_mode_names[psr & 0xf]; 902 } 903 904 /** 905 * arm_cpu_update_virq: Update CPU_INTERRUPT_VIRQ bit in cs->interrupt_request 906 * 907 * Update the CPU_INTERRUPT_VIRQ bit in cs->interrupt_request, following 908 * a change to either the input VIRQ line from the GIC or the HCR_EL2.VI bit. 909 * Must be called with the iothread lock held. 910 */ 911 void arm_cpu_update_virq(ARMCPU *cpu); 912 913 /** 914 * arm_cpu_update_vfiq: Update CPU_INTERRUPT_VFIQ bit in cs->interrupt_request 915 * 916 * Update the CPU_INTERRUPT_VFIQ bit in cs->interrupt_request, following 917 * a change to either the input VFIQ line from the GIC or the HCR_EL2.VF bit. 918 * Must be called with the iothread lock held. 919 */ 920 void arm_cpu_update_vfiq(ARMCPU *cpu); 921 922 /** 923 * arm_mmu_idx: 924 * @env: The cpu environment 925 * 926 * Return the full ARMMMUIdx for the current translation regime. 927 */ 928 ARMMMUIdx arm_mmu_idx(CPUARMState *env); 929 930 /** 931 * arm_stage1_mmu_idx: 932 * @env: The cpu environment 933 * 934 * Return the ARMMMUIdx for the stage1 traversal for the current regime. 935 */ 936 #ifdef CONFIG_USER_ONLY 937 static inline ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) 938 { 939 return ARMMMUIdx_S1NSE0; 940 } 941 #else 942 ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env); 943 #endif 944 945 /* 946 * Parameters of a given virtual address, as extracted from the 947 * translation control register (TCR) for a given regime. 948 */ 949 typedef struct ARMVAParameters { 950 unsigned tsz : 8; 951 unsigned select : 1; 952 bool tbi : 1; 953 bool tbid : 1; 954 bool epd : 1; 955 bool hpd : 1; 956 bool using16k : 1; 957 bool using64k : 1; 958 } ARMVAParameters; 959 960 #ifdef CONFIG_USER_ONLY 961 static inline ARMVAParameters aa64_va_parameters_both(CPUARMState *env, 962 uint64_t va, 963 ARMMMUIdx mmu_idx) 964 { 965 return (ARMVAParameters) { 966 /* 48-bit address space */ 967 .tsz = 16, 968 /* We can't handle tagged addresses properly in user-only mode */ 969 .tbi = false, 970 }; 971 } 972 973 static inline ARMVAParameters aa64_va_parameters(CPUARMState *env, 974 uint64_t va, 975 ARMMMUIdx mmu_idx, bool data) 976 { 977 return aa64_va_parameters_both(env, va, mmu_idx); 978 } 979 #else 980 ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, 981 ARMMMUIdx mmu_idx); 982 ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, 983 ARMMMUIdx mmu_idx, bool data); 984 #endif 985 986 #endif 987