1 /* 2 * QEMU ARM CPU -- internal functions and types 3 * 4 * Copyright (c) 2014 Linaro Ltd 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 * 20 * This header defines functions, types, etc which need to be shared 21 * between different source files within target/arm/ but which are 22 * private to it and not required by the rest of QEMU. 23 */ 24 25 #ifndef TARGET_ARM_INTERNALS_H 26 #define TARGET_ARM_INTERNALS_H 27 28 #include "hw/registerfields.h" 29 30 /* register banks for CPU modes */ 31 #define BANK_USRSYS 0 32 #define BANK_SVC 1 33 #define BANK_ABT 2 34 #define BANK_UND 3 35 #define BANK_IRQ 4 36 #define BANK_FIQ 5 37 #define BANK_HYP 6 38 #define BANK_MON 7 39 40 static inline bool excp_is_internal(int excp) 41 { 42 /* Return true if this exception number represents a QEMU-internal 43 * exception that will not be passed to the guest. 44 */ 45 return excp == EXCP_INTERRUPT 46 || excp == EXCP_HLT 47 || excp == EXCP_DEBUG 48 || excp == EXCP_HALTED 49 || excp == EXCP_EXCEPTION_EXIT 50 || excp == EXCP_KERNEL_TRAP 51 || excp == EXCP_SEMIHOST; 52 } 53 54 /* Scale factor for generic timers, ie number of ns per tick. 55 * This gives a 62.5MHz timer. 56 */ 57 #define GTIMER_SCALE 16 58 59 /* Bit definitions for the v7M CONTROL register */ 60 FIELD(V7M_CONTROL, NPRIV, 0, 1) 61 FIELD(V7M_CONTROL, SPSEL, 1, 1) 62 FIELD(V7M_CONTROL, FPCA, 2, 1) 63 64 /* Bit definitions for v7M exception return payload */ 65 FIELD(V7M_EXCRET, ES, 0, 1) 66 FIELD(V7M_EXCRET, RES0, 1, 1) 67 FIELD(V7M_EXCRET, SPSEL, 2, 1) 68 FIELD(V7M_EXCRET, MODE, 3, 1) 69 FIELD(V7M_EXCRET, FTYPE, 4, 1) 70 FIELD(V7M_EXCRET, DCRS, 5, 1) 71 FIELD(V7M_EXCRET, S, 6, 1) 72 FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */ 73 74 /* We use a few fake FSR values for internal purposes in M profile. 75 * M profile cores don't have A/R format FSRs, but currently our 76 * get_phys_addr() code assumes A/R profile and reports failures via 77 * an A/R format FSR value. We then translate that into the proper 78 * M profile exception and FSR status bit in arm_v7m_cpu_do_interrupt(). 79 * Mostly the FSR values we use for this are those defined for v7PMSA, 80 * since we share some of that codepath. A few kinds of fault are 81 * only for M profile and have no A/R equivalent, though, so we have 82 * to pick a value from the reserved range (which we never otherwise 83 * generate) to use for these. 84 * These values will never be visible to the guest. 85 */ 86 #define M_FAKE_FSR_NSC_EXEC 0xf /* NS executing in S&NSC memory */ 87 #define M_FAKE_FSR_SFAULT 0xe /* SecureFault INVTRAN, INVEP or AUVIOL */ 88 89 /* 90 * For AArch64, map a given EL to an index in the banked_spsr array. 91 * Note that this mapping and the AArch32 mapping defined in bank_number() 92 * must agree such that the AArch64<->AArch32 SPSRs have the architecturally 93 * mandated mapping between each other. 94 */ 95 static inline unsigned int aarch64_banked_spsr_index(unsigned int el) 96 { 97 static const unsigned int map[4] = { 98 [1] = BANK_SVC, /* EL1. */ 99 [2] = BANK_HYP, /* EL2. */ 100 [3] = BANK_MON, /* EL3. */ 101 }; 102 assert(el >= 1 && el <= 3); 103 return map[el]; 104 } 105 106 /* Map CPU modes onto saved register banks. */ 107 static inline int bank_number(int mode) 108 { 109 switch (mode) { 110 case ARM_CPU_MODE_USR: 111 case ARM_CPU_MODE_SYS: 112 return BANK_USRSYS; 113 case ARM_CPU_MODE_SVC: 114 return BANK_SVC; 115 case ARM_CPU_MODE_ABT: 116 return BANK_ABT; 117 case ARM_CPU_MODE_UND: 118 return BANK_UND; 119 case ARM_CPU_MODE_IRQ: 120 return BANK_IRQ; 121 case ARM_CPU_MODE_FIQ: 122 return BANK_FIQ; 123 case ARM_CPU_MODE_HYP: 124 return BANK_HYP; 125 case ARM_CPU_MODE_MON: 126 return BANK_MON; 127 } 128 g_assert_not_reached(); 129 } 130 131 void switch_mode(CPUARMState *, int); 132 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu); 133 void arm_translate_init(void); 134 135 enum arm_fprounding { 136 FPROUNDING_TIEEVEN, 137 FPROUNDING_POSINF, 138 FPROUNDING_NEGINF, 139 FPROUNDING_ZERO, 140 FPROUNDING_TIEAWAY, 141 FPROUNDING_ODD 142 }; 143 144 int arm_rmode_to_sf(int rmode); 145 146 static inline void aarch64_save_sp(CPUARMState *env, int el) 147 { 148 if (env->pstate & PSTATE_SP) { 149 env->sp_el[el] = env->xregs[31]; 150 } else { 151 env->sp_el[0] = env->xregs[31]; 152 } 153 } 154 155 static inline void aarch64_restore_sp(CPUARMState *env, int el) 156 { 157 if (env->pstate & PSTATE_SP) { 158 env->xregs[31] = env->sp_el[el]; 159 } else { 160 env->xregs[31] = env->sp_el[0]; 161 } 162 } 163 164 static inline void update_spsel(CPUARMState *env, uint32_t imm) 165 { 166 unsigned int cur_el = arm_current_el(env); 167 /* Update PSTATE SPSel bit; this requires us to update the 168 * working stack pointer in xregs[31]. 169 */ 170 if (!((imm ^ env->pstate) & PSTATE_SP)) { 171 return; 172 } 173 aarch64_save_sp(env, cur_el); 174 env->pstate = deposit32(env->pstate, 0, 1, imm); 175 176 /* We rely on illegal updates to SPsel from EL0 to get trapped 177 * at translation time. 178 */ 179 assert(cur_el >= 1 && cur_el <= 3); 180 aarch64_restore_sp(env, cur_el); 181 } 182 183 /* 184 * arm_pamax 185 * @cpu: ARMCPU 186 * 187 * Returns the implementation defined bit-width of physical addresses. 188 * The ARMv8 reference manuals refer to this as PAMax(). 189 */ 190 static inline unsigned int arm_pamax(ARMCPU *cpu) 191 { 192 static const unsigned int pamax_map[] = { 193 [0] = 32, 194 [1] = 36, 195 [2] = 40, 196 [3] = 42, 197 [4] = 44, 198 [5] = 48, 199 }; 200 unsigned int parange = extract32(cpu->id_aa64mmfr0, 0, 4); 201 202 /* id_aa64mmfr0 is a read-only register so values outside of the 203 * supported mappings can be considered an implementation error. */ 204 assert(parange < ARRAY_SIZE(pamax_map)); 205 return pamax_map[parange]; 206 } 207 208 /* Return true if extended addresses are enabled. 209 * This is always the case if our translation regime is 64 bit, 210 * but depends on TTBCR.EAE for 32 bit. 211 */ 212 static inline bool extended_addresses_enabled(CPUARMState *env) 213 { 214 TCR *tcr = &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1]; 215 return arm_el_is_aa64(env, 1) || 216 (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE)); 217 } 218 219 /* Valid Syndrome Register EC field values */ 220 enum arm_exception_class { 221 EC_UNCATEGORIZED = 0x00, 222 EC_WFX_TRAP = 0x01, 223 EC_CP15RTTRAP = 0x03, 224 EC_CP15RRTTRAP = 0x04, 225 EC_CP14RTTRAP = 0x05, 226 EC_CP14DTTRAP = 0x06, 227 EC_ADVSIMDFPACCESSTRAP = 0x07, 228 EC_FPIDTRAP = 0x08, 229 EC_CP14RRTTRAP = 0x0c, 230 EC_ILLEGALSTATE = 0x0e, 231 EC_AA32_SVC = 0x11, 232 EC_AA32_HVC = 0x12, 233 EC_AA32_SMC = 0x13, 234 EC_AA64_SVC = 0x15, 235 EC_AA64_HVC = 0x16, 236 EC_AA64_SMC = 0x17, 237 EC_SYSTEMREGISTERTRAP = 0x18, 238 EC_INSNABORT = 0x20, 239 EC_INSNABORT_SAME_EL = 0x21, 240 EC_PCALIGNMENT = 0x22, 241 EC_DATAABORT = 0x24, 242 EC_DATAABORT_SAME_EL = 0x25, 243 EC_SPALIGNMENT = 0x26, 244 EC_AA32_FPTRAP = 0x28, 245 EC_AA64_FPTRAP = 0x2c, 246 EC_SERROR = 0x2f, 247 EC_BREAKPOINT = 0x30, 248 EC_BREAKPOINT_SAME_EL = 0x31, 249 EC_SOFTWARESTEP = 0x32, 250 EC_SOFTWARESTEP_SAME_EL = 0x33, 251 EC_WATCHPOINT = 0x34, 252 EC_WATCHPOINT_SAME_EL = 0x35, 253 EC_AA32_BKPT = 0x38, 254 EC_VECTORCATCH = 0x3a, 255 EC_AA64_BKPT = 0x3c, 256 }; 257 258 #define ARM_EL_EC_SHIFT 26 259 #define ARM_EL_IL_SHIFT 25 260 #define ARM_EL_ISV_SHIFT 24 261 #define ARM_EL_IL (1 << ARM_EL_IL_SHIFT) 262 #define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT) 263 264 /* Utility functions for constructing various kinds of syndrome value. 265 * Note that in general we follow the AArch64 syndrome values; in a 266 * few cases the value in HSR for exceptions taken to AArch32 Hyp 267 * mode differs slightly, so if we ever implemented Hyp mode then the 268 * syndrome value would need some massaging on exception entry. 269 * (One example of this is that AArch64 defaults to IL bit set for 270 * exceptions which don't specifically indicate information about the 271 * trapping instruction, whereas AArch32 defaults to IL bit clear.) 272 */ 273 static inline uint32_t syn_uncategorized(void) 274 { 275 return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL; 276 } 277 278 static inline uint32_t syn_aa64_svc(uint32_t imm16) 279 { 280 return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 281 } 282 283 static inline uint32_t syn_aa64_hvc(uint32_t imm16) 284 { 285 return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 286 } 287 288 static inline uint32_t syn_aa64_smc(uint32_t imm16) 289 { 290 return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 291 } 292 293 static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit) 294 { 295 return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) 296 | (is_16bit ? 0 : ARM_EL_IL); 297 } 298 299 static inline uint32_t syn_aa32_hvc(uint32_t imm16) 300 { 301 return (EC_AA32_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 302 } 303 304 static inline uint32_t syn_aa32_smc(void) 305 { 306 return (EC_AA32_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL; 307 } 308 309 static inline uint32_t syn_aa64_bkpt(uint32_t imm16) 310 { 311 return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); 312 } 313 314 static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit) 315 { 316 return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) 317 | (is_16bit ? 0 : ARM_EL_IL); 318 } 319 320 static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2, 321 int crn, int crm, int rt, 322 int isread) 323 { 324 return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL 325 | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5) 326 | (crm << 1) | isread; 327 } 328 329 static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2, 330 int crn, int crm, int rt, int isread, 331 bool is_16bit) 332 { 333 return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT) 334 | (is_16bit ? 0 : ARM_EL_IL) 335 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) 336 | (crn << 10) | (rt << 5) | (crm << 1) | isread; 337 } 338 339 static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2, 340 int crn, int crm, int rt, int isread, 341 bool is_16bit) 342 { 343 return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT) 344 | (is_16bit ? 0 : ARM_EL_IL) 345 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) 346 | (crn << 10) | (rt << 5) | (crm << 1) | isread; 347 } 348 349 static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm, 350 int rt, int rt2, int isread, 351 bool is_16bit) 352 { 353 return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT) 354 | (is_16bit ? 0 : ARM_EL_IL) 355 | (cv << 24) | (cond << 20) | (opc1 << 16) 356 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; 357 } 358 359 static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm, 360 int rt, int rt2, int isread, 361 bool is_16bit) 362 { 363 return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT) 364 | (is_16bit ? 0 : ARM_EL_IL) 365 | (cv << 24) | (cond << 20) | (opc1 << 16) 366 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; 367 } 368 369 static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit) 370 { 371 return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) 372 | (is_16bit ? 0 : ARM_EL_IL) 373 | (cv << 24) | (cond << 20); 374 } 375 376 static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc) 377 { 378 return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 379 | ARM_EL_IL | (ea << 9) | (s1ptw << 7) | fsc; 380 } 381 382 static inline uint32_t syn_data_abort_no_iss(int same_el, 383 int ea, int cm, int s1ptw, 384 int wnr, int fsc) 385 { 386 return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 387 | ARM_EL_IL 388 | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc; 389 } 390 391 static inline uint32_t syn_data_abort_with_iss(int same_el, 392 int sas, int sse, int srt, 393 int sf, int ar, 394 int ea, int cm, int s1ptw, 395 int wnr, int fsc, 396 bool is_16bit) 397 { 398 return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 399 | (is_16bit ? 0 : ARM_EL_IL) 400 | ARM_EL_ISV | (sas << 22) | (sse << 21) | (srt << 16) 401 | (sf << 15) | (ar << 14) 402 | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc; 403 } 404 405 static inline uint32_t syn_swstep(int same_el, int isv, int ex) 406 { 407 return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 408 | ARM_EL_IL | (isv << 24) | (ex << 6) | 0x22; 409 } 410 411 static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr) 412 { 413 return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 414 | ARM_EL_IL | (cm << 8) | (wnr << 6) | 0x22; 415 } 416 417 static inline uint32_t syn_breakpoint(int same_el) 418 { 419 return (EC_BREAKPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) 420 | ARM_EL_IL | 0x22; 421 } 422 423 static inline uint32_t syn_wfx(int cv, int cond, int ti) 424 { 425 return (EC_WFX_TRAP << ARM_EL_EC_SHIFT) | 426 (cv << 24) | (cond << 20) | ti; 427 } 428 429 /* Update a QEMU watchpoint based on the information the guest has set in the 430 * DBGWCR<n>_EL1 and DBGWVR<n>_EL1 registers. 431 */ 432 void hw_watchpoint_update(ARMCPU *cpu, int n); 433 /* Update the QEMU watchpoints for every guest watchpoint. This does a 434 * complete delete-and-reinstate of the QEMU watchpoint list and so is 435 * suitable for use after migration or on reset. 436 */ 437 void hw_watchpoint_update_all(ARMCPU *cpu); 438 /* Update a QEMU breakpoint based on the information the guest has set in the 439 * DBGBCR<n>_EL1 and DBGBVR<n>_EL1 registers. 440 */ 441 void hw_breakpoint_update(ARMCPU *cpu, int n); 442 /* Update the QEMU breakpoints for every guest breakpoint. This does a 443 * complete delete-and-reinstate of the QEMU breakpoint list and so is 444 * suitable for use after migration or on reset. 445 */ 446 void hw_breakpoint_update_all(ARMCPU *cpu); 447 448 /* Callback function for checking if a watchpoint should trigger. */ 449 bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); 450 451 /* Adjust addresses (in BE32 mode) before testing against watchpoint 452 * addresses. 453 */ 454 vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len); 455 456 /* Callback function for when a watchpoint or breakpoint triggers. */ 457 void arm_debug_excp_handler(CPUState *cs); 458 459 #ifdef CONFIG_USER_ONLY 460 static inline bool arm_is_psci_call(ARMCPU *cpu, int excp_type) 461 { 462 return false; 463 } 464 #else 465 /* Return true if the r0/x0 value indicates that this SMC/HVC is a PSCI call. */ 466 bool arm_is_psci_call(ARMCPU *cpu, int excp_type); 467 /* Actually handle a PSCI call */ 468 void arm_handle_psci_call(ARMCPU *cpu); 469 #endif 470 471 /** 472 * arm_clear_exclusive: clear the exclusive monitor 473 * @env: CPU env 474 * Clear the CPU's exclusive monitor, like the guest CLREX instruction. 475 */ 476 static inline void arm_clear_exclusive(CPUARMState *env) 477 { 478 env->exclusive_addr = -1; 479 } 480 481 /** 482 * ARMMMUFaultInfo: Information describing an ARM MMU Fault 483 * @s2addr: Address that caused a fault at stage 2 484 * @stage2: True if we faulted at stage 2 485 * @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table walk 486 * @ea: True if we should set the EA (external abort type) bit in syndrome 487 */ 488 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; 489 struct ARMMMUFaultInfo { 490 target_ulong s2addr; 491 bool stage2; 492 bool s1ptw; 493 bool ea; 494 }; 495 496 /* Do a page table walk and add page to TLB if possible */ 497 bool arm_tlb_fill(CPUState *cpu, vaddr address, 498 MMUAccessType access_type, int mmu_idx, 499 uint32_t *fsr, ARMMMUFaultInfo *fi); 500 501 /* Return true if the stage 1 translation regime is using LPAE format page 502 * tables */ 503 bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx); 504 505 /* Raise a data fault alignment exception for the specified virtual address */ 506 void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, 507 MMUAccessType access_type, 508 int mmu_idx, uintptr_t retaddr); 509 510 /* arm_cpu_do_transaction_failed: handle a memory system error response 511 * (eg "no device/memory present at address") by raising an external abort 512 * exception 513 */ 514 void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 515 vaddr addr, unsigned size, 516 MMUAccessType access_type, 517 int mmu_idx, MemTxAttrs attrs, 518 MemTxResult response, uintptr_t retaddr); 519 520 /* Call the EL change hook if one has been registered */ 521 static inline void arm_call_el_change_hook(ARMCPU *cpu) 522 { 523 if (cpu->el_change_hook) { 524 cpu->el_change_hook(cpu, cpu->el_change_hook_opaque); 525 } 526 } 527 528 /* Return true if this address translation regime is secure */ 529 static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) 530 { 531 switch (mmu_idx) { 532 case ARMMMUIdx_S12NSE0: 533 case ARMMMUIdx_S12NSE1: 534 case ARMMMUIdx_S1NSE0: 535 case ARMMMUIdx_S1NSE1: 536 case ARMMMUIdx_S1E2: 537 case ARMMMUIdx_S2NS: 538 case ARMMMUIdx_MPriv: 539 case ARMMMUIdx_MNegPri: 540 case ARMMMUIdx_MUser: 541 return false; 542 case ARMMMUIdx_S1E3: 543 case ARMMMUIdx_S1SE0: 544 case ARMMMUIdx_S1SE1: 545 case ARMMMUIdx_MSPriv: 546 case ARMMMUIdx_MSNegPri: 547 case ARMMMUIdx_MSUser: 548 return true; 549 default: 550 g_assert_not_reached(); 551 } 552 } 553 554 #endif 555