1 /* 2 * QEMU ARM CPU -- internal functions and types 3 * 4 * Copyright (c) 2014 Linaro Ltd 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 * 20 * This header defines functions, types, etc which need to be shared 21 * between different source files within target/arm/ but which are 22 * private to it and not required by the rest of QEMU. 23 */ 24 25 #ifndef TARGET_ARM_INTERNALS_H 26 #define TARGET_ARM_INTERNALS_H 27 28 #include "hw/registerfields.h" 29 #include "tcg/tcg-gvec-desc.h" 30 #include "syndrome.h" 31 32 /* register banks for CPU modes */ 33 #define BANK_USRSYS 0 34 #define BANK_SVC 1 35 #define BANK_ABT 2 36 #define BANK_UND 3 37 #define BANK_IRQ 4 38 #define BANK_FIQ 5 39 #define BANK_HYP 6 40 #define BANK_MON 7 41 42 static inline bool excp_is_internal(int excp) 43 { 44 /* Return true if this exception number represents a QEMU-internal 45 * exception that will not be passed to the guest. 46 */ 47 return excp == EXCP_INTERRUPT 48 || excp == EXCP_HLT 49 || excp == EXCP_DEBUG 50 || excp == EXCP_HALTED 51 || excp == EXCP_EXCEPTION_EXIT 52 || excp == EXCP_KERNEL_TRAP 53 || excp == EXCP_SEMIHOST; 54 } 55 56 /* Scale factor for generic timers, ie number of ns per tick. 57 * This gives a 62.5MHz timer. 58 */ 59 #define GTIMER_SCALE 16 60 61 /* Bit definitions for the v7M CONTROL register */ 62 FIELD(V7M_CONTROL, NPRIV, 0, 1) 63 FIELD(V7M_CONTROL, SPSEL, 1, 1) 64 FIELD(V7M_CONTROL, FPCA, 2, 1) 65 FIELD(V7M_CONTROL, SFPA, 3, 1) 66 67 /* Bit definitions for v7M exception return payload */ 68 FIELD(V7M_EXCRET, ES, 0, 1) 69 FIELD(V7M_EXCRET, RES0, 1, 1) 70 FIELD(V7M_EXCRET, SPSEL, 2, 1) 71 FIELD(V7M_EXCRET, MODE, 3, 1) 72 FIELD(V7M_EXCRET, FTYPE, 4, 1) 73 FIELD(V7M_EXCRET, DCRS, 5, 1) 74 FIELD(V7M_EXCRET, S, 6, 1) 75 FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */ 76 77 /* Minimum value which is a magic number for exception return */ 78 #define EXC_RETURN_MIN_MAGIC 0xff000000 79 /* Minimum number which is a magic number for function or exception return 80 * when using v8M security extension 81 */ 82 #define FNC_RETURN_MIN_MAGIC 0xfefffffe 83 84 /* We use a few fake FSR values for internal purposes in M profile. 85 * M profile cores don't have A/R format FSRs, but currently our 86 * get_phys_addr() code assumes A/R profile and reports failures via 87 * an A/R format FSR value. We then translate that into the proper 88 * M profile exception and FSR status bit in arm_v7m_cpu_do_interrupt(). 89 * Mostly the FSR values we use for this are those defined for v7PMSA, 90 * since we share some of that codepath. A few kinds of fault are 91 * only for M profile and have no A/R equivalent, though, so we have 92 * to pick a value from the reserved range (which we never otherwise 93 * generate) to use for these. 94 * These values will never be visible to the guest. 95 */ 96 #define M_FAKE_FSR_NSC_EXEC 0xf /* NS executing in S&NSC memory */ 97 #define M_FAKE_FSR_SFAULT 0xe /* SecureFault INVTRAN, INVEP or AUVIOL */ 98 99 /** 100 * raise_exception: Raise the specified exception. 101 * Raise a guest exception with the specified value, syndrome register 102 * and target exception level. This should be called from helper functions, 103 * and never returns because we will longjump back up to the CPU main loop. 104 */ 105 void QEMU_NORETURN raise_exception(CPUARMState *env, uint32_t excp, 106 uint32_t syndrome, uint32_t target_el); 107 108 /* 109 * Similarly, but also use unwinding to restore cpu state. 110 */ 111 void QEMU_NORETURN raise_exception_ra(CPUARMState *env, uint32_t excp, 112 uint32_t syndrome, uint32_t target_el, 113 uintptr_t ra); 114 115 /* 116 * For AArch64, map a given EL to an index in the banked_spsr array. 117 * Note that this mapping and the AArch32 mapping defined in bank_number() 118 * must agree such that the AArch64<->AArch32 SPSRs have the architecturally 119 * mandated mapping between each other. 120 */ 121 static inline unsigned int aarch64_banked_spsr_index(unsigned int el) 122 { 123 static const unsigned int map[4] = { 124 [1] = BANK_SVC, /* EL1. */ 125 [2] = BANK_HYP, /* EL2. */ 126 [3] = BANK_MON, /* EL3. */ 127 }; 128 assert(el >= 1 && el <= 3); 129 return map[el]; 130 } 131 132 /* Map CPU modes onto saved register banks. */ 133 static inline int bank_number(int mode) 134 { 135 switch (mode) { 136 case ARM_CPU_MODE_USR: 137 case ARM_CPU_MODE_SYS: 138 return BANK_USRSYS; 139 case ARM_CPU_MODE_SVC: 140 return BANK_SVC; 141 case ARM_CPU_MODE_ABT: 142 return BANK_ABT; 143 case ARM_CPU_MODE_UND: 144 return BANK_UND; 145 case ARM_CPU_MODE_IRQ: 146 return BANK_IRQ; 147 case ARM_CPU_MODE_FIQ: 148 return BANK_FIQ; 149 case ARM_CPU_MODE_HYP: 150 return BANK_HYP; 151 case ARM_CPU_MODE_MON: 152 return BANK_MON; 153 } 154 g_assert_not_reached(); 155 } 156 157 /** 158 * r14_bank_number: Map CPU mode onto register bank for r14 159 * 160 * Given an AArch32 CPU mode, return the index into the saved register 161 * banks to use for the R14 (LR) in that mode. This is the same as 162 * bank_number(), except for the special case of Hyp mode, where 163 * R14 is shared with USR and SYS, unlike its R13 and SPSR. 164 * This should be used as the index into env->banked_r14[], and 165 * bank_number() used for the index into env->banked_r13[] and 166 * env->banked_spsr[]. 167 */ 168 static inline int r14_bank_number(int mode) 169 { 170 return (mode == ARM_CPU_MODE_HYP) ? BANK_USRSYS : bank_number(mode); 171 } 172 173 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu); 174 void arm_translate_init(void); 175 176 #ifdef CONFIG_TCG 177 void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb); 178 #endif /* CONFIG_TCG */ 179 180 /** 181 * aarch64_sve_zcr_get_valid_len: 182 * @cpu: cpu context 183 * @start_len: maximum len to consider 184 * 185 * Return the maximum supported sve vector length <= @start_len. 186 * Note that both @start_len and the return value are in units 187 * of ZCR_ELx.LEN, so the vector bit length is (x + 1) * 128. 188 */ 189 uint32_t aarch64_sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len); 190 191 enum arm_fprounding { 192 FPROUNDING_TIEEVEN, 193 FPROUNDING_POSINF, 194 FPROUNDING_NEGINF, 195 FPROUNDING_ZERO, 196 FPROUNDING_TIEAWAY, 197 FPROUNDING_ODD 198 }; 199 200 int arm_rmode_to_sf(int rmode); 201 202 static inline void aarch64_save_sp(CPUARMState *env, int el) 203 { 204 if (env->pstate & PSTATE_SP) { 205 env->sp_el[el] = env->xregs[31]; 206 } else { 207 env->sp_el[0] = env->xregs[31]; 208 } 209 } 210 211 static inline void aarch64_restore_sp(CPUARMState *env, int el) 212 { 213 if (env->pstate & PSTATE_SP) { 214 env->xregs[31] = env->sp_el[el]; 215 } else { 216 env->xregs[31] = env->sp_el[0]; 217 } 218 } 219 220 static inline void update_spsel(CPUARMState *env, uint32_t imm) 221 { 222 unsigned int cur_el = arm_current_el(env); 223 /* Update PSTATE SPSel bit; this requires us to update the 224 * working stack pointer in xregs[31]. 225 */ 226 if (!((imm ^ env->pstate) & PSTATE_SP)) { 227 return; 228 } 229 aarch64_save_sp(env, cur_el); 230 env->pstate = deposit32(env->pstate, 0, 1, imm); 231 232 /* We rely on illegal updates to SPsel from EL0 to get trapped 233 * at translation time. 234 */ 235 assert(cur_el >= 1 && cur_el <= 3); 236 aarch64_restore_sp(env, cur_el); 237 } 238 239 /* 240 * arm_pamax 241 * @cpu: ARMCPU 242 * 243 * Returns the implementation defined bit-width of physical addresses. 244 * The ARMv8 reference manuals refer to this as PAMax(). 245 */ 246 unsigned int arm_pamax(ARMCPU *cpu); 247 248 /* Return true if extended addresses are enabled. 249 * This is always the case if our translation regime is 64 bit, 250 * but depends on TTBCR.EAE for 32 bit. 251 */ 252 static inline bool extended_addresses_enabled(CPUARMState *env) 253 { 254 TCR *tcr = &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1]; 255 return arm_el_is_aa64(env, 1) || 256 (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE)); 257 } 258 259 /* Update a QEMU watchpoint based on the information the guest has set in the 260 * DBGWCR<n>_EL1 and DBGWVR<n>_EL1 registers. 261 */ 262 void hw_watchpoint_update(ARMCPU *cpu, int n); 263 /* Update the QEMU watchpoints for every guest watchpoint. This does a 264 * complete delete-and-reinstate of the QEMU watchpoint list and so is 265 * suitable for use after migration or on reset. 266 */ 267 void hw_watchpoint_update_all(ARMCPU *cpu); 268 /* Update a QEMU breakpoint based on the information the guest has set in the 269 * DBGBCR<n>_EL1 and DBGBVR<n>_EL1 registers. 270 */ 271 void hw_breakpoint_update(ARMCPU *cpu, int n); 272 /* Update the QEMU breakpoints for every guest breakpoint. This does a 273 * complete delete-and-reinstate of the QEMU breakpoint list and so is 274 * suitable for use after migration or on reset. 275 */ 276 void hw_breakpoint_update_all(ARMCPU *cpu); 277 278 /* Callback function for checking if a breakpoint should trigger. */ 279 bool arm_debug_check_breakpoint(CPUState *cs); 280 281 /* Callback function for checking if a watchpoint should trigger. */ 282 bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); 283 284 /* Adjust addresses (in BE32 mode) before testing against watchpoint 285 * addresses. 286 */ 287 vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len); 288 289 /* Callback function for when a watchpoint or breakpoint triggers. */ 290 void arm_debug_excp_handler(CPUState *cs); 291 292 #if defined(CONFIG_USER_ONLY) || !defined(CONFIG_TCG) 293 static inline bool arm_is_psci_call(ARMCPU *cpu, int excp_type) 294 { 295 return false; 296 } 297 static inline void arm_handle_psci_call(ARMCPU *cpu) 298 { 299 g_assert_not_reached(); 300 } 301 #else 302 /* Return true if the r0/x0 value indicates that this SMC/HVC is a PSCI call. */ 303 bool arm_is_psci_call(ARMCPU *cpu, int excp_type); 304 /* Actually handle a PSCI call */ 305 void arm_handle_psci_call(ARMCPU *cpu); 306 #endif 307 308 /** 309 * arm_clear_exclusive: clear the exclusive monitor 310 * @env: CPU env 311 * Clear the CPU's exclusive monitor, like the guest CLREX instruction. 312 */ 313 static inline void arm_clear_exclusive(CPUARMState *env) 314 { 315 env->exclusive_addr = -1; 316 } 317 318 /** 319 * ARMFaultType: type of an ARM MMU fault 320 * This corresponds to the v8A pseudocode's Fault enumeration, 321 * with extensions for QEMU internal conditions. 322 */ 323 typedef enum ARMFaultType { 324 ARMFault_None, 325 ARMFault_AccessFlag, 326 ARMFault_Alignment, 327 ARMFault_Background, 328 ARMFault_Domain, 329 ARMFault_Permission, 330 ARMFault_Translation, 331 ARMFault_AddressSize, 332 ARMFault_SyncExternal, 333 ARMFault_SyncExternalOnWalk, 334 ARMFault_SyncParity, 335 ARMFault_SyncParityOnWalk, 336 ARMFault_AsyncParity, 337 ARMFault_AsyncExternal, 338 ARMFault_Debug, 339 ARMFault_TLBConflict, 340 ARMFault_Lockdown, 341 ARMFault_Exclusive, 342 ARMFault_ICacheMaint, 343 ARMFault_QEMU_NSCExec, /* v8M: NS executing in S&NSC memory */ 344 ARMFault_QEMU_SFault, /* v8M: SecureFault INVTRAN, INVEP or AUVIOL */ 345 } ARMFaultType; 346 347 /** 348 * ARMMMUFaultInfo: Information describing an ARM MMU Fault 349 * @type: Type of fault 350 * @level: Table walk level (for translation, access flag and permission faults) 351 * @domain: Domain of the fault address (for non-LPAE CPUs only) 352 * @s2addr: Address that caused a fault at stage 2 353 * @stage2: True if we faulted at stage 2 354 * @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table walk 355 * @s1ns: True if we faulted on a non-secure IPA while in secure state 356 * @ea: True if we should set the EA (external abort type) bit in syndrome 357 */ 358 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; 359 struct ARMMMUFaultInfo { 360 ARMFaultType type; 361 target_ulong s2addr; 362 int level; 363 int domain; 364 bool stage2; 365 bool s1ptw; 366 bool s1ns; 367 bool ea; 368 }; 369 370 /** 371 * arm_fi_to_sfsc: Convert fault info struct to short-format FSC 372 * Compare pseudocode EncodeSDFSC(), though unlike that function 373 * we set up a whole FSR-format code including domain field and 374 * putting the high bit of the FSC into bit 10. 375 */ 376 static inline uint32_t arm_fi_to_sfsc(ARMMMUFaultInfo *fi) 377 { 378 uint32_t fsc; 379 380 switch (fi->type) { 381 case ARMFault_None: 382 return 0; 383 case ARMFault_AccessFlag: 384 fsc = fi->level == 1 ? 0x3 : 0x6; 385 break; 386 case ARMFault_Alignment: 387 fsc = 0x1; 388 break; 389 case ARMFault_Permission: 390 fsc = fi->level == 1 ? 0xd : 0xf; 391 break; 392 case ARMFault_Domain: 393 fsc = fi->level == 1 ? 0x9 : 0xb; 394 break; 395 case ARMFault_Translation: 396 fsc = fi->level == 1 ? 0x5 : 0x7; 397 break; 398 case ARMFault_SyncExternal: 399 fsc = 0x8 | (fi->ea << 12); 400 break; 401 case ARMFault_SyncExternalOnWalk: 402 fsc = fi->level == 1 ? 0xc : 0xe; 403 fsc |= (fi->ea << 12); 404 break; 405 case ARMFault_SyncParity: 406 fsc = 0x409; 407 break; 408 case ARMFault_SyncParityOnWalk: 409 fsc = fi->level == 1 ? 0x40c : 0x40e; 410 break; 411 case ARMFault_AsyncParity: 412 fsc = 0x408; 413 break; 414 case ARMFault_AsyncExternal: 415 fsc = 0x406 | (fi->ea << 12); 416 break; 417 case ARMFault_Debug: 418 fsc = 0x2; 419 break; 420 case ARMFault_TLBConflict: 421 fsc = 0x400; 422 break; 423 case ARMFault_Lockdown: 424 fsc = 0x404; 425 break; 426 case ARMFault_Exclusive: 427 fsc = 0x405; 428 break; 429 case ARMFault_ICacheMaint: 430 fsc = 0x4; 431 break; 432 case ARMFault_Background: 433 fsc = 0x0; 434 break; 435 case ARMFault_QEMU_NSCExec: 436 fsc = M_FAKE_FSR_NSC_EXEC; 437 break; 438 case ARMFault_QEMU_SFault: 439 fsc = M_FAKE_FSR_SFAULT; 440 break; 441 default: 442 /* Other faults can't occur in a context that requires a 443 * short-format status code. 444 */ 445 g_assert_not_reached(); 446 } 447 448 fsc |= (fi->domain << 4); 449 return fsc; 450 } 451 452 /** 453 * arm_fi_to_lfsc: Convert fault info struct to long-format FSC 454 * Compare pseudocode EncodeLDFSC(), though unlike that function 455 * we fill in also the LPAE bit 9 of a DFSR format. 456 */ 457 static inline uint32_t arm_fi_to_lfsc(ARMMMUFaultInfo *fi) 458 { 459 uint32_t fsc; 460 461 switch (fi->type) { 462 case ARMFault_None: 463 return 0; 464 case ARMFault_AddressSize: 465 fsc = fi->level & 3; 466 break; 467 case ARMFault_AccessFlag: 468 fsc = (fi->level & 3) | (0x2 << 2); 469 break; 470 case ARMFault_Permission: 471 fsc = (fi->level & 3) | (0x3 << 2); 472 break; 473 case ARMFault_Translation: 474 fsc = (fi->level & 3) | (0x1 << 2); 475 break; 476 case ARMFault_SyncExternal: 477 fsc = 0x10 | (fi->ea << 12); 478 break; 479 case ARMFault_SyncExternalOnWalk: 480 fsc = (fi->level & 3) | (0x5 << 2) | (fi->ea << 12); 481 break; 482 case ARMFault_SyncParity: 483 fsc = 0x18; 484 break; 485 case ARMFault_SyncParityOnWalk: 486 fsc = (fi->level & 3) | (0x7 << 2); 487 break; 488 case ARMFault_AsyncParity: 489 fsc = 0x19; 490 break; 491 case ARMFault_AsyncExternal: 492 fsc = 0x11 | (fi->ea << 12); 493 break; 494 case ARMFault_Alignment: 495 fsc = 0x21; 496 break; 497 case ARMFault_Debug: 498 fsc = 0x22; 499 break; 500 case ARMFault_TLBConflict: 501 fsc = 0x30; 502 break; 503 case ARMFault_Lockdown: 504 fsc = 0x34; 505 break; 506 case ARMFault_Exclusive: 507 fsc = 0x35; 508 break; 509 default: 510 /* Other faults can't occur in a context that requires a 511 * long-format status code. 512 */ 513 g_assert_not_reached(); 514 } 515 516 fsc |= 1 << 9; 517 return fsc; 518 } 519 520 static inline bool arm_extabort_type(MemTxResult result) 521 { 522 /* The EA bit in syndromes and fault status registers is an 523 * IMPDEF classification of external aborts. ARM implementations 524 * usually use this to indicate AXI bus Decode error (0) or 525 * Slave error (1); in QEMU we follow that. 526 */ 527 return result != MEMTX_DECODE_ERROR; 528 } 529 530 #ifdef CONFIG_USER_ONLY 531 void arm_cpu_record_sigsegv(CPUState *cpu, vaddr addr, 532 MMUAccessType access_type, 533 bool maperr, uintptr_t ra); 534 void arm_cpu_record_sigbus(CPUState *cpu, vaddr addr, 535 MMUAccessType access_type, uintptr_t ra); 536 #else 537 bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 538 MMUAccessType access_type, int mmu_idx, 539 bool probe, uintptr_t retaddr); 540 #endif 541 542 static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) 543 { 544 return mmu_idx & ARM_MMU_IDX_COREIDX_MASK; 545 } 546 547 static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx) 548 { 549 if (arm_feature(env, ARM_FEATURE_M)) { 550 return mmu_idx | ARM_MMU_IDX_M; 551 } else { 552 return mmu_idx | ARM_MMU_IDX_A; 553 } 554 } 555 556 static inline ARMMMUIdx core_to_aa64_mmu_idx(int mmu_idx) 557 { 558 /* AArch64 is always a-profile. */ 559 return mmu_idx | ARM_MMU_IDX_A; 560 } 561 562 int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx); 563 564 /* 565 * Return the MMU index for a v7M CPU with all relevant information 566 * manually specified. 567 */ 568 ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, 569 bool secstate, bool priv, bool negpri); 570 571 /* 572 * Return the MMU index for a v7M CPU in the specified security and 573 * privilege state. 574 */ 575 ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, 576 bool secstate, bool priv); 577 578 /* Return the MMU index for a v7M CPU in the specified security state */ 579 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); 580 581 /* Return true if the stage 1 translation regime is using LPAE format page 582 * tables */ 583 bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx); 584 585 /* Raise a data fault alignment exception for the specified virtual address */ 586 void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, 587 MMUAccessType access_type, 588 int mmu_idx, uintptr_t retaddr) QEMU_NORETURN; 589 590 /* arm_cpu_do_transaction_failed: handle a memory system error response 591 * (eg "no device/memory present at address") by raising an external abort 592 * exception 593 */ 594 void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 595 vaddr addr, unsigned size, 596 MMUAccessType access_type, 597 int mmu_idx, MemTxAttrs attrs, 598 MemTxResult response, uintptr_t retaddr); 599 600 /* Call any registered EL change hooks */ 601 static inline void arm_call_pre_el_change_hook(ARMCPU *cpu) 602 { 603 ARMELChangeHook *hook, *next; 604 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 605 hook->hook(cpu, hook->opaque); 606 } 607 } 608 static inline void arm_call_el_change_hook(ARMCPU *cpu) 609 { 610 ARMELChangeHook *hook, *next; 611 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 612 hook->hook(cpu, hook->opaque); 613 } 614 } 615 616 /* Return true if this address translation regime has two ranges. */ 617 static inline bool regime_has_2_ranges(ARMMMUIdx mmu_idx) 618 { 619 switch (mmu_idx) { 620 case ARMMMUIdx_Stage1_E0: 621 case ARMMMUIdx_Stage1_E1: 622 case ARMMMUIdx_Stage1_E1_PAN: 623 case ARMMMUIdx_Stage1_SE0: 624 case ARMMMUIdx_Stage1_SE1: 625 case ARMMMUIdx_Stage1_SE1_PAN: 626 case ARMMMUIdx_E10_0: 627 case ARMMMUIdx_E10_1: 628 case ARMMMUIdx_E10_1_PAN: 629 case ARMMMUIdx_E20_0: 630 case ARMMMUIdx_E20_2: 631 case ARMMMUIdx_E20_2_PAN: 632 case ARMMMUIdx_SE10_0: 633 case ARMMMUIdx_SE10_1: 634 case ARMMMUIdx_SE10_1_PAN: 635 case ARMMMUIdx_SE20_0: 636 case ARMMMUIdx_SE20_2: 637 case ARMMMUIdx_SE20_2_PAN: 638 return true; 639 default: 640 return false; 641 } 642 } 643 644 /* Return true if this address translation regime is secure */ 645 static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) 646 { 647 switch (mmu_idx) { 648 case ARMMMUIdx_E10_0: 649 case ARMMMUIdx_E10_1: 650 case ARMMMUIdx_E10_1_PAN: 651 case ARMMMUIdx_E20_0: 652 case ARMMMUIdx_E20_2: 653 case ARMMMUIdx_E20_2_PAN: 654 case ARMMMUIdx_Stage1_E0: 655 case ARMMMUIdx_Stage1_E1: 656 case ARMMMUIdx_Stage1_E1_PAN: 657 case ARMMMUIdx_E2: 658 case ARMMMUIdx_Stage2: 659 case ARMMMUIdx_MPrivNegPri: 660 case ARMMMUIdx_MUserNegPri: 661 case ARMMMUIdx_MPriv: 662 case ARMMMUIdx_MUser: 663 return false; 664 case ARMMMUIdx_SE3: 665 case ARMMMUIdx_SE10_0: 666 case ARMMMUIdx_SE10_1: 667 case ARMMMUIdx_SE10_1_PAN: 668 case ARMMMUIdx_SE20_0: 669 case ARMMMUIdx_SE20_2: 670 case ARMMMUIdx_SE20_2_PAN: 671 case ARMMMUIdx_Stage1_SE0: 672 case ARMMMUIdx_Stage1_SE1: 673 case ARMMMUIdx_Stage1_SE1_PAN: 674 case ARMMMUIdx_SE2: 675 case ARMMMUIdx_Stage2_S: 676 case ARMMMUIdx_MSPrivNegPri: 677 case ARMMMUIdx_MSUserNegPri: 678 case ARMMMUIdx_MSPriv: 679 case ARMMMUIdx_MSUser: 680 return true; 681 default: 682 g_assert_not_reached(); 683 } 684 } 685 686 static inline bool regime_is_pan(CPUARMState *env, ARMMMUIdx mmu_idx) 687 { 688 switch (mmu_idx) { 689 case ARMMMUIdx_Stage1_E1_PAN: 690 case ARMMMUIdx_Stage1_SE1_PAN: 691 case ARMMMUIdx_E10_1_PAN: 692 case ARMMMUIdx_E20_2_PAN: 693 case ARMMMUIdx_SE10_1_PAN: 694 case ARMMMUIdx_SE20_2_PAN: 695 return true; 696 default: 697 return false; 698 } 699 } 700 701 /* Return the exception level which controls this address translation regime */ 702 static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) 703 { 704 switch (mmu_idx) { 705 case ARMMMUIdx_SE20_0: 706 case ARMMMUIdx_SE20_2: 707 case ARMMMUIdx_SE20_2_PAN: 708 case ARMMMUIdx_E20_0: 709 case ARMMMUIdx_E20_2: 710 case ARMMMUIdx_E20_2_PAN: 711 case ARMMMUIdx_Stage2: 712 case ARMMMUIdx_Stage2_S: 713 case ARMMMUIdx_SE2: 714 case ARMMMUIdx_E2: 715 return 2; 716 case ARMMMUIdx_SE3: 717 return 3; 718 case ARMMMUIdx_SE10_0: 719 case ARMMMUIdx_Stage1_SE0: 720 return arm_el_is_aa64(env, 3) ? 1 : 3; 721 case ARMMMUIdx_SE10_1: 722 case ARMMMUIdx_SE10_1_PAN: 723 case ARMMMUIdx_Stage1_E0: 724 case ARMMMUIdx_Stage1_E1: 725 case ARMMMUIdx_Stage1_E1_PAN: 726 case ARMMMUIdx_Stage1_SE1: 727 case ARMMMUIdx_Stage1_SE1_PAN: 728 case ARMMMUIdx_E10_0: 729 case ARMMMUIdx_E10_1: 730 case ARMMMUIdx_E10_1_PAN: 731 case ARMMMUIdx_MPrivNegPri: 732 case ARMMMUIdx_MUserNegPri: 733 case ARMMMUIdx_MPriv: 734 case ARMMMUIdx_MUser: 735 case ARMMMUIdx_MSPrivNegPri: 736 case ARMMMUIdx_MSUserNegPri: 737 case ARMMMUIdx_MSPriv: 738 case ARMMMUIdx_MSUser: 739 return 1; 740 default: 741 g_assert_not_reached(); 742 } 743 } 744 745 /* Return the TCR controlling this translation regime */ 746 static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) 747 { 748 if (mmu_idx == ARMMMUIdx_Stage2) { 749 return &env->cp15.vtcr_el2; 750 } 751 if (mmu_idx == ARMMMUIdx_Stage2_S) { 752 /* 753 * Note: Secure stage 2 nominally shares fields from VTCR_EL2, but 754 * those are not currently used by QEMU, so just return VSTCR_EL2. 755 */ 756 return &env->cp15.vstcr_el2; 757 } 758 return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; 759 } 760 761 /* Return the FSR value for a debug exception (watchpoint, hardware 762 * breakpoint or BKPT insn) targeting the specified exception level. 763 */ 764 static inline uint32_t arm_debug_exception_fsr(CPUARMState *env) 765 { 766 ARMMMUFaultInfo fi = { .type = ARMFault_Debug }; 767 int target_el = arm_debug_target_el(env); 768 bool using_lpae = false; 769 770 if (target_el == 2 || arm_el_is_aa64(env, target_el)) { 771 using_lpae = true; 772 } else { 773 if (arm_feature(env, ARM_FEATURE_LPAE) && 774 (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) { 775 using_lpae = true; 776 } 777 } 778 779 if (using_lpae) { 780 return arm_fi_to_lfsc(&fi); 781 } else { 782 return arm_fi_to_sfsc(&fi); 783 } 784 } 785 786 /** 787 * arm_num_brps: Return number of implemented breakpoints. 788 * Note that the ID register BRPS field is "number of bps - 1", 789 * and we return the actual number of breakpoints. 790 */ 791 static inline int arm_num_brps(ARMCPU *cpu) 792 { 793 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 794 return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, BRPS) + 1; 795 } else { 796 return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, BRPS) + 1; 797 } 798 } 799 800 /** 801 * arm_num_wrps: Return number of implemented watchpoints. 802 * Note that the ID register WRPS field is "number of wps - 1", 803 * and we return the actual number of watchpoints. 804 */ 805 static inline int arm_num_wrps(ARMCPU *cpu) 806 { 807 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 808 return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, WRPS) + 1; 809 } else { 810 return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, WRPS) + 1; 811 } 812 } 813 814 /** 815 * arm_num_ctx_cmps: Return number of implemented context comparators. 816 * Note that the ID register CTX_CMPS field is "number of cmps - 1", 817 * and we return the actual number of comparators. 818 */ 819 static inline int arm_num_ctx_cmps(ARMCPU *cpu) 820 { 821 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 822 return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS) + 1; 823 } else { 824 return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, CTX_CMPS) + 1; 825 } 826 } 827 828 /** 829 * v7m_using_psp: Return true if using process stack pointer 830 * Return true if the CPU is currently using the process stack 831 * pointer, or false if it is using the main stack pointer. 832 */ 833 static inline bool v7m_using_psp(CPUARMState *env) 834 { 835 /* Handler mode always uses the main stack; for thread mode 836 * the CONTROL.SPSEL bit determines the answer. 837 * Note that in v7M it is not possible to be in Handler mode with 838 * CONTROL.SPSEL non-zero, but in v8M it is, so we must check both. 839 */ 840 return !arm_v7m_is_handler_mode(env) && 841 env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK; 842 } 843 844 /** 845 * v7m_sp_limit: Return SP limit for current CPU state 846 * Return the SP limit value for the current CPU security state 847 * and stack pointer. 848 */ 849 static inline uint32_t v7m_sp_limit(CPUARMState *env) 850 { 851 if (v7m_using_psp(env)) { 852 return env->v7m.psplim[env->v7m.secure]; 853 } else { 854 return env->v7m.msplim[env->v7m.secure]; 855 } 856 } 857 858 /** 859 * v7m_cpacr_pass: 860 * Return true if the v7M CPACR permits access to the FPU for the specified 861 * security state and privilege level. 862 */ 863 static inline bool v7m_cpacr_pass(CPUARMState *env, 864 bool is_secure, bool is_priv) 865 { 866 switch (extract32(env->v7m.cpacr[is_secure], 20, 2)) { 867 case 0: 868 case 2: /* UNPREDICTABLE: we treat like 0 */ 869 return false; 870 case 1: 871 return is_priv; 872 case 3: 873 return true; 874 default: 875 g_assert_not_reached(); 876 } 877 } 878 879 /** 880 * aarch32_mode_name(): Return name of the AArch32 CPU mode 881 * @psr: Program Status Register indicating CPU mode 882 * 883 * Returns, for debug logging purposes, a printable representation 884 * of the AArch32 CPU mode ("svc", "usr", etc) as indicated by 885 * the low bits of the specified PSR. 886 */ 887 static inline const char *aarch32_mode_name(uint32_t psr) 888 { 889 static const char cpu_mode_names[16][4] = { 890 "usr", "fiq", "irq", "svc", "???", "???", "mon", "abt", 891 "???", "???", "hyp", "und", "???", "???", "???", "sys" 892 }; 893 894 return cpu_mode_names[psr & 0xf]; 895 } 896 897 /** 898 * arm_cpu_update_virq: Update CPU_INTERRUPT_VIRQ bit in cs->interrupt_request 899 * 900 * Update the CPU_INTERRUPT_VIRQ bit in cs->interrupt_request, following 901 * a change to either the input VIRQ line from the GIC or the HCR_EL2.VI bit. 902 * Must be called with the iothread lock held. 903 */ 904 void arm_cpu_update_virq(ARMCPU *cpu); 905 906 /** 907 * arm_cpu_update_vfiq: Update CPU_INTERRUPT_VFIQ bit in cs->interrupt_request 908 * 909 * Update the CPU_INTERRUPT_VFIQ bit in cs->interrupt_request, following 910 * a change to either the input VFIQ line from the GIC or the HCR_EL2.VF bit. 911 * Must be called with the iothread lock held. 912 */ 913 void arm_cpu_update_vfiq(ARMCPU *cpu); 914 915 /** 916 * arm_mmu_idx_el: 917 * @env: The cpu environment 918 * @el: The EL to use. 919 * 920 * Return the full ARMMMUIdx for the translation regime for EL. 921 */ 922 ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el); 923 924 /** 925 * arm_mmu_idx: 926 * @env: The cpu environment 927 * 928 * Return the full ARMMMUIdx for the current translation regime. 929 */ 930 ARMMMUIdx arm_mmu_idx(CPUARMState *env); 931 932 /** 933 * arm_stage1_mmu_idx: 934 * @env: The cpu environment 935 * 936 * Return the ARMMMUIdx for the stage1 traversal for the current regime. 937 */ 938 #ifdef CONFIG_USER_ONLY 939 static inline ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) 940 { 941 return ARMMMUIdx_Stage1_E0; 942 } 943 #else 944 ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env); 945 #endif 946 947 /** 948 * arm_mmu_idx_is_stage1_of_2: 949 * @mmu_idx: The ARMMMUIdx to test 950 * 951 * Return true if @mmu_idx is a NOTLB mmu_idx that is the 952 * first stage of a two stage regime. 953 */ 954 static inline bool arm_mmu_idx_is_stage1_of_2(ARMMMUIdx mmu_idx) 955 { 956 switch (mmu_idx) { 957 case ARMMMUIdx_Stage1_E0: 958 case ARMMMUIdx_Stage1_E1: 959 case ARMMMUIdx_Stage1_E1_PAN: 960 case ARMMMUIdx_Stage1_SE0: 961 case ARMMMUIdx_Stage1_SE1: 962 case ARMMMUIdx_Stage1_SE1_PAN: 963 return true; 964 default: 965 return false; 966 } 967 } 968 969 static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features, 970 const ARMISARegisters *id) 971 { 972 uint32_t valid = CPSR_M | CPSR_AIF | CPSR_IL | CPSR_NZCV; 973 974 if ((features >> ARM_FEATURE_V4T) & 1) { 975 valid |= CPSR_T; 976 } 977 if ((features >> ARM_FEATURE_V5) & 1) { 978 valid |= CPSR_Q; /* V5TE in reality*/ 979 } 980 if ((features >> ARM_FEATURE_V6) & 1) { 981 valid |= CPSR_E | CPSR_GE; 982 } 983 if ((features >> ARM_FEATURE_THUMB2) & 1) { 984 valid |= CPSR_IT; 985 } 986 if (isar_feature_aa32_jazelle(id)) { 987 valid |= CPSR_J; 988 } 989 if (isar_feature_aa32_pan(id)) { 990 valid |= CPSR_PAN; 991 } 992 if (isar_feature_aa32_dit(id)) { 993 valid |= CPSR_DIT; 994 } 995 if (isar_feature_aa32_ssbs(id)) { 996 valid |= CPSR_SSBS; 997 } 998 999 return valid; 1000 } 1001 1002 static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id) 1003 { 1004 uint32_t valid; 1005 1006 valid = PSTATE_M | PSTATE_DAIF | PSTATE_IL | PSTATE_SS | PSTATE_NZCV; 1007 if (isar_feature_aa64_bti(id)) { 1008 valid |= PSTATE_BTYPE; 1009 } 1010 if (isar_feature_aa64_pan(id)) { 1011 valid |= PSTATE_PAN; 1012 } 1013 if (isar_feature_aa64_uao(id)) { 1014 valid |= PSTATE_UAO; 1015 } 1016 if (isar_feature_aa64_dit(id)) { 1017 valid |= PSTATE_DIT; 1018 } 1019 if (isar_feature_aa64_ssbs(id)) { 1020 valid |= PSTATE_SSBS; 1021 } 1022 if (isar_feature_aa64_mte(id)) { 1023 valid |= PSTATE_TCO; 1024 } 1025 1026 return valid; 1027 } 1028 1029 /* 1030 * Parameters of a given virtual address, as extracted from the 1031 * translation control register (TCR) for a given regime. 1032 */ 1033 typedef struct ARMVAParameters { 1034 unsigned tsz : 8; 1035 unsigned ps : 3; 1036 unsigned select : 1; 1037 bool tbi : 1; 1038 bool epd : 1; 1039 bool hpd : 1; 1040 bool using16k : 1; 1041 bool using64k : 1; 1042 bool tsz_oob : 1; /* tsz has been clamped to legal range */ 1043 } ARMVAParameters; 1044 1045 ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, 1046 ARMMMUIdx mmu_idx, bool data); 1047 1048 static inline int exception_target_el(CPUARMState *env) 1049 { 1050 int target_el = MAX(1, arm_current_el(env)); 1051 1052 /* 1053 * No such thing as secure EL1 if EL3 is aarch32, 1054 * so update the target EL to EL3 in this case. 1055 */ 1056 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el == 1) { 1057 target_el = 3; 1058 } 1059 1060 return target_el; 1061 } 1062 1063 /* Determine if allocation tags are available. */ 1064 static inline bool allocation_tag_access_enabled(CPUARMState *env, int el, 1065 uint64_t sctlr) 1066 { 1067 if (el < 3 1068 && arm_feature(env, ARM_FEATURE_EL3) 1069 && !(env->cp15.scr_el3 & SCR_ATA)) { 1070 return false; 1071 } 1072 if (el < 2 && arm_feature(env, ARM_FEATURE_EL2)) { 1073 uint64_t hcr = arm_hcr_el2_eff(env); 1074 if (!(hcr & HCR_ATA) && (!(hcr & HCR_E2H) || !(hcr & HCR_TGE))) { 1075 return false; 1076 } 1077 } 1078 sctlr &= (el == 0 ? SCTLR_ATA0 : SCTLR_ATA); 1079 return sctlr != 0; 1080 } 1081 1082 #ifndef CONFIG_USER_ONLY 1083 1084 /* Security attributes for an address, as returned by v8m_security_lookup. */ 1085 typedef struct V8M_SAttributes { 1086 bool subpage; /* true if these attrs don't cover the whole TARGET_PAGE */ 1087 bool ns; 1088 bool nsc; 1089 uint8_t sregion; 1090 bool srvalid; 1091 uint8_t iregion; 1092 bool irvalid; 1093 } V8M_SAttributes; 1094 1095 void v8m_security_lookup(CPUARMState *env, uint32_t address, 1096 MMUAccessType access_type, ARMMMUIdx mmu_idx, 1097 V8M_SAttributes *sattrs); 1098 1099 bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, 1100 MMUAccessType access_type, ARMMMUIdx mmu_idx, 1101 hwaddr *phys_ptr, MemTxAttrs *txattrs, 1102 int *prot, bool *is_subpage, 1103 ARMMMUFaultInfo *fi, uint32_t *mregion); 1104 1105 /* Cacheability and shareability attributes for a memory access */ 1106 typedef struct ARMCacheAttrs { 1107 unsigned int attrs:8; /* as in the MAIR register encoding */ 1108 unsigned int shareability:2; /* as in the SH field of the VMSAv8-64 PTEs */ 1109 } ARMCacheAttrs; 1110 1111 bool get_phys_addr(CPUARMState *env, target_ulong address, 1112 MMUAccessType access_type, ARMMMUIdx mmu_idx, 1113 hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, 1114 target_ulong *page_size, 1115 ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) 1116 __attribute__((nonnull)); 1117 1118 void arm_log_exception(CPUState *cs); 1119 1120 #endif /* !CONFIG_USER_ONLY */ 1121 1122 /* 1123 * The log2 of the words in the tag block, for GMID_EL1.BS. 1124 * The is the maximum, 256 bytes, which manipulates 64-bits of tags. 1125 */ 1126 #define GMID_EL1_BS 6 1127 1128 /* We associate one allocation tag per 16 bytes, the minimum. */ 1129 #define LOG2_TAG_GRANULE 4 1130 #define TAG_GRANULE (1 << LOG2_TAG_GRANULE) 1131 1132 /* 1133 * SVE predicates are 1/8 the size of SVE vectors, and cannot use 1134 * the same simd_desc() encoding due to restrictions on size. 1135 * Use these instead. 1136 */ 1137 FIELD(PREDDESC, OPRSZ, 0, 6) 1138 FIELD(PREDDESC, ESZ, 6, 2) 1139 FIELD(PREDDESC, DATA, 8, 24) 1140 1141 /* 1142 * The SVE simd_data field, for memory ops, contains either 1143 * rd (5 bits) or a shift count (2 bits). 1144 */ 1145 #define SVE_MTEDESC_SHIFT 5 1146 1147 /* Bits within a descriptor passed to the helper_mte_check* functions. */ 1148 FIELD(MTEDESC, MIDX, 0, 4) 1149 FIELD(MTEDESC, TBI, 4, 2) 1150 FIELD(MTEDESC, TCMA, 6, 2) 1151 FIELD(MTEDESC, WRITE, 8, 1) 1152 FIELD(MTEDESC, SIZEM1, 9, SIMD_DATA_BITS - 9) /* size - 1 */ 1153 1154 bool mte_probe(CPUARMState *env, uint32_t desc, uint64_t ptr); 1155 uint64_t mte_check(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_t ra); 1156 1157 static inline int allocation_tag_from_addr(uint64_t ptr) 1158 { 1159 return extract64(ptr, 56, 4); 1160 } 1161 1162 static inline uint64_t address_with_allocation_tag(uint64_t ptr, int rtag) 1163 { 1164 return deposit64(ptr, 56, 4, rtag); 1165 } 1166 1167 /* Return true if tbi bits mean that the access is checked. */ 1168 static inline bool tbi_check(uint32_t desc, int bit55) 1169 { 1170 return (desc >> (R_MTEDESC_TBI_SHIFT + bit55)) & 1; 1171 } 1172 1173 /* Return true if tcma bits mean that the access is unchecked. */ 1174 static inline bool tcma_check(uint32_t desc, int bit55, int ptr_tag) 1175 { 1176 /* 1177 * We had extracted bit55 and ptr_tag for other reasons, so fold 1178 * (ptr<59:55> == 00000 || ptr<59:55> == 11111) into a single test. 1179 */ 1180 bool match = ((ptr_tag + bit55) & 0xf) == 0; 1181 bool tcma = (desc >> (R_MTEDESC_TCMA_SHIFT + bit55)) & 1; 1182 return tcma && match; 1183 } 1184 1185 /* 1186 * For TBI, ideally, we would do nothing. Proper behaviour on fault is 1187 * for the tag to be present in the FAR_ELx register. But for user-only 1188 * mode, we do not have a TLB with which to implement this, so we must 1189 * remove the top byte. 1190 */ 1191 static inline uint64_t useronly_clean_ptr(uint64_t ptr) 1192 { 1193 #ifdef CONFIG_USER_ONLY 1194 /* TBI0 is known to be enabled, while TBI1 is disabled. */ 1195 ptr &= sextract64(ptr, 0, 56); 1196 #endif 1197 return ptr; 1198 } 1199 1200 static inline uint64_t useronly_maybe_clean_ptr(uint32_t desc, uint64_t ptr) 1201 { 1202 #ifdef CONFIG_USER_ONLY 1203 int64_t clean_ptr = sextract64(ptr, 0, 56); 1204 if (tbi_check(desc, clean_ptr < 0)) { 1205 ptr = clean_ptr; 1206 } 1207 #endif 1208 return ptr; 1209 } 1210 1211 /* Values for M-profile PSR.ECI for MVE insns */ 1212 enum MVEECIState { 1213 ECI_NONE = 0, /* No completed beats */ 1214 ECI_A0 = 1, /* Completed: A0 */ 1215 ECI_A0A1 = 2, /* Completed: A0, A1 */ 1216 /* 3 is reserved */ 1217 ECI_A0A1A2 = 4, /* Completed: A0, A1, A2 */ 1218 ECI_A0A1A2B0 = 5, /* Completed: A0, A1, A2, B0 */ 1219 /* All other values reserved */ 1220 }; 1221 1222 /* Definitions for the PMU registers */ 1223 #define PMCRN_MASK 0xf800 1224 #define PMCRN_SHIFT 11 1225 #define PMCRLC 0x40 1226 #define PMCRDP 0x20 1227 #define PMCRX 0x10 1228 #define PMCRD 0x8 1229 #define PMCRC 0x4 1230 #define PMCRP 0x2 1231 #define PMCRE 0x1 1232 /* 1233 * Mask of PMCR bits writeable by guest (not including WO bits like C, P, 1234 * which can be written as 1 to trigger behaviour but which stay RAZ). 1235 */ 1236 #define PMCR_WRITEABLE_MASK (PMCRLC | PMCRDP | PMCRX | PMCRD | PMCRE) 1237 1238 #define PMXEVTYPER_P 0x80000000 1239 #define PMXEVTYPER_U 0x40000000 1240 #define PMXEVTYPER_NSK 0x20000000 1241 #define PMXEVTYPER_NSU 0x10000000 1242 #define PMXEVTYPER_NSH 0x08000000 1243 #define PMXEVTYPER_M 0x04000000 1244 #define PMXEVTYPER_MT 0x02000000 1245 #define PMXEVTYPER_EVTCOUNT 0x0000ffff 1246 #define PMXEVTYPER_MASK (PMXEVTYPER_P | PMXEVTYPER_U | PMXEVTYPER_NSK | \ 1247 PMXEVTYPER_NSU | PMXEVTYPER_NSH | \ 1248 PMXEVTYPER_M | PMXEVTYPER_MT | \ 1249 PMXEVTYPER_EVTCOUNT) 1250 1251 #define PMCCFILTR 0xf8000000 1252 #define PMCCFILTR_M PMXEVTYPER_M 1253 #define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M) 1254 1255 static inline uint32_t pmu_num_counters(CPUARMState *env) 1256 { 1257 return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT; 1258 } 1259 1260 /* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */ 1261 static inline uint64_t pmu_counter_mask(CPUARMState *env) 1262 { 1263 return (1 << 31) | ((1 << pmu_num_counters(env)) - 1); 1264 } 1265 1266 #ifdef TARGET_AARCH64 1267 int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg); 1268 int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg); 1269 int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg); 1270 int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg); 1271 #endif 1272 1273 #endif 1274