1 /* 2 * QEMU Hypervisor.framework support for Apple Silicon 3 4 * Copyright 2020 Alexander Graf <agraf@csgraf.de> 5 * Copyright 2020 Google LLC 6 * 7 * This work is licensed under the terms of the GNU GPL, version 2 or later. 8 * See the COPYING file in the top-level directory. 9 * 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qemu/error-report.h" 14 15 #include "sysemu/runstate.h" 16 #include "sysemu/hvf.h" 17 #include "sysemu/hvf_int.h" 18 #include "sysemu/hw_accel.h" 19 #include "hvf_arm.h" 20 #include "cpregs.h" 21 22 #include <mach/mach_time.h> 23 24 #include "exec/address-spaces.h" 25 #include "hw/irq.h" 26 #include "qemu/main-loop.h" 27 #include "sysemu/cpus.h" 28 #include "arm-powerctl.h" 29 #include "target/arm/cpu.h" 30 #include "target/arm/internals.h" 31 #include "trace/trace-target_arm_hvf.h" 32 #include "migration/vmstate.h" 33 34 #include "exec/gdbstub.h" 35 36 #define HVF_SYSREG(crn, crm, op0, op1, op2) \ 37 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2) 38 #define PL1_WRITE_MASK 0x4 39 40 #define SYSREG_OP0_SHIFT 20 41 #define SYSREG_OP0_MASK 0x3 42 #define SYSREG_OP0(sysreg) ((sysreg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK) 43 #define SYSREG_OP1_SHIFT 14 44 #define SYSREG_OP1_MASK 0x7 45 #define SYSREG_OP1(sysreg) ((sysreg >> SYSREG_OP1_SHIFT) & SYSREG_OP1_MASK) 46 #define SYSREG_CRN_SHIFT 10 47 #define SYSREG_CRN_MASK 0xf 48 #define SYSREG_CRN(sysreg) ((sysreg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK) 49 #define SYSREG_CRM_SHIFT 1 50 #define SYSREG_CRM_MASK 0xf 51 #define SYSREG_CRM(sysreg) ((sysreg >> SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK) 52 #define SYSREG_OP2_SHIFT 17 53 #define SYSREG_OP2_MASK 0x7 54 #define SYSREG_OP2(sysreg) ((sysreg >> SYSREG_OP2_SHIFT) & SYSREG_OP2_MASK) 55 56 #define SYSREG(op0, op1, crn, crm, op2) \ 57 ((op0 << SYSREG_OP0_SHIFT) | \ 58 (op1 << SYSREG_OP1_SHIFT) | \ 59 (crn << SYSREG_CRN_SHIFT) | \ 60 (crm << SYSREG_CRM_SHIFT) | \ 61 (op2 << SYSREG_OP2_SHIFT)) 62 #define SYSREG_MASK \ 63 SYSREG(SYSREG_OP0_MASK, \ 64 SYSREG_OP1_MASK, \ 65 SYSREG_CRN_MASK, \ 66 SYSREG_CRM_MASK, \ 67 SYSREG_OP2_MASK) 68 #define SYSREG_OSLAR_EL1 SYSREG(2, 0, 1, 0, 4) 69 #define SYSREG_OSLSR_EL1 SYSREG(2, 0, 1, 1, 4) 70 #define SYSREG_OSDLR_EL1 SYSREG(2, 0, 1, 3, 4) 71 #define SYSREG_CNTPCT_EL0 SYSREG(3, 3, 14, 0, 1) 72 #define SYSREG_PMCR_EL0 SYSREG(3, 3, 9, 12, 0) 73 #define SYSREG_PMUSERENR_EL0 SYSREG(3, 3, 9, 14, 0) 74 #define SYSREG_PMCNTENSET_EL0 SYSREG(3, 3, 9, 12, 1) 75 #define SYSREG_PMCNTENCLR_EL0 SYSREG(3, 3, 9, 12, 2) 76 #define SYSREG_PMINTENCLR_EL1 SYSREG(3, 0, 9, 14, 2) 77 #define SYSREG_PMOVSCLR_EL0 SYSREG(3, 3, 9, 12, 3) 78 #define SYSREG_PMSWINC_EL0 SYSREG(3, 3, 9, 12, 4) 79 #define SYSREG_PMSELR_EL0 SYSREG(3, 3, 9, 12, 5) 80 #define SYSREG_PMCEID0_EL0 SYSREG(3, 3, 9, 12, 6) 81 #define SYSREG_PMCEID1_EL0 SYSREG(3, 3, 9, 12, 7) 82 #define SYSREG_PMCCNTR_EL0 SYSREG(3, 3, 9, 13, 0) 83 #define SYSREG_PMCCFILTR_EL0 SYSREG(3, 3, 14, 15, 7) 84 85 #define SYSREG_ICC_AP0R0_EL1 SYSREG(3, 0, 12, 8, 4) 86 #define SYSREG_ICC_AP0R1_EL1 SYSREG(3, 0, 12, 8, 5) 87 #define SYSREG_ICC_AP0R2_EL1 SYSREG(3, 0, 12, 8, 6) 88 #define SYSREG_ICC_AP0R3_EL1 SYSREG(3, 0, 12, 8, 7) 89 #define SYSREG_ICC_AP1R0_EL1 SYSREG(3, 0, 12, 9, 0) 90 #define SYSREG_ICC_AP1R1_EL1 SYSREG(3, 0, 12, 9, 1) 91 #define SYSREG_ICC_AP1R2_EL1 SYSREG(3, 0, 12, 9, 2) 92 #define SYSREG_ICC_AP1R3_EL1 SYSREG(3, 0, 12, 9, 3) 93 #define SYSREG_ICC_ASGI1R_EL1 SYSREG(3, 0, 12, 11, 6) 94 #define SYSREG_ICC_BPR0_EL1 SYSREG(3, 0, 12, 8, 3) 95 #define SYSREG_ICC_BPR1_EL1 SYSREG(3, 0, 12, 12, 3) 96 #define SYSREG_ICC_CTLR_EL1 SYSREG(3, 0, 12, 12, 4) 97 #define SYSREG_ICC_DIR_EL1 SYSREG(3, 0, 12, 11, 1) 98 #define SYSREG_ICC_EOIR0_EL1 SYSREG(3, 0, 12, 8, 1) 99 #define SYSREG_ICC_EOIR1_EL1 SYSREG(3, 0, 12, 12, 1) 100 #define SYSREG_ICC_HPPIR0_EL1 SYSREG(3, 0, 12, 8, 2) 101 #define SYSREG_ICC_HPPIR1_EL1 SYSREG(3, 0, 12, 12, 2) 102 #define SYSREG_ICC_IAR0_EL1 SYSREG(3, 0, 12, 8, 0) 103 #define SYSREG_ICC_IAR1_EL1 SYSREG(3, 0, 12, 12, 0) 104 #define SYSREG_ICC_IGRPEN0_EL1 SYSREG(3, 0, 12, 12, 6) 105 #define SYSREG_ICC_IGRPEN1_EL1 SYSREG(3, 0, 12, 12, 7) 106 #define SYSREG_ICC_PMR_EL1 SYSREG(3, 0, 4, 6, 0) 107 #define SYSREG_ICC_RPR_EL1 SYSREG(3, 0, 12, 11, 3) 108 #define SYSREG_ICC_SGI0R_EL1 SYSREG(3, 0, 12, 11, 7) 109 #define SYSREG_ICC_SGI1R_EL1 SYSREG(3, 0, 12, 11, 5) 110 #define SYSREG_ICC_SRE_EL1 SYSREG(3, 0, 12, 12, 5) 111 112 #define SYSREG_MDSCR_EL1 SYSREG(2, 0, 0, 2, 2) 113 #define SYSREG_DBGBVR0_EL1 SYSREG(2, 0, 0, 0, 4) 114 #define SYSREG_DBGBCR0_EL1 SYSREG(2, 0, 0, 0, 5) 115 #define SYSREG_DBGWVR0_EL1 SYSREG(2, 0, 0, 0, 6) 116 #define SYSREG_DBGWCR0_EL1 SYSREG(2, 0, 0, 0, 7) 117 #define SYSREG_DBGBVR1_EL1 SYSREG(2, 0, 0, 1, 4) 118 #define SYSREG_DBGBCR1_EL1 SYSREG(2, 0, 0, 1, 5) 119 #define SYSREG_DBGWVR1_EL1 SYSREG(2, 0, 0, 1, 6) 120 #define SYSREG_DBGWCR1_EL1 SYSREG(2, 0, 0, 1, 7) 121 #define SYSREG_DBGBVR2_EL1 SYSREG(2, 0, 0, 2, 4) 122 #define SYSREG_DBGBCR2_EL1 SYSREG(2, 0, 0, 2, 5) 123 #define SYSREG_DBGWVR2_EL1 SYSREG(2, 0, 0, 2, 6) 124 #define SYSREG_DBGWCR2_EL1 SYSREG(2, 0, 0, 2, 7) 125 #define SYSREG_DBGBVR3_EL1 SYSREG(2, 0, 0, 3, 4) 126 #define SYSREG_DBGBCR3_EL1 SYSREG(2, 0, 0, 3, 5) 127 #define SYSREG_DBGWVR3_EL1 SYSREG(2, 0, 0, 3, 6) 128 #define SYSREG_DBGWCR3_EL1 SYSREG(2, 0, 0, 3, 7) 129 #define SYSREG_DBGBVR4_EL1 SYSREG(2, 0, 0, 4, 4) 130 #define SYSREG_DBGBCR4_EL1 SYSREG(2, 0, 0, 4, 5) 131 #define SYSREG_DBGWVR4_EL1 SYSREG(2, 0, 0, 4, 6) 132 #define SYSREG_DBGWCR4_EL1 SYSREG(2, 0, 0, 4, 7) 133 #define SYSREG_DBGBVR5_EL1 SYSREG(2, 0, 0, 5, 4) 134 #define SYSREG_DBGBCR5_EL1 SYSREG(2, 0, 0, 5, 5) 135 #define SYSREG_DBGWVR5_EL1 SYSREG(2, 0, 0, 5, 6) 136 #define SYSREG_DBGWCR5_EL1 SYSREG(2, 0, 0, 5, 7) 137 #define SYSREG_DBGBVR6_EL1 SYSREG(2, 0, 0, 6, 4) 138 #define SYSREG_DBGBCR6_EL1 SYSREG(2, 0, 0, 6, 5) 139 #define SYSREG_DBGWVR6_EL1 SYSREG(2, 0, 0, 6, 6) 140 #define SYSREG_DBGWCR6_EL1 SYSREG(2, 0, 0, 6, 7) 141 #define SYSREG_DBGBVR7_EL1 SYSREG(2, 0, 0, 7, 4) 142 #define SYSREG_DBGBCR7_EL1 SYSREG(2, 0, 0, 7, 5) 143 #define SYSREG_DBGWVR7_EL1 SYSREG(2, 0, 0, 7, 6) 144 #define SYSREG_DBGWCR7_EL1 SYSREG(2, 0, 0, 7, 7) 145 #define SYSREG_DBGBVR8_EL1 SYSREG(2, 0, 0, 8, 4) 146 #define SYSREG_DBGBCR8_EL1 SYSREG(2, 0, 0, 8, 5) 147 #define SYSREG_DBGWVR8_EL1 SYSREG(2, 0, 0, 8, 6) 148 #define SYSREG_DBGWCR8_EL1 SYSREG(2, 0, 0, 8, 7) 149 #define SYSREG_DBGBVR9_EL1 SYSREG(2, 0, 0, 9, 4) 150 #define SYSREG_DBGBCR9_EL1 SYSREG(2, 0, 0, 9, 5) 151 #define SYSREG_DBGWVR9_EL1 SYSREG(2, 0, 0, 9, 6) 152 #define SYSREG_DBGWCR9_EL1 SYSREG(2, 0, 0, 9, 7) 153 #define SYSREG_DBGBVR10_EL1 SYSREG(2, 0, 0, 10, 4) 154 #define SYSREG_DBGBCR10_EL1 SYSREG(2, 0, 0, 10, 5) 155 #define SYSREG_DBGWVR10_EL1 SYSREG(2, 0, 0, 10, 6) 156 #define SYSREG_DBGWCR10_EL1 SYSREG(2, 0, 0, 10, 7) 157 #define SYSREG_DBGBVR11_EL1 SYSREG(2, 0, 0, 11, 4) 158 #define SYSREG_DBGBCR11_EL1 SYSREG(2, 0, 0, 11, 5) 159 #define SYSREG_DBGWVR11_EL1 SYSREG(2, 0, 0, 11, 6) 160 #define SYSREG_DBGWCR11_EL1 SYSREG(2, 0, 0, 11, 7) 161 #define SYSREG_DBGBVR12_EL1 SYSREG(2, 0, 0, 12, 4) 162 #define SYSREG_DBGBCR12_EL1 SYSREG(2, 0, 0, 12, 5) 163 #define SYSREG_DBGWVR12_EL1 SYSREG(2, 0, 0, 12, 6) 164 #define SYSREG_DBGWCR12_EL1 SYSREG(2, 0, 0, 12, 7) 165 #define SYSREG_DBGBVR13_EL1 SYSREG(2, 0, 0, 13, 4) 166 #define SYSREG_DBGBCR13_EL1 SYSREG(2, 0, 0, 13, 5) 167 #define SYSREG_DBGWVR13_EL1 SYSREG(2, 0, 0, 13, 6) 168 #define SYSREG_DBGWCR13_EL1 SYSREG(2, 0, 0, 13, 7) 169 #define SYSREG_DBGBVR14_EL1 SYSREG(2, 0, 0, 14, 4) 170 #define SYSREG_DBGBCR14_EL1 SYSREG(2, 0, 0, 14, 5) 171 #define SYSREG_DBGWVR14_EL1 SYSREG(2, 0, 0, 14, 6) 172 #define SYSREG_DBGWCR14_EL1 SYSREG(2, 0, 0, 14, 7) 173 #define SYSREG_DBGBVR15_EL1 SYSREG(2, 0, 0, 15, 4) 174 #define SYSREG_DBGBCR15_EL1 SYSREG(2, 0, 0, 15, 5) 175 #define SYSREG_DBGWVR15_EL1 SYSREG(2, 0, 0, 15, 6) 176 #define SYSREG_DBGWCR15_EL1 SYSREG(2, 0, 0, 15, 7) 177 178 #define WFX_IS_WFE (1 << 0) 179 180 #define TMR_CTL_ENABLE (1 << 0) 181 #define TMR_CTL_IMASK (1 << 1) 182 #define TMR_CTL_ISTATUS (1 << 2) 183 184 static void hvf_wfi(CPUState *cpu); 185 186 typedef struct HVFVTimer { 187 /* Vtimer value during migration and paused state */ 188 uint64_t vtimer_val; 189 } HVFVTimer; 190 191 static HVFVTimer vtimer; 192 193 typedef struct ARMHostCPUFeatures { 194 ARMISARegisters isar; 195 uint64_t features; 196 uint64_t midr; 197 uint32_t reset_sctlr; 198 const char *dtb_compatible; 199 } ARMHostCPUFeatures; 200 201 static ARMHostCPUFeatures arm_host_cpu_features; 202 203 struct hvf_reg_match { 204 int reg; 205 uint64_t offset; 206 }; 207 208 static const struct hvf_reg_match hvf_reg_match[] = { 209 { HV_REG_X0, offsetof(CPUARMState, xregs[0]) }, 210 { HV_REG_X1, offsetof(CPUARMState, xregs[1]) }, 211 { HV_REG_X2, offsetof(CPUARMState, xregs[2]) }, 212 { HV_REG_X3, offsetof(CPUARMState, xregs[3]) }, 213 { HV_REG_X4, offsetof(CPUARMState, xregs[4]) }, 214 { HV_REG_X5, offsetof(CPUARMState, xregs[5]) }, 215 { HV_REG_X6, offsetof(CPUARMState, xregs[6]) }, 216 { HV_REG_X7, offsetof(CPUARMState, xregs[7]) }, 217 { HV_REG_X8, offsetof(CPUARMState, xregs[8]) }, 218 { HV_REG_X9, offsetof(CPUARMState, xregs[9]) }, 219 { HV_REG_X10, offsetof(CPUARMState, xregs[10]) }, 220 { HV_REG_X11, offsetof(CPUARMState, xregs[11]) }, 221 { HV_REG_X12, offsetof(CPUARMState, xregs[12]) }, 222 { HV_REG_X13, offsetof(CPUARMState, xregs[13]) }, 223 { HV_REG_X14, offsetof(CPUARMState, xregs[14]) }, 224 { HV_REG_X15, offsetof(CPUARMState, xregs[15]) }, 225 { HV_REG_X16, offsetof(CPUARMState, xregs[16]) }, 226 { HV_REG_X17, offsetof(CPUARMState, xregs[17]) }, 227 { HV_REG_X18, offsetof(CPUARMState, xregs[18]) }, 228 { HV_REG_X19, offsetof(CPUARMState, xregs[19]) }, 229 { HV_REG_X20, offsetof(CPUARMState, xregs[20]) }, 230 { HV_REG_X21, offsetof(CPUARMState, xregs[21]) }, 231 { HV_REG_X22, offsetof(CPUARMState, xregs[22]) }, 232 { HV_REG_X23, offsetof(CPUARMState, xregs[23]) }, 233 { HV_REG_X24, offsetof(CPUARMState, xregs[24]) }, 234 { HV_REG_X25, offsetof(CPUARMState, xregs[25]) }, 235 { HV_REG_X26, offsetof(CPUARMState, xregs[26]) }, 236 { HV_REG_X27, offsetof(CPUARMState, xregs[27]) }, 237 { HV_REG_X28, offsetof(CPUARMState, xregs[28]) }, 238 { HV_REG_X29, offsetof(CPUARMState, xregs[29]) }, 239 { HV_REG_X30, offsetof(CPUARMState, xregs[30]) }, 240 { HV_REG_PC, offsetof(CPUARMState, pc) }, 241 }; 242 243 static const struct hvf_reg_match hvf_fpreg_match[] = { 244 { HV_SIMD_FP_REG_Q0, offsetof(CPUARMState, vfp.zregs[0]) }, 245 { HV_SIMD_FP_REG_Q1, offsetof(CPUARMState, vfp.zregs[1]) }, 246 { HV_SIMD_FP_REG_Q2, offsetof(CPUARMState, vfp.zregs[2]) }, 247 { HV_SIMD_FP_REG_Q3, offsetof(CPUARMState, vfp.zregs[3]) }, 248 { HV_SIMD_FP_REG_Q4, offsetof(CPUARMState, vfp.zregs[4]) }, 249 { HV_SIMD_FP_REG_Q5, offsetof(CPUARMState, vfp.zregs[5]) }, 250 { HV_SIMD_FP_REG_Q6, offsetof(CPUARMState, vfp.zregs[6]) }, 251 { HV_SIMD_FP_REG_Q7, offsetof(CPUARMState, vfp.zregs[7]) }, 252 { HV_SIMD_FP_REG_Q8, offsetof(CPUARMState, vfp.zregs[8]) }, 253 { HV_SIMD_FP_REG_Q9, offsetof(CPUARMState, vfp.zregs[9]) }, 254 { HV_SIMD_FP_REG_Q10, offsetof(CPUARMState, vfp.zregs[10]) }, 255 { HV_SIMD_FP_REG_Q11, offsetof(CPUARMState, vfp.zregs[11]) }, 256 { HV_SIMD_FP_REG_Q12, offsetof(CPUARMState, vfp.zregs[12]) }, 257 { HV_SIMD_FP_REG_Q13, offsetof(CPUARMState, vfp.zregs[13]) }, 258 { HV_SIMD_FP_REG_Q14, offsetof(CPUARMState, vfp.zregs[14]) }, 259 { HV_SIMD_FP_REG_Q15, offsetof(CPUARMState, vfp.zregs[15]) }, 260 { HV_SIMD_FP_REG_Q16, offsetof(CPUARMState, vfp.zregs[16]) }, 261 { HV_SIMD_FP_REG_Q17, offsetof(CPUARMState, vfp.zregs[17]) }, 262 { HV_SIMD_FP_REG_Q18, offsetof(CPUARMState, vfp.zregs[18]) }, 263 { HV_SIMD_FP_REG_Q19, offsetof(CPUARMState, vfp.zregs[19]) }, 264 { HV_SIMD_FP_REG_Q20, offsetof(CPUARMState, vfp.zregs[20]) }, 265 { HV_SIMD_FP_REG_Q21, offsetof(CPUARMState, vfp.zregs[21]) }, 266 { HV_SIMD_FP_REG_Q22, offsetof(CPUARMState, vfp.zregs[22]) }, 267 { HV_SIMD_FP_REG_Q23, offsetof(CPUARMState, vfp.zregs[23]) }, 268 { HV_SIMD_FP_REG_Q24, offsetof(CPUARMState, vfp.zregs[24]) }, 269 { HV_SIMD_FP_REG_Q25, offsetof(CPUARMState, vfp.zregs[25]) }, 270 { HV_SIMD_FP_REG_Q26, offsetof(CPUARMState, vfp.zregs[26]) }, 271 { HV_SIMD_FP_REG_Q27, offsetof(CPUARMState, vfp.zregs[27]) }, 272 { HV_SIMD_FP_REG_Q28, offsetof(CPUARMState, vfp.zregs[28]) }, 273 { HV_SIMD_FP_REG_Q29, offsetof(CPUARMState, vfp.zregs[29]) }, 274 { HV_SIMD_FP_REG_Q30, offsetof(CPUARMState, vfp.zregs[30]) }, 275 { HV_SIMD_FP_REG_Q31, offsetof(CPUARMState, vfp.zregs[31]) }, 276 }; 277 278 struct hvf_sreg_match { 279 int reg; 280 uint32_t key; 281 uint32_t cp_idx; 282 }; 283 284 static struct hvf_sreg_match hvf_sreg_match[] = { 285 { HV_SYS_REG_DBGBVR0_EL1, HVF_SYSREG(0, 0, 14, 0, 4) }, 286 { HV_SYS_REG_DBGBCR0_EL1, HVF_SYSREG(0, 0, 14, 0, 5) }, 287 { HV_SYS_REG_DBGWVR0_EL1, HVF_SYSREG(0, 0, 14, 0, 6) }, 288 { HV_SYS_REG_DBGWCR0_EL1, HVF_SYSREG(0, 0, 14, 0, 7) }, 289 290 { HV_SYS_REG_DBGBVR1_EL1, HVF_SYSREG(0, 1, 14, 0, 4) }, 291 { HV_SYS_REG_DBGBCR1_EL1, HVF_SYSREG(0, 1, 14, 0, 5) }, 292 { HV_SYS_REG_DBGWVR1_EL1, HVF_SYSREG(0, 1, 14, 0, 6) }, 293 { HV_SYS_REG_DBGWCR1_EL1, HVF_SYSREG(0, 1, 14, 0, 7) }, 294 295 { HV_SYS_REG_DBGBVR2_EL1, HVF_SYSREG(0, 2, 14, 0, 4) }, 296 { HV_SYS_REG_DBGBCR2_EL1, HVF_SYSREG(0, 2, 14, 0, 5) }, 297 { HV_SYS_REG_DBGWVR2_EL1, HVF_SYSREG(0, 2, 14, 0, 6) }, 298 { HV_SYS_REG_DBGWCR2_EL1, HVF_SYSREG(0, 2, 14, 0, 7) }, 299 300 { HV_SYS_REG_DBGBVR3_EL1, HVF_SYSREG(0, 3, 14, 0, 4) }, 301 { HV_SYS_REG_DBGBCR3_EL1, HVF_SYSREG(0, 3, 14, 0, 5) }, 302 { HV_SYS_REG_DBGWVR3_EL1, HVF_SYSREG(0, 3, 14, 0, 6) }, 303 { HV_SYS_REG_DBGWCR3_EL1, HVF_SYSREG(0, 3, 14, 0, 7) }, 304 305 { HV_SYS_REG_DBGBVR4_EL1, HVF_SYSREG(0, 4, 14, 0, 4) }, 306 { HV_SYS_REG_DBGBCR4_EL1, HVF_SYSREG(0, 4, 14, 0, 5) }, 307 { HV_SYS_REG_DBGWVR4_EL1, HVF_SYSREG(0, 4, 14, 0, 6) }, 308 { HV_SYS_REG_DBGWCR4_EL1, HVF_SYSREG(0, 4, 14, 0, 7) }, 309 310 { HV_SYS_REG_DBGBVR5_EL1, HVF_SYSREG(0, 5, 14, 0, 4) }, 311 { HV_SYS_REG_DBGBCR5_EL1, HVF_SYSREG(0, 5, 14, 0, 5) }, 312 { HV_SYS_REG_DBGWVR5_EL1, HVF_SYSREG(0, 5, 14, 0, 6) }, 313 { HV_SYS_REG_DBGWCR5_EL1, HVF_SYSREG(0, 5, 14, 0, 7) }, 314 315 { HV_SYS_REG_DBGBVR6_EL1, HVF_SYSREG(0, 6, 14, 0, 4) }, 316 { HV_SYS_REG_DBGBCR6_EL1, HVF_SYSREG(0, 6, 14, 0, 5) }, 317 { HV_SYS_REG_DBGWVR6_EL1, HVF_SYSREG(0, 6, 14, 0, 6) }, 318 { HV_SYS_REG_DBGWCR6_EL1, HVF_SYSREG(0, 6, 14, 0, 7) }, 319 320 { HV_SYS_REG_DBGBVR7_EL1, HVF_SYSREG(0, 7, 14, 0, 4) }, 321 { HV_SYS_REG_DBGBCR7_EL1, HVF_SYSREG(0, 7, 14, 0, 5) }, 322 { HV_SYS_REG_DBGWVR7_EL1, HVF_SYSREG(0, 7, 14, 0, 6) }, 323 { HV_SYS_REG_DBGWCR7_EL1, HVF_SYSREG(0, 7, 14, 0, 7) }, 324 325 { HV_SYS_REG_DBGBVR8_EL1, HVF_SYSREG(0, 8, 14, 0, 4) }, 326 { HV_SYS_REG_DBGBCR8_EL1, HVF_SYSREG(0, 8, 14, 0, 5) }, 327 { HV_SYS_REG_DBGWVR8_EL1, HVF_SYSREG(0, 8, 14, 0, 6) }, 328 { HV_SYS_REG_DBGWCR8_EL1, HVF_SYSREG(0, 8, 14, 0, 7) }, 329 330 { HV_SYS_REG_DBGBVR9_EL1, HVF_SYSREG(0, 9, 14, 0, 4) }, 331 { HV_SYS_REG_DBGBCR9_EL1, HVF_SYSREG(0, 9, 14, 0, 5) }, 332 { HV_SYS_REG_DBGWVR9_EL1, HVF_SYSREG(0, 9, 14, 0, 6) }, 333 { HV_SYS_REG_DBGWCR9_EL1, HVF_SYSREG(0, 9, 14, 0, 7) }, 334 335 { HV_SYS_REG_DBGBVR10_EL1, HVF_SYSREG(0, 10, 14, 0, 4) }, 336 { HV_SYS_REG_DBGBCR10_EL1, HVF_SYSREG(0, 10, 14, 0, 5) }, 337 { HV_SYS_REG_DBGWVR10_EL1, HVF_SYSREG(0, 10, 14, 0, 6) }, 338 { HV_SYS_REG_DBGWCR10_EL1, HVF_SYSREG(0, 10, 14, 0, 7) }, 339 340 { HV_SYS_REG_DBGBVR11_EL1, HVF_SYSREG(0, 11, 14, 0, 4) }, 341 { HV_SYS_REG_DBGBCR11_EL1, HVF_SYSREG(0, 11, 14, 0, 5) }, 342 { HV_SYS_REG_DBGWVR11_EL1, HVF_SYSREG(0, 11, 14, 0, 6) }, 343 { HV_SYS_REG_DBGWCR11_EL1, HVF_SYSREG(0, 11, 14, 0, 7) }, 344 345 { HV_SYS_REG_DBGBVR12_EL1, HVF_SYSREG(0, 12, 14, 0, 4) }, 346 { HV_SYS_REG_DBGBCR12_EL1, HVF_SYSREG(0, 12, 14, 0, 5) }, 347 { HV_SYS_REG_DBGWVR12_EL1, HVF_SYSREG(0, 12, 14, 0, 6) }, 348 { HV_SYS_REG_DBGWCR12_EL1, HVF_SYSREG(0, 12, 14, 0, 7) }, 349 350 { HV_SYS_REG_DBGBVR13_EL1, HVF_SYSREG(0, 13, 14, 0, 4) }, 351 { HV_SYS_REG_DBGBCR13_EL1, HVF_SYSREG(0, 13, 14, 0, 5) }, 352 { HV_SYS_REG_DBGWVR13_EL1, HVF_SYSREG(0, 13, 14, 0, 6) }, 353 { HV_SYS_REG_DBGWCR13_EL1, HVF_SYSREG(0, 13, 14, 0, 7) }, 354 355 { HV_SYS_REG_DBGBVR14_EL1, HVF_SYSREG(0, 14, 14, 0, 4) }, 356 { HV_SYS_REG_DBGBCR14_EL1, HVF_SYSREG(0, 14, 14, 0, 5) }, 357 { HV_SYS_REG_DBGWVR14_EL1, HVF_SYSREG(0, 14, 14, 0, 6) }, 358 { HV_SYS_REG_DBGWCR14_EL1, HVF_SYSREG(0, 14, 14, 0, 7) }, 359 360 { HV_SYS_REG_DBGBVR15_EL1, HVF_SYSREG(0, 15, 14, 0, 4) }, 361 { HV_SYS_REG_DBGBCR15_EL1, HVF_SYSREG(0, 15, 14, 0, 5) }, 362 { HV_SYS_REG_DBGWVR15_EL1, HVF_SYSREG(0, 15, 14, 0, 6) }, 363 { HV_SYS_REG_DBGWCR15_EL1, HVF_SYSREG(0, 15, 14, 0, 7) }, 364 365 #ifdef SYNC_NO_RAW_REGS 366 /* 367 * The registers below are manually synced on init because they are 368 * marked as NO_RAW. We still list them to make number space sync easier. 369 */ 370 { HV_SYS_REG_MDCCINT_EL1, HVF_SYSREG(0, 2, 2, 0, 0) }, 371 { HV_SYS_REG_MIDR_EL1, HVF_SYSREG(0, 0, 3, 0, 0) }, 372 { HV_SYS_REG_MPIDR_EL1, HVF_SYSREG(0, 0, 3, 0, 5) }, 373 { HV_SYS_REG_ID_AA64PFR0_EL1, HVF_SYSREG(0, 4, 3, 0, 0) }, 374 #endif 375 { HV_SYS_REG_ID_AA64PFR1_EL1, HVF_SYSREG(0, 4, 3, 0, 2) }, 376 { HV_SYS_REG_ID_AA64DFR0_EL1, HVF_SYSREG(0, 5, 3, 0, 0) }, 377 { HV_SYS_REG_ID_AA64DFR1_EL1, HVF_SYSREG(0, 5, 3, 0, 1) }, 378 { HV_SYS_REG_ID_AA64ISAR0_EL1, HVF_SYSREG(0, 6, 3, 0, 0) }, 379 { HV_SYS_REG_ID_AA64ISAR1_EL1, HVF_SYSREG(0, 6, 3, 0, 1) }, 380 #ifdef SYNC_NO_MMFR0 381 /* We keep the hardware MMFR0 around. HW limits are there anyway */ 382 { HV_SYS_REG_ID_AA64MMFR0_EL1, HVF_SYSREG(0, 7, 3, 0, 0) }, 383 #endif 384 { HV_SYS_REG_ID_AA64MMFR1_EL1, HVF_SYSREG(0, 7, 3, 0, 1) }, 385 { HV_SYS_REG_ID_AA64MMFR2_EL1, HVF_SYSREG(0, 7, 3, 0, 2) }, 386 387 { HV_SYS_REG_MDSCR_EL1, HVF_SYSREG(0, 2, 2, 0, 2) }, 388 { HV_SYS_REG_SCTLR_EL1, HVF_SYSREG(1, 0, 3, 0, 0) }, 389 { HV_SYS_REG_CPACR_EL1, HVF_SYSREG(1, 0, 3, 0, 2) }, 390 { HV_SYS_REG_TTBR0_EL1, HVF_SYSREG(2, 0, 3, 0, 0) }, 391 { HV_SYS_REG_TTBR1_EL1, HVF_SYSREG(2, 0, 3, 0, 1) }, 392 { HV_SYS_REG_TCR_EL1, HVF_SYSREG(2, 0, 3, 0, 2) }, 393 394 { HV_SYS_REG_APIAKEYLO_EL1, HVF_SYSREG(2, 1, 3, 0, 0) }, 395 { HV_SYS_REG_APIAKEYHI_EL1, HVF_SYSREG(2, 1, 3, 0, 1) }, 396 { HV_SYS_REG_APIBKEYLO_EL1, HVF_SYSREG(2, 1, 3, 0, 2) }, 397 { HV_SYS_REG_APIBKEYHI_EL1, HVF_SYSREG(2, 1, 3, 0, 3) }, 398 { HV_SYS_REG_APDAKEYLO_EL1, HVF_SYSREG(2, 2, 3, 0, 0) }, 399 { HV_SYS_REG_APDAKEYHI_EL1, HVF_SYSREG(2, 2, 3, 0, 1) }, 400 { HV_SYS_REG_APDBKEYLO_EL1, HVF_SYSREG(2, 2, 3, 0, 2) }, 401 { HV_SYS_REG_APDBKEYHI_EL1, HVF_SYSREG(2, 2, 3, 0, 3) }, 402 { HV_SYS_REG_APGAKEYLO_EL1, HVF_SYSREG(2, 3, 3, 0, 0) }, 403 { HV_SYS_REG_APGAKEYHI_EL1, HVF_SYSREG(2, 3, 3, 0, 1) }, 404 405 { HV_SYS_REG_SPSR_EL1, HVF_SYSREG(4, 0, 3, 0, 0) }, 406 { HV_SYS_REG_ELR_EL1, HVF_SYSREG(4, 0, 3, 0, 1) }, 407 { HV_SYS_REG_SP_EL0, HVF_SYSREG(4, 1, 3, 0, 0) }, 408 { HV_SYS_REG_AFSR0_EL1, HVF_SYSREG(5, 1, 3, 0, 0) }, 409 { HV_SYS_REG_AFSR1_EL1, HVF_SYSREG(5, 1, 3, 0, 1) }, 410 { HV_SYS_REG_ESR_EL1, HVF_SYSREG(5, 2, 3, 0, 0) }, 411 { HV_SYS_REG_FAR_EL1, HVF_SYSREG(6, 0, 3, 0, 0) }, 412 { HV_SYS_REG_PAR_EL1, HVF_SYSREG(7, 4, 3, 0, 0) }, 413 { HV_SYS_REG_MAIR_EL1, HVF_SYSREG(10, 2, 3, 0, 0) }, 414 { HV_SYS_REG_AMAIR_EL1, HVF_SYSREG(10, 3, 3, 0, 0) }, 415 { HV_SYS_REG_VBAR_EL1, HVF_SYSREG(12, 0, 3, 0, 0) }, 416 { HV_SYS_REG_CONTEXTIDR_EL1, HVF_SYSREG(13, 0, 3, 0, 1) }, 417 { HV_SYS_REG_TPIDR_EL1, HVF_SYSREG(13, 0, 3, 0, 4) }, 418 { HV_SYS_REG_CNTKCTL_EL1, HVF_SYSREG(14, 1, 3, 0, 0) }, 419 { HV_SYS_REG_CSSELR_EL1, HVF_SYSREG(0, 0, 3, 2, 0) }, 420 { HV_SYS_REG_TPIDR_EL0, HVF_SYSREG(13, 0, 3, 3, 2) }, 421 { HV_SYS_REG_TPIDRRO_EL0, HVF_SYSREG(13, 0, 3, 3, 3) }, 422 { HV_SYS_REG_CNTV_CTL_EL0, HVF_SYSREG(14, 3, 3, 3, 1) }, 423 { HV_SYS_REG_CNTV_CVAL_EL0, HVF_SYSREG(14, 3, 3, 3, 2) }, 424 { HV_SYS_REG_SP_EL1, HVF_SYSREG(4, 1, 3, 4, 0) }, 425 }; 426 427 int hvf_get_registers(CPUState *cpu) 428 { 429 ARMCPU *arm_cpu = ARM_CPU(cpu); 430 CPUARMState *env = &arm_cpu->env; 431 hv_return_t ret; 432 uint64_t val; 433 hv_simd_fp_uchar16_t fpval; 434 int i; 435 436 for (i = 0; i < ARRAY_SIZE(hvf_reg_match); i++) { 437 ret = hv_vcpu_get_reg(cpu->hvf->fd, hvf_reg_match[i].reg, &val); 438 *(uint64_t *)((void *)env + hvf_reg_match[i].offset) = val; 439 assert_hvf_ok(ret); 440 } 441 442 for (i = 0; i < ARRAY_SIZE(hvf_fpreg_match); i++) { 443 ret = hv_vcpu_get_simd_fp_reg(cpu->hvf->fd, hvf_fpreg_match[i].reg, 444 &fpval); 445 memcpy((void *)env + hvf_fpreg_match[i].offset, &fpval, sizeof(fpval)); 446 assert_hvf_ok(ret); 447 } 448 449 val = 0; 450 ret = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_FPCR, &val); 451 assert_hvf_ok(ret); 452 vfp_set_fpcr(env, val); 453 454 val = 0; 455 ret = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_FPSR, &val); 456 assert_hvf_ok(ret); 457 vfp_set_fpsr(env, val); 458 459 ret = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_CPSR, &val); 460 assert_hvf_ok(ret); 461 pstate_write(env, val); 462 463 for (i = 0; i < ARRAY_SIZE(hvf_sreg_match); i++) { 464 if (hvf_sreg_match[i].cp_idx == -1) { 465 continue; 466 } 467 468 ret = hv_vcpu_get_sys_reg(cpu->hvf->fd, hvf_sreg_match[i].reg, &val); 469 assert_hvf_ok(ret); 470 471 arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx] = val; 472 } 473 assert(write_list_to_cpustate(arm_cpu)); 474 475 aarch64_restore_sp(env, arm_current_el(env)); 476 477 return 0; 478 } 479 480 int hvf_put_registers(CPUState *cpu) 481 { 482 ARMCPU *arm_cpu = ARM_CPU(cpu); 483 CPUARMState *env = &arm_cpu->env; 484 hv_return_t ret; 485 uint64_t val; 486 hv_simd_fp_uchar16_t fpval; 487 int i; 488 489 for (i = 0; i < ARRAY_SIZE(hvf_reg_match); i++) { 490 val = *(uint64_t *)((void *)env + hvf_reg_match[i].offset); 491 ret = hv_vcpu_set_reg(cpu->hvf->fd, hvf_reg_match[i].reg, val); 492 assert_hvf_ok(ret); 493 } 494 495 for (i = 0; i < ARRAY_SIZE(hvf_fpreg_match); i++) { 496 memcpy(&fpval, (void *)env + hvf_fpreg_match[i].offset, sizeof(fpval)); 497 ret = hv_vcpu_set_simd_fp_reg(cpu->hvf->fd, hvf_fpreg_match[i].reg, 498 fpval); 499 assert_hvf_ok(ret); 500 } 501 502 ret = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_FPCR, vfp_get_fpcr(env)); 503 assert_hvf_ok(ret); 504 505 ret = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_FPSR, vfp_get_fpsr(env)); 506 assert_hvf_ok(ret); 507 508 ret = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_CPSR, pstate_read(env)); 509 assert_hvf_ok(ret); 510 511 aarch64_save_sp(env, arm_current_el(env)); 512 513 assert(write_cpustate_to_list(arm_cpu, false)); 514 for (i = 0; i < ARRAY_SIZE(hvf_sreg_match); i++) { 515 if (hvf_sreg_match[i].cp_idx == -1) { 516 continue; 517 } 518 519 val = arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx]; 520 ret = hv_vcpu_set_sys_reg(cpu->hvf->fd, hvf_sreg_match[i].reg, val); 521 assert_hvf_ok(ret); 522 } 523 524 ret = hv_vcpu_set_vtimer_offset(cpu->hvf->fd, hvf_state->vtimer_offset); 525 assert_hvf_ok(ret); 526 527 return 0; 528 } 529 530 static void flush_cpu_state(CPUState *cpu) 531 { 532 if (cpu->vcpu_dirty) { 533 hvf_put_registers(cpu); 534 cpu->vcpu_dirty = false; 535 } 536 } 537 538 static void hvf_set_reg(CPUState *cpu, int rt, uint64_t val) 539 { 540 hv_return_t r; 541 542 flush_cpu_state(cpu); 543 544 if (rt < 31) { 545 r = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_X0 + rt, val); 546 assert_hvf_ok(r); 547 } 548 } 549 550 static uint64_t hvf_get_reg(CPUState *cpu, int rt) 551 { 552 uint64_t val = 0; 553 hv_return_t r; 554 555 flush_cpu_state(cpu); 556 557 if (rt < 31) { 558 r = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_X0 + rt, &val); 559 assert_hvf_ok(r); 560 } 561 562 return val; 563 } 564 565 static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) 566 { 567 ARMISARegisters host_isar = {}; 568 const struct isar_regs { 569 int reg; 570 uint64_t *val; 571 } regs[] = { 572 { HV_SYS_REG_ID_AA64PFR0_EL1, &host_isar.id_aa64pfr0 }, 573 { HV_SYS_REG_ID_AA64PFR1_EL1, &host_isar.id_aa64pfr1 }, 574 { HV_SYS_REG_ID_AA64DFR0_EL1, &host_isar.id_aa64dfr0 }, 575 { HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.id_aa64dfr1 }, 576 { HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.id_aa64isar0 }, 577 { HV_SYS_REG_ID_AA64ISAR1_EL1, &host_isar.id_aa64isar1 }, 578 { HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.id_aa64mmfr0 }, 579 { HV_SYS_REG_ID_AA64MMFR1_EL1, &host_isar.id_aa64mmfr1 }, 580 { HV_SYS_REG_ID_AA64MMFR2_EL1, &host_isar.id_aa64mmfr2 }, 581 }; 582 hv_vcpu_t fd; 583 hv_return_t r = HV_SUCCESS; 584 hv_vcpu_exit_t *exit; 585 int i; 586 587 ahcf->dtb_compatible = "arm,arm-v8"; 588 ahcf->features = (1ULL << ARM_FEATURE_V8) | 589 (1ULL << ARM_FEATURE_NEON) | 590 (1ULL << ARM_FEATURE_AARCH64) | 591 (1ULL << ARM_FEATURE_PMU) | 592 (1ULL << ARM_FEATURE_GENERIC_TIMER); 593 594 /* We set up a small vcpu to extract host registers */ 595 596 if (hv_vcpu_create(&fd, &exit, NULL) != HV_SUCCESS) { 597 return false; 598 } 599 600 for (i = 0; i < ARRAY_SIZE(regs); i++) { 601 r |= hv_vcpu_get_sys_reg(fd, regs[i].reg, regs[i].val); 602 } 603 r |= hv_vcpu_get_sys_reg(fd, HV_SYS_REG_MIDR_EL1, &ahcf->midr); 604 r |= hv_vcpu_destroy(fd); 605 606 ahcf->isar = host_isar; 607 608 /* 609 * A scratch vCPU returns SCTLR 0, so let's fill our default with the M1 610 * boot SCTLR from https://github.com/AsahiLinux/m1n1/issues/97 611 */ 612 ahcf->reset_sctlr = 0x30100180; 613 /* 614 * SPAN is disabled by default when SCTLR.SPAN=1. To improve compatibility, 615 * let's disable it on boot and then allow guest software to turn it on by 616 * setting it to 0. 617 */ 618 ahcf->reset_sctlr |= 0x00800000; 619 620 /* Make sure we don't advertise AArch32 support for EL0/EL1 */ 621 if ((host_isar.id_aa64pfr0 & 0xff) != 0x11) { 622 return false; 623 } 624 625 return r == HV_SUCCESS; 626 } 627 628 void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu) 629 { 630 if (!arm_host_cpu_features.dtb_compatible) { 631 if (!hvf_enabled() || 632 !hvf_arm_get_host_cpu_features(&arm_host_cpu_features)) { 633 /* 634 * We can't report this error yet, so flag that we need to 635 * in arm_cpu_realizefn(). 636 */ 637 cpu->host_cpu_probe_failed = true; 638 return; 639 } 640 } 641 642 cpu->dtb_compatible = arm_host_cpu_features.dtb_compatible; 643 cpu->isar = arm_host_cpu_features.isar; 644 cpu->env.features = arm_host_cpu_features.features; 645 cpu->midr = arm_host_cpu_features.midr; 646 cpu->reset_sctlr = arm_host_cpu_features.reset_sctlr; 647 } 648 649 void hvf_arch_vcpu_destroy(CPUState *cpu) 650 { 651 } 652 653 int hvf_arch_init_vcpu(CPUState *cpu) 654 { 655 ARMCPU *arm_cpu = ARM_CPU(cpu); 656 CPUARMState *env = &arm_cpu->env; 657 uint32_t sregs_match_len = ARRAY_SIZE(hvf_sreg_match); 658 uint32_t sregs_cnt = 0; 659 uint64_t pfr; 660 hv_return_t ret; 661 int i; 662 663 env->aarch64 = true; 664 asm volatile("mrs %0, cntfrq_el0" : "=r"(arm_cpu->gt_cntfrq_hz)); 665 666 /* Allocate enough space for our sysreg sync */ 667 arm_cpu->cpreg_indexes = g_renew(uint64_t, arm_cpu->cpreg_indexes, 668 sregs_match_len); 669 arm_cpu->cpreg_values = g_renew(uint64_t, arm_cpu->cpreg_values, 670 sregs_match_len); 671 arm_cpu->cpreg_vmstate_indexes = g_renew(uint64_t, 672 arm_cpu->cpreg_vmstate_indexes, 673 sregs_match_len); 674 arm_cpu->cpreg_vmstate_values = g_renew(uint64_t, 675 arm_cpu->cpreg_vmstate_values, 676 sregs_match_len); 677 678 memset(arm_cpu->cpreg_values, 0, sregs_match_len * sizeof(uint64_t)); 679 680 /* Populate cp list for all known sysregs */ 681 for (i = 0; i < sregs_match_len; i++) { 682 const ARMCPRegInfo *ri; 683 uint32_t key = hvf_sreg_match[i].key; 684 685 ri = get_arm_cp_reginfo(arm_cpu->cp_regs, key); 686 if (ri) { 687 assert(!(ri->type & ARM_CP_NO_RAW)); 688 hvf_sreg_match[i].cp_idx = sregs_cnt; 689 arm_cpu->cpreg_indexes[sregs_cnt++] = cpreg_to_kvm_id(key); 690 } else { 691 hvf_sreg_match[i].cp_idx = -1; 692 } 693 } 694 arm_cpu->cpreg_array_len = sregs_cnt; 695 arm_cpu->cpreg_vmstate_array_len = sregs_cnt; 696 697 assert(write_cpustate_to_list(arm_cpu, false)); 698 699 /* Set CP_NO_RAW system registers on init */ 700 ret = hv_vcpu_set_sys_reg(cpu->hvf->fd, HV_SYS_REG_MIDR_EL1, 701 arm_cpu->midr); 702 assert_hvf_ok(ret); 703 704 ret = hv_vcpu_set_sys_reg(cpu->hvf->fd, HV_SYS_REG_MPIDR_EL1, 705 arm_cpu->mp_affinity); 706 assert_hvf_ok(ret); 707 708 ret = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_ID_AA64PFR0_EL1, &pfr); 709 assert_hvf_ok(ret); 710 pfr |= env->gicv3state ? (1 << 24) : 0; 711 ret = hv_vcpu_set_sys_reg(cpu->hvf->fd, HV_SYS_REG_ID_AA64PFR0_EL1, pfr); 712 assert_hvf_ok(ret); 713 714 /* We're limited to underlying hardware caps, override internal versions */ 715 ret = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_ID_AA64MMFR0_EL1, 716 &arm_cpu->isar.id_aa64mmfr0); 717 assert_hvf_ok(ret); 718 719 return 0; 720 } 721 722 void hvf_kick_vcpu_thread(CPUState *cpu) 723 { 724 cpus_kick_thread(cpu); 725 hv_vcpus_exit(&cpu->hvf->fd, 1); 726 } 727 728 static void hvf_raise_exception(CPUState *cpu, uint32_t excp, 729 uint32_t syndrome) 730 { 731 ARMCPU *arm_cpu = ARM_CPU(cpu); 732 CPUARMState *env = &arm_cpu->env; 733 734 cpu->exception_index = excp; 735 env->exception.target_el = 1; 736 env->exception.syndrome = syndrome; 737 738 arm_cpu_do_interrupt(cpu); 739 } 740 741 static void hvf_psci_cpu_off(ARMCPU *arm_cpu) 742 { 743 int32_t ret = arm_set_cpu_off(arm_cpu->mp_affinity); 744 assert(ret == QEMU_ARM_POWERCTL_RET_SUCCESS); 745 } 746 747 /* 748 * Handle a PSCI call. 749 * 750 * Returns 0 on success 751 * -1 when the PSCI call is unknown, 752 */ 753 static bool hvf_handle_psci_call(CPUState *cpu) 754 { 755 ARMCPU *arm_cpu = ARM_CPU(cpu); 756 CPUARMState *env = &arm_cpu->env; 757 uint64_t param[4] = { 758 env->xregs[0], 759 env->xregs[1], 760 env->xregs[2], 761 env->xregs[3] 762 }; 763 uint64_t context_id, mpidr; 764 bool target_aarch64 = true; 765 CPUState *target_cpu_state; 766 ARMCPU *target_cpu; 767 target_ulong entry; 768 int target_el = 1; 769 int32_t ret = 0; 770 771 trace_hvf_psci_call(param[0], param[1], param[2], param[3], 772 arm_cpu->mp_affinity); 773 774 switch (param[0]) { 775 case QEMU_PSCI_0_2_FN_PSCI_VERSION: 776 ret = QEMU_PSCI_VERSION_1_1; 777 break; 778 case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE: 779 ret = QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED; /* No trusted OS */ 780 break; 781 case QEMU_PSCI_0_2_FN_AFFINITY_INFO: 782 case QEMU_PSCI_0_2_FN64_AFFINITY_INFO: 783 mpidr = param[1]; 784 785 switch (param[2]) { 786 case 0: 787 target_cpu_state = arm_get_cpu_by_id(mpidr); 788 if (!target_cpu_state) { 789 ret = QEMU_PSCI_RET_INVALID_PARAMS; 790 break; 791 } 792 target_cpu = ARM_CPU(target_cpu_state); 793 794 ret = target_cpu->power_state; 795 break; 796 default: 797 /* Everything above affinity level 0 is always on. */ 798 ret = 0; 799 } 800 break; 801 case QEMU_PSCI_0_2_FN_SYSTEM_RESET: 802 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 803 /* 804 * QEMU reset and shutdown are async requests, but PSCI 805 * mandates that we never return from the reset/shutdown 806 * call, so power the CPU off now so it doesn't execute 807 * anything further. 808 */ 809 hvf_psci_cpu_off(arm_cpu); 810 break; 811 case QEMU_PSCI_0_2_FN_SYSTEM_OFF: 812 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 813 hvf_psci_cpu_off(arm_cpu); 814 break; 815 case QEMU_PSCI_0_1_FN_CPU_ON: 816 case QEMU_PSCI_0_2_FN_CPU_ON: 817 case QEMU_PSCI_0_2_FN64_CPU_ON: 818 mpidr = param[1]; 819 entry = param[2]; 820 context_id = param[3]; 821 ret = arm_set_cpu_on(mpidr, entry, context_id, 822 target_el, target_aarch64); 823 break; 824 case QEMU_PSCI_0_1_FN_CPU_OFF: 825 case QEMU_PSCI_0_2_FN_CPU_OFF: 826 hvf_psci_cpu_off(arm_cpu); 827 break; 828 case QEMU_PSCI_0_1_FN_CPU_SUSPEND: 829 case QEMU_PSCI_0_2_FN_CPU_SUSPEND: 830 case QEMU_PSCI_0_2_FN64_CPU_SUSPEND: 831 /* Affinity levels are not supported in QEMU */ 832 if (param[1] & 0xfffe0000) { 833 ret = QEMU_PSCI_RET_INVALID_PARAMS; 834 break; 835 } 836 /* Powerdown is not supported, we always go into WFI */ 837 env->xregs[0] = 0; 838 hvf_wfi(cpu); 839 break; 840 case QEMU_PSCI_0_1_FN_MIGRATE: 841 case QEMU_PSCI_0_2_FN_MIGRATE: 842 ret = QEMU_PSCI_RET_NOT_SUPPORTED; 843 break; 844 case QEMU_PSCI_1_0_FN_PSCI_FEATURES: 845 switch (param[1]) { 846 case QEMU_PSCI_0_2_FN_PSCI_VERSION: 847 case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE: 848 case QEMU_PSCI_0_2_FN_AFFINITY_INFO: 849 case QEMU_PSCI_0_2_FN64_AFFINITY_INFO: 850 case QEMU_PSCI_0_2_FN_SYSTEM_RESET: 851 case QEMU_PSCI_0_2_FN_SYSTEM_OFF: 852 case QEMU_PSCI_0_1_FN_CPU_ON: 853 case QEMU_PSCI_0_2_FN_CPU_ON: 854 case QEMU_PSCI_0_2_FN64_CPU_ON: 855 case QEMU_PSCI_0_1_FN_CPU_OFF: 856 case QEMU_PSCI_0_2_FN_CPU_OFF: 857 case QEMU_PSCI_0_1_FN_CPU_SUSPEND: 858 case QEMU_PSCI_0_2_FN_CPU_SUSPEND: 859 case QEMU_PSCI_0_2_FN64_CPU_SUSPEND: 860 case QEMU_PSCI_1_0_FN_PSCI_FEATURES: 861 ret = 0; 862 break; 863 case QEMU_PSCI_0_1_FN_MIGRATE: 864 case QEMU_PSCI_0_2_FN_MIGRATE: 865 default: 866 ret = QEMU_PSCI_RET_NOT_SUPPORTED; 867 } 868 break; 869 default: 870 return false; 871 } 872 873 env->xregs[0] = ret; 874 return true; 875 } 876 877 static bool is_id_sysreg(uint32_t reg) 878 { 879 return SYSREG_OP0(reg) == 3 && 880 SYSREG_OP1(reg) == 0 && 881 SYSREG_CRN(reg) == 0 && 882 SYSREG_CRM(reg) >= 1 && 883 SYSREG_CRM(reg) < 8; 884 } 885 886 static uint32_t hvf_reg2cp_reg(uint32_t reg) 887 { 888 return ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, 889 (reg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK, 890 (reg >> SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK, 891 (reg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK, 892 (reg >> SYSREG_OP1_SHIFT) & SYSREG_OP1_MASK, 893 (reg >> SYSREG_OP2_SHIFT) & SYSREG_OP2_MASK); 894 } 895 896 static bool hvf_sysreg_read_cp(CPUState *cpu, uint32_t reg, uint64_t *val) 897 { 898 ARMCPU *arm_cpu = ARM_CPU(cpu); 899 CPUARMState *env = &arm_cpu->env; 900 const ARMCPRegInfo *ri; 901 902 ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg)); 903 if (ri) { 904 if (ri->accessfn) { 905 if (ri->accessfn(env, ri, true) != CP_ACCESS_OK) { 906 return false; 907 } 908 } 909 if (ri->type & ARM_CP_CONST) { 910 *val = ri->resetvalue; 911 } else if (ri->readfn) { 912 *val = ri->readfn(env, ri); 913 } else { 914 *val = CPREG_FIELD64(env, ri); 915 } 916 trace_hvf_vgic_read(ri->name, *val); 917 return true; 918 } 919 920 return false; 921 } 922 923 static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt) 924 { 925 ARMCPU *arm_cpu = ARM_CPU(cpu); 926 CPUARMState *env = &arm_cpu->env; 927 uint64_t val = 0; 928 929 switch (reg) { 930 case SYSREG_CNTPCT_EL0: 931 val = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / 932 gt_cntfrq_period_ns(arm_cpu); 933 break; 934 case SYSREG_PMCR_EL0: 935 val = env->cp15.c9_pmcr; 936 break; 937 case SYSREG_PMCCNTR_EL0: 938 pmu_op_start(env); 939 val = env->cp15.c15_ccnt; 940 pmu_op_finish(env); 941 break; 942 case SYSREG_PMCNTENCLR_EL0: 943 val = env->cp15.c9_pmcnten; 944 break; 945 case SYSREG_PMOVSCLR_EL0: 946 val = env->cp15.c9_pmovsr; 947 break; 948 case SYSREG_PMSELR_EL0: 949 val = env->cp15.c9_pmselr; 950 break; 951 case SYSREG_PMINTENCLR_EL1: 952 val = env->cp15.c9_pminten; 953 break; 954 case SYSREG_PMCCFILTR_EL0: 955 val = env->cp15.pmccfiltr_el0; 956 break; 957 case SYSREG_PMCNTENSET_EL0: 958 val = env->cp15.c9_pmcnten; 959 break; 960 case SYSREG_PMUSERENR_EL0: 961 val = env->cp15.c9_pmuserenr; 962 break; 963 case SYSREG_PMCEID0_EL0: 964 case SYSREG_PMCEID1_EL0: 965 /* We can't really count anything yet, declare all events invalid */ 966 val = 0; 967 break; 968 case SYSREG_OSLSR_EL1: 969 val = env->cp15.oslsr_el1; 970 break; 971 case SYSREG_OSDLR_EL1: 972 /* Dummy register */ 973 break; 974 case SYSREG_ICC_AP0R0_EL1: 975 case SYSREG_ICC_AP0R1_EL1: 976 case SYSREG_ICC_AP0R2_EL1: 977 case SYSREG_ICC_AP0R3_EL1: 978 case SYSREG_ICC_AP1R0_EL1: 979 case SYSREG_ICC_AP1R1_EL1: 980 case SYSREG_ICC_AP1R2_EL1: 981 case SYSREG_ICC_AP1R3_EL1: 982 case SYSREG_ICC_ASGI1R_EL1: 983 case SYSREG_ICC_BPR0_EL1: 984 case SYSREG_ICC_BPR1_EL1: 985 case SYSREG_ICC_DIR_EL1: 986 case SYSREG_ICC_EOIR0_EL1: 987 case SYSREG_ICC_EOIR1_EL1: 988 case SYSREG_ICC_HPPIR0_EL1: 989 case SYSREG_ICC_HPPIR1_EL1: 990 case SYSREG_ICC_IAR0_EL1: 991 case SYSREG_ICC_IAR1_EL1: 992 case SYSREG_ICC_IGRPEN0_EL1: 993 case SYSREG_ICC_IGRPEN1_EL1: 994 case SYSREG_ICC_PMR_EL1: 995 case SYSREG_ICC_SGI0R_EL1: 996 case SYSREG_ICC_SGI1R_EL1: 997 case SYSREG_ICC_SRE_EL1: 998 case SYSREG_ICC_CTLR_EL1: 999 /* Call the TCG sysreg handler. This is only safe for GICv3 regs. */ 1000 if (!hvf_sysreg_read_cp(cpu, reg, &val)) { 1001 hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); 1002 } 1003 break; 1004 case SYSREG_DBGBVR0_EL1: 1005 case SYSREG_DBGBVR1_EL1: 1006 case SYSREG_DBGBVR2_EL1: 1007 case SYSREG_DBGBVR3_EL1: 1008 case SYSREG_DBGBVR4_EL1: 1009 case SYSREG_DBGBVR5_EL1: 1010 case SYSREG_DBGBVR6_EL1: 1011 case SYSREG_DBGBVR7_EL1: 1012 case SYSREG_DBGBVR8_EL1: 1013 case SYSREG_DBGBVR9_EL1: 1014 case SYSREG_DBGBVR10_EL1: 1015 case SYSREG_DBGBVR11_EL1: 1016 case SYSREG_DBGBVR12_EL1: 1017 case SYSREG_DBGBVR13_EL1: 1018 case SYSREG_DBGBVR14_EL1: 1019 case SYSREG_DBGBVR15_EL1: 1020 val = env->cp15.dbgbvr[SYSREG_CRM(reg)]; 1021 break; 1022 case SYSREG_DBGBCR0_EL1: 1023 case SYSREG_DBGBCR1_EL1: 1024 case SYSREG_DBGBCR2_EL1: 1025 case SYSREG_DBGBCR3_EL1: 1026 case SYSREG_DBGBCR4_EL1: 1027 case SYSREG_DBGBCR5_EL1: 1028 case SYSREG_DBGBCR6_EL1: 1029 case SYSREG_DBGBCR7_EL1: 1030 case SYSREG_DBGBCR8_EL1: 1031 case SYSREG_DBGBCR9_EL1: 1032 case SYSREG_DBGBCR10_EL1: 1033 case SYSREG_DBGBCR11_EL1: 1034 case SYSREG_DBGBCR12_EL1: 1035 case SYSREG_DBGBCR13_EL1: 1036 case SYSREG_DBGBCR14_EL1: 1037 case SYSREG_DBGBCR15_EL1: 1038 val = env->cp15.dbgbcr[SYSREG_CRM(reg)]; 1039 break; 1040 case SYSREG_DBGWVR0_EL1: 1041 case SYSREG_DBGWVR1_EL1: 1042 case SYSREG_DBGWVR2_EL1: 1043 case SYSREG_DBGWVR3_EL1: 1044 case SYSREG_DBGWVR4_EL1: 1045 case SYSREG_DBGWVR5_EL1: 1046 case SYSREG_DBGWVR6_EL1: 1047 case SYSREG_DBGWVR7_EL1: 1048 case SYSREG_DBGWVR8_EL1: 1049 case SYSREG_DBGWVR9_EL1: 1050 case SYSREG_DBGWVR10_EL1: 1051 case SYSREG_DBGWVR11_EL1: 1052 case SYSREG_DBGWVR12_EL1: 1053 case SYSREG_DBGWVR13_EL1: 1054 case SYSREG_DBGWVR14_EL1: 1055 case SYSREG_DBGWVR15_EL1: 1056 val = env->cp15.dbgwvr[SYSREG_CRM(reg)]; 1057 break; 1058 case SYSREG_DBGWCR0_EL1: 1059 case SYSREG_DBGWCR1_EL1: 1060 case SYSREG_DBGWCR2_EL1: 1061 case SYSREG_DBGWCR3_EL1: 1062 case SYSREG_DBGWCR4_EL1: 1063 case SYSREG_DBGWCR5_EL1: 1064 case SYSREG_DBGWCR6_EL1: 1065 case SYSREG_DBGWCR7_EL1: 1066 case SYSREG_DBGWCR8_EL1: 1067 case SYSREG_DBGWCR9_EL1: 1068 case SYSREG_DBGWCR10_EL1: 1069 case SYSREG_DBGWCR11_EL1: 1070 case SYSREG_DBGWCR12_EL1: 1071 case SYSREG_DBGWCR13_EL1: 1072 case SYSREG_DBGWCR14_EL1: 1073 case SYSREG_DBGWCR15_EL1: 1074 val = env->cp15.dbgwcr[SYSREG_CRM(reg)]; 1075 break; 1076 default: 1077 if (is_id_sysreg(reg)) { 1078 /* ID system registers read as RES0 */ 1079 val = 0; 1080 break; 1081 } 1082 cpu_synchronize_state(cpu); 1083 trace_hvf_unhandled_sysreg_read(env->pc, reg, 1084 SYSREG_OP0(reg), 1085 SYSREG_OP1(reg), 1086 SYSREG_CRN(reg), 1087 SYSREG_CRM(reg), 1088 SYSREG_OP2(reg)); 1089 hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); 1090 return 1; 1091 } 1092 1093 trace_hvf_sysreg_read(reg, 1094 SYSREG_OP0(reg), 1095 SYSREG_OP1(reg), 1096 SYSREG_CRN(reg), 1097 SYSREG_CRM(reg), 1098 SYSREG_OP2(reg), 1099 val); 1100 hvf_set_reg(cpu, rt, val); 1101 1102 return 0; 1103 } 1104 1105 static void pmu_update_irq(CPUARMState *env) 1106 { 1107 ARMCPU *cpu = env_archcpu(env); 1108 qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) && 1109 (env->cp15.c9_pminten & env->cp15.c9_pmovsr)); 1110 } 1111 1112 static bool pmu_event_supported(uint16_t number) 1113 { 1114 return false; 1115 } 1116 1117 /* Returns true if the counter (pass 31 for PMCCNTR) should count events using 1118 * the current EL, security state, and register configuration. 1119 */ 1120 static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter) 1121 { 1122 uint64_t filter; 1123 bool enabled, filtered = true; 1124 int el = arm_current_el(env); 1125 1126 enabled = (env->cp15.c9_pmcr & PMCRE) && 1127 (env->cp15.c9_pmcnten & (1 << counter)); 1128 1129 if (counter == 31) { 1130 filter = env->cp15.pmccfiltr_el0; 1131 } else { 1132 filter = env->cp15.c14_pmevtyper[counter]; 1133 } 1134 1135 if (el == 0) { 1136 filtered = filter & PMXEVTYPER_U; 1137 } else if (el == 1) { 1138 filtered = filter & PMXEVTYPER_P; 1139 } 1140 1141 if (counter != 31) { 1142 /* 1143 * If not checking PMCCNTR, ensure the counter is setup to an event we 1144 * support 1145 */ 1146 uint16_t event = filter & PMXEVTYPER_EVTCOUNT; 1147 if (!pmu_event_supported(event)) { 1148 return false; 1149 } 1150 } 1151 1152 return enabled && !filtered; 1153 } 1154 1155 static void pmswinc_write(CPUARMState *env, uint64_t value) 1156 { 1157 unsigned int i; 1158 for (i = 0; i < pmu_num_counters(env); i++) { 1159 /* Increment a counter's count iff: */ 1160 if ((value & (1 << i)) && /* counter's bit is set */ 1161 /* counter is enabled and not filtered */ 1162 pmu_counter_enabled(env, i) && 1163 /* counter is SW_INCR */ 1164 (env->cp15.c14_pmevtyper[i] & PMXEVTYPER_EVTCOUNT) == 0x0) { 1165 /* 1166 * Detect if this write causes an overflow since we can't predict 1167 * PMSWINC overflows like we can for other events 1168 */ 1169 uint32_t new_pmswinc = env->cp15.c14_pmevcntr[i] + 1; 1170 1171 if (env->cp15.c14_pmevcntr[i] & ~new_pmswinc & INT32_MIN) { 1172 env->cp15.c9_pmovsr |= (1 << i); 1173 pmu_update_irq(env); 1174 } 1175 1176 env->cp15.c14_pmevcntr[i] = new_pmswinc; 1177 } 1178 } 1179 } 1180 1181 static bool hvf_sysreg_write_cp(CPUState *cpu, uint32_t reg, uint64_t val) 1182 { 1183 ARMCPU *arm_cpu = ARM_CPU(cpu); 1184 CPUARMState *env = &arm_cpu->env; 1185 const ARMCPRegInfo *ri; 1186 1187 ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg)); 1188 1189 if (ri) { 1190 if (ri->accessfn) { 1191 if (ri->accessfn(env, ri, false) != CP_ACCESS_OK) { 1192 return false; 1193 } 1194 } 1195 if (ri->writefn) { 1196 ri->writefn(env, ri, val); 1197 } else { 1198 CPREG_FIELD64(env, ri) = val; 1199 } 1200 1201 trace_hvf_vgic_write(ri->name, val); 1202 return true; 1203 } 1204 1205 return false; 1206 } 1207 1208 static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) 1209 { 1210 ARMCPU *arm_cpu = ARM_CPU(cpu); 1211 CPUARMState *env = &arm_cpu->env; 1212 1213 trace_hvf_sysreg_write(reg, 1214 SYSREG_OP0(reg), 1215 SYSREG_OP1(reg), 1216 SYSREG_CRN(reg), 1217 SYSREG_CRM(reg), 1218 SYSREG_OP2(reg), 1219 val); 1220 1221 switch (reg) { 1222 case SYSREG_PMCCNTR_EL0: 1223 pmu_op_start(env); 1224 env->cp15.c15_ccnt = val; 1225 pmu_op_finish(env); 1226 break; 1227 case SYSREG_PMCR_EL0: 1228 pmu_op_start(env); 1229 1230 if (val & PMCRC) { 1231 /* The counter has been reset */ 1232 env->cp15.c15_ccnt = 0; 1233 } 1234 1235 if (val & PMCRP) { 1236 unsigned int i; 1237 for (i = 0; i < pmu_num_counters(env); i++) { 1238 env->cp15.c14_pmevcntr[i] = 0; 1239 } 1240 } 1241 1242 env->cp15.c9_pmcr &= ~PMCR_WRITABLE_MASK; 1243 env->cp15.c9_pmcr |= (val & PMCR_WRITABLE_MASK); 1244 1245 pmu_op_finish(env); 1246 break; 1247 case SYSREG_PMUSERENR_EL0: 1248 env->cp15.c9_pmuserenr = val & 0xf; 1249 break; 1250 case SYSREG_PMCNTENSET_EL0: 1251 env->cp15.c9_pmcnten |= (val & pmu_counter_mask(env)); 1252 break; 1253 case SYSREG_PMCNTENCLR_EL0: 1254 env->cp15.c9_pmcnten &= ~(val & pmu_counter_mask(env)); 1255 break; 1256 case SYSREG_PMINTENCLR_EL1: 1257 pmu_op_start(env); 1258 env->cp15.c9_pminten |= val; 1259 pmu_op_finish(env); 1260 break; 1261 case SYSREG_PMOVSCLR_EL0: 1262 pmu_op_start(env); 1263 env->cp15.c9_pmovsr &= ~val; 1264 pmu_op_finish(env); 1265 break; 1266 case SYSREG_PMSWINC_EL0: 1267 pmu_op_start(env); 1268 pmswinc_write(env, val); 1269 pmu_op_finish(env); 1270 break; 1271 case SYSREG_PMSELR_EL0: 1272 env->cp15.c9_pmselr = val & 0x1f; 1273 break; 1274 case SYSREG_PMCCFILTR_EL0: 1275 pmu_op_start(env); 1276 env->cp15.pmccfiltr_el0 = val & PMCCFILTR_EL0; 1277 pmu_op_finish(env); 1278 break; 1279 case SYSREG_OSLAR_EL1: 1280 env->cp15.oslsr_el1 = val & 1; 1281 break; 1282 case SYSREG_OSDLR_EL1: 1283 /* Dummy register */ 1284 break; 1285 case SYSREG_ICC_AP0R0_EL1: 1286 case SYSREG_ICC_AP0R1_EL1: 1287 case SYSREG_ICC_AP0R2_EL1: 1288 case SYSREG_ICC_AP0R3_EL1: 1289 case SYSREG_ICC_AP1R0_EL1: 1290 case SYSREG_ICC_AP1R1_EL1: 1291 case SYSREG_ICC_AP1R2_EL1: 1292 case SYSREG_ICC_AP1R3_EL1: 1293 case SYSREG_ICC_ASGI1R_EL1: 1294 case SYSREG_ICC_BPR0_EL1: 1295 case SYSREG_ICC_BPR1_EL1: 1296 case SYSREG_ICC_CTLR_EL1: 1297 case SYSREG_ICC_DIR_EL1: 1298 case SYSREG_ICC_EOIR0_EL1: 1299 case SYSREG_ICC_EOIR1_EL1: 1300 case SYSREG_ICC_HPPIR0_EL1: 1301 case SYSREG_ICC_HPPIR1_EL1: 1302 case SYSREG_ICC_IAR0_EL1: 1303 case SYSREG_ICC_IAR1_EL1: 1304 case SYSREG_ICC_IGRPEN0_EL1: 1305 case SYSREG_ICC_IGRPEN1_EL1: 1306 case SYSREG_ICC_PMR_EL1: 1307 case SYSREG_ICC_SGI0R_EL1: 1308 case SYSREG_ICC_SGI1R_EL1: 1309 case SYSREG_ICC_SRE_EL1: 1310 /* Call the TCG sysreg handler. This is only safe for GICv3 regs. */ 1311 if (!hvf_sysreg_write_cp(cpu, reg, val)) { 1312 hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); 1313 } 1314 break; 1315 case SYSREG_MDSCR_EL1: 1316 env->cp15.mdscr_el1 = val; 1317 break; 1318 case SYSREG_DBGBVR0_EL1: 1319 case SYSREG_DBGBVR1_EL1: 1320 case SYSREG_DBGBVR2_EL1: 1321 case SYSREG_DBGBVR3_EL1: 1322 case SYSREG_DBGBVR4_EL1: 1323 case SYSREG_DBGBVR5_EL1: 1324 case SYSREG_DBGBVR6_EL1: 1325 case SYSREG_DBGBVR7_EL1: 1326 case SYSREG_DBGBVR8_EL1: 1327 case SYSREG_DBGBVR9_EL1: 1328 case SYSREG_DBGBVR10_EL1: 1329 case SYSREG_DBGBVR11_EL1: 1330 case SYSREG_DBGBVR12_EL1: 1331 case SYSREG_DBGBVR13_EL1: 1332 case SYSREG_DBGBVR14_EL1: 1333 case SYSREG_DBGBVR15_EL1: 1334 env->cp15.dbgbvr[SYSREG_CRM(reg)] = val; 1335 break; 1336 case SYSREG_DBGBCR0_EL1: 1337 case SYSREG_DBGBCR1_EL1: 1338 case SYSREG_DBGBCR2_EL1: 1339 case SYSREG_DBGBCR3_EL1: 1340 case SYSREG_DBGBCR4_EL1: 1341 case SYSREG_DBGBCR5_EL1: 1342 case SYSREG_DBGBCR6_EL1: 1343 case SYSREG_DBGBCR7_EL1: 1344 case SYSREG_DBGBCR8_EL1: 1345 case SYSREG_DBGBCR9_EL1: 1346 case SYSREG_DBGBCR10_EL1: 1347 case SYSREG_DBGBCR11_EL1: 1348 case SYSREG_DBGBCR12_EL1: 1349 case SYSREG_DBGBCR13_EL1: 1350 case SYSREG_DBGBCR14_EL1: 1351 case SYSREG_DBGBCR15_EL1: 1352 env->cp15.dbgbcr[SYSREG_CRM(reg)] = val; 1353 break; 1354 case SYSREG_DBGWVR0_EL1: 1355 case SYSREG_DBGWVR1_EL1: 1356 case SYSREG_DBGWVR2_EL1: 1357 case SYSREG_DBGWVR3_EL1: 1358 case SYSREG_DBGWVR4_EL1: 1359 case SYSREG_DBGWVR5_EL1: 1360 case SYSREG_DBGWVR6_EL1: 1361 case SYSREG_DBGWVR7_EL1: 1362 case SYSREG_DBGWVR8_EL1: 1363 case SYSREG_DBGWVR9_EL1: 1364 case SYSREG_DBGWVR10_EL1: 1365 case SYSREG_DBGWVR11_EL1: 1366 case SYSREG_DBGWVR12_EL1: 1367 case SYSREG_DBGWVR13_EL1: 1368 case SYSREG_DBGWVR14_EL1: 1369 case SYSREG_DBGWVR15_EL1: 1370 env->cp15.dbgwvr[SYSREG_CRM(reg)] = val; 1371 break; 1372 case SYSREG_DBGWCR0_EL1: 1373 case SYSREG_DBGWCR1_EL1: 1374 case SYSREG_DBGWCR2_EL1: 1375 case SYSREG_DBGWCR3_EL1: 1376 case SYSREG_DBGWCR4_EL1: 1377 case SYSREG_DBGWCR5_EL1: 1378 case SYSREG_DBGWCR6_EL1: 1379 case SYSREG_DBGWCR7_EL1: 1380 case SYSREG_DBGWCR8_EL1: 1381 case SYSREG_DBGWCR9_EL1: 1382 case SYSREG_DBGWCR10_EL1: 1383 case SYSREG_DBGWCR11_EL1: 1384 case SYSREG_DBGWCR12_EL1: 1385 case SYSREG_DBGWCR13_EL1: 1386 case SYSREG_DBGWCR14_EL1: 1387 case SYSREG_DBGWCR15_EL1: 1388 env->cp15.dbgwcr[SYSREG_CRM(reg)] = val; 1389 break; 1390 default: 1391 cpu_synchronize_state(cpu); 1392 trace_hvf_unhandled_sysreg_write(env->pc, reg, 1393 SYSREG_OP0(reg), 1394 SYSREG_OP1(reg), 1395 SYSREG_CRN(reg), 1396 SYSREG_CRM(reg), 1397 SYSREG_OP2(reg)); 1398 hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); 1399 return 1; 1400 } 1401 1402 return 0; 1403 } 1404 1405 static int hvf_inject_interrupts(CPUState *cpu) 1406 { 1407 if (cpu->interrupt_request & CPU_INTERRUPT_FIQ) { 1408 trace_hvf_inject_fiq(); 1409 hv_vcpu_set_pending_interrupt(cpu->hvf->fd, HV_INTERRUPT_TYPE_FIQ, 1410 true); 1411 } 1412 1413 if (cpu->interrupt_request & CPU_INTERRUPT_HARD) { 1414 trace_hvf_inject_irq(); 1415 hv_vcpu_set_pending_interrupt(cpu->hvf->fd, HV_INTERRUPT_TYPE_IRQ, 1416 true); 1417 } 1418 1419 return 0; 1420 } 1421 1422 static uint64_t hvf_vtimer_val_raw(void) 1423 { 1424 /* 1425 * mach_absolute_time() returns the vtimer value without the VM 1426 * offset that we define. Add our own offset on top. 1427 */ 1428 return mach_absolute_time() - hvf_state->vtimer_offset; 1429 } 1430 1431 static uint64_t hvf_vtimer_val(void) 1432 { 1433 if (!runstate_is_running()) { 1434 /* VM is paused, the vtimer value is in vtimer.vtimer_val */ 1435 return vtimer.vtimer_val; 1436 } 1437 1438 return hvf_vtimer_val_raw(); 1439 } 1440 1441 static void hvf_wait_for_ipi(CPUState *cpu, struct timespec *ts) 1442 { 1443 /* 1444 * Use pselect to sleep so that other threads can IPI us while we're 1445 * sleeping. 1446 */ 1447 qatomic_mb_set(&cpu->thread_kicked, false); 1448 qemu_mutex_unlock_iothread(); 1449 pselect(0, 0, 0, 0, ts, &cpu->hvf->unblock_ipi_mask); 1450 qemu_mutex_lock_iothread(); 1451 } 1452 1453 static void hvf_wfi(CPUState *cpu) 1454 { 1455 ARMCPU *arm_cpu = ARM_CPU(cpu); 1456 struct timespec ts; 1457 hv_return_t r; 1458 uint64_t ctl; 1459 uint64_t cval; 1460 int64_t ticks_to_sleep; 1461 uint64_t seconds; 1462 uint64_t nanos; 1463 uint32_t cntfrq; 1464 1465 if (cpu->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIQ)) { 1466 /* Interrupt pending, no need to wait */ 1467 return; 1468 } 1469 1470 r = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_CNTV_CTL_EL0, &ctl); 1471 assert_hvf_ok(r); 1472 1473 if (!(ctl & 1) || (ctl & 2)) { 1474 /* Timer disabled or masked, just wait for an IPI. */ 1475 hvf_wait_for_ipi(cpu, NULL); 1476 return; 1477 } 1478 1479 r = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_CNTV_CVAL_EL0, &cval); 1480 assert_hvf_ok(r); 1481 1482 ticks_to_sleep = cval - hvf_vtimer_val(); 1483 if (ticks_to_sleep < 0) { 1484 return; 1485 } 1486 1487 cntfrq = gt_cntfrq_period_ns(arm_cpu); 1488 seconds = muldiv64(ticks_to_sleep, cntfrq, NANOSECONDS_PER_SECOND); 1489 ticks_to_sleep -= muldiv64(seconds, NANOSECONDS_PER_SECOND, cntfrq); 1490 nanos = ticks_to_sleep * cntfrq; 1491 1492 /* 1493 * Don't sleep for less than the time a context switch would take, 1494 * so that we can satisfy fast timer requests on the same CPU. 1495 * Measurements on M1 show the sweet spot to be ~2ms. 1496 */ 1497 if (!seconds && nanos < (2 * SCALE_MS)) { 1498 return; 1499 } 1500 1501 ts = (struct timespec) { seconds, nanos }; 1502 hvf_wait_for_ipi(cpu, &ts); 1503 } 1504 1505 static void hvf_sync_vtimer(CPUState *cpu) 1506 { 1507 ARMCPU *arm_cpu = ARM_CPU(cpu); 1508 hv_return_t r; 1509 uint64_t ctl; 1510 bool irq_state; 1511 1512 if (!cpu->hvf->vtimer_masked) { 1513 /* We will get notified on vtimer changes by hvf, nothing to do */ 1514 return; 1515 } 1516 1517 r = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_CNTV_CTL_EL0, &ctl); 1518 assert_hvf_ok(r); 1519 1520 irq_state = (ctl & (TMR_CTL_ENABLE | TMR_CTL_IMASK | TMR_CTL_ISTATUS)) == 1521 (TMR_CTL_ENABLE | TMR_CTL_ISTATUS); 1522 qemu_set_irq(arm_cpu->gt_timer_outputs[GTIMER_VIRT], irq_state); 1523 1524 if (!irq_state) { 1525 /* Timer no longer asserting, we can unmask it */ 1526 hv_vcpu_set_vtimer_mask(cpu->hvf->fd, false); 1527 cpu->hvf->vtimer_masked = false; 1528 } 1529 } 1530 1531 int hvf_vcpu_exec(CPUState *cpu) 1532 { 1533 ARMCPU *arm_cpu = ARM_CPU(cpu); 1534 CPUARMState *env = &arm_cpu->env; 1535 hv_vcpu_exit_t *hvf_exit = cpu->hvf->exit; 1536 hv_return_t r; 1537 bool advance_pc = false; 1538 1539 if (hvf_inject_interrupts(cpu)) { 1540 return EXCP_INTERRUPT; 1541 } 1542 1543 if (cpu->halted) { 1544 return EXCP_HLT; 1545 } 1546 1547 flush_cpu_state(cpu); 1548 1549 qemu_mutex_unlock_iothread(); 1550 assert_hvf_ok(hv_vcpu_run(cpu->hvf->fd)); 1551 1552 /* handle VMEXIT */ 1553 uint64_t exit_reason = hvf_exit->reason; 1554 uint64_t syndrome = hvf_exit->exception.syndrome; 1555 uint32_t ec = syn_get_ec(syndrome); 1556 1557 qemu_mutex_lock_iothread(); 1558 switch (exit_reason) { 1559 case HV_EXIT_REASON_EXCEPTION: 1560 /* This is the main one, handle below. */ 1561 break; 1562 case HV_EXIT_REASON_VTIMER_ACTIVATED: 1563 qemu_set_irq(arm_cpu->gt_timer_outputs[GTIMER_VIRT], 1); 1564 cpu->hvf->vtimer_masked = true; 1565 return 0; 1566 case HV_EXIT_REASON_CANCELED: 1567 /* we got kicked, no exit to process */ 1568 return 0; 1569 default: 1570 g_assert_not_reached(); 1571 } 1572 1573 hvf_sync_vtimer(cpu); 1574 1575 switch (ec) { 1576 case EC_DATAABORT: { 1577 bool isv = syndrome & ARM_EL_ISV; 1578 bool iswrite = (syndrome >> 6) & 1; 1579 bool s1ptw = (syndrome >> 7) & 1; 1580 uint32_t sas = (syndrome >> 22) & 3; 1581 uint32_t len = 1 << sas; 1582 uint32_t srt = (syndrome >> 16) & 0x1f; 1583 uint32_t cm = (syndrome >> 8) & 0x1; 1584 uint64_t val = 0; 1585 1586 trace_hvf_data_abort(env->pc, hvf_exit->exception.virtual_address, 1587 hvf_exit->exception.physical_address, isv, 1588 iswrite, s1ptw, len, srt); 1589 1590 if (cm) { 1591 /* We don't cache MMIO regions */ 1592 advance_pc = true; 1593 break; 1594 } 1595 1596 assert(isv); 1597 1598 if (iswrite) { 1599 val = hvf_get_reg(cpu, srt); 1600 address_space_write(&address_space_memory, 1601 hvf_exit->exception.physical_address, 1602 MEMTXATTRS_UNSPECIFIED, &val, len); 1603 } else { 1604 address_space_read(&address_space_memory, 1605 hvf_exit->exception.physical_address, 1606 MEMTXATTRS_UNSPECIFIED, &val, len); 1607 hvf_set_reg(cpu, srt, val); 1608 } 1609 1610 advance_pc = true; 1611 break; 1612 } 1613 case EC_SYSTEMREGISTERTRAP: { 1614 bool isread = (syndrome >> 0) & 1; 1615 uint32_t rt = (syndrome >> 5) & 0x1f; 1616 uint32_t reg = syndrome & SYSREG_MASK; 1617 uint64_t val; 1618 int ret = 0; 1619 1620 if (isread) { 1621 ret = hvf_sysreg_read(cpu, reg, rt); 1622 } else { 1623 val = hvf_get_reg(cpu, rt); 1624 ret = hvf_sysreg_write(cpu, reg, val); 1625 } 1626 1627 advance_pc = !ret; 1628 break; 1629 } 1630 case EC_WFX_TRAP: 1631 advance_pc = true; 1632 if (!(syndrome & WFX_IS_WFE)) { 1633 hvf_wfi(cpu); 1634 } 1635 break; 1636 case EC_AA64_HVC: 1637 cpu_synchronize_state(cpu); 1638 if (arm_cpu->psci_conduit == QEMU_PSCI_CONDUIT_HVC) { 1639 if (!hvf_handle_psci_call(cpu)) { 1640 trace_hvf_unknown_hvc(env->xregs[0]); 1641 /* SMCCC 1.3 section 5.2 says every unknown SMCCC call returns -1 */ 1642 env->xregs[0] = -1; 1643 } 1644 } else { 1645 trace_hvf_unknown_hvc(env->xregs[0]); 1646 hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); 1647 } 1648 break; 1649 case EC_AA64_SMC: 1650 cpu_synchronize_state(cpu); 1651 if (arm_cpu->psci_conduit == QEMU_PSCI_CONDUIT_SMC) { 1652 advance_pc = true; 1653 1654 if (!hvf_handle_psci_call(cpu)) { 1655 trace_hvf_unknown_smc(env->xregs[0]); 1656 /* SMCCC 1.3 section 5.2 says every unknown SMCCC call returns -1 */ 1657 env->xregs[0] = -1; 1658 } 1659 } else { 1660 trace_hvf_unknown_smc(env->xregs[0]); 1661 hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); 1662 } 1663 break; 1664 default: 1665 cpu_synchronize_state(cpu); 1666 trace_hvf_exit(syndrome, ec, env->pc); 1667 error_report("0x%llx: unhandled exception ec=0x%x", env->pc, ec); 1668 } 1669 1670 if (advance_pc) { 1671 uint64_t pc; 1672 1673 flush_cpu_state(cpu); 1674 1675 r = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_PC, &pc); 1676 assert_hvf_ok(r); 1677 pc += 4; 1678 r = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_PC, pc); 1679 assert_hvf_ok(r); 1680 } 1681 1682 return 0; 1683 } 1684 1685 static const VMStateDescription vmstate_hvf_vtimer = { 1686 .name = "hvf-vtimer", 1687 .version_id = 1, 1688 .minimum_version_id = 1, 1689 .fields = (VMStateField[]) { 1690 VMSTATE_UINT64(vtimer_val, HVFVTimer), 1691 VMSTATE_END_OF_LIST() 1692 }, 1693 }; 1694 1695 static void hvf_vm_state_change(void *opaque, bool running, RunState state) 1696 { 1697 HVFVTimer *s = opaque; 1698 1699 if (running) { 1700 /* Update vtimer offset on all CPUs */ 1701 hvf_state->vtimer_offset = mach_absolute_time() - s->vtimer_val; 1702 cpu_synchronize_all_states(); 1703 } else { 1704 /* Remember vtimer value on every pause */ 1705 s->vtimer_val = hvf_vtimer_val_raw(); 1706 } 1707 } 1708 1709 int hvf_arch_init(void) 1710 { 1711 hvf_state->vtimer_offset = mach_absolute_time(); 1712 vmstate_register(NULL, 0, &vmstate_hvf_vtimer, &vtimer); 1713 qemu_add_vm_change_state_handler(hvf_vm_state_change, &vtimer); 1714 return 0; 1715 } 1716 1717 static const uint32_t brk_insn = 0xd4200000; 1718 1719 int hvf_arch_insert_sw_breakpoint(CPUState *cpu, struct hvf_sw_breakpoint *bp) 1720 { 1721 if (cpu_memory_rw_debug(cpu, bp->pc, (uint8_t *)&bp->saved_insn, 4, 0) || 1722 cpu_memory_rw_debug(cpu, bp->pc, (uint8_t *)&brk_insn, 4, 1)) { 1723 return -EINVAL; 1724 } 1725 return 0; 1726 } 1727 1728 int hvf_arch_remove_sw_breakpoint(CPUState *cpu, struct hvf_sw_breakpoint *bp) 1729 { 1730 static uint32_t brk; 1731 1732 if (cpu_memory_rw_debug(cpu, bp->pc, (uint8_t *)&brk, 4, 0) || 1733 brk != brk_insn || 1734 cpu_memory_rw_debug(cpu, bp->pc, (uint8_t *)&bp->saved_insn, 4, 1)) { 1735 return -EINVAL; 1736 } 1737 return 0; 1738 } 1739 1740 int hvf_arch_insert_hw_breakpoint(target_ulong addr, target_ulong len, int type) 1741 { 1742 switch (type) { 1743 case GDB_BREAKPOINT_HW: 1744 return insert_hw_breakpoint(addr); 1745 case GDB_WATCHPOINT_READ: 1746 case GDB_WATCHPOINT_WRITE: 1747 case GDB_WATCHPOINT_ACCESS: 1748 return insert_hw_watchpoint(addr, len, type); 1749 default: 1750 return -ENOSYS; 1751 } 1752 } 1753 1754 int hvf_arch_remove_hw_breakpoint(target_ulong addr, target_ulong len, int type) 1755 { 1756 switch (type) { 1757 case GDB_BREAKPOINT_HW: 1758 return delete_hw_breakpoint(addr); 1759 case GDB_WATCHPOINT_READ: 1760 case GDB_WATCHPOINT_WRITE: 1761 case GDB_WATCHPOINT_ACCESS: 1762 return delete_hw_watchpoint(addr, len, type); 1763 default: 1764 return -ENOSYS; 1765 } 1766 } 1767 1768 void hvf_arch_remove_all_hw_breakpoints(void) 1769 { 1770 if (cur_hw_wps > 0) { 1771 g_array_remove_range(hw_watchpoints, 0, cur_hw_wps); 1772 } 1773 if (cur_hw_bps > 0) { 1774 g_array_remove_range(hw_breakpoints, 0, cur_hw_bps); 1775 } 1776 } 1777