1 /* 2 * QEMU Hypervisor.framework support for Apple Silicon 3 4 * Copyright 2020 Alexander Graf <agraf@csgraf.de> 5 * Copyright 2020 Google LLC 6 * 7 * This work is licensed under the terms of the GNU GPL, version 2 or later. 8 * See the COPYING file in the top-level directory. 9 * 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qemu/error-report.h" 14 15 #include "sysemu/runstate.h" 16 #include "sysemu/hvf.h" 17 #include "sysemu/hvf_int.h" 18 #include "sysemu/hw_accel.h" 19 #include "hvf_arm.h" 20 #include "cpregs.h" 21 22 #include <mach/mach_time.h> 23 24 #include "exec/address-spaces.h" 25 #include "hw/irq.h" 26 #include "qemu/main-loop.h" 27 #include "sysemu/cpus.h" 28 #include "arm-powerctl.h" 29 #include "target/arm/cpu.h" 30 #include "target/arm/internals.h" 31 #include "target/arm/multiprocessing.h" 32 #include "target/arm/gtimer.h" 33 #include "trace/trace-target_arm_hvf.h" 34 #include "migration/vmstate.h" 35 36 #include "exec/gdbstub.h" 37 38 #define MDSCR_EL1_SS_SHIFT 0 39 #define MDSCR_EL1_MDE_SHIFT 15 40 41 static const uint16_t dbgbcr_regs[] = { 42 HV_SYS_REG_DBGBCR0_EL1, 43 HV_SYS_REG_DBGBCR1_EL1, 44 HV_SYS_REG_DBGBCR2_EL1, 45 HV_SYS_REG_DBGBCR3_EL1, 46 HV_SYS_REG_DBGBCR4_EL1, 47 HV_SYS_REG_DBGBCR5_EL1, 48 HV_SYS_REG_DBGBCR6_EL1, 49 HV_SYS_REG_DBGBCR7_EL1, 50 HV_SYS_REG_DBGBCR8_EL1, 51 HV_SYS_REG_DBGBCR9_EL1, 52 HV_SYS_REG_DBGBCR10_EL1, 53 HV_SYS_REG_DBGBCR11_EL1, 54 HV_SYS_REG_DBGBCR12_EL1, 55 HV_SYS_REG_DBGBCR13_EL1, 56 HV_SYS_REG_DBGBCR14_EL1, 57 HV_SYS_REG_DBGBCR15_EL1, 58 }; 59 60 static const uint16_t dbgbvr_regs[] = { 61 HV_SYS_REG_DBGBVR0_EL1, 62 HV_SYS_REG_DBGBVR1_EL1, 63 HV_SYS_REG_DBGBVR2_EL1, 64 HV_SYS_REG_DBGBVR3_EL1, 65 HV_SYS_REG_DBGBVR4_EL1, 66 HV_SYS_REG_DBGBVR5_EL1, 67 HV_SYS_REG_DBGBVR6_EL1, 68 HV_SYS_REG_DBGBVR7_EL1, 69 HV_SYS_REG_DBGBVR8_EL1, 70 HV_SYS_REG_DBGBVR9_EL1, 71 HV_SYS_REG_DBGBVR10_EL1, 72 HV_SYS_REG_DBGBVR11_EL1, 73 HV_SYS_REG_DBGBVR12_EL1, 74 HV_SYS_REG_DBGBVR13_EL1, 75 HV_SYS_REG_DBGBVR14_EL1, 76 HV_SYS_REG_DBGBVR15_EL1, 77 }; 78 79 static const uint16_t dbgwcr_regs[] = { 80 HV_SYS_REG_DBGWCR0_EL1, 81 HV_SYS_REG_DBGWCR1_EL1, 82 HV_SYS_REG_DBGWCR2_EL1, 83 HV_SYS_REG_DBGWCR3_EL1, 84 HV_SYS_REG_DBGWCR4_EL1, 85 HV_SYS_REG_DBGWCR5_EL1, 86 HV_SYS_REG_DBGWCR6_EL1, 87 HV_SYS_REG_DBGWCR7_EL1, 88 HV_SYS_REG_DBGWCR8_EL1, 89 HV_SYS_REG_DBGWCR9_EL1, 90 HV_SYS_REG_DBGWCR10_EL1, 91 HV_SYS_REG_DBGWCR11_EL1, 92 HV_SYS_REG_DBGWCR12_EL1, 93 HV_SYS_REG_DBGWCR13_EL1, 94 HV_SYS_REG_DBGWCR14_EL1, 95 HV_SYS_REG_DBGWCR15_EL1, 96 }; 97 98 static const uint16_t dbgwvr_regs[] = { 99 HV_SYS_REG_DBGWVR0_EL1, 100 HV_SYS_REG_DBGWVR1_EL1, 101 HV_SYS_REG_DBGWVR2_EL1, 102 HV_SYS_REG_DBGWVR3_EL1, 103 HV_SYS_REG_DBGWVR4_EL1, 104 HV_SYS_REG_DBGWVR5_EL1, 105 HV_SYS_REG_DBGWVR6_EL1, 106 HV_SYS_REG_DBGWVR7_EL1, 107 HV_SYS_REG_DBGWVR8_EL1, 108 HV_SYS_REG_DBGWVR9_EL1, 109 HV_SYS_REG_DBGWVR10_EL1, 110 HV_SYS_REG_DBGWVR11_EL1, 111 HV_SYS_REG_DBGWVR12_EL1, 112 HV_SYS_REG_DBGWVR13_EL1, 113 HV_SYS_REG_DBGWVR14_EL1, 114 HV_SYS_REG_DBGWVR15_EL1, 115 }; 116 117 static inline int hvf_arm_num_brps(hv_vcpu_config_t config) 118 { 119 uint64_t val; 120 hv_return_t ret; 121 ret = hv_vcpu_config_get_feature_reg(config, HV_FEATURE_REG_ID_AA64DFR0_EL1, 122 &val); 123 assert_hvf_ok(ret); 124 return FIELD_EX64(val, ID_AA64DFR0, BRPS) + 1; 125 } 126 127 static inline int hvf_arm_num_wrps(hv_vcpu_config_t config) 128 { 129 uint64_t val; 130 hv_return_t ret; 131 ret = hv_vcpu_config_get_feature_reg(config, HV_FEATURE_REG_ID_AA64DFR0_EL1, 132 &val); 133 assert_hvf_ok(ret); 134 return FIELD_EX64(val, ID_AA64DFR0, WRPS) + 1; 135 } 136 137 void hvf_arm_init_debug(void) 138 { 139 hv_vcpu_config_t config; 140 config = hv_vcpu_config_create(); 141 142 max_hw_bps = hvf_arm_num_brps(config); 143 hw_breakpoints = 144 g_array_sized_new(true, true, sizeof(HWBreakpoint), max_hw_bps); 145 146 max_hw_wps = hvf_arm_num_wrps(config); 147 hw_watchpoints = 148 g_array_sized_new(true, true, sizeof(HWWatchpoint), max_hw_wps); 149 } 150 151 #define HVF_SYSREG(crn, crm, op0, op1, op2) \ 152 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2) 153 #define PL1_WRITE_MASK 0x4 154 155 #define SYSREG_OP0_SHIFT 20 156 #define SYSREG_OP0_MASK 0x3 157 #define SYSREG_OP0(sysreg) ((sysreg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK) 158 #define SYSREG_OP1_SHIFT 14 159 #define SYSREG_OP1_MASK 0x7 160 #define SYSREG_OP1(sysreg) ((sysreg >> SYSREG_OP1_SHIFT) & SYSREG_OP1_MASK) 161 #define SYSREG_CRN_SHIFT 10 162 #define SYSREG_CRN_MASK 0xf 163 #define SYSREG_CRN(sysreg) ((sysreg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK) 164 #define SYSREG_CRM_SHIFT 1 165 #define SYSREG_CRM_MASK 0xf 166 #define SYSREG_CRM(sysreg) ((sysreg >> SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK) 167 #define SYSREG_OP2_SHIFT 17 168 #define SYSREG_OP2_MASK 0x7 169 #define SYSREG_OP2(sysreg) ((sysreg >> SYSREG_OP2_SHIFT) & SYSREG_OP2_MASK) 170 171 #define SYSREG(op0, op1, crn, crm, op2) \ 172 ((op0 << SYSREG_OP0_SHIFT) | \ 173 (op1 << SYSREG_OP1_SHIFT) | \ 174 (crn << SYSREG_CRN_SHIFT) | \ 175 (crm << SYSREG_CRM_SHIFT) | \ 176 (op2 << SYSREG_OP2_SHIFT)) 177 #define SYSREG_MASK \ 178 SYSREG(SYSREG_OP0_MASK, \ 179 SYSREG_OP1_MASK, \ 180 SYSREG_CRN_MASK, \ 181 SYSREG_CRM_MASK, \ 182 SYSREG_OP2_MASK) 183 #define SYSREG_OSLAR_EL1 SYSREG(2, 0, 1, 0, 4) 184 #define SYSREG_OSLSR_EL1 SYSREG(2, 0, 1, 1, 4) 185 #define SYSREG_OSDLR_EL1 SYSREG(2, 0, 1, 3, 4) 186 #define SYSREG_CNTPCT_EL0 SYSREG(3, 3, 14, 0, 1) 187 #define SYSREG_PMCR_EL0 SYSREG(3, 3, 9, 12, 0) 188 #define SYSREG_PMUSERENR_EL0 SYSREG(3, 3, 9, 14, 0) 189 #define SYSREG_PMCNTENSET_EL0 SYSREG(3, 3, 9, 12, 1) 190 #define SYSREG_PMCNTENCLR_EL0 SYSREG(3, 3, 9, 12, 2) 191 #define SYSREG_PMINTENCLR_EL1 SYSREG(3, 0, 9, 14, 2) 192 #define SYSREG_PMOVSCLR_EL0 SYSREG(3, 3, 9, 12, 3) 193 #define SYSREG_PMSWINC_EL0 SYSREG(3, 3, 9, 12, 4) 194 #define SYSREG_PMSELR_EL0 SYSREG(3, 3, 9, 12, 5) 195 #define SYSREG_PMCEID0_EL0 SYSREG(3, 3, 9, 12, 6) 196 #define SYSREG_PMCEID1_EL0 SYSREG(3, 3, 9, 12, 7) 197 #define SYSREG_PMCCNTR_EL0 SYSREG(3, 3, 9, 13, 0) 198 #define SYSREG_PMCCFILTR_EL0 SYSREG(3, 3, 14, 15, 7) 199 200 #define SYSREG_ICC_AP0R0_EL1 SYSREG(3, 0, 12, 8, 4) 201 #define SYSREG_ICC_AP0R1_EL1 SYSREG(3, 0, 12, 8, 5) 202 #define SYSREG_ICC_AP0R2_EL1 SYSREG(3, 0, 12, 8, 6) 203 #define SYSREG_ICC_AP0R3_EL1 SYSREG(3, 0, 12, 8, 7) 204 #define SYSREG_ICC_AP1R0_EL1 SYSREG(3, 0, 12, 9, 0) 205 #define SYSREG_ICC_AP1R1_EL1 SYSREG(3, 0, 12, 9, 1) 206 #define SYSREG_ICC_AP1R2_EL1 SYSREG(3, 0, 12, 9, 2) 207 #define SYSREG_ICC_AP1R3_EL1 SYSREG(3, 0, 12, 9, 3) 208 #define SYSREG_ICC_ASGI1R_EL1 SYSREG(3, 0, 12, 11, 6) 209 #define SYSREG_ICC_BPR0_EL1 SYSREG(3, 0, 12, 8, 3) 210 #define SYSREG_ICC_BPR1_EL1 SYSREG(3, 0, 12, 12, 3) 211 #define SYSREG_ICC_CTLR_EL1 SYSREG(3, 0, 12, 12, 4) 212 #define SYSREG_ICC_DIR_EL1 SYSREG(3, 0, 12, 11, 1) 213 #define SYSREG_ICC_EOIR0_EL1 SYSREG(3, 0, 12, 8, 1) 214 #define SYSREG_ICC_EOIR1_EL1 SYSREG(3, 0, 12, 12, 1) 215 #define SYSREG_ICC_HPPIR0_EL1 SYSREG(3, 0, 12, 8, 2) 216 #define SYSREG_ICC_HPPIR1_EL1 SYSREG(3, 0, 12, 12, 2) 217 #define SYSREG_ICC_IAR0_EL1 SYSREG(3, 0, 12, 8, 0) 218 #define SYSREG_ICC_IAR1_EL1 SYSREG(3, 0, 12, 12, 0) 219 #define SYSREG_ICC_IGRPEN0_EL1 SYSREG(3, 0, 12, 12, 6) 220 #define SYSREG_ICC_IGRPEN1_EL1 SYSREG(3, 0, 12, 12, 7) 221 #define SYSREG_ICC_PMR_EL1 SYSREG(3, 0, 4, 6, 0) 222 #define SYSREG_ICC_RPR_EL1 SYSREG(3, 0, 12, 11, 3) 223 #define SYSREG_ICC_SGI0R_EL1 SYSREG(3, 0, 12, 11, 7) 224 #define SYSREG_ICC_SGI1R_EL1 SYSREG(3, 0, 12, 11, 5) 225 #define SYSREG_ICC_SRE_EL1 SYSREG(3, 0, 12, 12, 5) 226 227 #define SYSREG_MDSCR_EL1 SYSREG(2, 0, 0, 2, 2) 228 #define SYSREG_DBGBVR0_EL1 SYSREG(2, 0, 0, 0, 4) 229 #define SYSREG_DBGBCR0_EL1 SYSREG(2, 0, 0, 0, 5) 230 #define SYSREG_DBGWVR0_EL1 SYSREG(2, 0, 0, 0, 6) 231 #define SYSREG_DBGWCR0_EL1 SYSREG(2, 0, 0, 0, 7) 232 #define SYSREG_DBGBVR1_EL1 SYSREG(2, 0, 0, 1, 4) 233 #define SYSREG_DBGBCR1_EL1 SYSREG(2, 0, 0, 1, 5) 234 #define SYSREG_DBGWVR1_EL1 SYSREG(2, 0, 0, 1, 6) 235 #define SYSREG_DBGWCR1_EL1 SYSREG(2, 0, 0, 1, 7) 236 #define SYSREG_DBGBVR2_EL1 SYSREG(2, 0, 0, 2, 4) 237 #define SYSREG_DBGBCR2_EL1 SYSREG(2, 0, 0, 2, 5) 238 #define SYSREG_DBGWVR2_EL1 SYSREG(2, 0, 0, 2, 6) 239 #define SYSREG_DBGWCR2_EL1 SYSREG(2, 0, 0, 2, 7) 240 #define SYSREG_DBGBVR3_EL1 SYSREG(2, 0, 0, 3, 4) 241 #define SYSREG_DBGBCR3_EL1 SYSREG(2, 0, 0, 3, 5) 242 #define SYSREG_DBGWVR3_EL1 SYSREG(2, 0, 0, 3, 6) 243 #define SYSREG_DBGWCR3_EL1 SYSREG(2, 0, 0, 3, 7) 244 #define SYSREG_DBGBVR4_EL1 SYSREG(2, 0, 0, 4, 4) 245 #define SYSREG_DBGBCR4_EL1 SYSREG(2, 0, 0, 4, 5) 246 #define SYSREG_DBGWVR4_EL1 SYSREG(2, 0, 0, 4, 6) 247 #define SYSREG_DBGWCR4_EL1 SYSREG(2, 0, 0, 4, 7) 248 #define SYSREG_DBGBVR5_EL1 SYSREG(2, 0, 0, 5, 4) 249 #define SYSREG_DBGBCR5_EL1 SYSREG(2, 0, 0, 5, 5) 250 #define SYSREG_DBGWVR5_EL1 SYSREG(2, 0, 0, 5, 6) 251 #define SYSREG_DBGWCR5_EL1 SYSREG(2, 0, 0, 5, 7) 252 #define SYSREG_DBGBVR6_EL1 SYSREG(2, 0, 0, 6, 4) 253 #define SYSREG_DBGBCR6_EL1 SYSREG(2, 0, 0, 6, 5) 254 #define SYSREG_DBGWVR6_EL1 SYSREG(2, 0, 0, 6, 6) 255 #define SYSREG_DBGWCR6_EL1 SYSREG(2, 0, 0, 6, 7) 256 #define SYSREG_DBGBVR7_EL1 SYSREG(2, 0, 0, 7, 4) 257 #define SYSREG_DBGBCR7_EL1 SYSREG(2, 0, 0, 7, 5) 258 #define SYSREG_DBGWVR7_EL1 SYSREG(2, 0, 0, 7, 6) 259 #define SYSREG_DBGWCR7_EL1 SYSREG(2, 0, 0, 7, 7) 260 #define SYSREG_DBGBVR8_EL1 SYSREG(2, 0, 0, 8, 4) 261 #define SYSREG_DBGBCR8_EL1 SYSREG(2, 0, 0, 8, 5) 262 #define SYSREG_DBGWVR8_EL1 SYSREG(2, 0, 0, 8, 6) 263 #define SYSREG_DBGWCR8_EL1 SYSREG(2, 0, 0, 8, 7) 264 #define SYSREG_DBGBVR9_EL1 SYSREG(2, 0, 0, 9, 4) 265 #define SYSREG_DBGBCR9_EL1 SYSREG(2, 0, 0, 9, 5) 266 #define SYSREG_DBGWVR9_EL1 SYSREG(2, 0, 0, 9, 6) 267 #define SYSREG_DBGWCR9_EL1 SYSREG(2, 0, 0, 9, 7) 268 #define SYSREG_DBGBVR10_EL1 SYSREG(2, 0, 0, 10, 4) 269 #define SYSREG_DBGBCR10_EL1 SYSREG(2, 0, 0, 10, 5) 270 #define SYSREG_DBGWVR10_EL1 SYSREG(2, 0, 0, 10, 6) 271 #define SYSREG_DBGWCR10_EL1 SYSREG(2, 0, 0, 10, 7) 272 #define SYSREG_DBGBVR11_EL1 SYSREG(2, 0, 0, 11, 4) 273 #define SYSREG_DBGBCR11_EL1 SYSREG(2, 0, 0, 11, 5) 274 #define SYSREG_DBGWVR11_EL1 SYSREG(2, 0, 0, 11, 6) 275 #define SYSREG_DBGWCR11_EL1 SYSREG(2, 0, 0, 11, 7) 276 #define SYSREG_DBGBVR12_EL1 SYSREG(2, 0, 0, 12, 4) 277 #define SYSREG_DBGBCR12_EL1 SYSREG(2, 0, 0, 12, 5) 278 #define SYSREG_DBGWVR12_EL1 SYSREG(2, 0, 0, 12, 6) 279 #define SYSREG_DBGWCR12_EL1 SYSREG(2, 0, 0, 12, 7) 280 #define SYSREG_DBGBVR13_EL1 SYSREG(2, 0, 0, 13, 4) 281 #define SYSREG_DBGBCR13_EL1 SYSREG(2, 0, 0, 13, 5) 282 #define SYSREG_DBGWVR13_EL1 SYSREG(2, 0, 0, 13, 6) 283 #define SYSREG_DBGWCR13_EL1 SYSREG(2, 0, 0, 13, 7) 284 #define SYSREG_DBGBVR14_EL1 SYSREG(2, 0, 0, 14, 4) 285 #define SYSREG_DBGBCR14_EL1 SYSREG(2, 0, 0, 14, 5) 286 #define SYSREG_DBGWVR14_EL1 SYSREG(2, 0, 0, 14, 6) 287 #define SYSREG_DBGWCR14_EL1 SYSREG(2, 0, 0, 14, 7) 288 #define SYSREG_DBGBVR15_EL1 SYSREG(2, 0, 0, 15, 4) 289 #define SYSREG_DBGBCR15_EL1 SYSREG(2, 0, 0, 15, 5) 290 #define SYSREG_DBGWVR15_EL1 SYSREG(2, 0, 0, 15, 6) 291 #define SYSREG_DBGWCR15_EL1 SYSREG(2, 0, 0, 15, 7) 292 293 #define WFX_IS_WFE (1 << 0) 294 295 #define TMR_CTL_ENABLE (1 << 0) 296 #define TMR_CTL_IMASK (1 << 1) 297 #define TMR_CTL_ISTATUS (1 << 2) 298 299 static void hvf_wfi(CPUState *cpu); 300 301 typedef struct HVFVTimer { 302 /* Vtimer value during migration and paused state */ 303 uint64_t vtimer_val; 304 } HVFVTimer; 305 306 static HVFVTimer vtimer; 307 308 typedef struct ARMHostCPUFeatures { 309 ARMISARegisters isar; 310 uint64_t features; 311 uint64_t midr; 312 uint32_t reset_sctlr; 313 const char *dtb_compatible; 314 } ARMHostCPUFeatures; 315 316 static ARMHostCPUFeatures arm_host_cpu_features; 317 318 struct hvf_reg_match { 319 int reg; 320 uint64_t offset; 321 }; 322 323 static const struct hvf_reg_match hvf_reg_match[] = { 324 { HV_REG_X0, offsetof(CPUARMState, xregs[0]) }, 325 { HV_REG_X1, offsetof(CPUARMState, xregs[1]) }, 326 { HV_REG_X2, offsetof(CPUARMState, xregs[2]) }, 327 { HV_REG_X3, offsetof(CPUARMState, xregs[3]) }, 328 { HV_REG_X4, offsetof(CPUARMState, xregs[4]) }, 329 { HV_REG_X5, offsetof(CPUARMState, xregs[5]) }, 330 { HV_REG_X6, offsetof(CPUARMState, xregs[6]) }, 331 { HV_REG_X7, offsetof(CPUARMState, xregs[7]) }, 332 { HV_REG_X8, offsetof(CPUARMState, xregs[8]) }, 333 { HV_REG_X9, offsetof(CPUARMState, xregs[9]) }, 334 { HV_REG_X10, offsetof(CPUARMState, xregs[10]) }, 335 { HV_REG_X11, offsetof(CPUARMState, xregs[11]) }, 336 { HV_REG_X12, offsetof(CPUARMState, xregs[12]) }, 337 { HV_REG_X13, offsetof(CPUARMState, xregs[13]) }, 338 { HV_REG_X14, offsetof(CPUARMState, xregs[14]) }, 339 { HV_REG_X15, offsetof(CPUARMState, xregs[15]) }, 340 { HV_REG_X16, offsetof(CPUARMState, xregs[16]) }, 341 { HV_REG_X17, offsetof(CPUARMState, xregs[17]) }, 342 { HV_REG_X18, offsetof(CPUARMState, xregs[18]) }, 343 { HV_REG_X19, offsetof(CPUARMState, xregs[19]) }, 344 { HV_REG_X20, offsetof(CPUARMState, xregs[20]) }, 345 { HV_REG_X21, offsetof(CPUARMState, xregs[21]) }, 346 { HV_REG_X22, offsetof(CPUARMState, xregs[22]) }, 347 { HV_REG_X23, offsetof(CPUARMState, xregs[23]) }, 348 { HV_REG_X24, offsetof(CPUARMState, xregs[24]) }, 349 { HV_REG_X25, offsetof(CPUARMState, xregs[25]) }, 350 { HV_REG_X26, offsetof(CPUARMState, xregs[26]) }, 351 { HV_REG_X27, offsetof(CPUARMState, xregs[27]) }, 352 { HV_REG_X28, offsetof(CPUARMState, xregs[28]) }, 353 { HV_REG_X29, offsetof(CPUARMState, xregs[29]) }, 354 { HV_REG_X30, offsetof(CPUARMState, xregs[30]) }, 355 { HV_REG_PC, offsetof(CPUARMState, pc) }, 356 }; 357 358 static const struct hvf_reg_match hvf_fpreg_match[] = { 359 { HV_SIMD_FP_REG_Q0, offsetof(CPUARMState, vfp.zregs[0]) }, 360 { HV_SIMD_FP_REG_Q1, offsetof(CPUARMState, vfp.zregs[1]) }, 361 { HV_SIMD_FP_REG_Q2, offsetof(CPUARMState, vfp.zregs[2]) }, 362 { HV_SIMD_FP_REG_Q3, offsetof(CPUARMState, vfp.zregs[3]) }, 363 { HV_SIMD_FP_REG_Q4, offsetof(CPUARMState, vfp.zregs[4]) }, 364 { HV_SIMD_FP_REG_Q5, offsetof(CPUARMState, vfp.zregs[5]) }, 365 { HV_SIMD_FP_REG_Q6, offsetof(CPUARMState, vfp.zregs[6]) }, 366 { HV_SIMD_FP_REG_Q7, offsetof(CPUARMState, vfp.zregs[7]) }, 367 { HV_SIMD_FP_REG_Q8, offsetof(CPUARMState, vfp.zregs[8]) }, 368 { HV_SIMD_FP_REG_Q9, offsetof(CPUARMState, vfp.zregs[9]) }, 369 { HV_SIMD_FP_REG_Q10, offsetof(CPUARMState, vfp.zregs[10]) }, 370 { HV_SIMD_FP_REG_Q11, offsetof(CPUARMState, vfp.zregs[11]) }, 371 { HV_SIMD_FP_REG_Q12, offsetof(CPUARMState, vfp.zregs[12]) }, 372 { HV_SIMD_FP_REG_Q13, offsetof(CPUARMState, vfp.zregs[13]) }, 373 { HV_SIMD_FP_REG_Q14, offsetof(CPUARMState, vfp.zregs[14]) }, 374 { HV_SIMD_FP_REG_Q15, offsetof(CPUARMState, vfp.zregs[15]) }, 375 { HV_SIMD_FP_REG_Q16, offsetof(CPUARMState, vfp.zregs[16]) }, 376 { HV_SIMD_FP_REG_Q17, offsetof(CPUARMState, vfp.zregs[17]) }, 377 { HV_SIMD_FP_REG_Q18, offsetof(CPUARMState, vfp.zregs[18]) }, 378 { HV_SIMD_FP_REG_Q19, offsetof(CPUARMState, vfp.zregs[19]) }, 379 { HV_SIMD_FP_REG_Q20, offsetof(CPUARMState, vfp.zregs[20]) }, 380 { HV_SIMD_FP_REG_Q21, offsetof(CPUARMState, vfp.zregs[21]) }, 381 { HV_SIMD_FP_REG_Q22, offsetof(CPUARMState, vfp.zregs[22]) }, 382 { HV_SIMD_FP_REG_Q23, offsetof(CPUARMState, vfp.zregs[23]) }, 383 { HV_SIMD_FP_REG_Q24, offsetof(CPUARMState, vfp.zregs[24]) }, 384 { HV_SIMD_FP_REG_Q25, offsetof(CPUARMState, vfp.zregs[25]) }, 385 { HV_SIMD_FP_REG_Q26, offsetof(CPUARMState, vfp.zregs[26]) }, 386 { HV_SIMD_FP_REG_Q27, offsetof(CPUARMState, vfp.zregs[27]) }, 387 { HV_SIMD_FP_REG_Q28, offsetof(CPUARMState, vfp.zregs[28]) }, 388 { HV_SIMD_FP_REG_Q29, offsetof(CPUARMState, vfp.zregs[29]) }, 389 { HV_SIMD_FP_REG_Q30, offsetof(CPUARMState, vfp.zregs[30]) }, 390 { HV_SIMD_FP_REG_Q31, offsetof(CPUARMState, vfp.zregs[31]) }, 391 }; 392 393 struct hvf_sreg_match { 394 int reg; 395 uint32_t key; 396 uint32_t cp_idx; 397 }; 398 399 static struct hvf_sreg_match hvf_sreg_match[] = { 400 { HV_SYS_REG_DBGBVR0_EL1, HVF_SYSREG(0, 0, 14, 0, 4) }, 401 { HV_SYS_REG_DBGBCR0_EL1, HVF_SYSREG(0, 0, 14, 0, 5) }, 402 { HV_SYS_REG_DBGWVR0_EL1, HVF_SYSREG(0, 0, 14, 0, 6) }, 403 { HV_SYS_REG_DBGWCR0_EL1, HVF_SYSREG(0, 0, 14, 0, 7) }, 404 405 { HV_SYS_REG_DBGBVR1_EL1, HVF_SYSREG(0, 1, 14, 0, 4) }, 406 { HV_SYS_REG_DBGBCR1_EL1, HVF_SYSREG(0, 1, 14, 0, 5) }, 407 { HV_SYS_REG_DBGWVR1_EL1, HVF_SYSREG(0, 1, 14, 0, 6) }, 408 { HV_SYS_REG_DBGWCR1_EL1, HVF_SYSREG(0, 1, 14, 0, 7) }, 409 410 { HV_SYS_REG_DBGBVR2_EL1, HVF_SYSREG(0, 2, 14, 0, 4) }, 411 { HV_SYS_REG_DBGBCR2_EL1, HVF_SYSREG(0, 2, 14, 0, 5) }, 412 { HV_SYS_REG_DBGWVR2_EL1, HVF_SYSREG(0, 2, 14, 0, 6) }, 413 { HV_SYS_REG_DBGWCR2_EL1, HVF_SYSREG(0, 2, 14, 0, 7) }, 414 415 { HV_SYS_REG_DBGBVR3_EL1, HVF_SYSREG(0, 3, 14, 0, 4) }, 416 { HV_SYS_REG_DBGBCR3_EL1, HVF_SYSREG(0, 3, 14, 0, 5) }, 417 { HV_SYS_REG_DBGWVR3_EL1, HVF_SYSREG(0, 3, 14, 0, 6) }, 418 { HV_SYS_REG_DBGWCR3_EL1, HVF_SYSREG(0, 3, 14, 0, 7) }, 419 420 { HV_SYS_REG_DBGBVR4_EL1, HVF_SYSREG(0, 4, 14, 0, 4) }, 421 { HV_SYS_REG_DBGBCR4_EL1, HVF_SYSREG(0, 4, 14, 0, 5) }, 422 { HV_SYS_REG_DBGWVR4_EL1, HVF_SYSREG(0, 4, 14, 0, 6) }, 423 { HV_SYS_REG_DBGWCR4_EL1, HVF_SYSREG(0, 4, 14, 0, 7) }, 424 425 { HV_SYS_REG_DBGBVR5_EL1, HVF_SYSREG(0, 5, 14, 0, 4) }, 426 { HV_SYS_REG_DBGBCR5_EL1, HVF_SYSREG(0, 5, 14, 0, 5) }, 427 { HV_SYS_REG_DBGWVR5_EL1, HVF_SYSREG(0, 5, 14, 0, 6) }, 428 { HV_SYS_REG_DBGWCR5_EL1, HVF_SYSREG(0, 5, 14, 0, 7) }, 429 430 { HV_SYS_REG_DBGBVR6_EL1, HVF_SYSREG(0, 6, 14, 0, 4) }, 431 { HV_SYS_REG_DBGBCR6_EL1, HVF_SYSREG(0, 6, 14, 0, 5) }, 432 { HV_SYS_REG_DBGWVR6_EL1, HVF_SYSREG(0, 6, 14, 0, 6) }, 433 { HV_SYS_REG_DBGWCR6_EL1, HVF_SYSREG(0, 6, 14, 0, 7) }, 434 435 { HV_SYS_REG_DBGBVR7_EL1, HVF_SYSREG(0, 7, 14, 0, 4) }, 436 { HV_SYS_REG_DBGBCR7_EL1, HVF_SYSREG(0, 7, 14, 0, 5) }, 437 { HV_SYS_REG_DBGWVR7_EL1, HVF_SYSREG(0, 7, 14, 0, 6) }, 438 { HV_SYS_REG_DBGWCR7_EL1, HVF_SYSREG(0, 7, 14, 0, 7) }, 439 440 { HV_SYS_REG_DBGBVR8_EL1, HVF_SYSREG(0, 8, 14, 0, 4) }, 441 { HV_SYS_REG_DBGBCR8_EL1, HVF_SYSREG(0, 8, 14, 0, 5) }, 442 { HV_SYS_REG_DBGWVR8_EL1, HVF_SYSREG(0, 8, 14, 0, 6) }, 443 { HV_SYS_REG_DBGWCR8_EL1, HVF_SYSREG(0, 8, 14, 0, 7) }, 444 445 { HV_SYS_REG_DBGBVR9_EL1, HVF_SYSREG(0, 9, 14, 0, 4) }, 446 { HV_SYS_REG_DBGBCR9_EL1, HVF_SYSREG(0, 9, 14, 0, 5) }, 447 { HV_SYS_REG_DBGWVR9_EL1, HVF_SYSREG(0, 9, 14, 0, 6) }, 448 { HV_SYS_REG_DBGWCR9_EL1, HVF_SYSREG(0, 9, 14, 0, 7) }, 449 450 { HV_SYS_REG_DBGBVR10_EL1, HVF_SYSREG(0, 10, 14, 0, 4) }, 451 { HV_SYS_REG_DBGBCR10_EL1, HVF_SYSREG(0, 10, 14, 0, 5) }, 452 { HV_SYS_REG_DBGWVR10_EL1, HVF_SYSREG(0, 10, 14, 0, 6) }, 453 { HV_SYS_REG_DBGWCR10_EL1, HVF_SYSREG(0, 10, 14, 0, 7) }, 454 455 { HV_SYS_REG_DBGBVR11_EL1, HVF_SYSREG(0, 11, 14, 0, 4) }, 456 { HV_SYS_REG_DBGBCR11_EL1, HVF_SYSREG(0, 11, 14, 0, 5) }, 457 { HV_SYS_REG_DBGWVR11_EL1, HVF_SYSREG(0, 11, 14, 0, 6) }, 458 { HV_SYS_REG_DBGWCR11_EL1, HVF_SYSREG(0, 11, 14, 0, 7) }, 459 460 { HV_SYS_REG_DBGBVR12_EL1, HVF_SYSREG(0, 12, 14, 0, 4) }, 461 { HV_SYS_REG_DBGBCR12_EL1, HVF_SYSREG(0, 12, 14, 0, 5) }, 462 { HV_SYS_REG_DBGWVR12_EL1, HVF_SYSREG(0, 12, 14, 0, 6) }, 463 { HV_SYS_REG_DBGWCR12_EL1, HVF_SYSREG(0, 12, 14, 0, 7) }, 464 465 { HV_SYS_REG_DBGBVR13_EL1, HVF_SYSREG(0, 13, 14, 0, 4) }, 466 { HV_SYS_REG_DBGBCR13_EL1, HVF_SYSREG(0, 13, 14, 0, 5) }, 467 { HV_SYS_REG_DBGWVR13_EL1, HVF_SYSREG(0, 13, 14, 0, 6) }, 468 { HV_SYS_REG_DBGWCR13_EL1, HVF_SYSREG(0, 13, 14, 0, 7) }, 469 470 { HV_SYS_REG_DBGBVR14_EL1, HVF_SYSREG(0, 14, 14, 0, 4) }, 471 { HV_SYS_REG_DBGBCR14_EL1, HVF_SYSREG(0, 14, 14, 0, 5) }, 472 { HV_SYS_REG_DBGWVR14_EL1, HVF_SYSREG(0, 14, 14, 0, 6) }, 473 { HV_SYS_REG_DBGWCR14_EL1, HVF_SYSREG(0, 14, 14, 0, 7) }, 474 475 { HV_SYS_REG_DBGBVR15_EL1, HVF_SYSREG(0, 15, 14, 0, 4) }, 476 { HV_SYS_REG_DBGBCR15_EL1, HVF_SYSREG(0, 15, 14, 0, 5) }, 477 { HV_SYS_REG_DBGWVR15_EL1, HVF_SYSREG(0, 15, 14, 0, 6) }, 478 { HV_SYS_REG_DBGWCR15_EL1, HVF_SYSREG(0, 15, 14, 0, 7) }, 479 480 #ifdef SYNC_NO_RAW_REGS 481 /* 482 * The registers below are manually synced on init because they are 483 * marked as NO_RAW. We still list them to make number space sync easier. 484 */ 485 { HV_SYS_REG_MDCCINT_EL1, HVF_SYSREG(0, 2, 2, 0, 0) }, 486 { HV_SYS_REG_MIDR_EL1, HVF_SYSREG(0, 0, 3, 0, 0) }, 487 { HV_SYS_REG_MPIDR_EL1, HVF_SYSREG(0, 0, 3, 0, 5) }, 488 { HV_SYS_REG_ID_AA64PFR0_EL1, HVF_SYSREG(0, 4, 3, 0, 0) }, 489 #endif 490 { HV_SYS_REG_ID_AA64PFR1_EL1, HVF_SYSREG(0, 4, 3, 0, 2) }, 491 { HV_SYS_REG_ID_AA64DFR0_EL1, HVF_SYSREG(0, 5, 3, 0, 0) }, 492 { HV_SYS_REG_ID_AA64DFR1_EL1, HVF_SYSREG(0, 5, 3, 0, 1) }, 493 { HV_SYS_REG_ID_AA64ISAR0_EL1, HVF_SYSREG(0, 6, 3, 0, 0) }, 494 { HV_SYS_REG_ID_AA64ISAR1_EL1, HVF_SYSREG(0, 6, 3, 0, 1) }, 495 #ifdef SYNC_NO_MMFR0 496 /* We keep the hardware MMFR0 around. HW limits are there anyway */ 497 { HV_SYS_REG_ID_AA64MMFR0_EL1, HVF_SYSREG(0, 7, 3, 0, 0) }, 498 #endif 499 { HV_SYS_REG_ID_AA64MMFR1_EL1, HVF_SYSREG(0, 7, 3, 0, 1) }, 500 { HV_SYS_REG_ID_AA64MMFR2_EL1, HVF_SYSREG(0, 7, 3, 0, 2) }, 501 502 { HV_SYS_REG_MDSCR_EL1, HVF_SYSREG(0, 2, 2, 0, 2) }, 503 { HV_SYS_REG_SCTLR_EL1, HVF_SYSREG(1, 0, 3, 0, 0) }, 504 { HV_SYS_REG_CPACR_EL1, HVF_SYSREG(1, 0, 3, 0, 2) }, 505 { HV_SYS_REG_TTBR0_EL1, HVF_SYSREG(2, 0, 3, 0, 0) }, 506 { HV_SYS_REG_TTBR1_EL1, HVF_SYSREG(2, 0, 3, 0, 1) }, 507 { HV_SYS_REG_TCR_EL1, HVF_SYSREG(2, 0, 3, 0, 2) }, 508 509 { HV_SYS_REG_APIAKEYLO_EL1, HVF_SYSREG(2, 1, 3, 0, 0) }, 510 { HV_SYS_REG_APIAKEYHI_EL1, HVF_SYSREG(2, 1, 3, 0, 1) }, 511 { HV_SYS_REG_APIBKEYLO_EL1, HVF_SYSREG(2, 1, 3, 0, 2) }, 512 { HV_SYS_REG_APIBKEYHI_EL1, HVF_SYSREG(2, 1, 3, 0, 3) }, 513 { HV_SYS_REG_APDAKEYLO_EL1, HVF_SYSREG(2, 2, 3, 0, 0) }, 514 { HV_SYS_REG_APDAKEYHI_EL1, HVF_SYSREG(2, 2, 3, 0, 1) }, 515 { HV_SYS_REG_APDBKEYLO_EL1, HVF_SYSREG(2, 2, 3, 0, 2) }, 516 { HV_SYS_REG_APDBKEYHI_EL1, HVF_SYSREG(2, 2, 3, 0, 3) }, 517 { HV_SYS_REG_APGAKEYLO_EL1, HVF_SYSREG(2, 3, 3, 0, 0) }, 518 { HV_SYS_REG_APGAKEYHI_EL1, HVF_SYSREG(2, 3, 3, 0, 1) }, 519 520 { HV_SYS_REG_SPSR_EL1, HVF_SYSREG(4, 0, 3, 0, 0) }, 521 { HV_SYS_REG_ELR_EL1, HVF_SYSREG(4, 0, 3, 0, 1) }, 522 { HV_SYS_REG_SP_EL0, HVF_SYSREG(4, 1, 3, 0, 0) }, 523 { HV_SYS_REG_AFSR0_EL1, HVF_SYSREG(5, 1, 3, 0, 0) }, 524 { HV_SYS_REG_AFSR1_EL1, HVF_SYSREG(5, 1, 3, 0, 1) }, 525 { HV_SYS_REG_ESR_EL1, HVF_SYSREG(5, 2, 3, 0, 0) }, 526 { HV_SYS_REG_FAR_EL1, HVF_SYSREG(6, 0, 3, 0, 0) }, 527 { HV_SYS_REG_PAR_EL1, HVF_SYSREG(7, 4, 3, 0, 0) }, 528 { HV_SYS_REG_MAIR_EL1, HVF_SYSREG(10, 2, 3, 0, 0) }, 529 { HV_SYS_REG_AMAIR_EL1, HVF_SYSREG(10, 3, 3, 0, 0) }, 530 { HV_SYS_REG_VBAR_EL1, HVF_SYSREG(12, 0, 3, 0, 0) }, 531 { HV_SYS_REG_CONTEXTIDR_EL1, HVF_SYSREG(13, 0, 3, 0, 1) }, 532 { HV_SYS_REG_TPIDR_EL1, HVF_SYSREG(13, 0, 3, 0, 4) }, 533 { HV_SYS_REG_CNTKCTL_EL1, HVF_SYSREG(14, 1, 3, 0, 0) }, 534 { HV_SYS_REG_CSSELR_EL1, HVF_SYSREG(0, 0, 3, 2, 0) }, 535 { HV_SYS_REG_TPIDR_EL0, HVF_SYSREG(13, 0, 3, 3, 2) }, 536 { HV_SYS_REG_TPIDRRO_EL0, HVF_SYSREG(13, 0, 3, 3, 3) }, 537 { HV_SYS_REG_CNTV_CTL_EL0, HVF_SYSREG(14, 3, 3, 3, 1) }, 538 { HV_SYS_REG_CNTV_CVAL_EL0, HVF_SYSREG(14, 3, 3, 3, 2) }, 539 { HV_SYS_REG_SP_EL1, HVF_SYSREG(4, 1, 3, 4, 0) }, 540 }; 541 542 int hvf_get_registers(CPUState *cpu) 543 { 544 ARMCPU *arm_cpu = ARM_CPU(cpu); 545 CPUARMState *env = &arm_cpu->env; 546 hv_return_t ret; 547 uint64_t val; 548 hv_simd_fp_uchar16_t fpval; 549 int i; 550 551 for (i = 0; i < ARRAY_SIZE(hvf_reg_match); i++) { 552 ret = hv_vcpu_get_reg(cpu->accel->fd, hvf_reg_match[i].reg, &val); 553 *(uint64_t *)((void *)env + hvf_reg_match[i].offset) = val; 554 assert_hvf_ok(ret); 555 } 556 557 for (i = 0; i < ARRAY_SIZE(hvf_fpreg_match); i++) { 558 ret = hv_vcpu_get_simd_fp_reg(cpu->accel->fd, hvf_fpreg_match[i].reg, 559 &fpval); 560 memcpy((void *)env + hvf_fpreg_match[i].offset, &fpval, sizeof(fpval)); 561 assert_hvf_ok(ret); 562 } 563 564 val = 0; 565 ret = hv_vcpu_get_reg(cpu->accel->fd, HV_REG_FPCR, &val); 566 assert_hvf_ok(ret); 567 vfp_set_fpcr(env, val); 568 569 val = 0; 570 ret = hv_vcpu_get_reg(cpu->accel->fd, HV_REG_FPSR, &val); 571 assert_hvf_ok(ret); 572 vfp_set_fpsr(env, val); 573 574 ret = hv_vcpu_get_reg(cpu->accel->fd, HV_REG_CPSR, &val); 575 assert_hvf_ok(ret); 576 pstate_write(env, val); 577 578 for (i = 0; i < ARRAY_SIZE(hvf_sreg_match); i++) { 579 if (hvf_sreg_match[i].cp_idx == -1) { 580 continue; 581 } 582 583 if (cpu->accel->guest_debug_enabled) { 584 /* Handle debug registers */ 585 switch (hvf_sreg_match[i].reg) { 586 case HV_SYS_REG_DBGBVR0_EL1: 587 case HV_SYS_REG_DBGBCR0_EL1: 588 case HV_SYS_REG_DBGWVR0_EL1: 589 case HV_SYS_REG_DBGWCR0_EL1: 590 case HV_SYS_REG_DBGBVR1_EL1: 591 case HV_SYS_REG_DBGBCR1_EL1: 592 case HV_SYS_REG_DBGWVR1_EL1: 593 case HV_SYS_REG_DBGWCR1_EL1: 594 case HV_SYS_REG_DBGBVR2_EL1: 595 case HV_SYS_REG_DBGBCR2_EL1: 596 case HV_SYS_REG_DBGWVR2_EL1: 597 case HV_SYS_REG_DBGWCR2_EL1: 598 case HV_SYS_REG_DBGBVR3_EL1: 599 case HV_SYS_REG_DBGBCR3_EL1: 600 case HV_SYS_REG_DBGWVR3_EL1: 601 case HV_SYS_REG_DBGWCR3_EL1: 602 case HV_SYS_REG_DBGBVR4_EL1: 603 case HV_SYS_REG_DBGBCR4_EL1: 604 case HV_SYS_REG_DBGWVR4_EL1: 605 case HV_SYS_REG_DBGWCR4_EL1: 606 case HV_SYS_REG_DBGBVR5_EL1: 607 case HV_SYS_REG_DBGBCR5_EL1: 608 case HV_SYS_REG_DBGWVR5_EL1: 609 case HV_SYS_REG_DBGWCR5_EL1: 610 case HV_SYS_REG_DBGBVR6_EL1: 611 case HV_SYS_REG_DBGBCR6_EL1: 612 case HV_SYS_REG_DBGWVR6_EL1: 613 case HV_SYS_REG_DBGWCR6_EL1: 614 case HV_SYS_REG_DBGBVR7_EL1: 615 case HV_SYS_REG_DBGBCR7_EL1: 616 case HV_SYS_REG_DBGWVR7_EL1: 617 case HV_SYS_REG_DBGWCR7_EL1: 618 case HV_SYS_REG_DBGBVR8_EL1: 619 case HV_SYS_REG_DBGBCR8_EL1: 620 case HV_SYS_REG_DBGWVR8_EL1: 621 case HV_SYS_REG_DBGWCR8_EL1: 622 case HV_SYS_REG_DBGBVR9_EL1: 623 case HV_SYS_REG_DBGBCR9_EL1: 624 case HV_SYS_REG_DBGWVR9_EL1: 625 case HV_SYS_REG_DBGWCR9_EL1: 626 case HV_SYS_REG_DBGBVR10_EL1: 627 case HV_SYS_REG_DBGBCR10_EL1: 628 case HV_SYS_REG_DBGWVR10_EL1: 629 case HV_SYS_REG_DBGWCR10_EL1: 630 case HV_SYS_REG_DBGBVR11_EL1: 631 case HV_SYS_REG_DBGBCR11_EL1: 632 case HV_SYS_REG_DBGWVR11_EL1: 633 case HV_SYS_REG_DBGWCR11_EL1: 634 case HV_SYS_REG_DBGBVR12_EL1: 635 case HV_SYS_REG_DBGBCR12_EL1: 636 case HV_SYS_REG_DBGWVR12_EL1: 637 case HV_SYS_REG_DBGWCR12_EL1: 638 case HV_SYS_REG_DBGBVR13_EL1: 639 case HV_SYS_REG_DBGBCR13_EL1: 640 case HV_SYS_REG_DBGWVR13_EL1: 641 case HV_SYS_REG_DBGWCR13_EL1: 642 case HV_SYS_REG_DBGBVR14_EL1: 643 case HV_SYS_REG_DBGBCR14_EL1: 644 case HV_SYS_REG_DBGWVR14_EL1: 645 case HV_SYS_REG_DBGWCR14_EL1: 646 case HV_SYS_REG_DBGBVR15_EL1: 647 case HV_SYS_REG_DBGBCR15_EL1: 648 case HV_SYS_REG_DBGWVR15_EL1: 649 case HV_SYS_REG_DBGWCR15_EL1: { 650 /* 651 * If the guest is being debugged, the vCPU's debug registers 652 * are holding the gdbstub's view of the registers (set in 653 * hvf_arch_update_guest_debug()). 654 * Since the environment is used to store only the guest's view 655 * of the registers, don't update it with the values from the 656 * vCPU but simply keep the values from the previous 657 * environment. 658 */ 659 const ARMCPRegInfo *ri; 660 ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_sreg_match[i].key); 661 val = read_raw_cp_reg(env, ri); 662 663 arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx] = val; 664 continue; 665 } 666 } 667 } 668 669 ret = hv_vcpu_get_sys_reg(cpu->accel->fd, hvf_sreg_match[i].reg, &val); 670 assert_hvf_ok(ret); 671 672 arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx] = val; 673 } 674 assert(write_list_to_cpustate(arm_cpu)); 675 676 aarch64_restore_sp(env, arm_current_el(env)); 677 678 return 0; 679 } 680 681 int hvf_put_registers(CPUState *cpu) 682 { 683 ARMCPU *arm_cpu = ARM_CPU(cpu); 684 CPUARMState *env = &arm_cpu->env; 685 hv_return_t ret; 686 uint64_t val; 687 hv_simd_fp_uchar16_t fpval; 688 int i; 689 690 for (i = 0; i < ARRAY_SIZE(hvf_reg_match); i++) { 691 val = *(uint64_t *)((void *)env + hvf_reg_match[i].offset); 692 ret = hv_vcpu_set_reg(cpu->accel->fd, hvf_reg_match[i].reg, val); 693 assert_hvf_ok(ret); 694 } 695 696 for (i = 0; i < ARRAY_SIZE(hvf_fpreg_match); i++) { 697 memcpy(&fpval, (void *)env + hvf_fpreg_match[i].offset, sizeof(fpval)); 698 ret = hv_vcpu_set_simd_fp_reg(cpu->accel->fd, hvf_fpreg_match[i].reg, 699 fpval); 700 assert_hvf_ok(ret); 701 } 702 703 ret = hv_vcpu_set_reg(cpu->accel->fd, HV_REG_FPCR, vfp_get_fpcr(env)); 704 assert_hvf_ok(ret); 705 706 ret = hv_vcpu_set_reg(cpu->accel->fd, HV_REG_FPSR, vfp_get_fpsr(env)); 707 assert_hvf_ok(ret); 708 709 ret = hv_vcpu_set_reg(cpu->accel->fd, HV_REG_CPSR, pstate_read(env)); 710 assert_hvf_ok(ret); 711 712 aarch64_save_sp(env, arm_current_el(env)); 713 714 assert(write_cpustate_to_list(arm_cpu, false)); 715 for (i = 0; i < ARRAY_SIZE(hvf_sreg_match); i++) { 716 if (hvf_sreg_match[i].cp_idx == -1) { 717 continue; 718 } 719 720 if (cpu->accel->guest_debug_enabled) { 721 /* Handle debug registers */ 722 switch (hvf_sreg_match[i].reg) { 723 case HV_SYS_REG_DBGBVR0_EL1: 724 case HV_SYS_REG_DBGBCR0_EL1: 725 case HV_SYS_REG_DBGWVR0_EL1: 726 case HV_SYS_REG_DBGWCR0_EL1: 727 case HV_SYS_REG_DBGBVR1_EL1: 728 case HV_SYS_REG_DBGBCR1_EL1: 729 case HV_SYS_REG_DBGWVR1_EL1: 730 case HV_SYS_REG_DBGWCR1_EL1: 731 case HV_SYS_REG_DBGBVR2_EL1: 732 case HV_SYS_REG_DBGBCR2_EL1: 733 case HV_SYS_REG_DBGWVR2_EL1: 734 case HV_SYS_REG_DBGWCR2_EL1: 735 case HV_SYS_REG_DBGBVR3_EL1: 736 case HV_SYS_REG_DBGBCR3_EL1: 737 case HV_SYS_REG_DBGWVR3_EL1: 738 case HV_SYS_REG_DBGWCR3_EL1: 739 case HV_SYS_REG_DBGBVR4_EL1: 740 case HV_SYS_REG_DBGBCR4_EL1: 741 case HV_SYS_REG_DBGWVR4_EL1: 742 case HV_SYS_REG_DBGWCR4_EL1: 743 case HV_SYS_REG_DBGBVR5_EL1: 744 case HV_SYS_REG_DBGBCR5_EL1: 745 case HV_SYS_REG_DBGWVR5_EL1: 746 case HV_SYS_REG_DBGWCR5_EL1: 747 case HV_SYS_REG_DBGBVR6_EL1: 748 case HV_SYS_REG_DBGBCR6_EL1: 749 case HV_SYS_REG_DBGWVR6_EL1: 750 case HV_SYS_REG_DBGWCR6_EL1: 751 case HV_SYS_REG_DBGBVR7_EL1: 752 case HV_SYS_REG_DBGBCR7_EL1: 753 case HV_SYS_REG_DBGWVR7_EL1: 754 case HV_SYS_REG_DBGWCR7_EL1: 755 case HV_SYS_REG_DBGBVR8_EL1: 756 case HV_SYS_REG_DBGBCR8_EL1: 757 case HV_SYS_REG_DBGWVR8_EL1: 758 case HV_SYS_REG_DBGWCR8_EL1: 759 case HV_SYS_REG_DBGBVR9_EL1: 760 case HV_SYS_REG_DBGBCR9_EL1: 761 case HV_SYS_REG_DBGWVR9_EL1: 762 case HV_SYS_REG_DBGWCR9_EL1: 763 case HV_SYS_REG_DBGBVR10_EL1: 764 case HV_SYS_REG_DBGBCR10_EL1: 765 case HV_SYS_REG_DBGWVR10_EL1: 766 case HV_SYS_REG_DBGWCR10_EL1: 767 case HV_SYS_REG_DBGBVR11_EL1: 768 case HV_SYS_REG_DBGBCR11_EL1: 769 case HV_SYS_REG_DBGWVR11_EL1: 770 case HV_SYS_REG_DBGWCR11_EL1: 771 case HV_SYS_REG_DBGBVR12_EL1: 772 case HV_SYS_REG_DBGBCR12_EL1: 773 case HV_SYS_REG_DBGWVR12_EL1: 774 case HV_SYS_REG_DBGWCR12_EL1: 775 case HV_SYS_REG_DBGBVR13_EL1: 776 case HV_SYS_REG_DBGBCR13_EL1: 777 case HV_SYS_REG_DBGWVR13_EL1: 778 case HV_SYS_REG_DBGWCR13_EL1: 779 case HV_SYS_REG_DBGBVR14_EL1: 780 case HV_SYS_REG_DBGBCR14_EL1: 781 case HV_SYS_REG_DBGWVR14_EL1: 782 case HV_SYS_REG_DBGWCR14_EL1: 783 case HV_SYS_REG_DBGBVR15_EL1: 784 case HV_SYS_REG_DBGBCR15_EL1: 785 case HV_SYS_REG_DBGWVR15_EL1: 786 case HV_SYS_REG_DBGWCR15_EL1: 787 /* 788 * If the guest is being debugged, the vCPU's debug registers 789 * are already holding the gdbstub's view of the registers (set 790 * in hvf_arch_update_guest_debug()). 791 */ 792 continue; 793 } 794 } 795 796 val = arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx]; 797 ret = hv_vcpu_set_sys_reg(cpu->accel->fd, hvf_sreg_match[i].reg, val); 798 assert_hvf_ok(ret); 799 } 800 801 ret = hv_vcpu_set_vtimer_offset(cpu->accel->fd, hvf_state->vtimer_offset); 802 assert_hvf_ok(ret); 803 804 return 0; 805 } 806 807 static void flush_cpu_state(CPUState *cpu) 808 { 809 if (cpu->vcpu_dirty) { 810 hvf_put_registers(cpu); 811 cpu->vcpu_dirty = false; 812 } 813 } 814 815 static void hvf_set_reg(CPUState *cpu, int rt, uint64_t val) 816 { 817 hv_return_t r; 818 819 flush_cpu_state(cpu); 820 821 if (rt < 31) { 822 r = hv_vcpu_set_reg(cpu->accel->fd, HV_REG_X0 + rt, val); 823 assert_hvf_ok(r); 824 } 825 } 826 827 static uint64_t hvf_get_reg(CPUState *cpu, int rt) 828 { 829 uint64_t val = 0; 830 hv_return_t r; 831 832 flush_cpu_state(cpu); 833 834 if (rt < 31) { 835 r = hv_vcpu_get_reg(cpu->accel->fd, HV_REG_X0 + rt, &val); 836 assert_hvf_ok(r); 837 } 838 839 return val; 840 } 841 842 static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) 843 { 844 ARMISARegisters host_isar = {}; 845 const struct isar_regs { 846 int reg; 847 uint64_t *val; 848 } regs[] = { 849 { HV_SYS_REG_ID_AA64PFR0_EL1, &host_isar.id_aa64pfr0 }, 850 { HV_SYS_REG_ID_AA64PFR1_EL1, &host_isar.id_aa64pfr1 }, 851 { HV_SYS_REG_ID_AA64DFR0_EL1, &host_isar.id_aa64dfr0 }, 852 { HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.id_aa64dfr1 }, 853 { HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.id_aa64isar0 }, 854 { HV_SYS_REG_ID_AA64ISAR1_EL1, &host_isar.id_aa64isar1 }, 855 /* Add ID_AA64ISAR2_EL1 here when HVF supports it */ 856 { HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.id_aa64mmfr0 }, 857 { HV_SYS_REG_ID_AA64MMFR1_EL1, &host_isar.id_aa64mmfr1 }, 858 { HV_SYS_REG_ID_AA64MMFR2_EL1, &host_isar.id_aa64mmfr2 }, 859 }; 860 hv_vcpu_t fd; 861 hv_return_t r = HV_SUCCESS; 862 hv_vcpu_exit_t *exit; 863 int i; 864 865 ahcf->dtb_compatible = "arm,arm-v8"; 866 ahcf->features = (1ULL << ARM_FEATURE_V8) | 867 (1ULL << ARM_FEATURE_NEON) | 868 (1ULL << ARM_FEATURE_AARCH64) | 869 (1ULL << ARM_FEATURE_PMU) | 870 (1ULL << ARM_FEATURE_GENERIC_TIMER); 871 872 /* We set up a small vcpu to extract host registers */ 873 874 if (hv_vcpu_create(&fd, &exit, NULL) != HV_SUCCESS) { 875 return false; 876 } 877 878 for (i = 0; i < ARRAY_SIZE(regs); i++) { 879 r |= hv_vcpu_get_sys_reg(fd, regs[i].reg, regs[i].val); 880 } 881 r |= hv_vcpu_get_sys_reg(fd, HV_SYS_REG_MIDR_EL1, &ahcf->midr); 882 r |= hv_vcpu_destroy(fd); 883 884 ahcf->isar = host_isar; 885 886 /* 887 * A scratch vCPU returns SCTLR 0, so let's fill our default with the M1 888 * boot SCTLR from https://github.com/AsahiLinux/m1n1/issues/97 889 */ 890 ahcf->reset_sctlr = 0x30100180; 891 /* 892 * SPAN is disabled by default when SCTLR.SPAN=1. To improve compatibility, 893 * let's disable it on boot and then allow guest software to turn it on by 894 * setting it to 0. 895 */ 896 ahcf->reset_sctlr |= 0x00800000; 897 898 /* Make sure we don't advertise AArch32 support for EL0/EL1 */ 899 if ((host_isar.id_aa64pfr0 & 0xff) != 0x11) { 900 return false; 901 } 902 903 return r == HV_SUCCESS; 904 } 905 906 void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu) 907 { 908 if (!arm_host_cpu_features.dtb_compatible) { 909 if (!hvf_enabled() || 910 !hvf_arm_get_host_cpu_features(&arm_host_cpu_features)) { 911 /* 912 * We can't report this error yet, so flag that we need to 913 * in arm_cpu_realizefn(). 914 */ 915 cpu->host_cpu_probe_failed = true; 916 return; 917 } 918 } 919 920 cpu->dtb_compatible = arm_host_cpu_features.dtb_compatible; 921 cpu->isar = arm_host_cpu_features.isar; 922 cpu->env.features = arm_host_cpu_features.features; 923 cpu->midr = arm_host_cpu_features.midr; 924 cpu->reset_sctlr = arm_host_cpu_features.reset_sctlr; 925 } 926 927 void hvf_arch_vcpu_destroy(CPUState *cpu) 928 { 929 } 930 931 int hvf_arch_init_vcpu(CPUState *cpu) 932 { 933 ARMCPU *arm_cpu = ARM_CPU(cpu); 934 CPUARMState *env = &arm_cpu->env; 935 uint32_t sregs_match_len = ARRAY_SIZE(hvf_sreg_match); 936 uint32_t sregs_cnt = 0; 937 uint64_t pfr; 938 hv_return_t ret; 939 int i; 940 941 env->aarch64 = true; 942 asm volatile("mrs %0, cntfrq_el0" : "=r"(arm_cpu->gt_cntfrq_hz)); 943 944 /* Allocate enough space for our sysreg sync */ 945 arm_cpu->cpreg_indexes = g_renew(uint64_t, arm_cpu->cpreg_indexes, 946 sregs_match_len); 947 arm_cpu->cpreg_values = g_renew(uint64_t, arm_cpu->cpreg_values, 948 sregs_match_len); 949 arm_cpu->cpreg_vmstate_indexes = g_renew(uint64_t, 950 arm_cpu->cpreg_vmstate_indexes, 951 sregs_match_len); 952 arm_cpu->cpreg_vmstate_values = g_renew(uint64_t, 953 arm_cpu->cpreg_vmstate_values, 954 sregs_match_len); 955 956 memset(arm_cpu->cpreg_values, 0, sregs_match_len * sizeof(uint64_t)); 957 958 /* Populate cp list for all known sysregs */ 959 for (i = 0; i < sregs_match_len; i++) { 960 const ARMCPRegInfo *ri; 961 uint32_t key = hvf_sreg_match[i].key; 962 963 ri = get_arm_cp_reginfo(arm_cpu->cp_regs, key); 964 if (ri) { 965 assert(!(ri->type & ARM_CP_NO_RAW)); 966 hvf_sreg_match[i].cp_idx = sregs_cnt; 967 arm_cpu->cpreg_indexes[sregs_cnt++] = cpreg_to_kvm_id(key); 968 } else { 969 hvf_sreg_match[i].cp_idx = -1; 970 } 971 } 972 arm_cpu->cpreg_array_len = sregs_cnt; 973 arm_cpu->cpreg_vmstate_array_len = sregs_cnt; 974 975 assert(write_cpustate_to_list(arm_cpu, false)); 976 977 /* Set CP_NO_RAW system registers on init */ 978 ret = hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_MIDR_EL1, 979 arm_cpu->midr); 980 assert_hvf_ok(ret); 981 982 ret = hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_MPIDR_EL1, 983 arm_cpu->mp_affinity); 984 assert_hvf_ok(ret); 985 986 ret = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64PFR0_EL1, &pfr); 987 assert_hvf_ok(ret); 988 pfr |= env->gicv3state ? (1 << 24) : 0; 989 ret = hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64PFR0_EL1, pfr); 990 assert_hvf_ok(ret); 991 992 /* We're limited to underlying hardware caps, override internal versions */ 993 ret = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64MMFR0_EL1, 994 &arm_cpu->isar.id_aa64mmfr0); 995 assert_hvf_ok(ret); 996 997 return 0; 998 } 999 1000 void hvf_kick_vcpu_thread(CPUState *cpu) 1001 { 1002 cpus_kick_thread(cpu); 1003 hv_vcpus_exit(&cpu->accel->fd, 1); 1004 } 1005 1006 static void hvf_raise_exception(CPUState *cpu, uint32_t excp, 1007 uint32_t syndrome) 1008 { 1009 ARMCPU *arm_cpu = ARM_CPU(cpu); 1010 CPUARMState *env = &arm_cpu->env; 1011 1012 cpu->exception_index = excp; 1013 env->exception.target_el = 1; 1014 env->exception.syndrome = syndrome; 1015 1016 arm_cpu_do_interrupt(cpu); 1017 } 1018 1019 static void hvf_psci_cpu_off(ARMCPU *arm_cpu) 1020 { 1021 int32_t ret = arm_set_cpu_off(arm_cpu_mp_affinity(arm_cpu)); 1022 assert(ret == QEMU_ARM_POWERCTL_RET_SUCCESS); 1023 } 1024 1025 /* 1026 * Handle a PSCI call. 1027 * 1028 * Returns 0 on success 1029 * -1 when the PSCI call is unknown, 1030 */ 1031 static bool hvf_handle_psci_call(CPUState *cpu) 1032 { 1033 ARMCPU *arm_cpu = ARM_CPU(cpu); 1034 CPUARMState *env = &arm_cpu->env; 1035 uint64_t param[4] = { 1036 env->xregs[0], 1037 env->xregs[1], 1038 env->xregs[2], 1039 env->xregs[3] 1040 }; 1041 uint64_t context_id, mpidr; 1042 bool target_aarch64 = true; 1043 CPUState *target_cpu_state; 1044 ARMCPU *target_cpu; 1045 target_ulong entry; 1046 int target_el = 1; 1047 int32_t ret = 0; 1048 1049 trace_hvf_psci_call(param[0], param[1], param[2], param[3], 1050 arm_cpu_mp_affinity(arm_cpu)); 1051 1052 switch (param[0]) { 1053 case QEMU_PSCI_0_2_FN_PSCI_VERSION: 1054 ret = QEMU_PSCI_VERSION_1_1; 1055 break; 1056 case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE: 1057 ret = QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED; /* No trusted OS */ 1058 break; 1059 case QEMU_PSCI_0_2_FN_AFFINITY_INFO: 1060 case QEMU_PSCI_0_2_FN64_AFFINITY_INFO: 1061 mpidr = param[1]; 1062 1063 switch (param[2]) { 1064 case 0: 1065 target_cpu_state = arm_get_cpu_by_id(mpidr); 1066 if (!target_cpu_state) { 1067 ret = QEMU_PSCI_RET_INVALID_PARAMS; 1068 break; 1069 } 1070 target_cpu = ARM_CPU(target_cpu_state); 1071 1072 ret = target_cpu->power_state; 1073 break; 1074 default: 1075 /* Everything above affinity level 0 is always on. */ 1076 ret = 0; 1077 } 1078 break; 1079 case QEMU_PSCI_0_2_FN_SYSTEM_RESET: 1080 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 1081 /* 1082 * QEMU reset and shutdown are async requests, but PSCI 1083 * mandates that we never return from the reset/shutdown 1084 * call, so power the CPU off now so it doesn't execute 1085 * anything further. 1086 */ 1087 hvf_psci_cpu_off(arm_cpu); 1088 break; 1089 case QEMU_PSCI_0_2_FN_SYSTEM_OFF: 1090 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 1091 hvf_psci_cpu_off(arm_cpu); 1092 break; 1093 case QEMU_PSCI_0_1_FN_CPU_ON: 1094 case QEMU_PSCI_0_2_FN_CPU_ON: 1095 case QEMU_PSCI_0_2_FN64_CPU_ON: 1096 mpidr = param[1]; 1097 entry = param[2]; 1098 context_id = param[3]; 1099 ret = arm_set_cpu_on(mpidr, entry, context_id, 1100 target_el, target_aarch64); 1101 break; 1102 case QEMU_PSCI_0_1_FN_CPU_OFF: 1103 case QEMU_PSCI_0_2_FN_CPU_OFF: 1104 hvf_psci_cpu_off(arm_cpu); 1105 break; 1106 case QEMU_PSCI_0_1_FN_CPU_SUSPEND: 1107 case QEMU_PSCI_0_2_FN_CPU_SUSPEND: 1108 case QEMU_PSCI_0_2_FN64_CPU_SUSPEND: 1109 /* Affinity levels are not supported in QEMU */ 1110 if (param[1] & 0xfffe0000) { 1111 ret = QEMU_PSCI_RET_INVALID_PARAMS; 1112 break; 1113 } 1114 /* Powerdown is not supported, we always go into WFI */ 1115 env->xregs[0] = 0; 1116 hvf_wfi(cpu); 1117 break; 1118 case QEMU_PSCI_0_1_FN_MIGRATE: 1119 case QEMU_PSCI_0_2_FN_MIGRATE: 1120 ret = QEMU_PSCI_RET_NOT_SUPPORTED; 1121 break; 1122 case QEMU_PSCI_1_0_FN_PSCI_FEATURES: 1123 switch (param[1]) { 1124 case QEMU_PSCI_0_2_FN_PSCI_VERSION: 1125 case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE: 1126 case QEMU_PSCI_0_2_FN_AFFINITY_INFO: 1127 case QEMU_PSCI_0_2_FN64_AFFINITY_INFO: 1128 case QEMU_PSCI_0_2_FN_SYSTEM_RESET: 1129 case QEMU_PSCI_0_2_FN_SYSTEM_OFF: 1130 case QEMU_PSCI_0_1_FN_CPU_ON: 1131 case QEMU_PSCI_0_2_FN_CPU_ON: 1132 case QEMU_PSCI_0_2_FN64_CPU_ON: 1133 case QEMU_PSCI_0_1_FN_CPU_OFF: 1134 case QEMU_PSCI_0_2_FN_CPU_OFF: 1135 case QEMU_PSCI_0_1_FN_CPU_SUSPEND: 1136 case QEMU_PSCI_0_2_FN_CPU_SUSPEND: 1137 case QEMU_PSCI_0_2_FN64_CPU_SUSPEND: 1138 case QEMU_PSCI_1_0_FN_PSCI_FEATURES: 1139 ret = 0; 1140 break; 1141 case QEMU_PSCI_0_1_FN_MIGRATE: 1142 case QEMU_PSCI_0_2_FN_MIGRATE: 1143 default: 1144 ret = QEMU_PSCI_RET_NOT_SUPPORTED; 1145 } 1146 break; 1147 default: 1148 return false; 1149 } 1150 1151 env->xregs[0] = ret; 1152 return true; 1153 } 1154 1155 static bool is_id_sysreg(uint32_t reg) 1156 { 1157 return SYSREG_OP0(reg) == 3 && 1158 SYSREG_OP1(reg) == 0 && 1159 SYSREG_CRN(reg) == 0 && 1160 SYSREG_CRM(reg) >= 1 && 1161 SYSREG_CRM(reg) < 8; 1162 } 1163 1164 static uint32_t hvf_reg2cp_reg(uint32_t reg) 1165 { 1166 return ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, 1167 (reg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK, 1168 (reg >> SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK, 1169 (reg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK, 1170 (reg >> SYSREG_OP1_SHIFT) & SYSREG_OP1_MASK, 1171 (reg >> SYSREG_OP2_SHIFT) & SYSREG_OP2_MASK); 1172 } 1173 1174 static bool hvf_sysreg_read_cp(CPUState *cpu, uint32_t reg, uint64_t *val) 1175 { 1176 ARMCPU *arm_cpu = ARM_CPU(cpu); 1177 CPUARMState *env = &arm_cpu->env; 1178 const ARMCPRegInfo *ri; 1179 1180 ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg)); 1181 if (ri) { 1182 if (ri->accessfn) { 1183 if (ri->accessfn(env, ri, true) != CP_ACCESS_OK) { 1184 return false; 1185 } 1186 } 1187 if (ri->type & ARM_CP_CONST) { 1188 *val = ri->resetvalue; 1189 } else if (ri->readfn) { 1190 *val = ri->readfn(env, ri); 1191 } else { 1192 *val = CPREG_FIELD64(env, ri); 1193 } 1194 trace_hvf_vgic_read(ri->name, *val); 1195 return true; 1196 } 1197 1198 return false; 1199 } 1200 1201 static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt) 1202 { 1203 ARMCPU *arm_cpu = ARM_CPU(cpu); 1204 CPUARMState *env = &arm_cpu->env; 1205 uint64_t val = 0; 1206 1207 switch (reg) { 1208 case SYSREG_CNTPCT_EL0: 1209 val = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / 1210 gt_cntfrq_period_ns(arm_cpu); 1211 break; 1212 case SYSREG_PMCR_EL0: 1213 val = env->cp15.c9_pmcr; 1214 break; 1215 case SYSREG_PMCCNTR_EL0: 1216 pmu_op_start(env); 1217 val = env->cp15.c15_ccnt; 1218 pmu_op_finish(env); 1219 break; 1220 case SYSREG_PMCNTENCLR_EL0: 1221 val = env->cp15.c9_pmcnten; 1222 break; 1223 case SYSREG_PMOVSCLR_EL0: 1224 val = env->cp15.c9_pmovsr; 1225 break; 1226 case SYSREG_PMSELR_EL0: 1227 val = env->cp15.c9_pmselr; 1228 break; 1229 case SYSREG_PMINTENCLR_EL1: 1230 val = env->cp15.c9_pminten; 1231 break; 1232 case SYSREG_PMCCFILTR_EL0: 1233 val = env->cp15.pmccfiltr_el0; 1234 break; 1235 case SYSREG_PMCNTENSET_EL0: 1236 val = env->cp15.c9_pmcnten; 1237 break; 1238 case SYSREG_PMUSERENR_EL0: 1239 val = env->cp15.c9_pmuserenr; 1240 break; 1241 case SYSREG_PMCEID0_EL0: 1242 case SYSREG_PMCEID1_EL0: 1243 /* We can't really count anything yet, declare all events invalid */ 1244 val = 0; 1245 break; 1246 case SYSREG_OSLSR_EL1: 1247 val = env->cp15.oslsr_el1; 1248 break; 1249 case SYSREG_OSDLR_EL1: 1250 /* Dummy register */ 1251 break; 1252 case SYSREG_ICC_AP0R0_EL1: 1253 case SYSREG_ICC_AP0R1_EL1: 1254 case SYSREG_ICC_AP0R2_EL1: 1255 case SYSREG_ICC_AP0R3_EL1: 1256 case SYSREG_ICC_AP1R0_EL1: 1257 case SYSREG_ICC_AP1R1_EL1: 1258 case SYSREG_ICC_AP1R2_EL1: 1259 case SYSREG_ICC_AP1R3_EL1: 1260 case SYSREG_ICC_ASGI1R_EL1: 1261 case SYSREG_ICC_BPR0_EL1: 1262 case SYSREG_ICC_BPR1_EL1: 1263 case SYSREG_ICC_DIR_EL1: 1264 case SYSREG_ICC_EOIR0_EL1: 1265 case SYSREG_ICC_EOIR1_EL1: 1266 case SYSREG_ICC_HPPIR0_EL1: 1267 case SYSREG_ICC_HPPIR1_EL1: 1268 case SYSREG_ICC_IAR0_EL1: 1269 case SYSREG_ICC_IAR1_EL1: 1270 case SYSREG_ICC_IGRPEN0_EL1: 1271 case SYSREG_ICC_IGRPEN1_EL1: 1272 case SYSREG_ICC_PMR_EL1: 1273 case SYSREG_ICC_SGI0R_EL1: 1274 case SYSREG_ICC_SGI1R_EL1: 1275 case SYSREG_ICC_SRE_EL1: 1276 case SYSREG_ICC_CTLR_EL1: 1277 /* Call the TCG sysreg handler. This is only safe for GICv3 regs. */ 1278 if (!hvf_sysreg_read_cp(cpu, reg, &val)) { 1279 hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); 1280 } 1281 break; 1282 case SYSREG_DBGBVR0_EL1: 1283 case SYSREG_DBGBVR1_EL1: 1284 case SYSREG_DBGBVR2_EL1: 1285 case SYSREG_DBGBVR3_EL1: 1286 case SYSREG_DBGBVR4_EL1: 1287 case SYSREG_DBGBVR5_EL1: 1288 case SYSREG_DBGBVR6_EL1: 1289 case SYSREG_DBGBVR7_EL1: 1290 case SYSREG_DBGBVR8_EL1: 1291 case SYSREG_DBGBVR9_EL1: 1292 case SYSREG_DBGBVR10_EL1: 1293 case SYSREG_DBGBVR11_EL1: 1294 case SYSREG_DBGBVR12_EL1: 1295 case SYSREG_DBGBVR13_EL1: 1296 case SYSREG_DBGBVR14_EL1: 1297 case SYSREG_DBGBVR15_EL1: 1298 val = env->cp15.dbgbvr[SYSREG_CRM(reg)]; 1299 break; 1300 case SYSREG_DBGBCR0_EL1: 1301 case SYSREG_DBGBCR1_EL1: 1302 case SYSREG_DBGBCR2_EL1: 1303 case SYSREG_DBGBCR3_EL1: 1304 case SYSREG_DBGBCR4_EL1: 1305 case SYSREG_DBGBCR5_EL1: 1306 case SYSREG_DBGBCR6_EL1: 1307 case SYSREG_DBGBCR7_EL1: 1308 case SYSREG_DBGBCR8_EL1: 1309 case SYSREG_DBGBCR9_EL1: 1310 case SYSREG_DBGBCR10_EL1: 1311 case SYSREG_DBGBCR11_EL1: 1312 case SYSREG_DBGBCR12_EL1: 1313 case SYSREG_DBGBCR13_EL1: 1314 case SYSREG_DBGBCR14_EL1: 1315 case SYSREG_DBGBCR15_EL1: 1316 val = env->cp15.dbgbcr[SYSREG_CRM(reg)]; 1317 break; 1318 case SYSREG_DBGWVR0_EL1: 1319 case SYSREG_DBGWVR1_EL1: 1320 case SYSREG_DBGWVR2_EL1: 1321 case SYSREG_DBGWVR3_EL1: 1322 case SYSREG_DBGWVR4_EL1: 1323 case SYSREG_DBGWVR5_EL1: 1324 case SYSREG_DBGWVR6_EL1: 1325 case SYSREG_DBGWVR7_EL1: 1326 case SYSREG_DBGWVR8_EL1: 1327 case SYSREG_DBGWVR9_EL1: 1328 case SYSREG_DBGWVR10_EL1: 1329 case SYSREG_DBGWVR11_EL1: 1330 case SYSREG_DBGWVR12_EL1: 1331 case SYSREG_DBGWVR13_EL1: 1332 case SYSREG_DBGWVR14_EL1: 1333 case SYSREG_DBGWVR15_EL1: 1334 val = env->cp15.dbgwvr[SYSREG_CRM(reg)]; 1335 break; 1336 case SYSREG_DBGWCR0_EL1: 1337 case SYSREG_DBGWCR1_EL1: 1338 case SYSREG_DBGWCR2_EL1: 1339 case SYSREG_DBGWCR3_EL1: 1340 case SYSREG_DBGWCR4_EL1: 1341 case SYSREG_DBGWCR5_EL1: 1342 case SYSREG_DBGWCR6_EL1: 1343 case SYSREG_DBGWCR7_EL1: 1344 case SYSREG_DBGWCR8_EL1: 1345 case SYSREG_DBGWCR9_EL1: 1346 case SYSREG_DBGWCR10_EL1: 1347 case SYSREG_DBGWCR11_EL1: 1348 case SYSREG_DBGWCR12_EL1: 1349 case SYSREG_DBGWCR13_EL1: 1350 case SYSREG_DBGWCR14_EL1: 1351 case SYSREG_DBGWCR15_EL1: 1352 val = env->cp15.dbgwcr[SYSREG_CRM(reg)]; 1353 break; 1354 default: 1355 if (is_id_sysreg(reg)) { 1356 /* ID system registers read as RES0 */ 1357 val = 0; 1358 break; 1359 } 1360 cpu_synchronize_state(cpu); 1361 trace_hvf_unhandled_sysreg_read(env->pc, reg, 1362 SYSREG_OP0(reg), 1363 SYSREG_OP1(reg), 1364 SYSREG_CRN(reg), 1365 SYSREG_CRM(reg), 1366 SYSREG_OP2(reg)); 1367 hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); 1368 return 1; 1369 } 1370 1371 trace_hvf_sysreg_read(reg, 1372 SYSREG_OP0(reg), 1373 SYSREG_OP1(reg), 1374 SYSREG_CRN(reg), 1375 SYSREG_CRM(reg), 1376 SYSREG_OP2(reg), 1377 val); 1378 hvf_set_reg(cpu, rt, val); 1379 1380 return 0; 1381 } 1382 1383 static void pmu_update_irq(CPUARMState *env) 1384 { 1385 ARMCPU *cpu = env_archcpu(env); 1386 qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) && 1387 (env->cp15.c9_pminten & env->cp15.c9_pmovsr)); 1388 } 1389 1390 static bool pmu_event_supported(uint16_t number) 1391 { 1392 return false; 1393 } 1394 1395 /* Returns true if the counter (pass 31 for PMCCNTR) should count events using 1396 * the current EL, security state, and register configuration. 1397 */ 1398 static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter) 1399 { 1400 uint64_t filter; 1401 bool enabled, filtered = true; 1402 int el = arm_current_el(env); 1403 1404 enabled = (env->cp15.c9_pmcr & PMCRE) && 1405 (env->cp15.c9_pmcnten & (1 << counter)); 1406 1407 if (counter == 31) { 1408 filter = env->cp15.pmccfiltr_el0; 1409 } else { 1410 filter = env->cp15.c14_pmevtyper[counter]; 1411 } 1412 1413 if (el == 0) { 1414 filtered = filter & PMXEVTYPER_U; 1415 } else if (el == 1) { 1416 filtered = filter & PMXEVTYPER_P; 1417 } 1418 1419 if (counter != 31) { 1420 /* 1421 * If not checking PMCCNTR, ensure the counter is setup to an event we 1422 * support 1423 */ 1424 uint16_t event = filter & PMXEVTYPER_EVTCOUNT; 1425 if (!pmu_event_supported(event)) { 1426 return false; 1427 } 1428 } 1429 1430 return enabled && !filtered; 1431 } 1432 1433 static void pmswinc_write(CPUARMState *env, uint64_t value) 1434 { 1435 unsigned int i; 1436 for (i = 0; i < pmu_num_counters(env); i++) { 1437 /* Increment a counter's count iff: */ 1438 if ((value & (1 << i)) && /* counter's bit is set */ 1439 /* counter is enabled and not filtered */ 1440 pmu_counter_enabled(env, i) && 1441 /* counter is SW_INCR */ 1442 (env->cp15.c14_pmevtyper[i] & PMXEVTYPER_EVTCOUNT) == 0x0) { 1443 /* 1444 * Detect if this write causes an overflow since we can't predict 1445 * PMSWINC overflows like we can for other events 1446 */ 1447 uint32_t new_pmswinc = env->cp15.c14_pmevcntr[i] + 1; 1448 1449 if (env->cp15.c14_pmevcntr[i] & ~new_pmswinc & INT32_MIN) { 1450 env->cp15.c9_pmovsr |= (1 << i); 1451 pmu_update_irq(env); 1452 } 1453 1454 env->cp15.c14_pmevcntr[i] = new_pmswinc; 1455 } 1456 } 1457 } 1458 1459 static bool hvf_sysreg_write_cp(CPUState *cpu, uint32_t reg, uint64_t val) 1460 { 1461 ARMCPU *arm_cpu = ARM_CPU(cpu); 1462 CPUARMState *env = &arm_cpu->env; 1463 const ARMCPRegInfo *ri; 1464 1465 ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg)); 1466 1467 if (ri) { 1468 if (ri->accessfn) { 1469 if (ri->accessfn(env, ri, false) != CP_ACCESS_OK) { 1470 return false; 1471 } 1472 } 1473 if (ri->writefn) { 1474 ri->writefn(env, ri, val); 1475 } else { 1476 CPREG_FIELD64(env, ri) = val; 1477 } 1478 1479 trace_hvf_vgic_write(ri->name, val); 1480 return true; 1481 } 1482 1483 return false; 1484 } 1485 1486 static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) 1487 { 1488 ARMCPU *arm_cpu = ARM_CPU(cpu); 1489 CPUARMState *env = &arm_cpu->env; 1490 1491 trace_hvf_sysreg_write(reg, 1492 SYSREG_OP0(reg), 1493 SYSREG_OP1(reg), 1494 SYSREG_CRN(reg), 1495 SYSREG_CRM(reg), 1496 SYSREG_OP2(reg), 1497 val); 1498 1499 switch (reg) { 1500 case SYSREG_PMCCNTR_EL0: 1501 pmu_op_start(env); 1502 env->cp15.c15_ccnt = val; 1503 pmu_op_finish(env); 1504 break; 1505 case SYSREG_PMCR_EL0: 1506 pmu_op_start(env); 1507 1508 if (val & PMCRC) { 1509 /* The counter has been reset */ 1510 env->cp15.c15_ccnt = 0; 1511 } 1512 1513 if (val & PMCRP) { 1514 unsigned int i; 1515 for (i = 0; i < pmu_num_counters(env); i++) { 1516 env->cp15.c14_pmevcntr[i] = 0; 1517 } 1518 } 1519 1520 env->cp15.c9_pmcr &= ~PMCR_WRITABLE_MASK; 1521 env->cp15.c9_pmcr |= (val & PMCR_WRITABLE_MASK); 1522 1523 pmu_op_finish(env); 1524 break; 1525 case SYSREG_PMUSERENR_EL0: 1526 env->cp15.c9_pmuserenr = val & 0xf; 1527 break; 1528 case SYSREG_PMCNTENSET_EL0: 1529 env->cp15.c9_pmcnten |= (val & pmu_counter_mask(env)); 1530 break; 1531 case SYSREG_PMCNTENCLR_EL0: 1532 env->cp15.c9_pmcnten &= ~(val & pmu_counter_mask(env)); 1533 break; 1534 case SYSREG_PMINTENCLR_EL1: 1535 pmu_op_start(env); 1536 env->cp15.c9_pminten |= val; 1537 pmu_op_finish(env); 1538 break; 1539 case SYSREG_PMOVSCLR_EL0: 1540 pmu_op_start(env); 1541 env->cp15.c9_pmovsr &= ~val; 1542 pmu_op_finish(env); 1543 break; 1544 case SYSREG_PMSWINC_EL0: 1545 pmu_op_start(env); 1546 pmswinc_write(env, val); 1547 pmu_op_finish(env); 1548 break; 1549 case SYSREG_PMSELR_EL0: 1550 env->cp15.c9_pmselr = val & 0x1f; 1551 break; 1552 case SYSREG_PMCCFILTR_EL0: 1553 pmu_op_start(env); 1554 env->cp15.pmccfiltr_el0 = val & PMCCFILTR_EL0; 1555 pmu_op_finish(env); 1556 break; 1557 case SYSREG_OSLAR_EL1: 1558 env->cp15.oslsr_el1 = val & 1; 1559 break; 1560 case SYSREG_OSDLR_EL1: 1561 /* Dummy register */ 1562 break; 1563 case SYSREG_ICC_AP0R0_EL1: 1564 case SYSREG_ICC_AP0R1_EL1: 1565 case SYSREG_ICC_AP0R2_EL1: 1566 case SYSREG_ICC_AP0R3_EL1: 1567 case SYSREG_ICC_AP1R0_EL1: 1568 case SYSREG_ICC_AP1R1_EL1: 1569 case SYSREG_ICC_AP1R2_EL1: 1570 case SYSREG_ICC_AP1R3_EL1: 1571 case SYSREG_ICC_ASGI1R_EL1: 1572 case SYSREG_ICC_BPR0_EL1: 1573 case SYSREG_ICC_BPR1_EL1: 1574 case SYSREG_ICC_CTLR_EL1: 1575 case SYSREG_ICC_DIR_EL1: 1576 case SYSREG_ICC_EOIR0_EL1: 1577 case SYSREG_ICC_EOIR1_EL1: 1578 case SYSREG_ICC_HPPIR0_EL1: 1579 case SYSREG_ICC_HPPIR1_EL1: 1580 case SYSREG_ICC_IAR0_EL1: 1581 case SYSREG_ICC_IAR1_EL1: 1582 case SYSREG_ICC_IGRPEN0_EL1: 1583 case SYSREG_ICC_IGRPEN1_EL1: 1584 case SYSREG_ICC_PMR_EL1: 1585 case SYSREG_ICC_SGI0R_EL1: 1586 case SYSREG_ICC_SGI1R_EL1: 1587 case SYSREG_ICC_SRE_EL1: 1588 /* Call the TCG sysreg handler. This is only safe for GICv3 regs. */ 1589 if (!hvf_sysreg_write_cp(cpu, reg, val)) { 1590 hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); 1591 } 1592 break; 1593 case SYSREG_MDSCR_EL1: 1594 env->cp15.mdscr_el1 = val; 1595 break; 1596 case SYSREG_DBGBVR0_EL1: 1597 case SYSREG_DBGBVR1_EL1: 1598 case SYSREG_DBGBVR2_EL1: 1599 case SYSREG_DBGBVR3_EL1: 1600 case SYSREG_DBGBVR4_EL1: 1601 case SYSREG_DBGBVR5_EL1: 1602 case SYSREG_DBGBVR6_EL1: 1603 case SYSREG_DBGBVR7_EL1: 1604 case SYSREG_DBGBVR8_EL1: 1605 case SYSREG_DBGBVR9_EL1: 1606 case SYSREG_DBGBVR10_EL1: 1607 case SYSREG_DBGBVR11_EL1: 1608 case SYSREG_DBGBVR12_EL1: 1609 case SYSREG_DBGBVR13_EL1: 1610 case SYSREG_DBGBVR14_EL1: 1611 case SYSREG_DBGBVR15_EL1: 1612 env->cp15.dbgbvr[SYSREG_CRM(reg)] = val; 1613 break; 1614 case SYSREG_DBGBCR0_EL1: 1615 case SYSREG_DBGBCR1_EL1: 1616 case SYSREG_DBGBCR2_EL1: 1617 case SYSREG_DBGBCR3_EL1: 1618 case SYSREG_DBGBCR4_EL1: 1619 case SYSREG_DBGBCR5_EL1: 1620 case SYSREG_DBGBCR6_EL1: 1621 case SYSREG_DBGBCR7_EL1: 1622 case SYSREG_DBGBCR8_EL1: 1623 case SYSREG_DBGBCR9_EL1: 1624 case SYSREG_DBGBCR10_EL1: 1625 case SYSREG_DBGBCR11_EL1: 1626 case SYSREG_DBGBCR12_EL1: 1627 case SYSREG_DBGBCR13_EL1: 1628 case SYSREG_DBGBCR14_EL1: 1629 case SYSREG_DBGBCR15_EL1: 1630 env->cp15.dbgbcr[SYSREG_CRM(reg)] = val; 1631 break; 1632 case SYSREG_DBGWVR0_EL1: 1633 case SYSREG_DBGWVR1_EL1: 1634 case SYSREG_DBGWVR2_EL1: 1635 case SYSREG_DBGWVR3_EL1: 1636 case SYSREG_DBGWVR4_EL1: 1637 case SYSREG_DBGWVR5_EL1: 1638 case SYSREG_DBGWVR6_EL1: 1639 case SYSREG_DBGWVR7_EL1: 1640 case SYSREG_DBGWVR8_EL1: 1641 case SYSREG_DBGWVR9_EL1: 1642 case SYSREG_DBGWVR10_EL1: 1643 case SYSREG_DBGWVR11_EL1: 1644 case SYSREG_DBGWVR12_EL1: 1645 case SYSREG_DBGWVR13_EL1: 1646 case SYSREG_DBGWVR14_EL1: 1647 case SYSREG_DBGWVR15_EL1: 1648 env->cp15.dbgwvr[SYSREG_CRM(reg)] = val; 1649 break; 1650 case SYSREG_DBGWCR0_EL1: 1651 case SYSREG_DBGWCR1_EL1: 1652 case SYSREG_DBGWCR2_EL1: 1653 case SYSREG_DBGWCR3_EL1: 1654 case SYSREG_DBGWCR4_EL1: 1655 case SYSREG_DBGWCR5_EL1: 1656 case SYSREG_DBGWCR6_EL1: 1657 case SYSREG_DBGWCR7_EL1: 1658 case SYSREG_DBGWCR8_EL1: 1659 case SYSREG_DBGWCR9_EL1: 1660 case SYSREG_DBGWCR10_EL1: 1661 case SYSREG_DBGWCR11_EL1: 1662 case SYSREG_DBGWCR12_EL1: 1663 case SYSREG_DBGWCR13_EL1: 1664 case SYSREG_DBGWCR14_EL1: 1665 case SYSREG_DBGWCR15_EL1: 1666 env->cp15.dbgwcr[SYSREG_CRM(reg)] = val; 1667 break; 1668 default: 1669 cpu_synchronize_state(cpu); 1670 trace_hvf_unhandled_sysreg_write(env->pc, reg, 1671 SYSREG_OP0(reg), 1672 SYSREG_OP1(reg), 1673 SYSREG_CRN(reg), 1674 SYSREG_CRM(reg), 1675 SYSREG_OP2(reg)); 1676 hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); 1677 return 1; 1678 } 1679 1680 return 0; 1681 } 1682 1683 static int hvf_inject_interrupts(CPUState *cpu) 1684 { 1685 if (cpu->interrupt_request & CPU_INTERRUPT_FIQ) { 1686 trace_hvf_inject_fiq(); 1687 hv_vcpu_set_pending_interrupt(cpu->accel->fd, HV_INTERRUPT_TYPE_FIQ, 1688 true); 1689 } 1690 1691 if (cpu->interrupt_request & CPU_INTERRUPT_HARD) { 1692 trace_hvf_inject_irq(); 1693 hv_vcpu_set_pending_interrupt(cpu->accel->fd, HV_INTERRUPT_TYPE_IRQ, 1694 true); 1695 } 1696 1697 return 0; 1698 } 1699 1700 static uint64_t hvf_vtimer_val_raw(void) 1701 { 1702 /* 1703 * mach_absolute_time() returns the vtimer value without the VM 1704 * offset that we define. Add our own offset on top. 1705 */ 1706 return mach_absolute_time() - hvf_state->vtimer_offset; 1707 } 1708 1709 static uint64_t hvf_vtimer_val(void) 1710 { 1711 if (!runstate_is_running()) { 1712 /* VM is paused, the vtimer value is in vtimer.vtimer_val */ 1713 return vtimer.vtimer_val; 1714 } 1715 1716 return hvf_vtimer_val_raw(); 1717 } 1718 1719 static void hvf_wait_for_ipi(CPUState *cpu, struct timespec *ts) 1720 { 1721 /* 1722 * Use pselect to sleep so that other threads can IPI us while we're 1723 * sleeping. 1724 */ 1725 qatomic_set_mb(&cpu->thread_kicked, false); 1726 bql_unlock(); 1727 pselect(0, 0, 0, 0, ts, &cpu->accel->unblock_ipi_mask); 1728 bql_lock(); 1729 } 1730 1731 static void hvf_wfi(CPUState *cpu) 1732 { 1733 ARMCPU *arm_cpu = ARM_CPU(cpu); 1734 struct timespec ts; 1735 hv_return_t r; 1736 uint64_t ctl; 1737 uint64_t cval; 1738 int64_t ticks_to_sleep; 1739 uint64_t seconds; 1740 uint64_t nanos; 1741 uint32_t cntfrq; 1742 1743 if (cpu->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIQ)) { 1744 /* Interrupt pending, no need to wait */ 1745 return; 1746 } 1747 1748 r = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTV_CTL_EL0, &ctl); 1749 assert_hvf_ok(r); 1750 1751 if (!(ctl & 1) || (ctl & 2)) { 1752 /* Timer disabled or masked, just wait for an IPI. */ 1753 hvf_wait_for_ipi(cpu, NULL); 1754 return; 1755 } 1756 1757 r = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTV_CVAL_EL0, &cval); 1758 assert_hvf_ok(r); 1759 1760 ticks_to_sleep = cval - hvf_vtimer_val(); 1761 if (ticks_to_sleep < 0) { 1762 return; 1763 } 1764 1765 cntfrq = gt_cntfrq_period_ns(arm_cpu); 1766 seconds = muldiv64(ticks_to_sleep, cntfrq, NANOSECONDS_PER_SECOND); 1767 ticks_to_sleep -= muldiv64(seconds, NANOSECONDS_PER_SECOND, cntfrq); 1768 nanos = ticks_to_sleep * cntfrq; 1769 1770 /* 1771 * Don't sleep for less than the time a context switch would take, 1772 * so that we can satisfy fast timer requests on the same CPU. 1773 * Measurements on M1 show the sweet spot to be ~2ms. 1774 */ 1775 if (!seconds && nanos < (2 * SCALE_MS)) { 1776 return; 1777 } 1778 1779 ts = (struct timespec) { seconds, nanos }; 1780 hvf_wait_for_ipi(cpu, &ts); 1781 } 1782 1783 static void hvf_sync_vtimer(CPUState *cpu) 1784 { 1785 ARMCPU *arm_cpu = ARM_CPU(cpu); 1786 hv_return_t r; 1787 uint64_t ctl; 1788 bool irq_state; 1789 1790 if (!cpu->accel->vtimer_masked) { 1791 /* We will get notified on vtimer changes by hvf, nothing to do */ 1792 return; 1793 } 1794 1795 r = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTV_CTL_EL0, &ctl); 1796 assert_hvf_ok(r); 1797 1798 irq_state = (ctl & (TMR_CTL_ENABLE | TMR_CTL_IMASK | TMR_CTL_ISTATUS)) == 1799 (TMR_CTL_ENABLE | TMR_CTL_ISTATUS); 1800 qemu_set_irq(arm_cpu->gt_timer_outputs[GTIMER_VIRT], irq_state); 1801 1802 if (!irq_state) { 1803 /* Timer no longer asserting, we can unmask it */ 1804 hv_vcpu_set_vtimer_mask(cpu->accel->fd, false); 1805 cpu->accel->vtimer_masked = false; 1806 } 1807 } 1808 1809 int hvf_vcpu_exec(CPUState *cpu) 1810 { 1811 ARMCPU *arm_cpu = ARM_CPU(cpu); 1812 CPUARMState *env = &arm_cpu->env; 1813 int ret; 1814 hv_vcpu_exit_t *hvf_exit = cpu->accel->exit; 1815 hv_return_t r; 1816 bool advance_pc = false; 1817 1818 if (!(cpu->singlestep_enabled & SSTEP_NOIRQ) && 1819 hvf_inject_interrupts(cpu)) { 1820 return EXCP_INTERRUPT; 1821 } 1822 1823 if (cpu->halted) { 1824 return EXCP_HLT; 1825 } 1826 1827 flush_cpu_state(cpu); 1828 1829 bql_unlock(); 1830 assert_hvf_ok(hv_vcpu_run(cpu->accel->fd)); 1831 1832 /* handle VMEXIT */ 1833 uint64_t exit_reason = hvf_exit->reason; 1834 uint64_t syndrome = hvf_exit->exception.syndrome; 1835 uint32_t ec = syn_get_ec(syndrome); 1836 1837 ret = 0; 1838 bql_lock(); 1839 switch (exit_reason) { 1840 case HV_EXIT_REASON_EXCEPTION: 1841 /* This is the main one, handle below. */ 1842 break; 1843 case HV_EXIT_REASON_VTIMER_ACTIVATED: 1844 qemu_set_irq(arm_cpu->gt_timer_outputs[GTIMER_VIRT], 1); 1845 cpu->accel->vtimer_masked = true; 1846 return 0; 1847 case HV_EXIT_REASON_CANCELED: 1848 /* we got kicked, no exit to process */ 1849 return 0; 1850 default: 1851 g_assert_not_reached(); 1852 } 1853 1854 hvf_sync_vtimer(cpu); 1855 1856 switch (ec) { 1857 case EC_SOFTWARESTEP: { 1858 ret = EXCP_DEBUG; 1859 1860 if (!cpu->singlestep_enabled) { 1861 error_report("EC_SOFTWARESTEP but single-stepping not enabled"); 1862 } 1863 break; 1864 } 1865 case EC_AA64_BKPT: { 1866 ret = EXCP_DEBUG; 1867 1868 cpu_synchronize_state(cpu); 1869 1870 if (!hvf_find_sw_breakpoint(cpu, env->pc)) { 1871 /* Re-inject into the guest */ 1872 ret = 0; 1873 hvf_raise_exception(cpu, EXCP_BKPT, syn_aa64_bkpt(0)); 1874 } 1875 break; 1876 } 1877 case EC_BREAKPOINT: { 1878 ret = EXCP_DEBUG; 1879 1880 cpu_synchronize_state(cpu); 1881 1882 if (!find_hw_breakpoint(cpu, env->pc)) { 1883 error_report("EC_BREAKPOINT but unknown hw breakpoint"); 1884 } 1885 break; 1886 } 1887 case EC_WATCHPOINT: { 1888 ret = EXCP_DEBUG; 1889 1890 cpu_synchronize_state(cpu); 1891 1892 CPUWatchpoint *wp = 1893 find_hw_watchpoint(cpu, hvf_exit->exception.virtual_address); 1894 if (!wp) { 1895 error_report("EXCP_DEBUG but unknown hw watchpoint"); 1896 } 1897 cpu->watchpoint_hit = wp; 1898 break; 1899 } 1900 case EC_DATAABORT: { 1901 bool isv = syndrome & ARM_EL_ISV; 1902 bool iswrite = (syndrome >> 6) & 1; 1903 bool s1ptw = (syndrome >> 7) & 1; 1904 uint32_t sas = (syndrome >> 22) & 3; 1905 uint32_t len = 1 << sas; 1906 uint32_t srt = (syndrome >> 16) & 0x1f; 1907 uint32_t cm = (syndrome >> 8) & 0x1; 1908 uint64_t val = 0; 1909 1910 trace_hvf_data_abort(env->pc, hvf_exit->exception.virtual_address, 1911 hvf_exit->exception.physical_address, isv, 1912 iswrite, s1ptw, len, srt); 1913 1914 if (cm) { 1915 /* We don't cache MMIO regions */ 1916 advance_pc = true; 1917 break; 1918 } 1919 1920 assert(isv); 1921 1922 if (iswrite) { 1923 val = hvf_get_reg(cpu, srt); 1924 address_space_write(&address_space_memory, 1925 hvf_exit->exception.physical_address, 1926 MEMTXATTRS_UNSPECIFIED, &val, len); 1927 } else { 1928 address_space_read(&address_space_memory, 1929 hvf_exit->exception.physical_address, 1930 MEMTXATTRS_UNSPECIFIED, &val, len); 1931 hvf_set_reg(cpu, srt, val); 1932 } 1933 1934 advance_pc = true; 1935 break; 1936 } 1937 case EC_SYSTEMREGISTERTRAP: { 1938 bool isread = (syndrome >> 0) & 1; 1939 uint32_t rt = (syndrome >> 5) & 0x1f; 1940 uint32_t reg = syndrome & SYSREG_MASK; 1941 uint64_t val; 1942 int sysreg_ret = 0; 1943 1944 if (isread) { 1945 sysreg_ret = hvf_sysreg_read(cpu, reg, rt); 1946 } else { 1947 val = hvf_get_reg(cpu, rt); 1948 sysreg_ret = hvf_sysreg_write(cpu, reg, val); 1949 } 1950 1951 advance_pc = !sysreg_ret; 1952 break; 1953 } 1954 case EC_WFX_TRAP: 1955 advance_pc = true; 1956 if (!(syndrome & WFX_IS_WFE)) { 1957 hvf_wfi(cpu); 1958 } 1959 break; 1960 case EC_AA64_HVC: 1961 cpu_synchronize_state(cpu); 1962 if (arm_cpu->psci_conduit == QEMU_PSCI_CONDUIT_HVC) { 1963 if (!hvf_handle_psci_call(cpu)) { 1964 trace_hvf_unknown_hvc(env->xregs[0]); 1965 /* SMCCC 1.3 section 5.2 says every unknown SMCCC call returns -1 */ 1966 env->xregs[0] = -1; 1967 } 1968 } else { 1969 trace_hvf_unknown_hvc(env->xregs[0]); 1970 hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); 1971 } 1972 break; 1973 case EC_AA64_SMC: 1974 cpu_synchronize_state(cpu); 1975 if (arm_cpu->psci_conduit == QEMU_PSCI_CONDUIT_SMC) { 1976 advance_pc = true; 1977 1978 if (!hvf_handle_psci_call(cpu)) { 1979 trace_hvf_unknown_smc(env->xregs[0]); 1980 /* SMCCC 1.3 section 5.2 says every unknown SMCCC call returns -1 */ 1981 env->xregs[0] = -1; 1982 } 1983 } else { 1984 trace_hvf_unknown_smc(env->xregs[0]); 1985 hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); 1986 } 1987 break; 1988 default: 1989 cpu_synchronize_state(cpu); 1990 trace_hvf_exit(syndrome, ec, env->pc); 1991 error_report("0x%llx: unhandled exception ec=0x%x", env->pc, ec); 1992 } 1993 1994 if (advance_pc) { 1995 uint64_t pc; 1996 1997 flush_cpu_state(cpu); 1998 1999 r = hv_vcpu_get_reg(cpu->accel->fd, HV_REG_PC, &pc); 2000 assert_hvf_ok(r); 2001 pc += 4; 2002 r = hv_vcpu_set_reg(cpu->accel->fd, HV_REG_PC, pc); 2003 assert_hvf_ok(r); 2004 2005 /* Handle single-stepping over instructions which trigger a VM exit */ 2006 if (cpu->singlestep_enabled) { 2007 ret = EXCP_DEBUG; 2008 } 2009 } 2010 2011 return ret; 2012 } 2013 2014 static const VMStateDescription vmstate_hvf_vtimer = { 2015 .name = "hvf-vtimer", 2016 .version_id = 1, 2017 .minimum_version_id = 1, 2018 .fields = (const VMStateField[]) { 2019 VMSTATE_UINT64(vtimer_val, HVFVTimer), 2020 VMSTATE_END_OF_LIST() 2021 }, 2022 }; 2023 2024 static void hvf_vm_state_change(void *opaque, bool running, RunState state) 2025 { 2026 HVFVTimer *s = opaque; 2027 2028 if (running) { 2029 /* Update vtimer offset on all CPUs */ 2030 hvf_state->vtimer_offset = mach_absolute_time() - s->vtimer_val; 2031 cpu_synchronize_all_states(); 2032 } else { 2033 /* Remember vtimer value on every pause */ 2034 s->vtimer_val = hvf_vtimer_val_raw(); 2035 } 2036 } 2037 2038 int hvf_arch_init(void) 2039 { 2040 hvf_state->vtimer_offset = mach_absolute_time(); 2041 vmstate_register(NULL, 0, &vmstate_hvf_vtimer, &vtimer); 2042 qemu_add_vm_change_state_handler(hvf_vm_state_change, &vtimer); 2043 2044 hvf_arm_init_debug(); 2045 2046 return 0; 2047 } 2048 2049 static const uint32_t brk_insn = 0xd4200000; 2050 2051 int hvf_arch_insert_sw_breakpoint(CPUState *cpu, struct hvf_sw_breakpoint *bp) 2052 { 2053 if (cpu_memory_rw_debug(cpu, bp->pc, (uint8_t *)&bp->saved_insn, 4, 0) || 2054 cpu_memory_rw_debug(cpu, bp->pc, (uint8_t *)&brk_insn, 4, 1)) { 2055 return -EINVAL; 2056 } 2057 return 0; 2058 } 2059 2060 int hvf_arch_remove_sw_breakpoint(CPUState *cpu, struct hvf_sw_breakpoint *bp) 2061 { 2062 static uint32_t brk; 2063 2064 if (cpu_memory_rw_debug(cpu, bp->pc, (uint8_t *)&brk, 4, 0) || 2065 brk != brk_insn || 2066 cpu_memory_rw_debug(cpu, bp->pc, (uint8_t *)&bp->saved_insn, 4, 1)) { 2067 return -EINVAL; 2068 } 2069 return 0; 2070 } 2071 2072 int hvf_arch_insert_hw_breakpoint(vaddr addr, vaddr len, int type) 2073 { 2074 switch (type) { 2075 case GDB_BREAKPOINT_HW: 2076 return insert_hw_breakpoint(addr); 2077 case GDB_WATCHPOINT_READ: 2078 case GDB_WATCHPOINT_WRITE: 2079 case GDB_WATCHPOINT_ACCESS: 2080 return insert_hw_watchpoint(addr, len, type); 2081 default: 2082 return -ENOSYS; 2083 } 2084 } 2085 2086 int hvf_arch_remove_hw_breakpoint(vaddr addr, vaddr len, int type) 2087 { 2088 switch (type) { 2089 case GDB_BREAKPOINT_HW: 2090 return delete_hw_breakpoint(addr); 2091 case GDB_WATCHPOINT_READ: 2092 case GDB_WATCHPOINT_WRITE: 2093 case GDB_WATCHPOINT_ACCESS: 2094 return delete_hw_watchpoint(addr, len, type); 2095 default: 2096 return -ENOSYS; 2097 } 2098 } 2099 2100 void hvf_arch_remove_all_hw_breakpoints(void) 2101 { 2102 if (cur_hw_wps > 0) { 2103 g_array_remove_range(hw_watchpoints, 0, cur_hw_wps); 2104 } 2105 if (cur_hw_bps > 0) { 2106 g_array_remove_range(hw_breakpoints, 0, cur_hw_bps); 2107 } 2108 } 2109 2110 /* 2111 * Update the vCPU with the gdbstub's view of debug registers. This view 2112 * consists of all hardware breakpoints and watchpoints inserted so far while 2113 * debugging the guest. 2114 */ 2115 static void hvf_put_gdbstub_debug_registers(CPUState *cpu) 2116 { 2117 hv_return_t r = HV_SUCCESS; 2118 int i; 2119 2120 for (i = 0; i < cur_hw_bps; i++) { 2121 HWBreakpoint *bp = get_hw_bp(i); 2122 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbcr_regs[i], bp->bcr); 2123 assert_hvf_ok(r); 2124 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbvr_regs[i], bp->bvr); 2125 assert_hvf_ok(r); 2126 } 2127 for (i = cur_hw_bps; i < max_hw_bps; i++) { 2128 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbcr_regs[i], 0); 2129 assert_hvf_ok(r); 2130 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbvr_regs[i], 0); 2131 assert_hvf_ok(r); 2132 } 2133 2134 for (i = 0; i < cur_hw_wps; i++) { 2135 HWWatchpoint *wp = get_hw_wp(i); 2136 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwcr_regs[i], wp->wcr); 2137 assert_hvf_ok(r); 2138 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwvr_regs[i], wp->wvr); 2139 assert_hvf_ok(r); 2140 } 2141 for (i = cur_hw_wps; i < max_hw_wps; i++) { 2142 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwcr_regs[i], 0); 2143 assert_hvf_ok(r); 2144 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwvr_regs[i], 0); 2145 assert_hvf_ok(r); 2146 } 2147 } 2148 2149 /* 2150 * Update the vCPU with the guest's view of debug registers. This view is kept 2151 * in the environment at all times. 2152 */ 2153 static void hvf_put_guest_debug_registers(CPUState *cpu) 2154 { 2155 ARMCPU *arm_cpu = ARM_CPU(cpu); 2156 CPUARMState *env = &arm_cpu->env; 2157 hv_return_t r = HV_SUCCESS; 2158 int i; 2159 2160 for (i = 0; i < max_hw_bps; i++) { 2161 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbcr_regs[i], 2162 env->cp15.dbgbcr[i]); 2163 assert_hvf_ok(r); 2164 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbvr_regs[i], 2165 env->cp15.dbgbvr[i]); 2166 assert_hvf_ok(r); 2167 } 2168 2169 for (i = 0; i < max_hw_wps; i++) { 2170 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwcr_regs[i], 2171 env->cp15.dbgwcr[i]); 2172 assert_hvf_ok(r); 2173 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwvr_regs[i], 2174 env->cp15.dbgwvr[i]); 2175 assert_hvf_ok(r); 2176 } 2177 } 2178 2179 static inline bool hvf_arm_hw_debug_active(CPUState *cpu) 2180 { 2181 return ((cur_hw_wps > 0) || (cur_hw_bps > 0)); 2182 } 2183 2184 static void hvf_arch_set_traps(void) 2185 { 2186 CPUState *cpu; 2187 bool should_enable_traps = false; 2188 hv_return_t r = HV_SUCCESS; 2189 2190 /* Check whether guest debugging is enabled for at least one vCPU; if it 2191 * is, enable exiting the guest on all vCPUs */ 2192 CPU_FOREACH(cpu) { 2193 should_enable_traps |= cpu->accel->guest_debug_enabled; 2194 } 2195 CPU_FOREACH(cpu) { 2196 /* Set whether debug exceptions exit the guest */ 2197 r = hv_vcpu_set_trap_debug_exceptions(cpu->accel->fd, 2198 should_enable_traps); 2199 assert_hvf_ok(r); 2200 2201 /* Set whether accesses to debug registers exit the guest */ 2202 r = hv_vcpu_set_trap_debug_reg_accesses(cpu->accel->fd, 2203 should_enable_traps); 2204 assert_hvf_ok(r); 2205 } 2206 } 2207 2208 void hvf_arch_update_guest_debug(CPUState *cpu) 2209 { 2210 ARMCPU *arm_cpu = ARM_CPU(cpu); 2211 CPUARMState *env = &arm_cpu->env; 2212 2213 /* Check whether guest debugging is enabled */ 2214 cpu->accel->guest_debug_enabled = cpu->singlestep_enabled || 2215 hvf_sw_breakpoints_active(cpu) || 2216 hvf_arm_hw_debug_active(cpu); 2217 2218 /* Update debug registers */ 2219 if (cpu->accel->guest_debug_enabled) { 2220 hvf_put_gdbstub_debug_registers(cpu); 2221 } else { 2222 hvf_put_guest_debug_registers(cpu); 2223 } 2224 2225 cpu_synchronize_state(cpu); 2226 2227 /* Enable/disable single-stepping */ 2228 if (cpu->singlestep_enabled) { 2229 env->cp15.mdscr_el1 = 2230 deposit64(env->cp15.mdscr_el1, MDSCR_EL1_SS_SHIFT, 1, 1); 2231 pstate_write(env, pstate_read(env) | PSTATE_SS); 2232 } else { 2233 env->cp15.mdscr_el1 = 2234 deposit64(env->cp15.mdscr_el1, MDSCR_EL1_SS_SHIFT, 1, 0); 2235 } 2236 2237 /* Enable/disable Breakpoint exceptions */ 2238 if (hvf_arm_hw_debug_active(cpu)) { 2239 env->cp15.mdscr_el1 = 2240 deposit64(env->cp15.mdscr_el1, MDSCR_EL1_MDE_SHIFT, 1, 1); 2241 } else { 2242 env->cp15.mdscr_el1 = 2243 deposit64(env->cp15.mdscr_el1, MDSCR_EL1_MDE_SHIFT, 1, 0); 2244 } 2245 2246 hvf_arch_set_traps(); 2247 } 2248 2249 bool hvf_arch_supports_guest_debug(void) 2250 { 2251 return true; 2252 } 2253