1 /* 2 * QEMU Hypervisor.framework support for Apple Silicon 3 4 * Copyright 2020 Alexander Graf <agraf@csgraf.de> 5 * Copyright 2020 Google LLC 6 * 7 * This work is licensed under the terms of the GNU GPL, version 2 or later. 8 * See the COPYING file in the top-level directory. 9 * 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qemu/error-report.h" 14 15 #include "sysemu/runstate.h" 16 #include "sysemu/hvf.h" 17 #include "sysemu/hvf_int.h" 18 #include "sysemu/hw_accel.h" 19 #include "hvf_arm.h" 20 #include "cpregs.h" 21 22 #include <mach/mach_time.h> 23 24 #include "exec/address-spaces.h" 25 #include "hw/irq.h" 26 #include "qemu/main-loop.h" 27 #include "sysemu/cpus.h" 28 #include "arm-powerctl.h" 29 #include "target/arm/cpu.h" 30 #include "target/arm/internals.h" 31 #include "trace/trace-target_arm_hvf.h" 32 #include "migration/vmstate.h" 33 34 #define HVF_SYSREG(crn, crm, op0, op1, op2) \ 35 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2) 36 #define PL1_WRITE_MASK 0x4 37 38 #define SYSREG_OP0_SHIFT 20 39 #define SYSREG_OP0_MASK 0x3 40 #define SYSREG_OP0(sysreg) ((sysreg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK) 41 #define SYSREG_OP1_SHIFT 14 42 #define SYSREG_OP1_MASK 0x7 43 #define SYSREG_OP1(sysreg) ((sysreg >> SYSREG_OP1_SHIFT) & SYSREG_OP1_MASK) 44 #define SYSREG_CRN_SHIFT 10 45 #define SYSREG_CRN_MASK 0xf 46 #define SYSREG_CRN(sysreg) ((sysreg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK) 47 #define SYSREG_CRM_SHIFT 1 48 #define SYSREG_CRM_MASK 0xf 49 #define SYSREG_CRM(sysreg) ((sysreg >> SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK) 50 #define SYSREG_OP2_SHIFT 17 51 #define SYSREG_OP2_MASK 0x7 52 #define SYSREG_OP2(sysreg) ((sysreg >> SYSREG_OP2_SHIFT) & SYSREG_OP2_MASK) 53 54 #define SYSREG(op0, op1, crn, crm, op2) \ 55 ((op0 << SYSREG_OP0_SHIFT) | \ 56 (op1 << SYSREG_OP1_SHIFT) | \ 57 (crn << SYSREG_CRN_SHIFT) | \ 58 (crm << SYSREG_CRM_SHIFT) | \ 59 (op2 << SYSREG_OP2_SHIFT)) 60 #define SYSREG_MASK \ 61 SYSREG(SYSREG_OP0_MASK, \ 62 SYSREG_OP1_MASK, \ 63 SYSREG_CRN_MASK, \ 64 SYSREG_CRM_MASK, \ 65 SYSREG_OP2_MASK) 66 #define SYSREG_OSLAR_EL1 SYSREG(2, 0, 1, 0, 4) 67 #define SYSREG_OSLSR_EL1 SYSREG(2, 0, 1, 1, 4) 68 #define SYSREG_OSDLR_EL1 SYSREG(2, 0, 1, 3, 4) 69 #define SYSREG_CNTPCT_EL0 SYSREG(3, 3, 14, 0, 1) 70 #define SYSREG_PMCR_EL0 SYSREG(3, 3, 9, 12, 0) 71 #define SYSREG_PMUSERENR_EL0 SYSREG(3, 3, 9, 14, 0) 72 #define SYSREG_PMCNTENSET_EL0 SYSREG(3, 3, 9, 12, 1) 73 #define SYSREG_PMCNTENCLR_EL0 SYSREG(3, 3, 9, 12, 2) 74 #define SYSREG_PMINTENCLR_EL1 SYSREG(3, 0, 9, 14, 2) 75 #define SYSREG_PMOVSCLR_EL0 SYSREG(3, 3, 9, 12, 3) 76 #define SYSREG_PMSWINC_EL0 SYSREG(3, 3, 9, 12, 4) 77 #define SYSREG_PMSELR_EL0 SYSREG(3, 3, 9, 12, 5) 78 #define SYSREG_PMCEID0_EL0 SYSREG(3, 3, 9, 12, 6) 79 #define SYSREG_PMCEID1_EL0 SYSREG(3, 3, 9, 12, 7) 80 #define SYSREG_PMCCNTR_EL0 SYSREG(3, 3, 9, 13, 0) 81 #define SYSREG_PMCCFILTR_EL0 SYSREG(3, 3, 14, 15, 7) 82 83 #define SYSREG_ICC_AP0R0_EL1 SYSREG(3, 0, 12, 8, 4) 84 #define SYSREG_ICC_AP0R1_EL1 SYSREG(3, 0, 12, 8, 5) 85 #define SYSREG_ICC_AP0R2_EL1 SYSREG(3, 0, 12, 8, 6) 86 #define SYSREG_ICC_AP0R3_EL1 SYSREG(3, 0, 12, 8, 7) 87 #define SYSREG_ICC_AP1R0_EL1 SYSREG(3, 0, 12, 9, 0) 88 #define SYSREG_ICC_AP1R1_EL1 SYSREG(3, 0, 12, 9, 1) 89 #define SYSREG_ICC_AP1R2_EL1 SYSREG(3, 0, 12, 9, 2) 90 #define SYSREG_ICC_AP1R3_EL1 SYSREG(3, 0, 12, 9, 3) 91 #define SYSREG_ICC_ASGI1R_EL1 SYSREG(3, 0, 12, 11, 6) 92 #define SYSREG_ICC_BPR0_EL1 SYSREG(3, 0, 12, 8, 3) 93 #define SYSREG_ICC_BPR1_EL1 SYSREG(3, 0, 12, 12, 3) 94 #define SYSREG_ICC_CTLR_EL1 SYSREG(3, 0, 12, 12, 4) 95 #define SYSREG_ICC_DIR_EL1 SYSREG(3, 0, 12, 11, 1) 96 #define SYSREG_ICC_EOIR0_EL1 SYSREG(3, 0, 12, 8, 1) 97 #define SYSREG_ICC_EOIR1_EL1 SYSREG(3, 0, 12, 12, 1) 98 #define SYSREG_ICC_HPPIR0_EL1 SYSREG(3, 0, 12, 8, 2) 99 #define SYSREG_ICC_HPPIR1_EL1 SYSREG(3, 0, 12, 12, 2) 100 #define SYSREG_ICC_IAR0_EL1 SYSREG(3, 0, 12, 8, 0) 101 #define SYSREG_ICC_IAR1_EL1 SYSREG(3, 0, 12, 12, 0) 102 #define SYSREG_ICC_IGRPEN0_EL1 SYSREG(3, 0, 12, 12, 6) 103 #define SYSREG_ICC_IGRPEN1_EL1 SYSREG(3, 0, 12, 12, 7) 104 #define SYSREG_ICC_PMR_EL1 SYSREG(3, 0, 4, 6, 0) 105 #define SYSREG_ICC_RPR_EL1 SYSREG(3, 0, 12, 11, 3) 106 #define SYSREG_ICC_SGI0R_EL1 SYSREG(3, 0, 12, 11, 7) 107 #define SYSREG_ICC_SGI1R_EL1 SYSREG(3, 0, 12, 11, 5) 108 #define SYSREG_ICC_SRE_EL1 SYSREG(3, 0, 12, 12, 5) 109 110 #define WFX_IS_WFE (1 << 0) 111 112 #define TMR_CTL_ENABLE (1 << 0) 113 #define TMR_CTL_IMASK (1 << 1) 114 #define TMR_CTL_ISTATUS (1 << 2) 115 116 static void hvf_wfi(CPUState *cpu); 117 118 typedef struct HVFVTimer { 119 /* Vtimer value during migration and paused state */ 120 uint64_t vtimer_val; 121 } HVFVTimer; 122 123 static HVFVTimer vtimer; 124 125 typedef struct ARMHostCPUFeatures { 126 ARMISARegisters isar; 127 uint64_t features; 128 uint64_t midr; 129 uint32_t reset_sctlr; 130 const char *dtb_compatible; 131 } ARMHostCPUFeatures; 132 133 static ARMHostCPUFeatures arm_host_cpu_features; 134 135 struct hvf_reg_match { 136 int reg; 137 uint64_t offset; 138 }; 139 140 static const struct hvf_reg_match hvf_reg_match[] = { 141 { HV_REG_X0, offsetof(CPUARMState, xregs[0]) }, 142 { HV_REG_X1, offsetof(CPUARMState, xregs[1]) }, 143 { HV_REG_X2, offsetof(CPUARMState, xregs[2]) }, 144 { HV_REG_X3, offsetof(CPUARMState, xregs[3]) }, 145 { HV_REG_X4, offsetof(CPUARMState, xregs[4]) }, 146 { HV_REG_X5, offsetof(CPUARMState, xregs[5]) }, 147 { HV_REG_X6, offsetof(CPUARMState, xregs[6]) }, 148 { HV_REG_X7, offsetof(CPUARMState, xregs[7]) }, 149 { HV_REG_X8, offsetof(CPUARMState, xregs[8]) }, 150 { HV_REG_X9, offsetof(CPUARMState, xregs[9]) }, 151 { HV_REG_X10, offsetof(CPUARMState, xregs[10]) }, 152 { HV_REG_X11, offsetof(CPUARMState, xregs[11]) }, 153 { HV_REG_X12, offsetof(CPUARMState, xregs[12]) }, 154 { HV_REG_X13, offsetof(CPUARMState, xregs[13]) }, 155 { HV_REG_X14, offsetof(CPUARMState, xregs[14]) }, 156 { HV_REG_X15, offsetof(CPUARMState, xregs[15]) }, 157 { HV_REG_X16, offsetof(CPUARMState, xregs[16]) }, 158 { HV_REG_X17, offsetof(CPUARMState, xregs[17]) }, 159 { HV_REG_X18, offsetof(CPUARMState, xregs[18]) }, 160 { HV_REG_X19, offsetof(CPUARMState, xregs[19]) }, 161 { HV_REG_X20, offsetof(CPUARMState, xregs[20]) }, 162 { HV_REG_X21, offsetof(CPUARMState, xregs[21]) }, 163 { HV_REG_X22, offsetof(CPUARMState, xregs[22]) }, 164 { HV_REG_X23, offsetof(CPUARMState, xregs[23]) }, 165 { HV_REG_X24, offsetof(CPUARMState, xregs[24]) }, 166 { HV_REG_X25, offsetof(CPUARMState, xregs[25]) }, 167 { HV_REG_X26, offsetof(CPUARMState, xregs[26]) }, 168 { HV_REG_X27, offsetof(CPUARMState, xregs[27]) }, 169 { HV_REG_X28, offsetof(CPUARMState, xregs[28]) }, 170 { HV_REG_X29, offsetof(CPUARMState, xregs[29]) }, 171 { HV_REG_X30, offsetof(CPUARMState, xregs[30]) }, 172 { HV_REG_PC, offsetof(CPUARMState, pc) }, 173 }; 174 175 static const struct hvf_reg_match hvf_fpreg_match[] = { 176 { HV_SIMD_FP_REG_Q0, offsetof(CPUARMState, vfp.zregs[0]) }, 177 { HV_SIMD_FP_REG_Q1, offsetof(CPUARMState, vfp.zregs[1]) }, 178 { HV_SIMD_FP_REG_Q2, offsetof(CPUARMState, vfp.zregs[2]) }, 179 { HV_SIMD_FP_REG_Q3, offsetof(CPUARMState, vfp.zregs[3]) }, 180 { HV_SIMD_FP_REG_Q4, offsetof(CPUARMState, vfp.zregs[4]) }, 181 { HV_SIMD_FP_REG_Q5, offsetof(CPUARMState, vfp.zregs[5]) }, 182 { HV_SIMD_FP_REG_Q6, offsetof(CPUARMState, vfp.zregs[6]) }, 183 { HV_SIMD_FP_REG_Q7, offsetof(CPUARMState, vfp.zregs[7]) }, 184 { HV_SIMD_FP_REG_Q8, offsetof(CPUARMState, vfp.zregs[8]) }, 185 { HV_SIMD_FP_REG_Q9, offsetof(CPUARMState, vfp.zregs[9]) }, 186 { HV_SIMD_FP_REG_Q10, offsetof(CPUARMState, vfp.zregs[10]) }, 187 { HV_SIMD_FP_REG_Q11, offsetof(CPUARMState, vfp.zregs[11]) }, 188 { HV_SIMD_FP_REG_Q12, offsetof(CPUARMState, vfp.zregs[12]) }, 189 { HV_SIMD_FP_REG_Q13, offsetof(CPUARMState, vfp.zregs[13]) }, 190 { HV_SIMD_FP_REG_Q14, offsetof(CPUARMState, vfp.zregs[14]) }, 191 { HV_SIMD_FP_REG_Q15, offsetof(CPUARMState, vfp.zregs[15]) }, 192 { HV_SIMD_FP_REG_Q16, offsetof(CPUARMState, vfp.zregs[16]) }, 193 { HV_SIMD_FP_REG_Q17, offsetof(CPUARMState, vfp.zregs[17]) }, 194 { HV_SIMD_FP_REG_Q18, offsetof(CPUARMState, vfp.zregs[18]) }, 195 { HV_SIMD_FP_REG_Q19, offsetof(CPUARMState, vfp.zregs[19]) }, 196 { HV_SIMD_FP_REG_Q20, offsetof(CPUARMState, vfp.zregs[20]) }, 197 { HV_SIMD_FP_REG_Q21, offsetof(CPUARMState, vfp.zregs[21]) }, 198 { HV_SIMD_FP_REG_Q22, offsetof(CPUARMState, vfp.zregs[22]) }, 199 { HV_SIMD_FP_REG_Q23, offsetof(CPUARMState, vfp.zregs[23]) }, 200 { HV_SIMD_FP_REG_Q24, offsetof(CPUARMState, vfp.zregs[24]) }, 201 { HV_SIMD_FP_REG_Q25, offsetof(CPUARMState, vfp.zregs[25]) }, 202 { HV_SIMD_FP_REG_Q26, offsetof(CPUARMState, vfp.zregs[26]) }, 203 { HV_SIMD_FP_REG_Q27, offsetof(CPUARMState, vfp.zregs[27]) }, 204 { HV_SIMD_FP_REG_Q28, offsetof(CPUARMState, vfp.zregs[28]) }, 205 { HV_SIMD_FP_REG_Q29, offsetof(CPUARMState, vfp.zregs[29]) }, 206 { HV_SIMD_FP_REG_Q30, offsetof(CPUARMState, vfp.zregs[30]) }, 207 { HV_SIMD_FP_REG_Q31, offsetof(CPUARMState, vfp.zregs[31]) }, 208 }; 209 210 struct hvf_sreg_match { 211 int reg; 212 uint32_t key; 213 uint32_t cp_idx; 214 }; 215 216 static struct hvf_sreg_match hvf_sreg_match[] = { 217 { HV_SYS_REG_DBGBVR0_EL1, HVF_SYSREG(0, 0, 14, 0, 4) }, 218 { HV_SYS_REG_DBGBCR0_EL1, HVF_SYSREG(0, 0, 14, 0, 5) }, 219 { HV_SYS_REG_DBGWVR0_EL1, HVF_SYSREG(0, 0, 14, 0, 6) }, 220 { HV_SYS_REG_DBGWCR0_EL1, HVF_SYSREG(0, 0, 14, 0, 7) }, 221 222 { HV_SYS_REG_DBGBVR1_EL1, HVF_SYSREG(0, 1, 14, 0, 4) }, 223 { HV_SYS_REG_DBGBCR1_EL1, HVF_SYSREG(0, 1, 14, 0, 5) }, 224 { HV_SYS_REG_DBGWVR1_EL1, HVF_SYSREG(0, 1, 14, 0, 6) }, 225 { HV_SYS_REG_DBGWCR1_EL1, HVF_SYSREG(0, 1, 14, 0, 7) }, 226 227 { HV_SYS_REG_DBGBVR2_EL1, HVF_SYSREG(0, 2, 14, 0, 4) }, 228 { HV_SYS_REG_DBGBCR2_EL1, HVF_SYSREG(0, 2, 14, 0, 5) }, 229 { HV_SYS_REG_DBGWVR2_EL1, HVF_SYSREG(0, 2, 14, 0, 6) }, 230 { HV_SYS_REG_DBGWCR2_EL1, HVF_SYSREG(0, 2, 14, 0, 7) }, 231 232 { HV_SYS_REG_DBGBVR3_EL1, HVF_SYSREG(0, 3, 14, 0, 4) }, 233 { HV_SYS_REG_DBGBCR3_EL1, HVF_SYSREG(0, 3, 14, 0, 5) }, 234 { HV_SYS_REG_DBGWVR3_EL1, HVF_SYSREG(0, 3, 14, 0, 6) }, 235 { HV_SYS_REG_DBGWCR3_EL1, HVF_SYSREG(0, 3, 14, 0, 7) }, 236 237 { HV_SYS_REG_DBGBVR4_EL1, HVF_SYSREG(0, 4, 14, 0, 4) }, 238 { HV_SYS_REG_DBGBCR4_EL1, HVF_SYSREG(0, 4, 14, 0, 5) }, 239 { HV_SYS_REG_DBGWVR4_EL1, HVF_SYSREG(0, 4, 14, 0, 6) }, 240 { HV_SYS_REG_DBGWCR4_EL1, HVF_SYSREG(0, 4, 14, 0, 7) }, 241 242 { HV_SYS_REG_DBGBVR5_EL1, HVF_SYSREG(0, 5, 14, 0, 4) }, 243 { HV_SYS_REG_DBGBCR5_EL1, HVF_SYSREG(0, 5, 14, 0, 5) }, 244 { HV_SYS_REG_DBGWVR5_EL1, HVF_SYSREG(0, 5, 14, 0, 6) }, 245 { HV_SYS_REG_DBGWCR5_EL1, HVF_SYSREG(0, 5, 14, 0, 7) }, 246 247 { HV_SYS_REG_DBGBVR6_EL1, HVF_SYSREG(0, 6, 14, 0, 4) }, 248 { HV_SYS_REG_DBGBCR6_EL1, HVF_SYSREG(0, 6, 14, 0, 5) }, 249 { HV_SYS_REG_DBGWVR6_EL1, HVF_SYSREG(0, 6, 14, 0, 6) }, 250 { HV_SYS_REG_DBGWCR6_EL1, HVF_SYSREG(0, 6, 14, 0, 7) }, 251 252 { HV_SYS_REG_DBGBVR7_EL1, HVF_SYSREG(0, 7, 14, 0, 4) }, 253 { HV_SYS_REG_DBGBCR7_EL1, HVF_SYSREG(0, 7, 14, 0, 5) }, 254 { HV_SYS_REG_DBGWVR7_EL1, HVF_SYSREG(0, 7, 14, 0, 6) }, 255 { HV_SYS_REG_DBGWCR7_EL1, HVF_SYSREG(0, 7, 14, 0, 7) }, 256 257 { HV_SYS_REG_DBGBVR8_EL1, HVF_SYSREG(0, 8, 14, 0, 4) }, 258 { HV_SYS_REG_DBGBCR8_EL1, HVF_SYSREG(0, 8, 14, 0, 5) }, 259 { HV_SYS_REG_DBGWVR8_EL1, HVF_SYSREG(0, 8, 14, 0, 6) }, 260 { HV_SYS_REG_DBGWCR8_EL1, HVF_SYSREG(0, 8, 14, 0, 7) }, 261 262 { HV_SYS_REG_DBGBVR9_EL1, HVF_SYSREG(0, 9, 14, 0, 4) }, 263 { HV_SYS_REG_DBGBCR9_EL1, HVF_SYSREG(0, 9, 14, 0, 5) }, 264 { HV_SYS_REG_DBGWVR9_EL1, HVF_SYSREG(0, 9, 14, 0, 6) }, 265 { HV_SYS_REG_DBGWCR9_EL1, HVF_SYSREG(0, 9, 14, 0, 7) }, 266 267 { HV_SYS_REG_DBGBVR10_EL1, HVF_SYSREG(0, 10, 14, 0, 4) }, 268 { HV_SYS_REG_DBGBCR10_EL1, HVF_SYSREG(0, 10, 14, 0, 5) }, 269 { HV_SYS_REG_DBGWVR10_EL1, HVF_SYSREG(0, 10, 14, 0, 6) }, 270 { HV_SYS_REG_DBGWCR10_EL1, HVF_SYSREG(0, 10, 14, 0, 7) }, 271 272 { HV_SYS_REG_DBGBVR11_EL1, HVF_SYSREG(0, 11, 14, 0, 4) }, 273 { HV_SYS_REG_DBGBCR11_EL1, HVF_SYSREG(0, 11, 14, 0, 5) }, 274 { HV_SYS_REG_DBGWVR11_EL1, HVF_SYSREG(0, 11, 14, 0, 6) }, 275 { HV_SYS_REG_DBGWCR11_EL1, HVF_SYSREG(0, 11, 14, 0, 7) }, 276 277 { HV_SYS_REG_DBGBVR12_EL1, HVF_SYSREG(0, 12, 14, 0, 4) }, 278 { HV_SYS_REG_DBGBCR12_EL1, HVF_SYSREG(0, 12, 14, 0, 5) }, 279 { HV_SYS_REG_DBGWVR12_EL1, HVF_SYSREG(0, 12, 14, 0, 6) }, 280 { HV_SYS_REG_DBGWCR12_EL1, HVF_SYSREG(0, 12, 14, 0, 7) }, 281 282 { HV_SYS_REG_DBGBVR13_EL1, HVF_SYSREG(0, 13, 14, 0, 4) }, 283 { HV_SYS_REG_DBGBCR13_EL1, HVF_SYSREG(0, 13, 14, 0, 5) }, 284 { HV_SYS_REG_DBGWVR13_EL1, HVF_SYSREG(0, 13, 14, 0, 6) }, 285 { HV_SYS_REG_DBGWCR13_EL1, HVF_SYSREG(0, 13, 14, 0, 7) }, 286 287 { HV_SYS_REG_DBGBVR14_EL1, HVF_SYSREG(0, 14, 14, 0, 4) }, 288 { HV_SYS_REG_DBGBCR14_EL1, HVF_SYSREG(0, 14, 14, 0, 5) }, 289 { HV_SYS_REG_DBGWVR14_EL1, HVF_SYSREG(0, 14, 14, 0, 6) }, 290 { HV_SYS_REG_DBGWCR14_EL1, HVF_SYSREG(0, 14, 14, 0, 7) }, 291 292 { HV_SYS_REG_DBGBVR15_EL1, HVF_SYSREG(0, 15, 14, 0, 4) }, 293 { HV_SYS_REG_DBGBCR15_EL1, HVF_SYSREG(0, 15, 14, 0, 5) }, 294 { HV_SYS_REG_DBGWVR15_EL1, HVF_SYSREG(0, 15, 14, 0, 6) }, 295 { HV_SYS_REG_DBGWCR15_EL1, HVF_SYSREG(0, 15, 14, 0, 7) }, 296 297 #ifdef SYNC_NO_RAW_REGS 298 /* 299 * The registers below are manually synced on init because they are 300 * marked as NO_RAW. We still list them to make number space sync easier. 301 */ 302 { HV_SYS_REG_MDCCINT_EL1, HVF_SYSREG(0, 2, 2, 0, 0) }, 303 { HV_SYS_REG_MIDR_EL1, HVF_SYSREG(0, 0, 3, 0, 0) }, 304 { HV_SYS_REG_MPIDR_EL1, HVF_SYSREG(0, 0, 3, 0, 5) }, 305 { HV_SYS_REG_ID_AA64PFR0_EL1, HVF_SYSREG(0, 4, 3, 0, 0) }, 306 #endif 307 { HV_SYS_REG_ID_AA64PFR1_EL1, HVF_SYSREG(0, 4, 3, 0, 2) }, 308 { HV_SYS_REG_ID_AA64DFR0_EL1, HVF_SYSREG(0, 5, 3, 0, 0) }, 309 { HV_SYS_REG_ID_AA64DFR1_EL1, HVF_SYSREG(0, 5, 3, 0, 1) }, 310 { HV_SYS_REG_ID_AA64ISAR0_EL1, HVF_SYSREG(0, 6, 3, 0, 0) }, 311 { HV_SYS_REG_ID_AA64ISAR1_EL1, HVF_SYSREG(0, 6, 3, 0, 1) }, 312 #ifdef SYNC_NO_MMFR0 313 /* We keep the hardware MMFR0 around. HW limits are there anyway */ 314 { HV_SYS_REG_ID_AA64MMFR0_EL1, HVF_SYSREG(0, 7, 3, 0, 0) }, 315 #endif 316 { HV_SYS_REG_ID_AA64MMFR1_EL1, HVF_SYSREG(0, 7, 3, 0, 1) }, 317 { HV_SYS_REG_ID_AA64MMFR2_EL1, HVF_SYSREG(0, 7, 3, 0, 2) }, 318 319 { HV_SYS_REG_MDSCR_EL1, HVF_SYSREG(0, 2, 2, 0, 2) }, 320 { HV_SYS_REG_SCTLR_EL1, HVF_SYSREG(1, 0, 3, 0, 0) }, 321 { HV_SYS_REG_CPACR_EL1, HVF_SYSREG(1, 0, 3, 0, 2) }, 322 { HV_SYS_REG_TTBR0_EL1, HVF_SYSREG(2, 0, 3, 0, 0) }, 323 { HV_SYS_REG_TTBR1_EL1, HVF_SYSREG(2, 0, 3, 0, 1) }, 324 { HV_SYS_REG_TCR_EL1, HVF_SYSREG(2, 0, 3, 0, 2) }, 325 326 { HV_SYS_REG_APIAKEYLO_EL1, HVF_SYSREG(2, 1, 3, 0, 0) }, 327 { HV_SYS_REG_APIAKEYHI_EL1, HVF_SYSREG(2, 1, 3, 0, 1) }, 328 { HV_SYS_REG_APIBKEYLO_EL1, HVF_SYSREG(2, 1, 3, 0, 2) }, 329 { HV_SYS_REG_APIBKEYHI_EL1, HVF_SYSREG(2, 1, 3, 0, 3) }, 330 { HV_SYS_REG_APDAKEYLO_EL1, HVF_SYSREG(2, 2, 3, 0, 0) }, 331 { HV_SYS_REG_APDAKEYHI_EL1, HVF_SYSREG(2, 2, 3, 0, 1) }, 332 { HV_SYS_REG_APDBKEYLO_EL1, HVF_SYSREG(2, 2, 3, 0, 2) }, 333 { HV_SYS_REG_APDBKEYHI_EL1, HVF_SYSREG(2, 2, 3, 0, 3) }, 334 { HV_SYS_REG_APGAKEYLO_EL1, HVF_SYSREG(2, 3, 3, 0, 0) }, 335 { HV_SYS_REG_APGAKEYHI_EL1, HVF_SYSREG(2, 3, 3, 0, 1) }, 336 337 { HV_SYS_REG_SPSR_EL1, HVF_SYSREG(4, 0, 3, 0, 0) }, 338 { HV_SYS_REG_ELR_EL1, HVF_SYSREG(4, 0, 3, 0, 1) }, 339 { HV_SYS_REG_SP_EL0, HVF_SYSREG(4, 1, 3, 0, 0) }, 340 { HV_SYS_REG_AFSR0_EL1, HVF_SYSREG(5, 1, 3, 0, 0) }, 341 { HV_SYS_REG_AFSR1_EL1, HVF_SYSREG(5, 1, 3, 0, 1) }, 342 { HV_SYS_REG_ESR_EL1, HVF_SYSREG(5, 2, 3, 0, 0) }, 343 { HV_SYS_REG_FAR_EL1, HVF_SYSREG(6, 0, 3, 0, 0) }, 344 { HV_SYS_REG_PAR_EL1, HVF_SYSREG(7, 4, 3, 0, 0) }, 345 { HV_SYS_REG_MAIR_EL1, HVF_SYSREG(10, 2, 3, 0, 0) }, 346 { HV_SYS_REG_AMAIR_EL1, HVF_SYSREG(10, 3, 3, 0, 0) }, 347 { HV_SYS_REG_VBAR_EL1, HVF_SYSREG(12, 0, 3, 0, 0) }, 348 { HV_SYS_REG_CONTEXTIDR_EL1, HVF_SYSREG(13, 0, 3, 0, 1) }, 349 { HV_SYS_REG_TPIDR_EL1, HVF_SYSREG(13, 0, 3, 0, 4) }, 350 { HV_SYS_REG_CNTKCTL_EL1, HVF_SYSREG(14, 1, 3, 0, 0) }, 351 { HV_SYS_REG_CSSELR_EL1, HVF_SYSREG(0, 0, 3, 2, 0) }, 352 { HV_SYS_REG_TPIDR_EL0, HVF_SYSREG(13, 0, 3, 3, 2) }, 353 { HV_SYS_REG_TPIDRRO_EL0, HVF_SYSREG(13, 0, 3, 3, 3) }, 354 { HV_SYS_REG_CNTV_CTL_EL0, HVF_SYSREG(14, 3, 3, 3, 1) }, 355 { HV_SYS_REG_CNTV_CVAL_EL0, HVF_SYSREG(14, 3, 3, 3, 2) }, 356 { HV_SYS_REG_SP_EL1, HVF_SYSREG(4, 1, 3, 4, 0) }, 357 }; 358 359 int hvf_get_registers(CPUState *cpu) 360 { 361 ARMCPU *arm_cpu = ARM_CPU(cpu); 362 CPUARMState *env = &arm_cpu->env; 363 hv_return_t ret; 364 uint64_t val; 365 hv_simd_fp_uchar16_t fpval; 366 int i; 367 368 for (i = 0; i < ARRAY_SIZE(hvf_reg_match); i++) { 369 ret = hv_vcpu_get_reg(cpu->hvf->fd, hvf_reg_match[i].reg, &val); 370 *(uint64_t *)((void *)env + hvf_reg_match[i].offset) = val; 371 assert_hvf_ok(ret); 372 } 373 374 for (i = 0; i < ARRAY_SIZE(hvf_fpreg_match); i++) { 375 ret = hv_vcpu_get_simd_fp_reg(cpu->hvf->fd, hvf_fpreg_match[i].reg, 376 &fpval); 377 memcpy((void *)env + hvf_fpreg_match[i].offset, &fpval, sizeof(fpval)); 378 assert_hvf_ok(ret); 379 } 380 381 val = 0; 382 ret = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_FPCR, &val); 383 assert_hvf_ok(ret); 384 vfp_set_fpcr(env, val); 385 386 val = 0; 387 ret = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_FPSR, &val); 388 assert_hvf_ok(ret); 389 vfp_set_fpsr(env, val); 390 391 ret = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_CPSR, &val); 392 assert_hvf_ok(ret); 393 pstate_write(env, val); 394 395 for (i = 0; i < ARRAY_SIZE(hvf_sreg_match); i++) { 396 if (hvf_sreg_match[i].cp_idx == -1) { 397 continue; 398 } 399 400 ret = hv_vcpu_get_sys_reg(cpu->hvf->fd, hvf_sreg_match[i].reg, &val); 401 assert_hvf_ok(ret); 402 403 arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx] = val; 404 } 405 assert(write_list_to_cpustate(arm_cpu)); 406 407 aarch64_restore_sp(env, arm_current_el(env)); 408 409 return 0; 410 } 411 412 int hvf_put_registers(CPUState *cpu) 413 { 414 ARMCPU *arm_cpu = ARM_CPU(cpu); 415 CPUARMState *env = &arm_cpu->env; 416 hv_return_t ret; 417 uint64_t val; 418 hv_simd_fp_uchar16_t fpval; 419 int i; 420 421 for (i = 0; i < ARRAY_SIZE(hvf_reg_match); i++) { 422 val = *(uint64_t *)((void *)env + hvf_reg_match[i].offset); 423 ret = hv_vcpu_set_reg(cpu->hvf->fd, hvf_reg_match[i].reg, val); 424 assert_hvf_ok(ret); 425 } 426 427 for (i = 0; i < ARRAY_SIZE(hvf_fpreg_match); i++) { 428 memcpy(&fpval, (void *)env + hvf_fpreg_match[i].offset, sizeof(fpval)); 429 ret = hv_vcpu_set_simd_fp_reg(cpu->hvf->fd, hvf_fpreg_match[i].reg, 430 fpval); 431 assert_hvf_ok(ret); 432 } 433 434 ret = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_FPCR, vfp_get_fpcr(env)); 435 assert_hvf_ok(ret); 436 437 ret = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_FPSR, vfp_get_fpsr(env)); 438 assert_hvf_ok(ret); 439 440 ret = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_CPSR, pstate_read(env)); 441 assert_hvf_ok(ret); 442 443 aarch64_save_sp(env, arm_current_el(env)); 444 445 assert(write_cpustate_to_list(arm_cpu, false)); 446 for (i = 0; i < ARRAY_SIZE(hvf_sreg_match); i++) { 447 if (hvf_sreg_match[i].cp_idx == -1) { 448 continue; 449 } 450 451 val = arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx]; 452 ret = hv_vcpu_set_sys_reg(cpu->hvf->fd, hvf_sreg_match[i].reg, val); 453 assert_hvf_ok(ret); 454 } 455 456 ret = hv_vcpu_set_vtimer_offset(cpu->hvf->fd, hvf_state->vtimer_offset); 457 assert_hvf_ok(ret); 458 459 return 0; 460 } 461 462 static void flush_cpu_state(CPUState *cpu) 463 { 464 if (cpu->vcpu_dirty) { 465 hvf_put_registers(cpu); 466 cpu->vcpu_dirty = false; 467 } 468 } 469 470 static void hvf_set_reg(CPUState *cpu, int rt, uint64_t val) 471 { 472 hv_return_t r; 473 474 flush_cpu_state(cpu); 475 476 if (rt < 31) { 477 r = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_X0 + rt, val); 478 assert_hvf_ok(r); 479 } 480 } 481 482 static uint64_t hvf_get_reg(CPUState *cpu, int rt) 483 { 484 uint64_t val = 0; 485 hv_return_t r; 486 487 flush_cpu_state(cpu); 488 489 if (rt < 31) { 490 r = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_X0 + rt, &val); 491 assert_hvf_ok(r); 492 } 493 494 return val; 495 } 496 497 static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) 498 { 499 ARMISARegisters host_isar = {}; 500 const struct isar_regs { 501 int reg; 502 uint64_t *val; 503 } regs[] = { 504 { HV_SYS_REG_ID_AA64PFR0_EL1, &host_isar.id_aa64pfr0 }, 505 { HV_SYS_REG_ID_AA64PFR1_EL1, &host_isar.id_aa64pfr1 }, 506 { HV_SYS_REG_ID_AA64DFR0_EL1, &host_isar.id_aa64dfr0 }, 507 { HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.id_aa64dfr1 }, 508 { HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.id_aa64isar0 }, 509 { HV_SYS_REG_ID_AA64ISAR1_EL1, &host_isar.id_aa64isar1 }, 510 { HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.id_aa64mmfr0 }, 511 { HV_SYS_REG_ID_AA64MMFR1_EL1, &host_isar.id_aa64mmfr1 }, 512 { HV_SYS_REG_ID_AA64MMFR2_EL1, &host_isar.id_aa64mmfr2 }, 513 }; 514 hv_vcpu_t fd; 515 hv_return_t r = HV_SUCCESS; 516 hv_vcpu_exit_t *exit; 517 int i; 518 519 ahcf->dtb_compatible = "arm,arm-v8"; 520 ahcf->features = (1ULL << ARM_FEATURE_V8) | 521 (1ULL << ARM_FEATURE_NEON) | 522 (1ULL << ARM_FEATURE_AARCH64) | 523 (1ULL << ARM_FEATURE_PMU) | 524 (1ULL << ARM_FEATURE_GENERIC_TIMER); 525 526 /* We set up a small vcpu to extract host registers */ 527 528 if (hv_vcpu_create(&fd, &exit, NULL) != HV_SUCCESS) { 529 return false; 530 } 531 532 for (i = 0; i < ARRAY_SIZE(regs); i++) { 533 r |= hv_vcpu_get_sys_reg(fd, regs[i].reg, regs[i].val); 534 } 535 r |= hv_vcpu_get_sys_reg(fd, HV_SYS_REG_MIDR_EL1, &ahcf->midr); 536 r |= hv_vcpu_destroy(fd); 537 538 ahcf->isar = host_isar; 539 540 /* 541 * A scratch vCPU returns SCTLR 0, so let's fill our default with the M1 542 * boot SCTLR from https://github.com/AsahiLinux/m1n1/issues/97 543 */ 544 ahcf->reset_sctlr = 0x30100180; 545 /* 546 * SPAN is disabled by default when SCTLR.SPAN=1. To improve compatibility, 547 * let's disable it on boot and then allow guest software to turn it on by 548 * setting it to 0. 549 */ 550 ahcf->reset_sctlr |= 0x00800000; 551 552 /* Make sure we don't advertise AArch32 support for EL0/EL1 */ 553 if ((host_isar.id_aa64pfr0 & 0xff) != 0x11) { 554 return false; 555 } 556 557 return r == HV_SUCCESS; 558 } 559 560 void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu) 561 { 562 if (!arm_host_cpu_features.dtb_compatible) { 563 if (!hvf_enabled() || 564 !hvf_arm_get_host_cpu_features(&arm_host_cpu_features)) { 565 /* 566 * We can't report this error yet, so flag that we need to 567 * in arm_cpu_realizefn(). 568 */ 569 cpu->host_cpu_probe_failed = true; 570 return; 571 } 572 } 573 574 cpu->dtb_compatible = arm_host_cpu_features.dtb_compatible; 575 cpu->isar = arm_host_cpu_features.isar; 576 cpu->env.features = arm_host_cpu_features.features; 577 cpu->midr = arm_host_cpu_features.midr; 578 cpu->reset_sctlr = arm_host_cpu_features.reset_sctlr; 579 } 580 581 void hvf_arch_vcpu_destroy(CPUState *cpu) 582 { 583 } 584 585 int hvf_arch_init_vcpu(CPUState *cpu) 586 { 587 ARMCPU *arm_cpu = ARM_CPU(cpu); 588 CPUARMState *env = &arm_cpu->env; 589 uint32_t sregs_match_len = ARRAY_SIZE(hvf_sreg_match); 590 uint32_t sregs_cnt = 0; 591 uint64_t pfr; 592 hv_return_t ret; 593 int i; 594 595 env->aarch64 = true; 596 asm volatile("mrs %0, cntfrq_el0" : "=r"(arm_cpu->gt_cntfrq_hz)); 597 598 /* Allocate enough space for our sysreg sync */ 599 arm_cpu->cpreg_indexes = g_renew(uint64_t, arm_cpu->cpreg_indexes, 600 sregs_match_len); 601 arm_cpu->cpreg_values = g_renew(uint64_t, arm_cpu->cpreg_values, 602 sregs_match_len); 603 arm_cpu->cpreg_vmstate_indexes = g_renew(uint64_t, 604 arm_cpu->cpreg_vmstate_indexes, 605 sregs_match_len); 606 arm_cpu->cpreg_vmstate_values = g_renew(uint64_t, 607 arm_cpu->cpreg_vmstate_values, 608 sregs_match_len); 609 610 memset(arm_cpu->cpreg_values, 0, sregs_match_len * sizeof(uint64_t)); 611 612 /* Populate cp list for all known sysregs */ 613 for (i = 0; i < sregs_match_len; i++) { 614 const ARMCPRegInfo *ri; 615 uint32_t key = hvf_sreg_match[i].key; 616 617 ri = get_arm_cp_reginfo(arm_cpu->cp_regs, key); 618 if (ri) { 619 assert(!(ri->type & ARM_CP_NO_RAW)); 620 hvf_sreg_match[i].cp_idx = sregs_cnt; 621 arm_cpu->cpreg_indexes[sregs_cnt++] = cpreg_to_kvm_id(key); 622 } else { 623 hvf_sreg_match[i].cp_idx = -1; 624 } 625 } 626 arm_cpu->cpreg_array_len = sregs_cnt; 627 arm_cpu->cpreg_vmstate_array_len = sregs_cnt; 628 629 assert(write_cpustate_to_list(arm_cpu, false)); 630 631 /* Set CP_NO_RAW system registers on init */ 632 ret = hv_vcpu_set_sys_reg(cpu->hvf->fd, HV_SYS_REG_MIDR_EL1, 633 arm_cpu->midr); 634 assert_hvf_ok(ret); 635 636 ret = hv_vcpu_set_sys_reg(cpu->hvf->fd, HV_SYS_REG_MPIDR_EL1, 637 arm_cpu->mp_affinity); 638 assert_hvf_ok(ret); 639 640 ret = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_ID_AA64PFR0_EL1, &pfr); 641 assert_hvf_ok(ret); 642 pfr |= env->gicv3state ? (1 << 24) : 0; 643 ret = hv_vcpu_set_sys_reg(cpu->hvf->fd, HV_SYS_REG_ID_AA64PFR0_EL1, pfr); 644 assert_hvf_ok(ret); 645 646 /* We're limited to underlying hardware caps, override internal versions */ 647 ret = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_ID_AA64MMFR0_EL1, 648 &arm_cpu->isar.id_aa64mmfr0); 649 assert_hvf_ok(ret); 650 651 return 0; 652 } 653 654 void hvf_kick_vcpu_thread(CPUState *cpu) 655 { 656 cpus_kick_thread(cpu); 657 hv_vcpus_exit(&cpu->hvf->fd, 1); 658 } 659 660 static void hvf_raise_exception(CPUState *cpu, uint32_t excp, 661 uint32_t syndrome) 662 { 663 ARMCPU *arm_cpu = ARM_CPU(cpu); 664 CPUARMState *env = &arm_cpu->env; 665 666 cpu->exception_index = excp; 667 env->exception.target_el = 1; 668 env->exception.syndrome = syndrome; 669 670 arm_cpu_do_interrupt(cpu); 671 } 672 673 static void hvf_psci_cpu_off(ARMCPU *arm_cpu) 674 { 675 int32_t ret = arm_set_cpu_off(arm_cpu->mp_affinity); 676 assert(ret == QEMU_ARM_POWERCTL_RET_SUCCESS); 677 } 678 679 /* 680 * Handle a PSCI call. 681 * 682 * Returns 0 on success 683 * -1 when the PSCI call is unknown, 684 */ 685 static bool hvf_handle_psci_call(CPUState *cpu) 686 { 687 ARMCPU *arm_cpu = ARM_CPU(cpu); 688 CPUARMState *env = &arm_cpu->env; 689 uint64_t param[4] = { 690 env->xregs[0], 691 env->xregs[1], 692 env->xregs[2], 693 env->xregs[3] 694 }; 695 uint64_t context_id, mpidr; 696 bool target_aarch64 = true; 697 CPUState *target_cpu_state; 698 ARMCPU *target_cpu; 699 target_ulong entry; 700 int target_el = 1; 701 int32_t ret = 0; 702 703 trace_hvf_psci_call(param[0], param[1], param[2], param[3], 704 arm_cpu->mp_affinity); 705 706 switch (param[0]) { 707 case QEMU_PSCI_0_2_FN_PSCI_VERSION: 708 ret = QEMU_PSCI_VERSION_1_1; 709 break; 710 case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE: 711 ret = QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED; /* No trusted OS */ 712 break; 713 case QEMU_PSCI_0_2_FN_AFFINITY_INFO: 714 case QEMU_PSCI_0_2_FN64_AFFINITY_INFO: 715 mpidr = param[1]; 716 717 switch (param[2]) { 718 case 0: 719 target_cpu_state = arm_get_cpu_by_id(mpidr); 720 if (!target_cpu_state) { 721 ret = QEMU_PSCI_RET_INVALID_PARAMS; 722 break; 723 } 724 target_cpu = ARM_CPU(target_cpu_state); 725 726 ret = target_cpu->power_state; 727 break; 728 default: 729 /* Everything above affinity level 0 is always on. */ 730 ret = 0; 731 } 732 break; 733 case QEMU_PSCI_0_2_FN_SYSTEM_RESET: 734 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 735 /* 736 * QEMU reset and shutdown are async requests, but PSCI 737 * mandates that we never return from the reset/shutdown 738 * call, so power the CPU off now so it doesn't execute 739 * anything further. 740 */ 741 hvf_psci_cpu_off(arm_cpu); 742 break; 743 case QEMU_PSCI_0_2_FN_SYSTEM_OFF: 744 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 745 hvf_psci_cpu_off(arm_cpu); 746 break; 747 case QEMU_PSCI_0_1_FN_CPU_ON: 748 case QEMU_PSCI_0_2_FN_CPU_ON: 749 case QEMU_PSCI_0_2_FN64_CPU_ON: 750 mpidr = param[1]; 751 entry = param[2]; 752 context_id = param[3]; 753 ret = arm_set_cpu_on(mpidr, entry, context_id, 754 target_el, target_aarch64); 755 break; 756 case QEMU_PSCI_0_1_FN_CPU_OFF: 757 case QEMU_PSCI_0_2_FN_CPU_OFF: 758 hvf_psci_cpu_off(arm_cpu); 759 break; 760 case QEMU_PSCI_0_1_FN_CPU_SUSPEND: 761 case QEMU_PSCI_0_2_FN_CPU_SUSPEND: 762 case QEMU_PSCI_0_2_FN64_CPU_SUSPEND: 763 /* Affinity levels are not supported in QEMU */ 764 if (param[1] & 0xfffe0000) { 765 ret = QEMU_PSCI_RET_INVALID_PARAMS; 766 break; 767 } 768 /* Powerdown is not supported, we always go into WFI */ 769 env->xregs[0] = 0; 770 hvf_wfi(cpu); 771 break; 772 case QEMU_PSCI_0_1_FN_MIGRATE: 773 case QEMU_PSCI_0_2_FN_MIGRATE: 774 ret = QEMU_PSCI_RET_NOT_SUPPORTED; 775 break; 776 case QEMU_PSCI_1_0_FN_PSCI_FEATURES: 777 switch (param[1]) { 778 case QEMU_PSCI_0_2_FN_PSCI_VERSION: 779 case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE: 780 case QEMU_PSCI_0_2_FN_AFFINITY_INFO: 781 case QEMU_PSCI_0_2_FN64_AFFINITY_INFO: 782 case QEMU_PSCI_0_2_FN_SYSTEM_RESET: 783 case QEMU_PSCI_0_2_FN_SYSTEM_OFF: 784 case QEMU_PSCI_0_1_FN_CPU_ON: 785 case QEMU_PSCI_0_2_FN_CPU_ON: 786 case QEMU_PSCI_0_2_FN64_CPU_ON: 787 case QEMU_PSCI_0_1_FN_CPU_OFF: 788 case QEMU_PSCI_0_2_FN_CPU_OFF: 789 case QEMU_PSCI_0_1_FN_CPU_SUSPEND: 790 case QEMU_PSCI_0_2_FN_CPU_SUSPEND: 791 case QEMU_PSCI_0_2_FN64_CPU_SUSPEND: 792 case QEMU_PSCI_1_0_FN_PSCI_FEATURES: 793 ret = 0; 794 break; 795 case QEMU_PSCI_0_1_FN_MIGRATE: 796 case QEMU_PSCI_0_2_FN_MIGRATE: 797 default: 798 ret = QEMU_PSCI_RET_NOT_SUPPORTED; 799 } 800 break; 801 default: 802 return false; 803 } 804 805 env->xregs[0] = ret; 806 return true; 807 } 808 809 static bool is_id_sysreg(uint32_t reg) 810 { 811 return SYSREG_OP0(reg) == 3 && 812 SYSREG_OP1(reg) == 0 && 813 SYSREG_CRN(reg) == 0 && 814 SYSREG_CRM(reg) >= 1 && 815 SYSREG_CRM(reg) < 8; 816 } 817 818 static uint32_t hvf_reg2cp_reg(uint32_t reg) 819 { 820 return ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, 821 (reg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK, 822 (reg >> SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK, 823 (reg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK, 824 (reg >> SYSREG_OP1_SHIFT) & SYSREG_OP1_MASK, 825 (reg >> SYSREG_OP2_SHIFT) & SYSREG_OP2_MASK); 826 } 827 828 static bool hvf_sysreg_read_cp(CPUState *cpu, uint32_t reg, uint64_t *val) 829 { 830 ARMCPU *arm_cpu = ARM_CPU(cpu); 831 CPUARMState *env = &arm_cpu->env; 832 const ARMCPRegInfo *ri; 833 834 ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg)); 835 if (ri) { 836 if (ri->accessfn) { 837 if (ri->accessfn(env, ri, true) != CP_ACCESS_OK) { 838 return false; 839 } 840 } 841 if (ri->type & ARM_CP_CONST) { 842 *val = ri->resetvalue; 843 } else if (ri->readfn) { 844 *val = ri->readfn(env, ri); 845 } else { 846 *val = CPREG_FIELD64(env, ri); 847 } 848 trace_hvf_vgic_read(ri->name, *val); 849 return true; 850 } 851 852 return false; 853 } 854 855 static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt) 856 { 857 ARMCPU *arm_cpu = ARM_CPU(cpu); 858 CPUARMState *env = &arm_cpu->env; 859 uint64_t val = 0; 860 861 switch (reg) { 862 case SYSREG_CNTPCT_EL0: 863 val = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / 864 gt_cntfrq_period_ns(arm_cpu); 865 break; 866 case SYSREG_PMCR_EL0: 867 val = env->cp15.c9_pmcr; 868 break; 869 case SYSREG_PMCCNTR_EL0: 870 pmu_op_start(env); 871 val = env->cp15.c15_ccnt; 872 pmu_op_finish(env); 873 break; 874 case SYSREG_PMCNTENCLR_EL0: 875 val = env->cp15.c9_pmcnten; 876 break; 877 case SYSREG_PMOVSCLR_EL0: 878 val = env->cp15.c9_pmovsr; 879 break; 880 case SYSREG_PMSELR_EL0: 881 val = env->cp15.c9_pmselr; 882 break; 883 case SYSREG_PMINTENCLR_EL1: 884 val = env->cp15.c9_pminten; 885 break; 886 case SYSREG_PMCCFILTR_EL0: 887 val = env->cp15.pmccfiltr_el0; 888 break; 889 case SYSREG_PMCNTENSET_EL0: 890 val = env->cp15.c9_pmcnten; 891 break; 892 case SYSREG_PMUSERENR_EL0: 893 val = env->cp15.c9_pmuserenr; 894 break; 895 case SYSREG_PMCEID0_EL0: 896 case SYSREG_PMCEID1_EL0: 897 /* We can't really count anything yet, declare all events invalid */ 898 val = 0; 899 break; 900 case SYSREG_OSLSR_EL1: 901 val = env->cp15.oslsr_el1; 902 break; 903 case SYSREG_OSDLR_EL1: 904 /* Dummy register */ 905 break; 906 case SYSREG_ICC_AP0R0_EL1: 907 case SYSREG_ICC_AP0R1_EL1: 908 case SYSREG_ICC_AP0R2_EL1: 909 case SYSREG_ICC_AP0R3_EL1: 910 case SYSREG_ICC_AP1R0_EL1: 911 case SYSREG_ICC_AP1R1_EL1: 912 case SYSREG_ICC_AP1R2_EL1: 913 case SYSREG_ICC_AP1R3_EL1: 914 case SYSREG_ICC_ASGI1R_EL1: 915 case SYSREG_ICC_BPR0_EL1: 916 case SYSREG_ICC_BPR1_EL1: 917 case SYSREG_ICC_DIR_EL1: 918 case SYSREG_ICC_EOIR0_EL1: 919 case SYSREG_ICC_EOIR1_EL1: 920 case SYSREG_ICC_HPPIR0_EL1: 921 case SYSREG_ICC_HPPIR1_EL1: 922 case SYSREG_ICC_IAR0_EL1: 923 case SYSREG_ICC_IAR1_EL1: 924 case SYSREG_ICC_IGRPEN0_EL1: 925 case SYSREG_ICC_IGRPEN1_EL1: 926 case SYSREG_ICC_PMR_EL1: 927 case SYSREG_ICC_SGI0R_EL1: 928 case SYSREG_ICC_SGI1R_EL1: 929 case SYSREG_ICC_SRE_EL1: 930 case SYSREG_ICC_CTLR_EL1: 931 /* Call the TCG sysreg handler. This is only safe for GICv3 regs. */ 932 if (!hvf_sysreg_read_cp(cpu, reg, &val)) { 933 hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); 934 } 935 break; 936 default: 937 if (is_id_sysreg(reg)) { 938 /* ID system registers read as RES0 */ 939 val = 0; 940 break; 941 } 942 cpu_synchronize_state(cpu); 943 trace_hvf_unhandled_sysreg_read(env->pc, reg, 944 SYSREG_OP0(reg), 945 SYSREG_OP1(reg), 946 SYSREG_CRN(reg), 947 SYSREG_CRM(reg), 948 SYSREG_OP2(reg)); 949 hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); 950 return 1; 951 } 952 953 trace_hvf_sysreg_read(reg, 954 SYSREG_OP0(reg), 955 SYSREG_OP1(reg), 956 SYSREG_CRN(reg), 957 SYSREG_CRM(reg), 958 SYSREG_OP2(reg), 959 val); 960 hvf_set_reg(cpu, rt, val); 961 962 return 0; 963 } 964 965 static void pmu_update_irq(CPUARMState *env) 966 { 967 ARMCPU *cpu = env_archcpu(env); 968 qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) && 969 (env->cp15.c9_pminten & env->cp15.c9_pmovsr)); 970 } 971 972 static bool pmu_event_supported(uint16_t number) 973 { 974 return false; 975 } 976 977 /* Returns true if the counter (pass 31 for PMCCNTR) should count events using 978 * the current EL, security state, and register configuration. 979 */ 980 static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter) 981 { 982 uint64_t filter; 983 bool enabled, filtered = true; 984 int el = arm_current_el(env); 985 986 enabled = (env->cp15.c9_pmcr & PMCRE) && 987 (env->cp15.c9_pmcnten & (1 << counter)); 988 989 if (counter == 31) { 990 filter = env->cp15.pmccfiltr_el0; 991 } else { 992 filter = env->cp15.c14_pmevtyper[counter]; 993 } 994 995 if (el == 0) { 996 filtered = filter & PMXEVTYPER_U; 997 } else if (el == 1) { 998 filtered = filter & PMXEVTYPER_P; 999 } 1000 1001 if (counter != 31) { 1002 /* 1003 * If not checking PMCCNTR, ensure the counter is setup to an event we 1004 * support 1005 */ 1006 uint16_t event = filter & PMXEVTYPER_EVTCOUNT; 1007 if (!pmu_event_supported(event)) { 1008 return false; 1009 } 1010 } 1011 1012 return enabled && !filtered; 1013 } 1014 1015 static void pmswinc_write(CPUARMState *env, uint64_t value) 1016 { 1017 unsigned int i; 1018 for (i = 0; i < pmu_num_counters(env); i++) { 1019 /* Increment a counter's count iff: */ 1020 if ((value & (1 << i)) && /* counter's bit is set */ 1021 /* counter is enabled and not filtered */ 1022 pmu_counter_enabled(env, i) && 1023 /* counter is SW_INCR */ 1024 (env->cp15.c14_pmevtyper[i] & PMXEVTYPER_EVTCOUNT) == 0x0) { 1025 /* 1026 * Detect if this write causes an overflow since we can't predict 1027 * PMSWINC overflows like we can for other events 1028 */ 1029 uint32_t new_pmswinc = env->cp15.c14_pmevcntr[i] + 1; 1030 1031 if (env->cp15.c14_pmevcntr[i] & ~new_pmswinc & INT32_MIN) { 1032 env->cp15.c9_pmovsr |= (1 << i); 1033 pmu_update_irq(env); 1034 } 1035 1036 env->cp15.c14_pmevcntr[i] = new_pmswinc; 1037 } 1038 } 1039 } 1040 1041 static bool hvf_sysreg_write_cp(CPUState *cpu, uint32_t reg, uint64_t val) 1042 { 1043 ARMCPU *arm_cpu = ARM_CPU(cpu); 1044 CPUARMState *env = &arm_cpu->env; 1045 const ARMCPRegInfo *ri; 1046 1047 ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg)); 1048 1049 if (ri) { 1050 if (ri->accessfn) { 1051 if (ri->accessfn(env, ri, false) != CP_ACCESS_OK) { 1052 return false; 1053 } 1054 } 1055 if (ri->writefn) { 1056 ri->writefn(env, ri, val); 1057 } else { 1058 CPREG_FIELD64(env, ri) = val; 1059 } 1060 1061 trace_hvf_vgic_write(ri->name, val); 1062 return true; 1063 } 1064 1065 return false; 1066 } 1067 1068 static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) 1069 { 1070 ARMCPU *arm_cpu = ARM_CPU(cpu); 1071 CPUARMState *env = &arm_cpu->env; 1072 1073 trace_hvf_sysreg_write(reg, 1074 SYSREG_OP0(reg), 1075 SYSREG_OP1(reg), 1076 SYSREG_CRN(reg), 1077 SYSREG_CRM(reg), 1078 SYSREG_OP2(reg), 1079 val); 1080 1081 switch (reg) { 1082 case SYSREG_PMCCNTR_EL0: 1083 pmu_op_start(env); 1084 env->cp15.c15_ccnt = val; 1085 pmu_op_finish(env); 1086 break; 1087 case SYSREG_PMCR_EL0: 1088 pmu_op_start(env); 1089 1090 if (val & PMCRC) { 1091 /* The counter has been reset */ 1092 env->cp15.c15_ccnt = 0; 1093 } 1094 1095 if (val & PMCRP) { 1096 unsigned int i; 1097 for (i = 0; i < pmu_num_counters(env); i++) { 1098 env->cp15.c14_pmevcntr[i] = 0; 1099 } 1100 } 1101 1102 env->cp15.c9_pmcr &= ~PMCR_WRITABLE_MASK; 1103 env->cp15.c9_pmcr |= (val & PMCR_WRITABLE_MASK); 1104 1105 pmu_op_finish(env); 1106 break; 1107 case SYSREG_PMUSERENR_EL0: 1108 env->cp15.c9_pmuserenr = val & 0xf; 1109 break; 1110 case SYSREG_PMCNTENSET_EL0: 1111 env->cp15.c9_pmcnten |= (val & pmu_counter_mask(env)); 1112 break; 1113 case SYSREG_PMCNTENCLR_EL0: 1114 env->cp15.c9_pmcnten &= ~(val & pmu_counter_mask(env)); 1115 break; 1116 case SYSREG_PMINTENCLR_EL1: 1117 pmu_op_start(env); 1118 env->cp15.c9_pminten |= val; 1119 pmu_op_finish(env); 1120 break; 1121 case SYSREG_PMOVSCLR_EL0: 1122 pmu_op_start(env); 1123 env->cp15.c9_pmovsr &= ~val; 1124 pmu_op_finish(env); 1125 break; 1126 case SYSREG_PMSWINC_EL0: 1127 pmu_op_start(env); 1128 pmswinc_write(env, val); 1129 pmu_op_finish(env); 1130 break; 1131 case SYSREG_PMSELR_EL0: 1132 env->cp15.c9_pmselr = val & 0x1f; 1133 break; 1134 case SYSREG_PMCCFILTR_EL0: 1135 pmu_op_start(env); 1136 env->cp15.pmccfiltr_el0 = val & PMCCFILTR_EL0; 1137 pmu_op_finish(env); 1138 break; 1139 case SYSREG_OSLAR_EL1: 1140 env->cp15.oslsr_el1 = val & 1; 1141 break; 1142 case SYSREG_OSDLR_EL1: 1143 /* Dummy register */ 1144 break; 1145 case SYSREG_ICC_AP0R0_EL1: 1146 case SYSREG_ICC_AP0R1_EL1: 1147 case SYSREG_ICC_AP0R2_EL1: 1148 case SYSREG_ICC_AP0R3_EL1: 1149 case SYSREG_ICC_AP1R0_EL1: 1150 case SYSREG_ICC_AP1R1_EL1: 1151 case SYSREG_ICC_AP1R2_EL1: 1152 case SYSREG_ICC_AP1R3_EL1: 1153 case SYSREG_ICC_ASGI1R_EL1: 1154 case SYSREG_ICC_BPR0_EL1: 1155 case SYSREG_ICC_BPR1_EL1: 1156 case SYSREG_ICC_CTLR_EL1: 1157 case SYSREG_ICC_DIR_EL1: 1158 case SYSREG_ICC_EOIR0_EL1: 1159 case SYSREG_ICC_EOIR1_EL1: 1160 case SYSREG_ICC_HPPIR0_EL1: 1161 case SYSREG_ICC_HPPIR1_EL1: 1162 case SYSREG_ICC_IAR0_EL1: 1163 case SYSREG_ICC_IAR1_EL1: 1164 case SYSREG_ICC_IGRPEN0_EL1: 1165 case SYSREG_ICC_IGRPEN1_EL1: 1166 case SYSREG_ICC_PMR_EL1: 1167 case SYSREG_ICC_SGI0R_EL1: 1168 case SYSREG_ICC_SGI1R_EL1: 1169 case SYSREG_ICC_SRE_EL1: 1170 /* Call the TCG sysreg handler. This is only safe for GICv3 regs. */ 1171 if (!hvf_sysreg_write_cp(cpu, reg, val)) { 1172 hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); 1173 } 1174 break; 1175 default: 1176 cpu_synchronize_state(cpu); 1177 trace_hvf_unhandled_sysreg_write(env->pc, reg, 1178 SYSREG_OP0(reg), 1179 SYSREG_OP1(reg), 1180 SYSREG_CRN(reg), 1181 SYSREG_CRM(reg), 1182 SYSREG_OP2(reg)); 1183 hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); 1184 return 1; 1185 } 1186 1187 return 0; 1188 } 1189 1190 static int hvf_inject_interrupts(CPUState *cpu) 1191 { 1192 if (cpu->interrupt_request & CPU_INTERRUPT_FIQ) { 1193 trace_hvf_inject_fiq(); 1194 hv_vcpu_set_pending_interrupt(cpu->hvf->fd, HV_INTERRUPT_TYPE_FIQ, 1195 true); 1196 } 1197 1198 if (cpu->interrupt_request & CPU_INTERRUPT_HARD) { 1199 trace_hvf_inject_irq(); 1200 hv_vcpu_set_pending_interrupt(cpu->hvf->fd, HV_INTERRUPT_TYPE_IRQ, 1201 true); 1202 } 1203 1204 return 0; 1205 } 1206 1207 static uint64_t hvf_vtimer_val_raw(void) 1208 { 1209 /* 1210 * mach_absolute_time() returns the vtimer value without the VM 1211 * offset that we define. Add our own offset on top. 1212 */ 1213 return mach_absolute_time() - hvf_state->vtimer_offset; 1214 } 1215 1216 static uint64_t hvf_vtimer_val(void) 1217 { 1218 if (!runstate_is_running()) { 1219 /* VM is paused, the vtimer value is in vtimer.vtimer_val */ 1220 return vtimer.vtimer_val; 1221 } 1222 1223 return hvf_vtimer_val_raw(); 1224 } 1225 1226 static void hvf_wait_for_ipi(CPUState *cpu, struct timespec *ts) 1227 { 1228 /* 1229 * Use pselect to sleep so that other threads can IPI us while we're 1230 * sleeping. 1231 */ 1232 qatomic_mb_set(&cpu->thread_kicked, false); 1233 qemu_mutex_unlock_iothread(); 1234 pselect(0, 0, 0, 0, ts, &cpu->hvf->unblock_ipi_mask); 1235 qemu_mutex_lock_iothread(); 1236 } 1237 1238 static void hvf_wfi(CPUState *cpu) 1239 { 1240 ARMCPU *arm_cpu = ARM_CPU(cpu); 1241 struct timespec ts; 1242 hv_return_t r; 1243 uint64_t ctl; 1244 uint64_t cval; 1245 int64_t ticks_to_sleep; 1246 uint64_t seconds; 1247 uint64_t nanos; 1248 uint32_t cntfrq; 1249 1250 if (cpu->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIQ)) { 1251 /* Interrupt pending, no need to wait */ 1252 return; 1253 } 1254 1255 r = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_CNTV_CTL_EL0, &ctl); 1256 assert_hvf_ok(r); 1257 1258 if (!(ctl & 1) || (ctl & 2)) { 1259 /* Timer disabled or masked, just wait for an IPI. */ 1260 hvf_wait_for_ipi(cpu, NULL); 1261 return; 1262 } 1263 1264 r = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_CNTV_CVAL_EL0, &cval); 1265 assert_hvf_ok(r); 1266 1267 ticks_to_sleep = cval - hvf_vtimer_val(); 1268 if (ticks_to_sleep < 0) { 1269 return; 1270 } 1271 1272 cntfrq = gt_cntfrq_period_ns(arm_cpu); 1273 seconds = muldiv64(ticks_to_sleep, cntfrq, NANOSECONDS_PER_SECOND); 1274 ticks_to_sleep -= muldiv64(seconds, NANOSECONDS_PER_SECOND, cntfrq); 1275 nanos = ticks_to_sleep * cntfrq; 1276 1277 /* 1278 * Don't sleep for less than the time a context switch would take, 1279 * so that we can satisfy fast timer requests on the same CPU. 1280 * Measurements on M1 show the sweet spot to be ~2ms. 1281 */ 1282 if (!seconds && nanos < (2 * SCALE_MS)) { 1283 return; 1284 } 1285 1286 ts = (struct timespec) { seconds, nanos }; 1287 hvf_wait_for_ipi(cpu, &ts); 1288 } 1289 1290 static void hvf_sync_vtimer(CPUState *cpu) 1291 { 1292 ARMCPU *arm_cpu = ARM_CPU(cpu); 1293 hv_return_t r; 1294 uint64_t ctl; 1295 bool irq_state; 1296 1297 if (!cpu->hvf->vtimer_masked) { 1298 /* We will get notified on vtimer changes by hvf, nothing to do */ 1299 return; 1300 } 1301 1302 r = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_CNTV_CTL_EL0, &ctl); 1303 assert_hvf_ok(r); 1304 1305 irq_state = (ctl & (TMR_CTL_ENABLE | TMR_CTL_IMASK | TMR_CTL_ISTATUS)) == 1306 (TMR_CTL_ENABLE | TMR_CTL_ISTATUS); 1307 qemu_set_irq(arm_cpu->gt_timer_outputs[GTIMER_VIRT], irq_state); 1308 1309 if (!irq_state) { 1310 /* Timer no longer asserting, we can unmask it */ 1311 hv_vcpu_set_vtimer_mask(cpu->hvf->fd, false); 1312 cpu->hvf->vtimer_masked = false; 1313 } 1314 } 1315 1316 int hvf_vcpu_exec(CPUState *cpu) 1317 { 1318 ARMCPU *arm_cpu = ARM_CPU(cpu); 1319 CPUARMState *env = &arm_cpu->env; 1320 hv_vcpu_exit_t *hvf_exit = cpu->hvf->exit; 1321 hv_return_t r; 1322 bool advance_pc = false; 1323 1324 if (hvf_inject_interrupts(cpu)) { 1325 return EXCP_INTERRUPT; 1326 } 1327 1328 if (cpu->halted) { 1329 return EXCP_HLT; 1330 } 1331 1332 flush_cpu_state(cpu); 1333 1334 qemu_mutex_unlock_iothread(); 1335 assert_hvf_ok(hv_vcpu_run(cpu->hvf->fd)); 1336 1337 /* handle VMEXIT */ 1338 uint64_t exit_reason = hvf_exit->reason; 1339 uint64_t syndrome = hvf_exit->exception.syndrome; 1340 uint32_t ec = syn_get_ec(syndrome); 1341 1342 qemu_mutex_lock_iothread(); 1343 switch (exit_reason) { 1344 case HV_EXIT_REASON_EXCEPTION: 1345 /* This is the main one, handle below. */ 1346 break; 1347 case HV_EXIT_REASON_VTIMER_ACTIVATED: 1348 qemu_set_irq(arm_cpu->gt_timer_outputs[GTIMER_VIRT], 1); 1349 cpu->hvf->vtimer_masked = true; 1350 return 0; 1351 case HV_EXIT_REASON_CANCELED: 1352 /* we got kicked, no exit to process */ 1353 return 0; 1354 default: 1355 g_assert_not_reached(); 1356 } 1357 1358 hvf_sync_vtimer(cpu); 1359 1360 switch (ec) { 1361 case EC_DATAABORT: { 1362 bool isv = syndrome & ARM_EL_ISV; 1363 bool iswrite = (syndrome >> 6) & 1; 1364 bool s1ptw = (syndrome >> 7) & 1; 1365 uint32_t sas = (syndrome >> 22) & 3; 1366 uint32_t len = 1 << sas; 1367 uint32_t srt = (syndrome >> 16) & 0x1f; 1368 uint32_t cm = (syndrome >> 8) & 0x1; 1369 uint64_t val = 0; 1370 1371 trace_hvf_data_abort(env->pc, hvf_exit->exception.virtual_address, 1372 hvf_exit->exception.physical_address, isv, 1373 iswrite, s1ptw, len, srt); 1374 1375 if (cm) { 1376 /* We don't cache MMIO regions */ 1377 advance_pc = true; 1378 break; 1379 } 1380 1381 assert(isv); 1382 1383 if (iswrite) { 1384 val = hvf_get_reg(cpu, srt); 1385 address_space_write(&address_space_memory, 1386 hvf_exit->exception.physical_address, 1387 MEMTXATTRS_UNSPECIFIED, &val, len); 1388 } else { 1389 address_space_read(&address_space_memory, 1390 hvf_exit->exception.physical_address, 1391 MEMTXATTRS_UNSPECIFIED, &val, len); 1392 hvf_set_reg(cpu, srt, val); 1393 } 1394 1395 advance_pc = true; 1396 break; 1397 } 1398 case EC_SYSTEMREGISTERTRAP: { 1399 bool isread = (syndrome >> 0) & 1; 1400 uint32_t rt = (syndrome >> 5) & 0x1f; 1401 uint32_t reg = syndrome & SYSREG_MASK; 1402 uint64_t val; 1403 int ret = 0; 1404 1405 if (isread) { 1406 ret = hvf_sysreg_read(cpu, reg, rt); 1407 } else { 1408 val = hvf_get_reg(cpu, rt); 1409 ret = hvf_sysreg_write(cpu, reg, val); 1410 } 1411 1412 advance_pc = !ret; 1413 break; 1414 } 1415 case EC_WFX_TRAP: 1416 advance_pc = true; 1417 if (!(syndrome & WFX_IS_WFE)) { 1418 hvf_wfi(cpu); 1419 } 1420 break; 1421 case EC_AA64_HVC: 1422 cpu_synchronize_state(cpu); 1423 if (arm_cpu->psci_conduit == QEMU_PSCI_CONDUIT_HVC) { 1424 if (!hvf_handle_psci_call(cpu)) { 1425 trace_hvf_unknown_hvc(env->xregs[0]); 1426 /* SMCCC 1.3 section 5.2 says every unknown SMCCC call returns -1 */ 1427 env->xregs[0] = -1; 1428 } 1429 } else { 1430 trace_hvf_unknown_hvc(env->xregs[0]); 1431 hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); 1432 } 1433 break; 1434 case EC_AA64_SMC: 1435 cpu_synchronize_state(cpu); 1436 if (arm_cpu->psci_conduit == QEMU_PSCI_CONDUIT_SMC) { 1437 advance_pc = true; 1438 1439 if (!hvf_handle_psci_call(cpu)) { 1440 trace_hvf_unknown_smc(env->xregs[0]); 1441 /* SMCCC 1.3 section 5.2 says every unknown SMCCC call returns -1 */ 1442 env->xregs[0] = -1; 1443 } 1444 } else { 1445 trace_hvf_unknown_smc(env->xregs[0]); 1446 hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); 1447 } 1448 break; 1449 default: 1450 cpu_synchronize_state(cpu); 1451 trace_hvf_exit(syndrome, ec, env->pc); 1452 error_report("0x%llx: unhandled exception ec=0x%x", env->pc, ec); 1453 } 1454 1455 if (advance_pc) { 1456 uint64_t pc; 1457 1458 flush_cpu_state(cpu); 1459 1460 r = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_PC, &pc); 1461 assert_hvf_ok(r); 1462 pc += 4; 1463 r = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_PC, pc); 1464 assert_hvf_ok(r); 1465 } 1466 1467 return 0; 1468 } 1469 1470 static const VMStateDescription vmstate_hvf_vtimer = { 1471 .name = "hvf-vtimer", 1472 .version_id = 1, 1473 .minimum_version_id = 1, 1474 .fields = (VMStateField[]) { 1475 VMSTATE_UINT64(vtimer_val, HVFVTimer), 1476 VMSTATE_END_OF_LIST() 1477 }, 1478 }; 1479 1480 static void hvf_vm_state_change(void *opaque, bool running, RunState state) 1481 { 1482 HVFVTimer *s = opaque; 1483 1484 if (running) { 1485 /* Update vtimer offset on all CPUs */ 1486 hvf_state->vtimer_offset = mach_absolute_time() - s->vtimer_val; 1487 cpu_synchronize_all_states(); 1488 } else { 1489 /* Remember vtimer value on every pause */ 1490 s->vtimer_val = hvf_vtimer_val_raw(); 1491 } 1492 } 1493 1494 int hvf_arch_init(void) 1495 { 1496 hvf_state->vtimer_offset = mach_absolute_time(); 1497 vmstate_register(NULL, 0, &vmstate_hvf_vtimer, &vtimer); 1498 qemu_add_vm_change_state_handler(hvf_vm_state_change, &vtimer); 1499 return 0; 1500 } 1501