xref: /openbmc/qemu/target/arm/helper.c (revision bed079da04dd9e0e249b9bc22bca8dce58b67f40)
1 #include "qemu/osdep.h"
2 #include "trace.h"
3 #include "cpu.h"
4 #include "internals.h"
5 #include "exec/gdbstub.h"
6 #include "exec/helper-proto.h"
7 #include "qemu/host-utils.h"
8 #include "sysemu/arch_init.h"
9 #include "sysemu/sysemu.h"
10 #include "qemu/bitops.h"
11 #include "qemu/crc32c.h"
12 #include "exec/exec-all.h"
13 #include "exec/cpu_ldst.h"
14 #include "arm_ldst.h"
15 #include <zlib.h> /* For crc32 */
16 #include "exec/semihost.h"
17 #include "sysemu/kvm.h"
18 
19 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
20 
21 #ifndef CONFIG_USER_ONLY
22 static bool get_phys_addr(CPUARMState *env, target_ulong address,
23                           MMUAccessType access_type, ARMMMUIdx mmu_idx,
24                           hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
25                           target_ulong *page_size, uint32_t *fsr,
26                           ARMMMUFaultInfo *fi);
27 
28 static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
29                                MMUAccessType access_type, ARMMMUIdx mmu_idx,
30                                hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
31                                target_ulong *page_size_ptr, uint32_t *fsr,
32                                ARMMMUFaultInfo *fi);
33 
34 /* Definitions for the PMCCNTR and PMCR registers */
35 #define PMCRD   0x8
36 #define PMCRC   0x4
37 #define PMCRE   0x1
38 #endif
39 
40 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
41 {
42     int nregs;
43 
44     /* VFP data registers are always little-endian.  */
45     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
46     if (reg < nregs) {
47         stfq_le_p(buf, env->vfp.regs[reg]);
48         return 8;
49     }
50     if (arm_feature(env, ARM_FEATURE_NEON)) {
51         /* Aliases for Q regs.  */
52         nregs += 16;
53         if (reg < nregs) {
54             stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
55             stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
56             return 16;
57         }
58     }
59     switch (reg - nregs) {
60     case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
61     case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
62     case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
63     }
64     return 0;
65 }
66 
67 static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
68 {
69     int nregs;
70 
71     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
72     if (reg < nregs) {
73         env->vfp.regs[reg] = ldfq_le_p(buf);
74         return 8;
75     }
76     if (arm_feature(env, ARM_FEATURE_NEON)) {
77         nregs += 16;
78         if (reg < nregs) {
79             env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
80             env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
81             return 16;
82         }
83     }
84     switch (reg - nregs) {
85     case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
86     case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
87     case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
88     }
89     return 0;
90 }
91 
92 static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
93 {
94     switch (reg) {
95     case 0 ... 31:
96         /* 128 bit FP register */
97         stfq_le_p(buf, env->vfp.regs[reg * 2]);
98         stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]);
99         return 16;
100     case 32:
101         /* FPSR */
102         stl_p(buf, vfp_get_fpsr(env));
103         return 4;
104     case 33:
105         /* FPCR */
106         stl_p(buf, vfp_get_fpcr(env));
107         return 4;
108     default:
109         return 0;
110     }
111 }
112 
113 static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
114 {
115     switch (reg) {
116     case 0 ... 31:
117         /* 128 bit FP register */
118         env->vfp.regs[reg * 2] = ldfq_le_p(buf);
119         env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8);
120         return 16;
121     case 32:
122         /* FPSR */
123         vfp_set_fpsr(env, ldl_p(buf));
124         return 4;
125     case 33:
126         /* FPCR */
127         vfp_set_fpcr(env, ldl_p(buf));
128         return 4;
129     default:
130         return 0;
131     }
132 }
133 
134 static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
135 {
136     assert(ri->fieldoffset);
137     if (cpreg_field_is_64bit(ri)) {
138         return CPREG_FIELD64(env, ri);
139     } else {
140         return CPREG_FIELD32(env, ri);
141     }
142 }
143 
144 static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
145                       uint64_t value)
146 {
147     assert(ri->fieldoffset);
148     if (cpreg_field_is_64bit(ri)) {
149         CPREG_FIELD64(env, ri) = value;
150     } else {
151         CPREG_FIELD32(env, ri) = value;
152     }
153 }
154 
155 static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri)
156 {
157     return (char *)env + ri->fieldoffset;
158 }
159 
160 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri)
161 {
162     /* Raw read of a coprocessor register (as needed for migration, etc). */
163     if (ri->type & ARM_CP_CONST) {
164         return ri->resetvalue;
165     } else if (ri->raw_readfn) {
166         return ri->raw_readfn(env, ri);
167     } else if (ri->readfn) {
168         return ri->readfn(env, ri);
169     } else {
170         return raw_read(env, ri);
171     }
172 }
173 
174 static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
175                              uint64_t v)
176 {
177     /* Raw write of a coprocessor register (as needed for migration, etc).
178      * Note that constant registers are treated as write-ignored; the
179      * caller should check for success by whether a readback gives the
180      * value written.
181      */
182     if (ri->type & ARM_CP_CONST) {
183         return;
184     } else if (ri->raw_writefn) {
185         ri->raw_writefn(env, ri, v);
186     } else if (ri->writefn) {
187         ri->writefn(env, ri, v);
188     } else {
189         raw_write(env, ri, v);
190     }
191 }
192 
193 static bool raw_accessors_invalid(const ARMCPRegInfo *ri)
194 {
195    /* Return true if the regdef would cause an assertion if you called
196     * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
197     * program bug for it not to have the NO_RAW flag).
198     * NB that returning false here doesn't necessarily mean that calling
199     * read/write_raw_cp_reg() is safe, because we can't distinguish "has
200     * read/write access functions which are safe for raw use" from "has
201     * read/write access functions which have side effects but has forgotten
202     * to provide raw access functions".
203     * The tests here line up with the conditions in read/write_raw_cp_reg()
204     * and assertions in raw_read()/raw_write().
205     */
206     if ((ri->type & ARM_CP_CONST) ||
207         ri->fieldoffset ||
208         ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) {
209         return false;
210     }
211     return true;
212 }
213 
214 bool write_cpustate_to_list(ARMCPU *cpu)
215 {
216     /* Write the coprocessor state from cpu->env to the (index,value) list. */
217     int i;
218     bool ok = true;
219 
220     for (i = 0; i < cpu->cpreg_array_len; i++) {
221         uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
222         const ARMCPRegInfo *ri;
223 
224         ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
225         if (!ri) {
226             ok = false;
227             continue;
228         }
229         if (ri->type & ARM_CP_NO_RAW) {
230             continue;
231         }
232         cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri);
233     }
234     return ok;
235 }
236 
237 bool write_list_to_cpustate(ARMCPU *cpu)
238 {
239     int i;
240     bool ok = true;
241 
242     for (i = 0; i < cpu->cpreg_array_len; i++) {
243         uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
244         uint64_t v = cpu->cpreg_values[i];
245         const ARMCPRegInfo *ri;
246 
247         ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
248         if (!ri) {
249             ok = false;
250             continue;
251         }
252         if (ri->type & ARM_CP_NO_RAW) {
253             continue;
254         }
255         /* Write value and confirm it reads back as written
256          * (to catch read-only registers and partially read-only
257          * registers where the incoming migration value doesn't match)
258          */
259         write_raw_cp_reg(&cpu->env, ri, v);
260         if (read_raw_cp_reg(&cpu->env, ri) != v) {
261             ok = false;
262         }
263     }
264     return ok;
265 }
266 
267 static void add_cpreg_to_list(gpointer key, gpointer opaque)
268 {
269     ARMCPU *cpu = opaque;
270     uint64_t regidx;
271     const ARMCPRegInfo *ri;
272 
273     regidx = *(uint32_t *)key;
274     ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
275 
276     if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
277         cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
278         /* The value array need not be initialized at this point */
279         cpu->cpreg_array_len++;
280     }
281 }
282 
283 static void count_cpreg(gpointer key, gpointer opaque)
284 {
285     ARMCPU *cpu = opaque;
286     uint64_t regidx;
287     const ARMCPRegInfo *ri;
288 
289     regidx = *(uint32_t *)key;
290     ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
291 
292     if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
293         cpu->cpreg_array_len++;
294     }
295 }
296 
297 static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
298 {
299     uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
300     uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
301 
302     if (aidx > bidx) {
303         return 1;
304     }
305     if (aidx < bidx) {
306         return -1;
307     }
308     return 0;
309 }
310 
311 void init_cpreg_list(ARMCPU *cpu)
312 {
313     /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
314      * Note that we require cpreg_tuples[] to be sorted by key ID.
315      */
316     GList *keys;
317     int arraylen;
318 
319     keys = g_hash_table_get_keys(cpu->cp_regs);
320     keys = g_list_sort(keys, cpreg_key_compare);
321 
322     cpu->cpreg_array_len = 0;
323 
324     g_list_foreach(keys, count_cpreg, cpu);
325 
326     arraylen = cpu->cpreg_array_len;
327     cpu->cpreg_indexes = g_new(uint64_t, arraylen);
328     cpu->cpreg_values = g_new(uint64_t, arraylen);
329     cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
330     cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
331     cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
332     cpu->cpreg_array_len = 0;
333 
334     g_list_foreach(keys, add_cpreg_to_list, cpu);
335 
336     assert(cpu->cpreg_array_len == arraylen);
337 
338     g_list_free(keys);
339 }
340 
341 /*
342  * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but
343  * they are accessible when EL3 is using AArch64 regardless of EL3.NS.
344  *
345  * access_el3_aa32ns: Used to check AArch32 register views.
346  * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views.
347  */
348 static CPAccessResult access_el3_aa32ns(CPUARMState *env,
349                                         const ARMCPRegInfo *ri,
350                                         bool isread)
351 {
352     bool secure = arm_is_secure_below_el3(env);
353 
354     assert(!arm_el_is_aa64(env, 3));
355     if (secure) {
356         return CP_ACCESS_TRAP_UNCATEGORIZED;
357     }
358     return CP_ACCESS_OK;
359 }
360 
361 static CPAccessResult access_el3_aa32ns_aa64any(CPUARMState *env,
362                                                 const ARMCPRegInfo *ri,
363                                                 bool isread)
364 {
365     if (!arm_el_is_aa64(env, 3)) {
366         return access_el3_aa32ns(env, ri, isread);
367     }
368     return CP_ACCESS_OK;
369 }
370 
371 /* Some secure-only AArch32 registers trap to EL3 if used from
372  * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
373  * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
374  * We assume that the .access field is set to PL1_RW.
375  */
376 static CPAccessResult access_trap_aa32s_el1(CPUARMState *env,
377                                             const ARMCPRegInfo *ri,
378                                             bool isread)
379 {
380     if (arm_current_el(env) == 3) {
381         return CP_ACCESS_OK;
382     }
383     if (arm_is_secure_below_el3(env)) {
384         return CP_ACCESS_TRAP_EL3;
385     }
386     /* This will be EL1 NS and EL2 NS, which just UNDEF */
387     return CP_ACCESS_TRAP_UNCATEGORIZED;
388 }
389 
390 /* Check for traps to "powerdown debug" registers, which are controlled
391  * by MDCR.TDOSA
392  */
393 static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *ri,
394                                    bool isread)
395 {
396     int el = arm_current_el(env);
397 
398     if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDOSA)
399         && !arm_is_secure_below_el3(env)) {
400         return CP_ACCESS_TRAP_EL2;
401     }
402     if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDOSA)) {
403         return CP_ACCESS_TRAP_EL3;
404     }
405     return CP_ACCESS_OK;
406 }
407 
408 /* Check for traps to "debug ROM" registers, which are controlled
409  * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3.
410  */
411 static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri,
412                                   bool isread)
413 {
414     int el = arm_current_el(env);
415 
416     if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDRA)
417         && !arm_is_secure_below_el3(env)) {
418         return CP_ACCESS_TRAP_EL2;
419     }
420     if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) {
421         return CP_ACCESS_TRAP_EL3;
422     }
423     return CP_ACCESS_OK;
424 }
425 
426 /* Check for traps to general debug registers, which are controlled
427  * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3.
428  */
429 static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri,
430                                   bool isread)
431 {
432     int el = arm_current_el(env);
433 
434     if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDA)
435         && !arm_is_secure_below_el3(env)) {
436         return CP_ACCESS_TRAP_EL2;
437     }
438     if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) {
439         return CP_ACCESS_TRAP_EL3;
440     }
441     return CP_ACCESS_OK;
442 }
443 
444 /* Check for traps to performance monitor registers, which are controlled
445  * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
446  */
447 static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri,
448                                  bool isread)
449 {
450     int el = arm_current_el(env);
451 
452     if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM)
453         && !arm_is_secure_below_el3(env)) {
454         return CP_ACCESS_TRAP_EL2;
455     }
456     if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) {
457         return CP_ACCESS_TRAP_EL3;
458     }
459     return CP_ACCESS_OK;
460 }
461 
462 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
463 {
464     ARMCPU *cpu = arm_env_get_cpu(env);
465 
466     raw_write(env, ri, value);
467     tlb_flush(CPU(cpu)); /* Flush TLB as domain not tracked in TLB */
468 }
469 
470 static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
471 {
472     ARMCPU *cpu = arm_env_get_cpu(env);
473 
474     if (raw_read(env, ri) != value) {
475         /* Unlike real hardware the qemu TLB uses virtual addresses,
476          * not modified virtual addresses, so this causes a TLB flush.
477          */
478         tlb_flush(CPU(cpu));
479         raw_write(env, ri, value);
480     }
481 }
482 
483 static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
484                              uint64_t value)
485 {
486     ARMCPU *cpu = arm_env_get_cpu(env);
487 
488     if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_PMSA)
489         && !extended_addresses_enabled(env)) {
490         /* For VMSA (when not using the LPAE long descriptor page table
491          * format) this register includes the ASID, so do a TLB flush.
492          * For PMSA it is purely a process ID and no action is needed.
493          */
494         tlb_flush(CPU(cpu));
495     }
496     raw_write(env, ri, value);
497 }
498 
499 static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
500                           uint64_t value)
501 {
502     /* Invalidate all (TLBIALL) */
503     ARMCPU *cpu = arm_env_get_cpu(env);
504 
505     tlb_flush(CPU(cpu));
506 }
507 
508 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
509                           uint64_t value)
510 {
511     /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
512     ARMCPU *cpu = arm_env_get_cpu(env);
513 
514     tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
515 }
516 
517 static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
518                            uint64_t value)
519 {
520     /* Invalidate by ASID (TLBIASID) */
521     ARMCPU *cpu = arm_env_get_cpu(env);
522 
523     tlb_flush(CPU(cpu));
524 }
525 
526 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
527                            uint64_t value)
528 {
529     /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
530     ARMCPU *cpu = arm_env_get_cpu(env);
531 
532     tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
533 }
534 
535 /* IS variants of TLB operations must affect all cores */
536 static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
537                              uint64_t value)
538 {
539     CPUState *cs = ENV_GET_CPU(env);
540 
541     tlb_flush_all_cpus_synced(cs);
542 }
543 
544 static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
545                              uint64_t value)
546 {
547     CPUState *cs = ENV_GET_CPU(env);
548 
549     tlb_flush_all_cpus_synced(cs);
550 }
551 
552 static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
553                              uint64_t value)
554 {
555     CPUState *cs = ENV_GET_CPU(env);
556 
557     tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK);
558 }
559 
560 static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
561                              uint64_t value)
562 {
563     CPUState *cs = ENV_GET_CPU(env);
564 
565     tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK);
566 }
567 
568 static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri,
569                                uint64_t value)
570 {
571     CPUState *cs = ENV_GET_CPU(env);
572 
573     tlb_flush_by_mmuidx(cs,
574                         ARMMMUIdxBit_S12NSE1 |
575                         ARMMMUIdxBit_S12NSE0 |
576                         ARMMMUIdxBit_S2NS);
577 }
578 
579 static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
580                                   uint64_t value)
581 {
582     CPUState *cs = ENV_GET_CPU(env);
583 
584     tlb_flush_by_mmuidx_all_cpus_synced(cs,
585                                         ARMMMUIdxBit_S12NSE1 |
586                                         ARMMMUIdxBit_S12NSE0 |
587                                         ARMMMUIdxBit_S2NS);
588 }
589 
590 static void tlbiipas2_write(CPUARMState *env, const ARMCPRegInfo *ri,
591                             uint64_t value)
592 {
593     /* Invalidate by IPA. This has to invalidate any structures that
594      * contain only stage 2 translation information, but does not need
595      * to apply to structures that contain combined stage 1 and stage 2
596      * translation information.
597      * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
598      */
599     CPUState *cs = ENV_GET_CPU(env);
600     uint64_t pageaddr;
601 
602     if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
603         return;
604     }
605 
606     pageaddr = sextract64(value << 12, 0, 40);
607 
608     tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S2NS);
609 }
610 
611 static void tlbiipas2_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
612                                uint64_t value)
613 {
614     CPUState *cs = ENV_GET_CPU(env);
615     uint64_t pageaddr;
616 
617     if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
618         return;
619     }
620 
621     pageaddr = sextract64(value << 12, 0, 40);
622 
623     tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
624                                              ARMMMUIdxBit_S2NS);
625 }
626 
627 static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
628                               uint64_t value)
629 {
630     CPUState *cs = ENV_GET_CPU(env);
631 
632     tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2);
633 }
634 
635 static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
636                                  uint64_t value)
637 {
638     CPUState *cs = ENV_GET_CPU(env);
639 
640     tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2);
641 }
642 
643 static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
644                               uint64_t value)
645 {
646     CPUState *cs = ENV_GET_CPU(env);
647     uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12);
648 
649     tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E2);
650 }
651 
652 static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
653                                  uint64_t value)
654 {
655     CPUState *cs = ENV_GET_CPU(env);
656     uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12);
657 
658     tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
659                                              ARMMMUIdxBit_S1E2);
660 }
661 
662 static const ARMCPRegInfo cp_reginfo[] = {
663     /* Define the secure and non-secure FCSE identifier CP registers
664      * separately because there is no secure bank in V8 (no _EL3).  This allows
665      * the secure register to be properly reset and migrated. There is also no
666      * v8 EL1 version of the register so the non-secure instance stands alone.
667      */
668     { .name = "FCSEIDR(NS)",
669       .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
670       .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS,
671       .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_ns),
672       .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
673     { .name = "FCSEIDR(S)",
674       .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
675       .access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
676       .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s),
677       .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
678     /* Define the secure and non-secure context identifier CP registers
679      * separately because there is no secure bank in V8 (no _EL3).  This allows
680      * the secure register to be properly reset and migrated.  In the
681      * non-secure case, the 32-bit register will have reset and migration
682      * disabled during registration as it is handled by the 64-bit instance.
683      */
684     { .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH,
685       .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
686       .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS,
687       .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]),
688       .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
689     { .name = "CONTEXTIDR(S)", .state = ARM_CP_STATE_AA32,
690       .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
691       .access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
692       .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s),
693       .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
694     REGINFO_SENTINEL
695 };
696 
697 static const ARMCPRegInfo not_v8_cp_reginfo[] = {
698     /* NB: Some of these registers exist in v8 but with more precise
699      * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
700      */
701     /* MMU Domain access control / MPU write buffer control */
702     { .name = "DACR",
703       .cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY,
704       .access = PL1_RW, .resetvalue = 0,
705       .writefn = dacr_write, .raw_writefn = raw_write,
706       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
707                              offsetoflow32(CPUARMState, cp15.dacr_ns) } },
708     /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
709      * For v6 and v5, these mappings are overly broad.
710      */
711     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 0,
712       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
713     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 1,
714       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
715     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 4,
716       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
717     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 8,
718       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
719     /* Cache maintenance ops; some of this space may be overridden later. */
720     { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
721       .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
722       .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
723     REGINFO_SENTINEL
724 };
725 
726 static const ARMCPRegInfo not_v6_cp_reginfo[] = {
727     /* Not all pre-v6 cores implemented this WFI, so this is slightly
728      * over-broad.
729      */
730     { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
731       .access = PL1_W, .type = ARM_CP_WFI },
732     REGINFO_SENTINEL
733 };
734 
735 static const ARMCPRegInfo not_v7_cp_reginfo[] = {
736     /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
737      * is UNPREDICTABLE; we choose to NOP as most implementations do).
738      */
739     { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
740       .access = PL1_W, .type = ARM_CP_WFI },
741     /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
742      * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
743      * OMAPCP will override this space.
744      */
745     { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
746       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
747       .resetvalue = 0 },
748     { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
749       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
750       .resetvalue = 0 },
751     /* v6 doesn't have the cache ID registers but Linux reads them anyway */
752     { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
753       .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
754       .resetvalue = 0 },
755     /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
756      * implementing it as RAZ means the "debug architecture version" bits
757      * will read as a reserved value, which should cause Linux to not try
758      * to use the debug hardware.
759      */
760     { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
761       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
762     /* MMU TLB control. Note that the wildcarding means we cover not just
763      * the unified TLB ops but also the dside/iside/inner-shareable variants.
764      */
765     { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
766       .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write,
767       .type = ARM_CP_NO_RAW },
768     { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
769       .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write,
770       .type = ARM_CP_NO_RAW },
771     { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
772       .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write,
773       .type = ARM_CP_NO_RAW },
774     { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
775       .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
776       .type = ARM_CP_NO_RAW },
777     { .name = "PRRR", .cp = 15, .crn = 10, .crm = 2,
778       .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP },
779     { .name = "NMRR", .cp = 15, .crn = 10, .crm = 2,
780       .opc1 = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_NOP },
781     REGINFO_SENTINEL
782 };
783 
784 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
785                         uint64_t value)
786 {
787     uint32_t mask = 0;
788 
789     /* In ARMv8 most bits of CPACR_EL1 are RES0. */
790     if (!arm_feature(env, ARM_FEATURE_V8)) {
791         /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
792          * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
793          * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
794          */
795         if (arm_feature(env, ARM_FEATURE_VFP)) {
796             /* VFP coprocessor: cp10 & cp11 [23:20] */
797             mask |= (1 << 31) | (1 << 30) | (0xf << 20);
798 
799             if (!arm_feature(env, ARM_FEATURE_NEON)) {
800                 /* ASEDIS [31] bit is RAO/WI */
801                 value |= (1 << 31);
802             }
803 
804             /* VFPv3 and upwards with NEON implement 32 double precision
805              * registers (D0-D31).
806              */
807             if (!arm_feature(env, ARM_FEATURE_NEON) ||
808                     !arm_feature(env, ARM_FEATURE_VFP3)) {
809                 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
810                 value |= (1 << 30);
811             }
812         }
813         value &= mask;
814     }
815     env->cp15.cpacr_el1 = value;
816 }
817 
818 static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
819                                    bool isread)
820 {
821     if (arm_feature(env, ARM_FEATURE_V8)) {
822         /* Check if CPACR accesses are to be trapped to EL2 */
823         if (arm_current_el(env) == 1 &&
824             (env->cp15.cptr_el[2] & CPTR_TCPAC) && !arm_is_secure(env)) {
825             return CP_ACCESS_TRAP_EL2;
826         /* Check if CPACR accesses are to be trapped to EL3 */
827         } else if (arm_current_el(env) < 3 &&
828                    (env->cp15.cptr_el[3] & CPTR_TCPAC)) {
829             return CP_ACCESS_TRAP_EL3;
830         }
831     }
832 
833     return CP_ACCESS_OK;
834 }
835 
836 static CPAccessResult cptr_access(CPUARMState *env, const ARMCPRegInfo *ri,
837                                   bool isread)
838 {
839     /* Check if CPTR accesses are set to trap to EL3 */
840     if (arm_current_el(env) == 2 && (env->cp15.cptr_el[3] & CPTR_TCPAC)) {
841         return CP_ACCESS_TRAP_EL3;
842     }
843 
844     return CP_ACCESS_OK;
845 }
846 
847 static const ARMCPRegInfo v6_cp_reginfo[] = {
848     /* prefetch by MVA in v6, NOP in v7 */
849     { .name = "MVA_prefetch",
850       .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
851       .access = PL1_W, .type = ARM_CP_NOP },
852     /* We need to break the TB after ISB to execute self-modifying code
853      * correctly and also to take any pending interrupts immediately.
854      * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
855      */
856     { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
857       .access = PL0_W, .type = ARM_CP_NO_RAW, .writefn = arm_cp_write_ignore },
858     { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
859       .access = PL0_W, .type = ARM_CP_NOP },
860     { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
861       .access = PL0_W, .type = ARM_CP_NOP },
862     { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
863       .access = PL1_RW,
864       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s),
865                              offsetof(CPUARMState, cp15.ifar_ns) },
866       .resetvalue = 0, },
867     /* Watchpoint Fault Address Register : should actually only be present
868      * for 1136, 1176, 11MPCore.
869      */
870     { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
871       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
872     { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
873       .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
874       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
875       .resetvalue = 0, .writefn = cpacr_write },
876     REGINFO_SENTINEL
877 };
878 
879 static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri,
880                                    bool isread)
881 {
882     /* Performance monitor registers user accessibility is controlled
883      * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable
884      * trapping to EL2 or EL3 for other accesses.
885      */
886     int el = arm_current_el(env);
887 
888     if (el == 0 && !(env->cp15.c9_pmuserenr & 1)) {
889         return CP_ACCESS_TRAP;
890     }
891     if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM)
892         && !arm_is_secure_below_el3(env)) {
893         return CP_ACCESS_TRAP_EL2;
894     }
895     if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) {
896         return CP_ACCESS_TRAP_EL3;
897     }
898 
899     return CP_ACCESS_OK;
900 }
901 
902 static CPAccessResult pmreg_access_xevcntr(CPUARMState *env,
903                                            const ARMCPRegInfo *ri,
904                                            bool isread)
905 {
906     /* ER: event counter read trap control */
907     if (arm_feature(env, ARM_FEATURE_V8)
908         && arm_current_el(env) == 0
909         && (env->cp15.c9_pmuserenr & (1 << 3)) != 0
910         && isread) {
911         return CP_ACCESS_OK;
912     }
913 
914     return pmreg_access(env, ri, isread);
915 }
916 
917 static CPAccessResult pmreg_access_swinc(CPUARMState *env,
918                                          const ARMCPRegInfo *ri,
919                                          bool isread)
920 {
921     /* SW: software increment write trap control */
922     if (arm_feature(env, ARM_FEATURE_V8)
923         && arm_current_el(env) == 0
924         && (env->cp15.c9_pmuserenr & (1 << 1)) != 0
925         && !isread) {
926         return CP_ACCESS_OK;
927     }
928 
929     return pmreg_access(env, ri, isread);
930 }
931 
932 #ifndef CONFIG_USER_ONLY
933 
934 static CPAccessResult pmreg_access_selr(CPUARMState *env,
935                                         const ARMCPRegInfo *ri,
936                                         bool isread)
937 {
938     /* ER: event counter read trap control */
939     if (arm_feature(env, ARM_FEATURE_V8)
940         && arm_current_el(env) == 0
941         && (env->cp15.c9_pmuserenr & (1 << 3)) != 0) {
942         return CP_ACCESS_OK;
943     }
944 
945     return pmreg_access(env, ri, isread);
946 }
947 
948 static CPAccessResult pmreg_access_ccntr(CPUARMState *env,
949                                          const ARMCPRegInfo *ri,
950                                          bool isread)
951 {
952     /* CR: cycle counter read trap control */
953     if (arm_feature(env, ARM_FEATURE_V8)
954         && arm_current_el(env) == 0
955         && (env->cp15.c9_pmuserenr & (1 << 2)) != 0
956         && isread) {
957         return CP_ACCESS_OK;
958     }
959 
960     return pmreg_access(env, ri, isread);
961 }
962 
963 static inline bool arm_ccnt_enabled(CPUARMState *env)
964 {
965     /* This does not support checking PMCCFILTR_EL0 register */
966 
967     if (!(env->cp15.c9_pmcr & PMCRE)) {
968         return false;
969     }
970 
971     return true;
972 }
973 
974 void pmccntr_sync(CPUARMState *env)
975 {
976     uint64_t temp_ticks;
977 
978     temp_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
979                           ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
980 
981     if (env->cp15.c9_pmcr & PMCRD) {
982         /* Increment once every 64 processor clock cycles */
983         temp_ticks /= 64;
984     }
985 
986     if (arm_ccnt_enabled(env)) {
987         env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
988     }
989 }
990 
991 static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
992                        uint64_t value)
993 {
994     pmccntr_sync(env);
995 
996     if (value & PMCRC) {
997         /* The counter has been reset */
998         env->cp15.c15_ccnt = 0;
999     }
1000 
1001     /* only the DP, X, D and E bits are writable */
1002     env->cp15.c9_pmcr &= ~0x39;
1003     env->cp15.c9_pmcr |= (value & 0x39);
1004 
1005     pmccntr_sync(env);
1006 }
1007 
1008 static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1009 {
1010     uint64_t total_ticks;
1011 
1012     if (!arm_ccnt_enabled(env)) {
1013         /* Counter is disabled, do not change value */
1014         return env->cp15.c15_ccnt;
1015     }
1016 
1017     total_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
1018                            ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
1019 
1020     if (env->cp15.c9_pmcr & PMCRD) {
1021         /* Increment once every 64 processor clock cycles */
1022         total_ticks /= 64;
1023     }
1024     return total_ticks - env->cp15.c15_ccnt;
1025 }
1026 
1027 static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1028                          uint64_t value)
1029 {
1030     /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
1031      * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the
1032      * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are
1033      * accessed.
1034      */
1035     env->cp15.c9_pmselr = value & 0x1f;
1036 }
1037 
1038 static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1039                         uint64_t value)
1040 {
1041     uint64_t total_ticks;
1042 
1043     if (!arm_ccnt_enabled(env)) {
1044         /* Counter is disabled, set the absolute value */
1045         env->cp15.c15_ccnt = value;
1046         return;
1047     }
1048 
1049     total_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
1050                            ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
1051 
1052     if (env->cp15.c9_pmcr & PMCRD) {
1053         /* Increment once every 64 processor clock cycles */
1054         total_ticks /= 64;
1055     }
1056     env->cp15.c15_ccnt = total_ticks - value;
1057 }
1058 
1059 static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri,
1060                             uint64_t value)
1061 {
1062     uint64_t cur_val = pmccntr_read(env, NULL);
1063 
1064     pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value));
1065 }
1066 
1067 #else /* CONFIG_USER_ONLY */
1068 
1069 void pmccntr_sync(CPUARMState *env)
1070 {
1071 }
1072 
1073 #endif
1074 
1075 static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1076                             uint64_t value)
1077 {
1078     pmccntr_sync(env);
1079     env->cp15.pmccfiltr_el0 = value & 0x7E000000;
1080     pmccntr_sync(env);
1081 }
1082 
1083 static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
1084                             uint64_t value)
1085 {
1086     value &= (1 << 31);
1087     env->cp15.c9_pmcnten |= value;
1088 }
1089 
1090 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1091                              uint64_t value)
1092 {
1093     value &= (1 << 31);
1094     env->cp15.c9_pmcnten &= ~value;
1095 }
1096 
1097 static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1098                          uint64_t value)
1099 {
1100     env->cp15.c9_pmovsr &= ~value;
1101 }
1102 
1103 static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
1104                              uint64_t value)
1105 {
1106     /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
1107      * PMSELR value is equal to or greater than the number of implemented
1108      * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI.
1109      */
1110     if (env->cp15.c9_pmselr == 0x1f) {
1111         pmccfiltr_write(env, ri, value);
1112     }
1113 }
1114 
1115 static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri)
1116 {
1117     /* We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER
1118      * are CONSTRAINED UNPREDICTABLE. See comments in pmxevtyper_write().
1119      */
1120     if (env->cp15.c9_pmselr == 0x1f) {
1121         return env->cp15.pmccfiltr_el0;
1122     } else {
1123         return 0;
1124     }
1125 }
1126 
1127 static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1128                             uint64_t value)
1129 {
1130     if (arm_feature(env, ARM_FEATURE_V8)) {
1131         env->cp15.c9_pmuserenr = value & 0xf;
1132     } else {
1133         env->cp15.c9_pmuserenr = value & 1;
1134     }
1135 }
1136 
1137 static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
1138                              uint64_t value)
1139 {
1140     /* We have no event counters so only the C bit can be changed */
1141     value &= (1 << 31);
1142     env->cp15.c9_pminten |= value;
1143 }
1144 
1145 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1146                              uint64_t value)
1147 {
1148     value &= (1 << 31);
1149     env->cp15.c9_pminten &= ~value;
1150 }
1151 
1152 static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
1153                        uint64_t value)
1154 {
1155     /* Note that even though the AArch64 view of this register has bits
1156      * [10:0] all RES0 we can only mask the bottom 5, to comply with the
1157      * architectural requirements for bits which are RES0 only in some
1158      * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
1159      * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
1160      */
1161     raw_write(env, ri, value & ~0x1FULL);
1162 }
1163 
1164 static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1165 {
1166     /* We only mask off bits that are RES0 both for AArch64 and AArch32.
1167      * For bits that vary between AArch32/64, code needs to check the
1168      * current execution mode before directly using the feature bit.
1169      */
1170     uint32_t valid_mask = SCR_AARCH64_MASK | SCR_AARCH32_MASK;
1171 
1172     if (!arm_feature(env, ARM_FEATURE_EL2)) {
1173         valid_mask &= ~SCR_HCE;
1174 
1175         /* On ARMv7, SMD (or SCD as it is called in v7) is only
1176          * supported if EL2 exists. The bit is UNK/SBZP when
1177          * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
1178          * when EL2 is unavailable.
1179          * On ARMv8, this bit is always available.
1180          */
1181         if (arm_feature(env, ARM_FEATURE_V7) &&
1182             !arm_feature(env, ARM_FEATURE_V8)) {
1183             valid_mask &= ~SCR_SMD;
1184         }
1185     }
1186 
1187     /* Clear all-context RES0 bits.  */
1188     value &= valid_mask;
1189     raw_write(env, ri, value);
1190 }
1191 
1192 static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1193 {
1194     ARMCPU *cpu = arm_env_get_cpu(env);
1195 
1196     /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
1197      * bank
1198      */
1199     uint32_t index = A32_BANKED_REG_GET(env, csselr,
1200                                         ri->secure & ARM_CP_SECSTATE_S);
1201 
1202     return cpu->ccsidr[index];
1203 }
1204 
1205 static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1206                          uint64_t value)
1207 {
1208     raw_write(env, ri, value & 0xf);
1209 }
1210 
1211 static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1212 {
1213     CPUState *cs = ENV_GET_CPU(env);
1214     uint64_t ret = 0;
1215 
1216     if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
1217         ret |= CPSR_I;
1218     }
1219     if (cs->interrupt_request & CPU_INTERRUPT_FIQ) {
1220         ret |= CPSR_F;
1221     }
1222     /* External aborts are not possible in QEMU so A bit is always clear */
1223     return ret;
1224 }
1225 
1226 static const ARMCPRegInfo v7_cp_reginfo[] = {
1227     /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
1228     { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
1229       .access = PL1_W, .type = ARM_CP_NOP },
1230     /* Performance monitors are implementation defined in v7,
1231      * but with an ARM recommended set of registers, which we
1232      * follow (although we don't actually implement any counters)
1233      *
1234      * Performance registers fall into three categories:
1235      *  (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
1236      *  (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
1237      *  (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
1238      * For the cases controlled by PMUSERENR we must set .access to PL0_RW
1239      * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
1240      */
1241     { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
1242       .access = PL0_RW, .type = ARM_CP_ALIAS,
1243       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
1244       .writefn = pmcntenset_write,
1245       .accessfn = pmreg_access,
1246       .raw_writefn = raw_write },
1247     { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64,
1248       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1,
1249       .access = PL0_RW, .accessfn = pmreg_access,
1250       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0,
1251       .writefn = pmcntenset_write, .raw_writefn = raw_write },
1252     { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
1253       .access = PL0_RW,
1254       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
1255       .accessfn = pmreg_access,
1256       .writefn = pmcntenclr_write,
1257       .type = ARM_CP_ALIAS },
1258     { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64,
1259       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2,
1260       .access = PL0_RW, .accessfn = pmreg_access,
1261       .type = ARM_CP_ALIAS,
1262       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
1263       .writefn = pmcntenclr_write },
1264     { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
1265       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
1266       .accessfn = pmreg_access,
1267       .writefn = pmovsr_write,
1268       .raw_writefn = raw_write },
1269     { .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64,
1270       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 3,
1271       .access = PL0_RW, .accessfn = pmreg_access,
1272       .type = ARM_CP_ALIAS,
1273       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
1274       .writefn = pmovsr_write,
1275       .raw_writefn = raw_write },
1276     /* Unimplemented so WI. */
1277     { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
1278       .access = PL0_W, .accessfn = pmreg_access_swinc, .type = ARM_CP_NOP },
1279 #ifndef CONFIG_USER_ONLY
1280     { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
1281       .access = PL0_RW, .type = ARM_CP_ALIAS,
1282       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr),
1283       .accessfn = pmreg_access_selr, .writefn = pmselr_write,
1284       .raw_writefn = raw_write},
1285     { .name = "PMSELR_EL0", .state = ARM_CP_STATE_AA64,
1286       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 5,
1287       .access = PL0_RW, .accessfn = pmreg_access_selr,
1288       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmselr),
1289       .writefn = pmselr_write, .raw_writefn = raw_write, },
1290     { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
1291       .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
1292       .readfn = pmccntr_read, .writefn = pmccntr_write32,
1293       .accessfn = pmreg_access_ccntr },
1294     { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64,
1295       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0,
1296       .access = PL0_RW, .accessfn = pmreg_access_ccntr,
1297       .type = ARM_CP_IO,
1298       .readfn = pmccntr_read, .writefn = pmccntr_write, },
1299 #endif
1300     { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64,
1301       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7,
1302       .writefn = pmccfiltr_write,
1303       .access = PL0_RW, .accessfn = pmreg_access,
1304       .type = ARM_CP_IO,
1305       .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0),
1306       .resetvalue = 0, },
1307     { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
1308       .access = PL0_RW, .type = ARM_CP_NO_RAW, .accessfn = pmreg_access,
1309       .writefn = pmxevtyper_write, .readfn = pmxevtyper_read },
1310     { .name = "PMXEVTYPER_EL0", .state = ARM_CP_STATE_AA64,
1311       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 1,
1312       .access = PL0_RW, .type = ARM_CP_NO_RAW, .accessfn = pmreg_access,
1313       .writefn = pmxevtyper_write, .readfn = pmxevtyper_read },
1314     /* Unimplemented, RAZ/WI. */
1315     { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
1316       .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
1317       .accessfn = pmreg_access_xevcntr },
1318     { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
1319       .access = PL0_R | PL1_RW, .accessfn = access_tpm,
1320       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
1321       .resetvalue = 0,
1322       .writefn = pmuserenr_write, .raw_writefn = raw_write },
1323     { .name = "PMUSERENR_EL0", .state = ARM_CP_STATE_AA64,
1324       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 0,
1325       .access = PL0_R | PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS,
1326       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
1327       .resetvalue = 0,
1328       .writefn = pmuserenr_write, .raw_writefn = raw_write },
1329     { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
1330       .access = PL1_RW, .accessfn = access_tpm,
1331       .type = ARM_CP_ALIAS,
1332       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pminten),
1333       .resetvalue = 0,
1334       .writefn = pmintenset_write, .raw_writefn = raw_write },
1335     { .name = "PMINTENSET_EL1", .state = ARM_CP_STATE_AA64,
1336       .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 1,
1337       .access = PL1_RW, .accessfn = access_tpm,
1338       .type = ARM_CP_IO,
1339       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
1340       .writefn = pmintenset_write, .raw_writefn = raw_write,
1341       .resetvalue = 0x0 },
1342     { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
1343       .access = PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS,
1344       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
1345       .writefn = pmintenclr_write, },
1346     { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64,
1347       .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2,
1348       .access = PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS,
1349       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
1350       .writefn = pmintenclr_write },
1351     { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
1352       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
1353       .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_RAW },
1354     { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
1355       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
1356       .access = PL1_RW, .writefn = csselr_write, .resetvalue = 0,
1357       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s),
1358                              offsetof(CPUARMState, cp15.csselr_ns) } },
1359     /* Auxiliary ID register: this actually has an IMPDEF value but for now
1360      * just RAZ for all cores:
1361      */
1362     { .name = "AIDR", .state = ARM_CP_STATE_BOTH,
1363       .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7,
1364       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1365     /* Auxiliary fault status registers: these also are IMPDEF, and we
1366      * choose to RAZ/WI for all cores.
1367      */
1368     { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH,
1369       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0,
1370       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1371     { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH,
1372       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
1373       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1374     /* MAIR can just read-as-written because we don't implement caches
1375      * and so don't need to care about memory attributes.
1376      */
1377     { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
1378       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
1379       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]),
1380       .resetvalue = 0 },
1381     { .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64,
1382       .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0,
1383       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]),
1384       .resetvalue = 0 },
1385     /* For non-long-descriptor page tables these are PRRR and NMRR;
1386      * regardless they still act as reads-as-written for QEMU.
1387      */
1388      /* MAIR0/1 are defined separately from their 64-bit counterpart which
1389       * allows them to assign the correct fieldoffset based on the endianness
1390       * handled in the field definitions.
1391       */
1392     { .name = "MAIR0", .state = ARM_CP_STATE_AA32,
1393       .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW,
1394       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair0_s),
1395                              offsetof(CPUARMState, cp15.mair0_ns) },
1396       .resetfn = arm_cp_reset_ignore },
1397     { .name = "MAIR1", .state = ARM_CP_STATE_AA32,
1398       .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW,
1399       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair1_s),
1400                              offsetof(CPUARMState, cp15.mair1_ns) },
1401       .resetfn = arm_cp_reset_ignore },
1402     { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
1403       .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,
1404       .type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read },
1405     /* 32 bit ITLB invalidates */
1406     { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0,
1407       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1408     { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
1409       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1410     { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2,
1411       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1412     /* 32 bit DTLB invalidates */
1413     { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0,
1414       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1415     { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
1416       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1417     { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2,
1418       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1419     /* 32 bit TLB invalidates */
1420     { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
1421       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1422     { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
1423       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1424     { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
1425       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1426     { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
1427       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write },
1428     REGINFO_SENTINEL
1429 };
1430 
1431 static const ARMCPRegInfo v7mp_cp_reginfo[] = {
1432     /* 32 bit TLB invalidates, Inner Shareable */
1433     { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
1434       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_is_write },
1435     { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
1436       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write },
1437     { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
1438       .type = ARM_CP_NO_RAW, .access = PL1_W,
1439       .writefn = tlbiasid_is_write },
1440     { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
1441       .type = ARM_CP_NO_RAW, .access = PL1_W,
1442       .writefn = tlbimvaa_is_write },
1443     REGINFO_SENTINEL
1444 };
1445 
1446 static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1447                         uint64_t value)
1448 {
1449     value &= 1;
1450     env->teecr = value;
1451 }
1452 
1453 static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri,
1454                                     bool isread)
1455 {
1456     if (arm_current_el(env) == 0 && (env->teecr & 1)) {
1457         return CP_ACCESS_TRAP;
1458     }
1459     return CP_ACCESS_OK;
1460 }
1461 
1462 static const ARMCPRegInfo t2ee_cp_reginfo[] = {
1463     { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
1464       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
1465       .resetvalue = 0,
1466       .writefn = teecr_write },
1467     { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
1468       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
1469       .accessfn = teehbr_access, .resetvalue = 0 },
1470     REGINFO_SENTINEL
1471 };
1472 
1473 static const ARMCPRegInfo v6k_cp_reginfo[] = {
1474     { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
1475       .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
1476       .access = PL0_RW,
1477       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 },
1478     { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
1479       .access = PL0_RW,
1480       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s),
1481                              offsetoflow32(CPUARMState, cp15.tpidrurw_ns) },
1482       .resetfn = arm_cp_reset_ignore },
1483     { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
1484       .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
1485       .access = PL0_R|PL1_W,
1486       .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]),
1487       .resetvalue = 0},
1488     { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
1489       .access = PL0_R|PL1_W,
1490       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s),
1491                              offsetoflow32(CPUARMState, cp15.tpidruro_ns) },
1492       .resetfn = arm_cp_reset_ignore },
1493     { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64,
1494       .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
1495       .access = PL1_RW,
1496       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 },
1497     { .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4,
1498       .access = PL1_RW,
1499       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s),
1500                              offsetoflow32(CPUARMState, cp15.tpidrprw_ns) },
1501       .resetvalue = 0 },
1502     REGINFO_SENTINEL
1503 };
1504 
1505 #ifndef CONFIG_USER_ONLY
1506 
1507 static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri,
1508                                        bool isread)
1509 {
1510     /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
1511      * Writable only at the highest implemented exception level.
1512      */
1513     int el = arm_current_el(env);
1514 
1515     switch (el) {
1516     case 0:
1517         if (!extract32(env->cp15.c14_cntkctl, 0, 2)) {
1518             return CP_ACCESS_TRAP;
1519         }
1520         break;
1521     case 1:
1522         if (!isread && ri->state == ARM_CP_STATE_AA32 &&
1523             arm_is_secure_below_el3(env)) {
1524             /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */
1525             return CP_ACCESS_TRAP_UNCATEGORIZED;
1526         }
1527         break;
1528     case 2:
1529     case 3:
1530         break;
1531     }
1532 
1533     if (!isread && el < arm_highest_el(env)) {
1534         return CP_ACCESS_TRAP_UNCATEGORIZED;
1535     }
1536 
1537     return CP_ACCESS_OK;
1538 }
1539 
1540 static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx,
1541                                         bool isread)
1542 {
1543     unsigned int cur_el = arm_current_el(env);
1544     bool secure = arm_is_secure(env);
1545 
1546     /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
1547     if (cur_el == 0 &&
1548         !extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
1549         return CP_ACCESS_TRAP;
1550     }
1551 
1552     if (arm_feature(env, ARM_FEATURE_EL2) &&
1553         timeridx == GTIMER_PHYS && !secure && cur_el < 2 &&
1554         !extract32(env->cp15.cnthctl_el2, 0, 1)) {
1555         return CP_ACCESS_TRAP_EL2;
1556     }
1557     return CP_ACCESS_OK;
1558 }
1559 
1560 static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx,
1561                                       bool isread)
1562 {
1563     unsigned int cur_el = arm_current_el(env);
1564     bool secure = arm_is_secure(env);
1565 
1566     /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
1567      * EL0[PV]TEN is zero.
1568      */
1569     if (cur_el == 0 &&
1570         !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
1571         return CP_ACCESS_TRAP;
1572     }
1573 
1574     if (arm_feature(env, ARM_FEATURE_EL2) &&
1575         timeridx == GTIMER_PHYS && !secure && cur_el < 2 &&
1576         !extract32(env->cp15.cnthctl_el2, 1, 1)) {
1577         return CP_ACCESS_TRAP_EL2;
1578     }
1579     return CP_ACCESS_OK;
1580 }
1581 
1582 static CPAccessResult gt_pct_access(CPUARMState *env,
1583                                     const ARMCPRegInfo *ri,
1584                                     bool isread)
1585 {
1586     return gt_counter_access(env, GTIMER_PHYS, isread);
1587 }
1588 
1589 static CPAccessResult gt_vct_access(CPUARMState *env,
1590                                     const ARMCPRegInfo *ri,
1591                                     bool isread)
1592 {
1593     return gt_counter_access(env, GTIMER_VIRT, isread);
1594 }
1595 
1596 static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri,
1597                                        bool isread)
1598 {
1599     return gt_timer_access(env, GTIMER_PHYS, isread);
1600 }
1601 
1602 static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri,
1603                                        bool isread)
1604 {
1605     return gt_timer_access(env, GTIMER_VIRT, isread);
1606 }
1607 
1608 static CPAccessResult gt_stimer_access(CPUARMState *env,
1609                                        const ARMCPRegInfo *ri,
1610                                        bool isread)
1611 {
1612     /* The AArch64 register view of the secure physical timer is
1613      * always accessible from EL3, and configurably accessible from
1614      * Secure EL1.
1615      */
1616     switch (arm_current_el(env)) {
1617     case 1:
1618         if (!arm_is_secure(env)) {
1619             return CP_ACCESS_TRAP;
1620         }
1621         if (!(env->cp15.scr_el3 & SCR_ST)) {
1622             return CP_ACCESS_TRAP_EL3;
1623         }
1624         return CP_ACCESS_OK;
1625     case 0:
1626     case 2:
1627         return CP_ACCESS_TRAP;
1628     case 3:
1629         return CP_ACCESS_OK;
1630     default:
1631         g_assert_not_reached();
1632     }
1633 }
1634 
1635 static uint64_t gt_get_countervalue(CPUARMState *env)
1636 {
1637     return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE;
1638 }
1639 
1640 static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
1641 {
1642     ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
1643 
1644     if (gt->ctl & 1) {
1645         /* Timer enabled: calculate and set current ISTATUS, irq, and
1646          * reset timer to when ISTATUS next has to change
1647          */
1648         uint64_t offset = timeridx == GTIMER_VIRT ?
1649                                       cpu->env.cp15.cntvoff_el2 : 0;
1650         uint64_t count = gt_get_countervalue(&cpu->env);
1651         /* Note that this must be unsigned 64 bit arithmetic: */
1652         int istatus = count - offset >= gt->cval;
1653         uint64_t nexttick;
1654         int irqstate;
1655 
1656         gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
1657 
1658         irqstate = (istatus && !(gt->ctl & 2));
1659         qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate);
1660 
1661         if (istatus) {
1662             /* Next transition is when count rolls back over to zero */
1663             nexttick = UINT64_MAX;
1664         } else {
1665             /* Next transition is when we hit cval */
1666             nexttick = gt->cval + offset;
1667         }
1668         /* Note that the desired next expiry time might be beyond the
1669          * signed-64-bit range of a QEMUTimer -- in this case we just
1670          * set the timer for as far in the future as possible. When the
1671          * timer expires we will reset the timer for any remaining period.
1672          */
1673         if (nexttick > INT64_MAX / GTIMER_SCALE) {
1674             nexttick = INT64_MAX / GTIMER_SCALE;
1675         }
1676         timer_mod(cpu->gt_timer[timeridx], nexttick);
1677         trace_arm_gt_recalc(timeridx, irqstate, nexttick);
1678     } else {
1679         /* Timer disabled: ISTATUS and timer output always clear */
1680         gt->ctl &= ~4;
1681         qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
1682         timer_del(cpu->gt_timer[timeridx]);
1683         trace_arm_gt_recalc_disabled(timeridx);
1684     }
1685 }
1686 
1687 static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri,
1688                            int timeridx)
1689 {
1690     ARMCPU *cpu = arm_env_get_cpu(env);
1691 
1692     timer_del(cpu->gt_timer[timeridx]);
1693 }
1694 
1695 static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
1696 {
1697     return gt_get_countervalue(env);
1698 }
1699 
1700 static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
1701 {
1702     return gt_get_countervalue(env) - env->cp15.cntvoff_el2;
1703 }
1704 
1705 static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1706                           int timeridx,
1707                           uint64_t value)
1708 {
1709     trace_arm_gt_cval_write(timeridx, value);
1710     env->cp15.c14_timer[timeridx].cval = value;
1711     gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1712 }
1713 
1714 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
1715                              int timeridx)
1716 {
1717     uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0;
1718 
1719     return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
1720                       (gt_get_countervalue(env) - offset));
1721 }
1722 
1723 static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1724                           int timeridx,
1725                           uint64_t value)
1726 {
1727     uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0;
1728 
1729     trace_arm_gt_tval_write(timeridx, value);
1730     env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset +
1731                                          sextract64(value, 0, 32);
1732     gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1733 }
1734 
1735 static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1736                          int timeridx,
1737                          uint64_t value)
1738 {
1739     ARMCPU *cpu = arm_env_get_cpu(env);
1740     uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
1741 
1742     trace_arm_gt_ctl_write(timeridx, value);
1743     env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value);
1744     if ((oldval ^ value) & 1) {
1745         /* Enable toggled */
1746         gt_recalc_timer(cpu, timeridx);
1747     } else if ((oldval ^ value) & 2) {
1748         /* IMASK toggled: don't need to recalculate,
1749          * just set the interrupt line based on ISTATUS
1750          */
1751         int irqstate = (oldval & 4) && !(value & 2);
1752 
1753         trace_arm_gt_imask_toggle(timeridx, irqstate);
1754         qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate);
1755     }
1756 }
1757 
1758 static void gt_phys_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1759 {
1760     gt_timer_reset(env, ri, GTIMER_PHYS);
1761 }
1762 
1763 static void gt_phys_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1764                                uint64_t value)
1765 {
1766     gt_cval_write(env, ri, GTIMER_PHYS, value);
1767 }
1768 
1769 static uint64_t gt_phys_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1770 {
1771     return gt_tval_read(env, ri, GTIMER_PHYS);
1772 }
1773 
1774 static void gt_phys_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1775                                uint64_t value)
1776 {
1777     gt_tval_write(env, ri, GTIMER_PHYS, value);
1778 }
1779 
1780 static void gt_phys_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1781                               uint64_t value)
1782 {
1783     gt_ctl_write(env, ri, GTIMER_PHYS, value);
1784 }
1785 
1786 static void gt_virt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1787 {
1788     gt_timer_reset(env, ri, GTIMER_VIRT);
1789 }
1790 
1791 static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1792                                uint64_t value)
1793 {
1794     gt_cval_write(env, ri, GTIMER_VIRT, value);
1795 }
1796 
1797 static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1798 {
1799     return gt_tval_read(env, ri, GTIMER_VIRT);
1800 }
1801 
1802 static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1803                                uint64_t value)
1804 {
1805     gt_tval_write(env, ri, GTIMER_VIRT, value);
1806 }
1807 
1808 static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1809                               uint64_t value)
1810 {
1811     gt_ctl_write(env, ri, GTIMER_VIRT, value);
1812 }
1813 
1814 static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri,
1815                               uint64_t value)
1816 {
1817     ARMCPU *cpu = arm_env_get_cpu(env);
1818 
1819     trace_arm_gt_cntvoff_write(value);
1820     raw_write(env, ri, value);
1821     gt_recalc_timer(cpu, GTIMER_VIRT);
1822 }
1823 
1824 static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1825 {
1826     gt_timer_reset(env, ri, GTIMER_HYP);
1827 }
1828 
1829 static void gt_hyp_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1830                               uint64_t value)
1831 {
1832     gt_cval_write(env, ri, GTIMER_HYP, value);
1833 }
1834 
1835 static uint64_t gt_hyp_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1836 {
1837     return gt_tval_read(env, ri, GTIMER_HYP);
1838 }
1839 
1840 static void gt_hyp_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1841                               uint64_t value)
1842 {
1843     gt_tval_write(env, ri, GTIMER_HYP, value);
1844 }
1845 
1846 static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1847                               uint64_t value)
1848 {
1849     gt_ctl_write(env, ri, GTIMER_HYP, value);
1850 }
1851 
1852 static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1853 {
1854     gt_timer_reset(env, ri, GTIMER_SEC);
1855 }
1856 
1857 static void gt_sec_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1858                               uint64_t value)
1859 {
1860     gt_cval_write(env, ri, GTIMER_SEC, value);
1861 }
1862 
1863 static uint64_t gt_sec_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1864 {
1865     return gt_tval_read(env, ri, GTIMER_SEC);
1866 }
1867 
1868 static void gt_sec_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1869                               uint64_t value)
1870 {
1871     gt_tval_write(env, ri, GTIMER_SEC, value);
1872 }
1873 
1874 static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1875                               uint64_t value)
1876 {
1877     gt_ctl_write(env, ri, GTIMER_SEC, value);
1878 }
1879 
1880 void arm_gt_ptimer_cb(void *opaque)
1881 {
1882     ARMCPU *cpu = opaque;
1883 
1884     gt_recalc_timer(cpu, GTIMER_PHYS);
1885 }
1886 
1887 void arm_gt_vtimer_cb(void *opaque)
1888 {
1889     ARMCPU *cpu = opaque;
1890 
1891     gt_recalc_timer(cpu, GTIMER_VIRT);
1892 }
1893 
1894 void arm_gt_htimer_cb(void *opaque)
1895 {
1896     ARMCPU *cpu = opaque;
1897 
1898     gt_recalc_timer(cpu, GTIMER_HYP);
1899 }
1900 
1901 void arm_gt_stimer_cb(void *opaque)
1902 {
1903     ARMCPU *cpu = opaque;
1904 
1905     gt_recalc_timer(cpu, GTIMER_SEC);
1906 }
1907 
1908 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1909     /* Note that CNTFRQ is purely reads-as-written for the benefit
1910      * of software; writing it doesn't actually change the timer frequency.
1911      * Our reset value matches the fixed frequency we implement the timer at.
1912      */
1913     { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0,
1914       .type = ARM_CP_ALIAS,
1915       .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1916       .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq),
1917     },
1918     { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64,
1919       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
1920       .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1921       .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
1922       .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE,
1923     },
1924     /* overall control: mostly access permissions */
1925     { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH,
1926       .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0,
1927       .access = PL1_RW,
1928       .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl),
1929       .resetvalue = 0,
1930     },
1931     /* per-timer control */
1932     { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
1933       .secure = ARM_CP_SECSTATE_NS,
1934       .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
1935       .accessfn = gt_ptimer_access,
1936       .fieldoffset = offsetoflow32(CPUARMState,
1937                                    cp15.c14_timer[GTIMER_PHYS].ctl),
1938       .writefn = gt_phys_ctl_write, .raw_writefn = raw_write,
1939     },
1940     { .name = "CNTP_CTL(S)",
1941       .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
1942       .secure = ARM_CP_SECSTATE_S,
1943       .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
1944       .accessfn = gt_ptimer_access,
1945       .fieldoffset = offsetoflow32(CPUARMState,
1946                                    cp15.c14_timer[GTIMER_SEC].ctl),
1947       .writefn = gt_sec_ctl_write, .raw_writefn = raw_write,
1948     },
1949     { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64,
1950       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1,
1951       .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1952       .accessfn = gt_ptimer_access,
1953       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
1954       .resetvalue = 0,
1955       .writefn = gt_phys_ctl_write, .raw_writefn = raw_write,
1956     },
1957     { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1,
1958       .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
1959       .accessfn = gt_vtimer_access,
1960       .fieldoffset = offsetoflow32(CPUARMState,
1961                                    cp15.c14_timer[GTIMER_VIRT].ctl),
1962       .writefn = gt_virt_ctl_write, .raw_writefn = raw_write,
1963     },
1964     { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64,
1965       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1,
1966       .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1967       .accessfn = gt_vtimer_access,
1968       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
1969       .resetvalue = 0,
1970       .writefn = gt_virt_ctl_write, .raw_writefn = raw_write,
1971     },
1972     /* TimerValue views: a 32 bit downcounting view of the underlying state */
1973     { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
1974       .secure = ARM_CP_SECSTATE_NS,
1975       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1976       .accessfn = gt_ptimer_access,
1977       .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write,
1978     },
1979     { .name = "CNTP_TVAL(S)",
1980       .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
1981       .secure = ARM_CP_SECSTATE_S,
1982       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1983       .accessfn = gt_ptimer_access,
1984       .readfn = gt_sec_tval_read, .writefn = gt_sec_tval_write,
1985     },
1986     { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1987       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0,
1988       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1989       .accessfn = gt_ptimer_access, .resetfn = gt_phys_timer_reset,
1990       .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write,
1991     },
1992     { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
1993       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1994       .accessfn = gt_vtimer_access,
1995       .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write,
1996     },
1997     { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1998       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0,
1999       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
2000       .accessfn = gt_vtimer_access, .resetfn = gt_virt_timer_reset,
2001       .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write,
2002     },
2003     /* The counter itself */
2004     { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0,
2005       .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
2006       .accessfn = gt_pct_access,
2007       .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
2008     },
2009     { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64,
2010       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1,
2011       .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
2012       .accessfn = gt_pct_access, .readfn = gt_cnt_read,
2013     },
2014     { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1,
2015       .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
2016       .accessfn = gt_vct_access,
2017       .readfn = gt_virt_cnt_read, .resetfn = arm_cp_reset_ignore,
2018     },
2019     { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
2020       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
2021       .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
2022       .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read,
2023     },
2024     /* Comparison value, indicating when the timer goes off */
2025     { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
2026       .secure = ARM_CP_SECSTATE_NS,
2027       .access = PL1_RW | PL0_R,
2028       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
2029       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
2030       .accessfn = gt_ptimer_access,
2031       .writefn = gt_phys_cval_write, .raw_writefn = raw_write,
2032     },
2033     { .name = "CNTP_CVAL(S)", .cp = 15, .crm = 14, .opc1 = 2,
2034       .secure = ARM_CP_SECSTATE_S,
2035       .access = PL1_RW | PL0_R,
2036       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
2037       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval),
2038       .accessfn = gt_ptimer_access,
2039       .writefn = gt_sec_cval_write, .raw_writefn = raw_write,
2040     },
2041     { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64,
2042       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2,
2043       .access = PL1_RW | PL0_R,
2044       .type = ARM_CP_IO,
2045       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
2046       .resetvalue = 0, .accessfn = gt_ptimer_access,
2047       .writefn = gt_phys_cval_write, .raw_writefn = raw_write,
2048     },
2049     { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
2050       .access = PL1_RW | PL0_R,
2051       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
2052       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
2053       .accessfn = gt_vtimer_access,
2054       .writefn = gt_virt_cval_write, .raw_writefn = raw_write,
2055     },
2056     { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64,
2057       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2,
2058       .access = PL1_RW | PL0_R,
2059       .type = ARM_CP_IO,
2060       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
2061       .resetvalue = 0, .accessfn = gt_vtimer_access,
2062       .writefn = gt_virt_cval_write, .raw_writefn = raw_write,
2063     },
2064     /* Secure timer -- this is actually restricted to only EL3
2065      * and configurably Secure-EL1 via the accessfn.
2066      */
2067     { .name = "CNTPS_TVAL_EL1", .state = ARM_CP_STATE_AA64,
2068       .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 0,
2069       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW,
2070       .accessfn = gt_stimer_access,
2071       .readfn = gt_sec_tval_read,
2072       .writefn = gt_sec_tval_write,
2073       .resetfn = gt_sec_timer_reset,
2074     },
2075     { .name = "CNTPS_CTL_EL1", .state = ARM_CP_STATE_AA64,
2076       .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 1,
2077       .type = ARM_CP_IO, .access = PL1_RW,
2078       .accessfn = gt_stimer_access,
2079       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].ctl),
2080       .resetvalue = 0,
2081       .writefn = gt_sec_ctl_write, .raw_writefn = raw_write,
2082     },
2083     { .name = "CNTPS_CVAL_EL1", .state = ARM_CP_STATE_AA64,
2084       .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 2,
2085       .type = ARM_CP_IO, .access = PL1_RW,
2086       .accessfn = gt_stimer_access,
2087       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval),
2088       .writefn = gt_sec_cval_write, .raw_writefn = raw_write,
2089     },
2090     REGINFO_SENTINEL
2091 };
2092 
2093 #else
2094 /* In user-mode none of the generic timer registers are accessible,
2095  * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
2096  * so instead just don't register any of them.
2097  */
2098 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
2099     REGINFO_SENTINEL
2100 };
2101 
2102 #endif
2103 
2104 static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
2105 {
2106     if (arm_feature(env, ARM_FEATURE_LPAE)) {
2107         raw_write(env, ri, value);
2108     } else if (arm_feature(env, ARM_FEATURE_V7)) {
2109         raw_write(env, ri, value & 0xfffff6ff);
2110     } else {
2111         raw_write(env, ri, value & 0xfffff1ff);
2112     }
2113 }
2114 
2115 #ifndef CONFIG_USER_ONLY
2116 /* get_phys_addr() isn't present for user-mode-only targets */
2117 
2118 static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,
2119                                  bool isread)
2120 {
2121     if (ri->opc2 & 4) {
2122         /* The ATS12NSO* operations must trap to EL3 if executed in
2123          * Secure EL1 (which can only happen if EL3 is AArch64).
2124          * They are simply UNDEF if executed from NS EL1.
2125          * They function normally from EL2 or EL3.
2126          */
2127         if (arm_current_el(env) == 1) {
2128             if (arm_is_secure_below_el3(env)) {
2129                 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3;
2130             }
2131             return CP_ACCESS_TRAP_UNCATEGORIZED;
2132         }
2133     }
2134     return CP_ACCESS_OK;
2135 }
2136 
2137 static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
2138                              MMUAccessType access_type, ARMMMUIdx mmu_idx)
2139 {
2140     hwaddr phys_addr;
2141     target_ulong page_size;
2142     int prot;
2143     uint32_t fsr;
2144     bool ret;
2145     uint64_t par64;
2146     MemTxAttrs attrs = {};
2147     ARMMMUFaultInfo fi = {};
2148 
2149     ret = get_phys_addr(env, value, access_type, mmu_idx,
2150                         &phys_addr, &attrs, &prot, &page_size, &fsr, &fi);
2151     if (extended_addresses_enabled(env)) {
2152         /* fsr is a DFSR/IFSR value for the long descriptor
2153          * translation table format, but with WnR always clear.
2154          * Convert it to a 64-bit PAR.
2155          */
2156         par64 = (1 << 11); /* LPAE bit always set */
2157         if (!ret) {
2158             par64 |= phys_addr & ~0xfffULL;
2159             if (!attrs.secure) {
2160                 par64 |= (1 << 9); /* NS */
2161             }
2162             /* We don't set the ATTR or SH fields in the PAR. */
2163         } else {
2164             par64 |= 1; /* F */
2165             par64 |= (fsr & 0x3f) << 1; /* FS */
2166             /* Note that S2WLK and FSTAGE are always zero, because we don't
2167              * implement virtualization and therefore there can't be a stage 2
2168              * fault.
2169              */
2170         }
2171     } else {
2172         /* fsr is a DFSR/IFSR value for the short descriptor
2173          * translation table format (with WnR always clear).
2174          * Convert it to a 32-bit PAR.
2175          */
2176         if (!ret) {
2177             /* We do not set any attribute bits in the PAR */
2178             if (page_size == (1 << 24)
2179                 && arm_feature(env, ARM_FEATURE_V7)) {
2180                 par64 = (phys_addr & 0xff000000) | (1 << 1);
2181             } else {
2182                 par64 = phys_addr & 0xfffff000;
2183             }
2184             if (!attrs.secure) {
2185                 par64 |= (1 << 9); /* NS */
2186             }
2187         } else {
2188             par64 = ((fsr & (1 << 10)) >> 5) | ((fsr & (1 << 12)) >> 6) |
2189                     ((fsr & 0xf) << 1) | 1;
2190         }
2191     }
2192     return par64;
2193 }
2194 
2195 static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
2196 {
2197     MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;
2198     uint64_t par64;
2199     ARMMMUIdx mmu_idx;
2200     int el = arm_current_el(env);
2201     bool secure = arm_is_secure_below_el3(env);
2202 
2203     switch (ri->opc2 & 6) {
2204     case 0:
2205         /* stage 1 current state PL1: ATS1CPR, ATS1CPW */
2206         switch (el) {
2207         case 3:
2208             mmu_idx = ARMMMUIdx_S1E3;
2209             break;
2210         case 2:
2211             mmu_idx = ARMMMUIdx_S1NSE1;
2212             break;
2213         case 1:
2214             mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1;
2215             break;
2216         default:
2217             g_assert_not_reached();
2218         }
2219         break;
2220     case 2:
2221         /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
2222         switch (el) {
2223         case 3:
2224             mmu_idx = ARMMMUIdx_S1SE0;
2225             break;
2226         case 2:
2227             mmu_idx = ARMMMUIdx_S1NSE0;
2228             break;
2229         case 1:
2230             mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;
2231             break;
2232         default:
2233             g_assert_not_reached();
2234         }
2235         break;
2236     case 4:
2237         /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
2238         mmu_idx = ARMMMUIdx_S12NSE1;
2239         break;
2240     case 6:
2241         /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
2242         mmu_idx = ARMMMUIdx_S12NSE0;
2243         break;
2244     default:
2245         g_assert_not_reached();
2246     }
2247 
2248     par64 = do_ats_write(env, value, access_type, mmu_idx);
2249 
2250     A32_BANKED_CURRENT_REG_SET(env, par, par64);
2251 }
2252 
2253 static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri,
2254                         uint64_t value)
2255 {
2256     MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;
2257     uint64_t par64;
2258 
2259     par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S2NS);
2260 
2261     A32_BANKED_CURRENT_REG_SET(env, par, par64);
2262 }
2263 
2264 static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri,
2265                                      bool isread)
2266 {
2267     if (arm_current_el(env) == 3 && !(env->cp15.scr_el3 & SCR_NS)) {
2268         return CP_ACCESS_TRAP;
2269     }
2270     return CP_ACCESS_OK;
2271 }
2272 
2273 static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
2274                         uint64_t value)
2275 {
2276     MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;
2277     ARMMMUIdx mmu_idx;
2278     int secure = arm_is_secure_below_el3(env);
2279 
2280     switch (ri->opc2 & 6) {
2281     case 0:
2282         switch (ri->opc1) {
2283         case 0: /* AT S1E1R, AT S1E1W */
2284             mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1;
2285             break;
2286         case 4: /* AT S1E2R, AT S1E2W */
2287             mmu_idx = ARMMMUIdx_S1E2;
2288             break;
2289         case 6: /* AT S1E3R, AT S1E3W */
2290             mmu_idx = ARMMMUIdx_S1E3;
2291             break;
2292         default:
2293             g_assert_not_reached();
2294         }
2295         break;
2296     case 2: /* AT S1E0R, AT S1E0W */
2297         mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;
2298         break;
2299     case 4: /* AT S12E1R, AT S12E1W */
2300         mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S12NSE1;
2301         break;
2302     case 6: /* AT S12E0R, AT S12E0W */
2303         mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S12NSE0;
2304         break;
2305     default:
2306         g_assert_not_reached();
2307     }
2308 
2309     env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx);
2310 }
2311 #endif
2312 
2313 static const ARMCPRegInfo vapa_cp_reginfo[] = {
2314     { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
2315       .access = PL1_RW, .resetvalue = 0,
2316       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s),
2317                              offsetoflow32(CPUARMState, cp15.par_ns) },
2318       .writefn = par_write },
2319 #ifndef CONFIG_USER_ONLY
2320     /* This underdecoding is safe because the reginfo is NO_RAW. */
2321     { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
2322       .access = PL1_W, .accessfn = ats_access,
2323       .writefn = ats_write, .type = ARM_CP_NO_RAW },
2324 #endif
2325     REGINFO_SENTINEL
2326 };
2327 
2328 /* Return basic MPU access permission bits.  */
2329 static uint32_t simple_mpu_ap_bits(uint32_t val)
2330 {
2331     uint32_t ret;
2332     uint32_t mask;
2333     int i;
2334     ret = 0;
2335     mask = 3;
2336     for (i = 0; i < 16; i += 2) {
2337         ret |= (val >> i) & mask;
2338         mask <<= 2;
2339     }
2340     return ret;
2341 }
2342 
2343 /* Pad basic MPU access permission bits to extended format.  */
2344 static uint32_t extended_mpu_ap_bits(uint32_t val)
2345 {
2346     uint32_t ret;
2347     uint32_t mask;
2348     int i;
2349     ret = 0;
2350     mask = 3;
2351     for (i = 0; i < 16; i += 2) {
2352         ret |= (val & mask) << i;
2353         mask <<= 2;
2354     }
2355     return ret;
2356 }
2357 
2358 static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
2359                                  uint64_t value)
2360 {
2361     env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value);
2362 }
2363 
2364 static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
2365 {
2366     return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap);
2367 }
2368 
2369 static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
2370                                  uint64_t value)
2371 {
2372     env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value);
2373 }
2374 
2375 static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
2376 {
2377     return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap);
2378 }
2379 
2380 static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri)
2381 {
2382     uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
2383 
2384     if (!u32p) {
2385         return 0;
2386     }
2387 
2388     u32p += env->pmsav7.rnr[M_REG_NS];
2389     return *u32p;
2390 }
2391 
2392 static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri,
2393                          uint64_t value)
2394 {
2395     ARMCPU *cpu = arm_env_get_cpu(env);
2396     uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
2397 
2398     if (!u32p) {
2399         return;
2400     }
2401 
2402     u32p += env->pmsav7.rnr[M_REG_NS];
2403     tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */
2404     *u32p = value;
2405 }
2406 
2407 static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2408                               uint64_t value)
2409 {
2410     ARMCPU *cpu = arm_env_get_cpu(env);
2411     uint32_t nrgs = cpu->pmsav7_dregion;
2412 
2413     if (value >= nrgs) {
2414         qemu_log_mask(LOG_GUEST_ERROR,
2415                       "PMSAv7 RGNR write >= # supported regions, %" PRIu32
2416                       " > %" PRIu32 "\n", (uint32_t)value, nrgs);
2417         return;
2418     }
2419 
2420     raw_write(env, ri, value);
2421 }
2422 
2423 static const ARMCPRegInfo pmsav7_cp_reginfo[] = {
2424     /* Reset for all these registers is handled in arm_cpu_reset(),
2425      * because the PMSAv7 is also used by M-profile CPUs, which do
2426      * not register cpregs but still need the state to be reset.
2427      */
2428     { .name = "DRBAR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 0,
2429       .access = PL1_RW, .type = ARM_CP_NO_RAW,
2430       .fieldoffset = offsetof(CPUARMState, pmsav7.drbar),
2431       .readfn = pmsav7_read, .writefn = pmsav7_write,
2432       .resetfn = arm_cp_reset_ignore },
2433     { .name = "DRSR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 2,
2434       .access = PL1_RW, .type = ARM_CP_NO_RAW,
2435       .fieldoffset = offsetof(CPUARMState, pmsav7.drsr),
2436       .readfn = pmsav7_read, .writefn = pmsav7_write,
2437       .resetfn = arm_cp_reset_ignore },
2438     { .name = "DRACR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 4,
2439       .access = PL1_RW, .type = ARM_CP_NO_RAW,
2440       .fieldoffset = offsetof(CPUARMState, pmsav7.dracr),
2441       .readfn = pmsav7_read, .writefn = pmsav7_write,
2442       .resetfn = arm_cp_reset_ignore },
2443     { .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0,
2444       .access = PL1_RW,
2445       .fieldoffset = offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]),
2446       .writefn = pmsav7_rgnr_write,
2447       .resetfn = arm_cp_reset_ignore },
2448     REGINFO_SENTINEL
2449 };
2450 
2451 static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
2452     { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
2453       .access = PL1_RW, .type = ARM_CP_ALIAS,
2454       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
2455       .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
2456     { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
2457       .access = PL1_RW, .type = ARM_CP_ALIAS,
2458       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
2459       .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
2460     { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
2461       .access = PL1_RW,
2462       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
2463       .resetvalue = 0, },
2464     { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
2465       .access = PL1_RW,
2466       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
2467       .resetvalue = 0, },
2468     { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
2469       .access = PL1_RW,
2470       .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
2471     { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
2472       .access = PL1_RW,
2473       .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
2474     /* Protection region base and size registers */
2475     { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0,
2476       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2477       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) },
2478     { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0,
2479       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2480       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) },
2481     { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0,
2482       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2483       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) },
2484     { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0,
2485       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2486       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) },
2487     { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0,
2488       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2489       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) },
2490     { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0,
2491       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2492       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) },
2493     { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0,
2494       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2495       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) },
2496     { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0,
2497       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2498       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) },
2499     REGINFO_SENTINEL
2500 };
2501 
2502 static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
2503                                  uint64_t value)
2504 {
2505     TCR *tcr = raw_ptr(env, ri);
2506     int maskshift = extract32(value, 0, 3);
2507 
2508     if (!arm_feature(env, ARM_FEATURE_V8)) {
2509         if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) {
2510             /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
2511              * using Long-desciptor translation table format */
2512             value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
2513         } else if (arm_feature(env, ARM_FEATURE_EL3)) {
2514             /* In an implementation that includes the Security Extensions
2515              * TTBCR has additional fields PD0 [4] and PD1 [5] for
2516              * Short-descriptor translation table format.
2517              */
2518             value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N;
2519         } else {
2520             value &= TTBCR_N;
2521         }
2522     }
2523 
2524     /* Update the masks corresponding to the TCR bank being written
2525      * Note that we always calculate mask and base_mask, but
2526      * they are only used for short-descriptor tables (ie if EAE is 0);
2527      * for long-descriptor tables the TCR fields are used differently
2528      * and the mask and base_mask values are meaningless.
2529      */
2530     tcr->raw_tcr = value;
2531     tcr->mask = ~(((uint32_t)0xffffffffu) >> maskshift);
2532     tcr->base_mask = ~((uint32_t)0x3fffu >> maskshift);
2533 }
2534 
2535 static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2536                              uint64_t value)
2537 {
2538     ARMCPU *cpu = arm_env_get_cpu(env);
2539 
2540     if (arm_feature(env, ARM_FEATURE_LPAE)) {
2541         /* With LPAE the TTBCR could result in a change of ASID
2542          * via the TTBCR.A1 bit, so do a TLB flush.
2543          */
2544         tlb_flush(CPU(cpu));
2545     }
2546     vmsa_ttbcr_raw_write(env, ri, value);
2547 }
2548 
2549 static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
2550 {
2551     TCR *tcr = raw_ptr(env, ri);
2552 
2553     /* Reset both the TCR as well as the masks corresponding to the bank of
2554      * the TCR being reset.
2555      */
2556     tcr->raw_tcr = 0;
2557     tcr->mask = 0;
2558     tcr->base_mask = 0xffffc000u;
2559 }
2560 
2561 static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2562                                uint64_t value)
2563 {
2564     ARMCPU *cpu = arm_env_get_cpu(env);
2565     TCR *tcr = raw_ptr(env, ri);
2566 
2567     /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
2568     tlb_flush(CPU(cpu));
2569     tcr->raw_tcr = value;
2570 }
2571 
2572 static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2573                             uint64_t value)
2574 {
2575     /* 64 bit accesses to the TTBRs can change the ASID and so we
2576      * must flush the TLB.
2577      */
2578     if (cpreg_field_is_64bit(ri)) {
2579         ARMCPU *cpu = arm_env_get_cpu(env);
2580 
2581         tlb_flush(CPU(cpu));
2582     }
2583     raw_write(env, ri, value);
2584 }
2585 
2586 static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2587                         uint64_t value)
2588 {
2589     ARMCPU *cpu = arm_env_get_cpu(env);
2590     CPUState *cs = CPU(cpu);
2591 
2592     /* Accesses to VTTBR may change the VMID so we must flush the TLB.  */
2593     if (raw_read(env, ri) != value) {
2594         tlb_flush_by_mmuidx(cs,
2595                             ARMMMUIdxBit_S12NSE1 |
2596                             ARMMMUIdxBit_S12NSE0 |
2597                             ARMMMUIdxBit_S2NS);
2598         raw_write(env, ri, value);
2599     }
2600 }
2601 
2602 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {
2603     { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
2604       .access = PL1_RW, .type = ARM_CP_ALIAS,
2605       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s),
2606                              offsetoflow32(CPUARMState, cp15.dfsr_ns) }, },
2607     { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
2608       .access = PL1_RW, .resetvalue = 0,
2609       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s),
2610                              offsetoflow32(CPUARMState, cp15.ifsr_ns) } },
2611     { .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0,
2612       .access = PL1_RW, .resetvalue = 0,
2613       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s),
2614                              offsetof(CPUARMState, cp15.dfar_ns) } },
2615     { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64,
2616       .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
2617       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
2618       .resetvalue = 0, },
2619     REGINFO_SENTINEL
2620 };
2621 
2622 static const ARMCPRegInfo vmsa_cp_reginfo[] = {
2623     { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64,
2624       .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0,
2625       .access = PL1_RW,
2626       .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, },
2627     { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
2628       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0,
2629       .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
2630       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
2631                              offsetof(CPUARMState, cp15.ttbr0_ns) } },
2632     { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
2633       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1,
2634       .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
2635       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
2636                              offsetof(CPUARMState, cp15.ttbr1_ns) } },
2637     { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
2638       .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
2639       .access = PL1_RW, .writefn = vmsa_tcr_el1_write,
2640       .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
2641       .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) },
2642     { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
2643       .access = PL1_RW, .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write,
2644       .raw_writefn = vmsa_ttbcr_raw_write,
2645       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]),
2646                              offsetoflow32(CPUARMState, cp15.tcr_el[1])} },
2647     REGINFO_SENTINEL
2648 };
2649 
2650 static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
2651                                 uint64_t value)
2652 {
2653     env->cp15.c15_ticonfig = value & 0xe7;
2654     /* The OS_TYPE bit in this register changes the reported CPUID! */
2655     env->cp15.c0_cpuid = (value & (1 << 5)) ?
2656         ARM_CPUID_TI915T : ARM_CPUID_TI925T;
2657 }
2658 
2659 static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
2660                                 uint64_t value)
2661 {
2662     env->cp15.c15_threadid = value & 0xffff;
2663 }
2664 
2665 static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
2666                            uint64_t value)
2667 {
2668     /* Wait-for-interrupt (deprecated) */
2669     cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT);
2670 }
2671 
2672 static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
2673                                   uint64_t value)
2674 {
2675     /* On OMAP there are registers indicating the max/min index of dcache lines
2676      * containing a dirty line; cache flush operations have to reset these.
2677      */
2678     env->cp15.c15_i_max = 0x000;
2679     env->cp15.c15_i_min = 0xff0;
2680 }
2681 
2682 static const ARMCPRegInfo omap_cp_reginfo[] = {
2683     { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
2684       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
2685       .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),
2686       .resetvalue = 0, },
2687     { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
2688       .access = PL1_RW, .type = ARM_CP_NOP },
2689     { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
2690       .access = PL1_RW,
2691       .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
2692       .writefn = omap_ticonfig_write },
2693     { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
2694       .access = PL1_RW,
2695       .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
2696     { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
2697       .access = PL1_RW, .resetvalue = 0xff0,
2698       .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
2699     { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
2700       .access = PL1_RW,
2701       .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
2702       .writefn = omap_threadid_write },
2703     { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
2704       .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
2705       .type = ARM_CP_NO_RAW,
2706       .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
2707     /* TODO: Peripheral port remap register:
2708      * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
2709      * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
2710      * when MMU is off.
2711      */
2712     { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
2713       .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
2714       .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW,
2715       .writefn = omap_cachemaint_write },
2716     { .name = "C9", .cp = 15, .crn = 9,
2717       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
2718       .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
2719     REGINFO_SENTINEL
2720 };
2721 
2722 static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
2723                               uint64_t value)
2724 {
2725     env->cp15.c15_cpar = value & 0x3fff;
2726 }
2727 
2728 static const ARMCPRegInfo xscale_cp_reginfo[] = {
2729     { .name = "XSCALE_CPAR",
2730       .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
2731       .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
2732       .writefn = xscale_cpar_write, },
2733     { .name = "XSCALE_AUXCR",
2734       .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
2735       .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
2736       .resetvalue = 0, },
2737     /* XScale specific cache-lockdown: since we have no cache we NOP these
2738      * and hope the guest does not really rely on cache behaviour.
2739      */
2740     { .name = "XSCALE_LOCK_ICACHE_LINE",
2741       .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
2742       .access = PL1_W, .type = ARM_CP_NOP },
2743     { .name = "XSCALE_UNLOCK_ICACHE",
2744       .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
2745       .access = PL1_W, .type = ARM_CP_NOP },
2746     { .name = "XSCALE_DCACHE_LOCK",
2747       .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0,
2748       .access = PL1_RW, .type = ARM_CP_NOP },
2749     { .name = "XSCALE_UNLOCK_DCACHE",
2750       .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1,
2751       .access = PL1_W, .type = ARM_CP_NOP },
2752     REGINFO_SENTINEL
2753 };
2754 
2755 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
2756     /* RAZ/WI the whole crn=15 space, when we don't have a more specific
2757      * implementation of this implementation-defined space.
2758      * Ideally this should eventually disappear in favour of actually
2759      * implementing the correct behaviour for all cores.
2760      */
2761     { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
2762       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
2763       .access = PL1_RW,
2764       .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE,
2765       .resetvalue = 0 },
2766     REGINFO_SENTINEL
2767 };
2768 
2769 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
2770     /* Cache status: RAZ because we have no cache so it's always clean */
2771     { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
2772       .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2773       .resetvalue = 0 },
2774     REGINFO_SENTINEL
2775 };
2776 
2777 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
2778     /* We never have a a block transfer operation in progress */
2779     { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
2780       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2781       .resetvalue = 0 },
2782     /* The cache ops themselves: these all NOP for QEMU */
2783     { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
2784       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2785     { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
2786       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2787     { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
2788       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2789     { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
2790       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2791     { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
2792       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2793     { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
2794       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2795     REGINFO_SENTINEL
2796 };
2797 
2798 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
2799     /* The cache test-and-clean instructions always return (1 << 30)
2800      * to indicate that there are no dirty cache lines.
2801      */
2802     { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
2803       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2804       .resetvalue = (1 << 30) },
2805     { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
2806       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2807       .resetvalue = (1 << 30) },
2808     REGINFO_SENTINEL
2809 };
2810 
2811 static const ARMCPRegInfo strongarm_cp_reginfo[] = {
2812     /* Ignore ReadBuffer accesses */
2813     { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
2814       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
2815       .access = PL1_RW, .resetvalue = 0,
2816       .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW },
2817     REGINFO_SENTINEL
2818 };
2819 
2820 static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2821 {
2822     ARMCPU *cpu = arm_env_get_cpu(env);
2823     unsigned int cur_el = arm_current_el(env);
2824     bool secure = arm_is_secure(env);
2825 
2826     if (arm_feature(&cpu->env, ARM_FEATURE_EL2) && !secure && cur_el == 1) {
2827         return env->cp15.vpidr_el2;
2828     }
2829     return raw_read(env, ri);
2830 }
2831 
2832 static uint64_t mpidr_read_val(CPUARMState *env)
2833 {
2834     ARMCPU *cpu = ARM_CPU(arm_env_get_cpu(env));
2835     uint64_t mpidr = cpu->mp_affinity;
2836 
2837     if (arm_feature(env, ARM_FEATURE_V7MP)) {
2838         mpidr |= (1U << 31);
2839         /* Cores which are uniprocessor (non-coherent)
2840          * but still implement the MP extensions set
2841          * bit 30. (For instance, Cortex-R5).
2842          */
2843         if (cpu->mp_is_up) {
2844             mpidr |= (1u << 30);
2845         }
2846     }
2847     return mpidr;
2848 }
2849 
2850 static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2851 {
2852     unsigned int cur_el = arm_current_el(env);
2853     bool secure = arm_is_secure(env);
2854 
2855     if (arm_feature(env, ARM_FEATURE_EL2) && !secure && cur_el == 1) {
2856         return env->cp15.vmpidr_el2;
2857     }
2858     return mpidr_read_val(env);
2859 }
2860 
2861 static const ARMCPRegInfo mpidr_cp_reginfo[] = {
2862     { .name = "MPIDR", .state = ARM_CP_STATE_BOTH,
2863       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
2864       .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW },
2865     REGINFO_SENTINEL
2866 };
2867 
2868 static const ARMCPRegInfo lpae_cp_reginfo[] = {
2869     /* NOP AMAIR0/1 */
2870     { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
2871       .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
2872       .access = PL1_RW, .type = ARM_CP_CONST,
2873       .resetvalue = 0 },
2874     /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
2875     { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
2876       .access = PL1_RW, .type = ARM_CP_CONST,
2877       .resetvalue = 0 },
2878     { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
2879       .access = PL1_RW, .type = ARM_CP_64BIT, .resetvalue = 0,
2880       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.par_s),
2881                              offsetof(CPUARMState, cp15.par_ns)} },
2882     { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
2883       .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
2884       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
2885                              offsetof(CPUARMState, cp15.ttbr0_ns) },
2886       .writefn = vmsa_ttbr_write, },
2887     { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
2888       .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
2889       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
2890                              offsetof(CPUARMState, cp15.ttbr1_ns) },
2891       .writefn = vmsa_ttbr_write, },
2892     REGINFO_SENTINEL
2893 };
2894 
2895 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2896 {
2897     return vfp_get_fpcr(env);
2898 }
2899 
2900 static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2901                             uint64_t value)
2902 {
2903     vfp_set_fpcr(env, value);
2904 }
2905 
2906 static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2907 {
2908     return vfp_get_fpsr(env);
2909 }
2910 
2911 static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2912                             uint64_t value)
2913 {
2914     vfp_set_fpsr(env, value);
2915 }
2916 
2917 static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri,
2918                                        bool isread)
2919 {
2920     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) {
2921         return CP_ACCESS_TRAP;
2922     }
2923     return CP_ACCESS_OK;
2924 }
2925 
2926 static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri,
2927                             uint64_t value)
2928 {
2929     env->daif = value & PSTATE_DAIF;
2930 }
2931 
2932 static CPAccessResult aa64_cacheop_access(CPUARMState *env,
2933                                           const ARMCPRegInfo *ri,
2934                                           bool isread)
2935 {
2936     /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
2937      * SCTLR_EL1.UCI is set.
2938      */
2939     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCI)) {
2940         return CP_ACCESS_TRAP;
2941     }
2942     return CP_ACCESS_OK;
2943 }
2944 
2945 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
2946  * Page D4-1736 (DDI0487A.b)
2947  */
2948 
2949 static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2950                                     uint64_t value)
2951 {
2952     CPUState *cs = ENV_GET_CPU(env);
2953 
2954     if (arm_is_secure_below_el3(env)) {
2955         tlb_flush_by_mmuidx(cs,
2956                             ARMMMUIdxBit_S1SE1 |
2957                             ARMMMUIdxBit_S1SE0);
2958     } else {
2959         tlb_flush_by_mmuidx(cs,
2960                             ARMMMUIdxBit_S12NSE1 |
2961                             ARMMMUIdxBit_S12NSE0);
2962     }
2963 }
2964 
2965 static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2966                                       uint64_t value)
2967 {
2968     CPUState *cs = ENV_GET_CPU(env);
2969     bool sec = arm_is_secure_below_el3(env);
2970 
2971     if (sec) {
2972         tlb_flush_by_mmuidx_all_cpus_synced(cs,
2973                                             ARMMMUIdxBit_S1SE1 |
2974                                             ARMMMUIdxBit_S1SE0);
2975     } else {
2976         tlb_flush_by_mmuidx_all_cpus_synced(cs,
2977                                             ARMMMUIdxBit_S12NSE1 |
2978                                             ARMMMUIdxBit_S12NSE0);
2979     }
2980 }
2981 
2982 static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2983                                   uint64_t value)
2984 {
2985     /* Note that the 'ALL' scope must invalidate both stage 1 and
2986      * stage 2 translations, whereas most other scopes only invalidate
2987      * stage 1 translations.
2988      */
2989     ARMCPU *cpu = arm_env_get_cpu(env);
2990     CPUState *cs = CPU(cpu);
2991 
2992     if (arm_is_secure_below_el3(env)) {
2993         tlb_flush_by_mmuidx(cs,
2994                             ARMMMUIdxBit_S1SE1 |
2995                             ARMMMUIdxBit_S1SE0);
2996     } else {
2997         if (arm_feature(env, ARM_FEATURE_EL2)) {
2998             tlb_flush_by_mmuidx(cs,
2999                                 ARMMMUIdxBit_S12NSE1 |
3000                                 ARMMMUIdxBit_S12NSE0 |
3001                                 ARMMMUIdxBit_S2NS);
3002         } else {
3003             tlb_flush_by_mmuidx(cs,
3004                                 ARMMMUIdxBit_S12NSE1 |
3005                                 ARMMMUIdxBit_S12NSE0);
3006         }
3007     }
3008 }
3009 
3010 static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri,
3011                                   uint64_t value)
3012 {
3013     ARMCPU *cpu = arm_env_get_cpu(env);
3014     CPUState *cs = CPU(cpu);
3015 
3016     tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2);
3017 }
3018 
3019 static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
3020                                   uint64_t value)
3021 {
3022     ARMCPU *cpu = arm_env_get_cpu(env);
3023     CPUState *cs = CPU(cpu);
3024 
3025     tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E3);
3026 }
3027 
3028 static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
3029                                     uint64_t value)
3030 {
3031     /* Note that the 'ALL' scope must invalidate both stage 1 and
3032      * stage 2 translations, whereas most other scopes only invalidate
3033      * stage 1 translations.
3034      */
3035     CPUState *cs = ENV_GET_CPU(env);
3036     bool sec = arm_is_secure_below_el3(env);
3037     bool has_el2 = arm_feature(env, ARM_FEATURE_EL2);
3038 
3039     if (sec) {
3040         tlb_flush_by_mmuidx_all_cpus_synced(cs,
3041                                             ARMMMUIdxBit_S1SE1 |
3042                                             ARMMMUIdxBit_S1SE0);
3043     } else if (has_el2) {
3044         tlb_flush_by_mmuidx_all_cpus_synced(cs,
3045                                             ARMMMUIdxBit_S12NSE1 |
3046                                             ARMMMUIdxBit_S12NSE0 |
3047                                             ARMMMUIdxBit_S2NS);
3048     } else {
3049           tlb_flush_by_mmuidx_all_cpus_synced(cs,
3050                                               ARMMMUIdxBit_S12NSE1 |
3051                                               ARMMMUIdxBit_S12NSE0);
3052     }
3053 }
3054 
3055 static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
3056                                     uint64_t value)
3057 {
3058     CPUState *cs = ENV_GET_CPU(env);
3059 
3060     tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2);
3061 }
3062 
3063 static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
3064                                     uint64_t value)
3065 {
3066     CPUState *cs = ENV_GET_CPU(env);
3067 
3068     tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E3);
3069 }
3070 
3071 static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
3072                                  uint64_t value)
3073 {
3074     /* Invalidate by VA, EL1&0 (AArch64 version).
3075      * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
3076      * since we don't support flush-for-specific-ASID-only or
3077      * flush-last-level-only.
3078      */
3079     ARMCPU *cpu = arm_env_get_cpu(env);
3080     CPUState *cs = CPU(cpu);
3081     uint64_t pageaddr = sextract64(value << 12, 0, 56);
3082 
3083     if (arm_is_secure_below_el3(env)) {
3084         tlb_flush_page_by_mmuidx(cs, pageaddr,
3085                                  ARMMMUIdxBit_S1SE1 |
3086                                  ARMMMUIdxBit_S1SE0);
3087     } else {
3088         tlb_flush_page_by_mmuidx(cs, pageaddr,
3089                                  ARMMMUIdxBit_S12NSE1 |
3090                                  ARMMMUIdxBit_S12NSE0);
3091     }
3092 }
3093 
3094 static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
3095                                  uint64_t value)
3096 {
3097     /* Invalidate by VA, EL2
3098      * Currently handles both VAE2 and VALE2, since we don't support
3099      * flush-last-level-only.
3100      */
3101     ARMCPU *cpu = arm_env_get_cpu(env);
3102     CPUState *cs = CPU(cpu);
3103     uint64_t pageaddr = sextract64(value << 12, 0, 56);
3104 
3105     tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E2);
3106 }
3107 
3108 static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
3109                                  uint64_t value)
3110 {
3111     /* Invalidate by VA, EL3
3112      * Currently handles both VAE3 and VALE3, since we don't support
3113      * flush-last-level-only.
3114      */
3115     ARMCPU *cpu = arm_env_get_cpu(env);
3116     CPUState *cs = CPU(cpu);
3117     uint64_t pageaddr = sextract64(value << 12, 0, 56);
3118 
3119     tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E3);
3120 }
3121 
3122 static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
3123                                    uint64_t value)
3124 {
3125     ARMCPU *cpu = arm_env_get_cpu(env);
3126     CPUState *cs = CPU(cpu);
3127     bool sec = arm_is_secure_below_el3(env);
3128     uint64_t pageaddr = sextract64(value << 12, 0, 56);
3129 
3130     if (sec) {
3131         tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
3132                                                  ARMMMUIdxBit_S1SE1 |
3133                                                  ARMMMUIdxBit_S1SE0);
3134     } else {
3135         tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
3136                                                  ARMMMUIdxBit_S12NSE1 |
3137                                                  ARMMMUIdxBit_S12NSE0);
3138     }
3139 }
3140 
3141 static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
3142                                    uint64_t value)
3143 {
3144     CPUState *cs = ENV_GET_CPU(env);
3145     uint64_t pageaddr = sextract64(value << 12, 0, 56);
3146 
3147     tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
3148                                              ARMMMUIdxBit_S1E2);
3149 }
3150 
3151 static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
3152                                    uint64_t value)
3153 {
3154     CPUState *cs = ENV_GET_CPU(env);
3155     uint64_t pageaddr = sextract64(value << 12, 0, 56);
3156 
3157     tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
3158                                              ARMMMUIdxBit_S1E3);
3159 }
3160 
3161 static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri,
3162                                     uint64_t value)
3163 {
3164     /* Invalidate by IPA. This has to invalidate any structures that
3165      * contain only stage 2 translation information, but does not need
3166      * to apply to structures that contain combined stage 1 and stage 2
3167      * translation information.
3168      * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
3169      */
3170     ARMCPU *cpu = arm_env_get_cpu(env);
3171     CPUState *cs = CPU(cpu);
3172     uint64_t pageaddr;
3173 
3174     if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
3175         return;
3176     }
3177 
3178     pageaddr = sextract64(value << 12, 0, 48);
3179 
3180     tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S2NS);
3181 }
3182 
3183 static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
3184                                       uint64_t value)
3185 {
3186     CPUState *cs = ENV_GET_CPU(env);
3187     uint64_t pageaddr;
3188 
3189     if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
3190         return;
3191     }
3192 
3193     pageaddr = sextract64(value << 12, 0, 48);
3194 
3195     tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
3196                                              ARMMMUIdxBit_S2NS);
3197 }
3198 
3199 static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri,
3200                                       bool isread)
3201 {
3202     /* We don't implement EL2, so the only control on DC ZVA is the
3203      * bit in the SCTLR which can prohibit access for EL0.
3204      */
3205     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_DZE)) {
3206         return CP_ACCESS_TRAP;
3207     }
3208     return CP_ACCESS_OK;
3209 }
3210 
3211 static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri)
3212 {
3213     ARMCPU *cpu = arm_env_get_cpu(env);
3214     int dzp_bit = 1 << 4;
3215 
3216     /* DZP indicates whether DC ZVA access is allowed */
3217     if (aa64_zva_access(env, NULL, false) == CP_ACCESS_OK) {
3218         dzp_bit = 0;
3219     }
3220     return cpu->dcz_blocksize | dzp_bit;
3221 }
3222 
3223 static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri,
3224                                     bool isread)
3225 {
3226     if (!(env->pstate & PSTATE_SP)) {
3227         /* Access to SP_EL0 is undefined if it's being used as
3228          * the stack pointer.
3229          */
3230         return CP_ACCESS_TRAP_UNCATEGORIZED;
3231     }
3232     return CP_ACCESS_OK;
3233 }
3234 
3235 static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri)
3236 {
3237     return env->pstate & PSTATE_SP;
3238 }
3239 
3240 static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
3241 {
3242     update_spsel(env, val);
3243 }
3244 
3245 static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3246                         uint64_t value)
3247 {
3248     ARMCPU *cpu = arm_env_get_cpu(env);
3249 
3250     if (raw_read(env, ri) == value) {
3251         /* Skip the TLB flush if nothing actually changed; Linux likes
3252          * to do a lot of pointless SCTLR writes.
3253          */
3254         return;
3255     }
3256 
3257     if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) {
3258         /* M bit is RAZ/WI for PMSA with no MPU implemented */
3259         value &= ~SCTLR_M;
3260     }
3261 
3262     raw_write(env, ri, value);
3263     /* ??? Lots of these bits are not implemented.  */
3264     /* This may enable/disable the MMU, so do a TLB flush.  */
3265     tlb_flush(CPU(cpu));
3266 }
3267 
3268 static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri,
3269                                      bool isread)
3270 {
3271     if ((env->cp15.cptr_el[2] & CPTR_TFP) && arm_current_el(env) == 2) {
3272         return CP_ACCESS_TRAP_FP_EL2;
3273     }
3274     if (env->cp15.cptr_el[3] & CPTR_TFP) {
3275         return CP_ACCESS_TRAP_FP_EL3;
3276     }
3277     return CP_ACCESS_OK;
3278 }
3279 
3280 static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3281                        uint64_t value)
3282 {
3283     env->cp15.mdcr_el3 = value & SDCR_VALID_MASK;
3284 }
3285 
3286 static const ARMCPRegInfo v8_cp_reginfo[] = {
3287     /* Minimal set of EL0-visible registers. This will need to be expanded
3288      * significantly for system emulation of AArch64 CPUs.
3289      */
3290     { .name = "NZCV", .state = ARM_CP_STATE_AA64,
3291       .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
3292       .access = PL0_RW, .type = ARM_CP_NZCV },
3293     { .name = "DAIF", .state = ARM_CP_STATE_AA64,
3294       .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2,
3295       .type = ARM_CP_NO_RAW,
3296       .access = PL0_RW, .accessfn = aa64_daif_access,
3297       .fieldoffset = offsetof(CPUARMState, daif),
3298       .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore },
3299     { .name = "FPCR", .state = ARM_CP_STATE_AA64,
3300       .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
3301       .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
3302     { .name = "FPSR", .state = ARM_CP_STATE_AA64,
3303       .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,
3304       .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write },
3305     { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
3306       .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
3307       .access = PL0_R, .type = ARM_CP_NO_RAW,
3308       .readfn = aa64_dczid_read },
3309     { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64,
3310       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1,
3311       .access = PL0_W, .type = ARM_CP_DC_ZVA,
3312 #ifndef CONFIG_USER_ONLY
3313       /* Avoid overhead of an access check that always passes in user-mode */
3314       .accessfn = aa64_zva_access,
3315 #endif
3316     },
3317     { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
3318       .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2,
3319       .access = PL1_R, .type = ARM_CP_CURRENTEL },
3320     /* Cache ops: all NOPs since we don't emulate caches */
3321     { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
3322       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
3323       .access = PL1_W, .type = ARM_CP_NOP },
3324     { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
3325       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
3326       .access = PL1_W, .type = ARM_CP_NOP },
3327     { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
3328       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
3329       .access = PL0_W, .type = ARM_CP_NOP,
3330       .accessfn = aa64_cacheop_access },
3331     { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
3332       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
3333       .access = PL1_W, .type = ARM_CP_NOP },
3334     { .name = "DC_ISW", .state = ARM_CP_STATE_AA64,
3335       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
3336       .access = PL1_W, .type = ARM_CP_NOP },
3337     { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
3338       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
3339       .access = PL0_W, .type = ARM_CP_NOP,
3340       .accessfn = aa64_cacheop_access },
3341     { .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
3342       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
3343       .access = PL1_W, .type = ARM_CP_NOP },
3344     { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
3345       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
3346       .access = PL0_W, .type = ARM_CP_NOP,
3347       .accessfn = aa64_cacheop_access },
3348     { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
3349       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
3350       .access = PL0_W, .type = ARM_CP_NOP,
3351       .accessfn = aa64_cacheop_access },
3352     { .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
3353       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
3354       .access = PL1_W, .type = ARM_CP_NOP },
3355     /* TLBI operations */
3356     { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
3357       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
3358       .access = PL1_W, .type = ARM_CP_NO_RAW,
3359       .writefn = tlbi_aa64_vmalle1is_write },
3360     { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
3361       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
3362       .access = PL1_W, .type = ARM_CP_NO_RAW,
3363       .writefn = tlbi_aa64_vae1is_write },
3364     { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
3365       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
3366       .access = PL1_W, .type = ARM_CP_NO_RAW,
3367       .writefn = tlbi_aa64_vmalle1is_write },
3368     { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
3369       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
3370       .access = PL1_W, .type = ARM_CP_NO_RAW,
3371       .writefn = tlbi_aa64_vae1is_write },
3372     { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
3373       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
3374       .access = PL1_W, .type = ARM_CP_NO_RAW,
3375       .writefn = tlbi_aa64_vae1is_write },
3376     { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
3377       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
3378       .access = PL1_W, .type = ARM_CP_NO_RAW,
3379       .writefn = tlbi_aa64_vae1is_write },
3380     { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
3381       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
3382       .access = PL1_W, .type = ARM_CP_NO_RAW,
3383       .writefn = tlbi_aa64_vmalle1_write },
3384     { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
3385       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
3386       .access = PL1_W, .type = ARM_CP_NO_RAW,
3387       .writefn = tlbi_aa64_vae1_write },
3388     { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
3389       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
3390       .access = PL1_W, .type = ARM_CP_NO_RAW,
3391       .writefn = tlbi_aa64_vmalle1_write },
3392     { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
3393       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
3394       .access = PL1_W, .type = ARM_CP_NO_RAW,
3395       .writefn = tlbi_aa64_vae1_write },
3396     { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
3397       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
3398       .access = PL1_W, .type = ARM_CP_NO_RAW,
3399       .writefn = tlbi_aa64_vae1_write },
3400     { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
3401       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
3402       .access = PL1_W, .type = ARM_CP_NO_RAW,
3403       .writefn = tlbi_aa64_vae1_write },
3404     { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64,
3405       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
3406       .access = PL2_W, .type = ARM_CP_NO_RAW,
3407       .writefn = tlbi_aa64_ipas2e1is_write },
3408     { .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64,
3409       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,
3410       .access = PL2_W, .type = ARM_CP_NO_RAW,
3411       .writefn = tlbi_aa64_ipas2e1is_write },
3412     { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,
3413       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
3414       .access = PL2_W, .type = ARM_CP_NO_RAW,
3415       .writefn = tlbi_aa64_alle1is_write },
3416     { .name = "TLBI_VMALLS12E1IS", .state = ARM_CP_STATE_AA64,
3417       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 6,
3418       .access = PL2_W, .type = ARM_CP_NO_RAW,
3419       .writefn = tlbi_aa64_alle1is_write },
3420     { .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64,
3421       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,
3422       .access = PL2_W, .type = ARM_CP_NO_RAW,
3423       .writefn = tlbi_aa64_ipas2e1_write },
3424     { .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64,
3425       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,
3426       .access = PL2_W, .type = ARM_CP_NO_RAW,
3427       .writefn = tlbi_aa64_ipas2e1_write },
3428     { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64,
3429       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
3430       .access = PL2_W, .type = ARM_CP_NO_RAW,
3431       .writefn = tlbi_aa64_alle1_write },
3432     { .name = "TLBI_VMALLS12E1", .state = ARM_CP_STATE_AA64,
3433       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6,
3434       .access = PL2_W, .type = ARM_CP_NO_RAW,
3435       .writefn = tlbi_aa64_alle1is_write },
3436 #ifndef CONFIG_USER_ONLY
3437     /* 64 bit address translation operations */
3438     { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
3439       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0,
3440       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3441     { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
3442       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1,
3443       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3444     { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64,
3445       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2,
3446       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3447     { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64,
3448       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3,
3449       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3450     { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64,
3451       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4,
3452       .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3453     { .name = "AT_S12E1W", .state = ARM_CP_STATE_AA64,
3454       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 5,
3455       .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3456     { .name = "AT_S12E0R", .state = ARM_CP_STATE_AA64,
3457       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 6,
3458       .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3459     { .name = "AT_S12E0W", .state = ARM_CP_STATE_AA64,
3460       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 7,
3461       .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3462     /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
3463     { .name = "AT_S1E3R", .state = ARM_CP_STATE_AA64,
3464       .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 0,
3465       .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3466     { .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64,
3467       .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1,
3468       .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3469     { .name = "PAR_EL1", .state = ARM_CP_STATE_AA64,
3470       .type = ARM_CP_ALIAS,
3471       .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0,
3472       .access = PL1_RW, .resetvalue = 0,
3473       .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]),
3474       .writefn = par_write },
3475 #endif
3476     /* TLB invalidate last level of translation table walk */
3477     { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
3478       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write },
3479     { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
3480       .type = ARM_CP_NO_RAW, .access = PL1_W,
3481       .writefn = tlbimvaa_is_write },
3482     { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
3483       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
3484     { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
3485       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write },
3486     { .name = "TLBIMVALH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5,
3487       .type = ARM_CP_NO_RAW, .access = PL2_W,
3488       .writefn = tlbimva_hyp_write },
3489     { .name = "TLBIMVALHIS",
3490       .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5,
3491       .type = ARM_CP_NO_RAW, .access = PL2_W,
3492       .writefn = tlbimva_hyp_is_write },
3493     { .name = "TLBIIPAS2",
3494       .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,
3495       .type = ARM_CP_NO_RAW, .access = PL2_W,
3496       .writefn = tlbiipas2_write },
3497     { .name = "TLBIIPAS2IS",
3498       .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
3499       .type = ARM_CP_NO_RAW, .access = PL2_W,
3500       .writefn = tlbiipas2_is_write },
3501     { .name = "TLBIIPAS2L",
3502       .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,
3503       .type = ARM_CP_NO_RAW, .access = PL2_W,
3504       .writefn = tlbiipas2_write },
3505     { .name = "TLBIIPAS2LIS",
3506       .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,
3507       .type = ARM_CP_NO_RAW, .access = PL2_W,
3508       .writefn = tlbiipas2_is_write },
3509     /* 32 bit cache operations */
3510     { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
3511       .type = ARM_CP_NOP, .access = PL1_W },
3512     { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6,
3513       .type = ARM_CP_NOP, .access = PL1_W },
3514     { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
3515       .type = ARM_CP_NOP, .access = PL1_W },
3516     { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1,
3517       .type = ARM_CP_NOP, .access = PL1_W },
3518     { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6,
3519       .type = ARM_CP_NOP, .access = PL1_W },
3520     { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7,
3521       .type = ARM_CP_NOP, .access = PL1_W },
3522     { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
3523       .type = ARM_CP_NOP, .access = PL1_W },
3524     { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
3525       .type = ARM_CP_NOP, .access = PL1_W },
3526     { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1,
3527       .type = ARM_CP_NOP, .access = PL1_W },
3528     { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
3529       .type = ARM_CP_NOP, .access = PL1_W },
3530     { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1,
3531       .type = ARM_CP_NOP, .access = PL1_W },
3532     { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1,
3533       .type = ARM_CP_NOP, .access = PL1_W },
3534     { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
3535       .type = ARM_CP_NOP, .access = PL1_W },
3536     /* MMU Domain access control / MPU write buffer control */
3537     { .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0,
3538       .access = PL1_RW, .resetvalue = 0,
3539       .writefn = dacr_write, .raw_writefn = raw_write,
3540       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
3541                              offsetoflow32(CPUARMState, cp15.dacr_ns) } },
3542     { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64,
3543       .type = ARM_CP_ALIAS,
3544       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1,
3545       .access = PL1_RW,
3546       .fieldoffset = offsetof(CPUARMState, elr_el[1]) },
3547     { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64,
3548       .type = ARM_CP_ALIAS,
3549       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
3550       .access = PL1_RW,
3551       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_SVC]) },
3552     /* We rely on the access checks not allowing the guest to write to the
3553      * state field when SPSel indicates that it's being used as the stack
3554      * pointer.
3555      */
3556     { .name = "SP_EL0", .state = ARM_CP_STATE_AA64,
3557       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0,
3558       .access = PL1_RW, .accessfn = sp_el0_access,
3559       .type = ARM_CP_ALIAS,
3560       .fieldoffset = offsetof(CPUARMState, sp_el[0]) },
3561     { .name = "SP_EL1", .state = ARM_CP_STATE_AA64,
3562       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0,
3563       .access = PL2_RW, .type = ARM_CP_ALIAS,
3564       .fieldoffset = offsetof(CPUARMState, sp_el[1]) },
3565     { .name = "SPSel", .state = ARM_CP_STATE_AA64,
3566       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
3567       .type = ARM_CP_NO_RAW,
3568       .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
3569     { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64,
3570       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0,
3571       .type = ARM_CP_ALIAS,
3572       .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]),
3573       .access = PL2_RW, .accessfn = fpexc32_access },
3574     { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64,
3575       .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0,
3576       .access = PL2_RW, .resetvalue = 0,
3577       .writefn = dacr_write, .raw_writefn = raw_write,
3578       .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) },
3579     { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64,
3580       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1,
3581       .access = PL2_RW, .resetvalue = 0,
3582       .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) },
3583     { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64,
3584       .type = ARM_CP_ALIAS,
3585       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 0,
3586       .access = PL2_RW,
3587       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_IRQ]) },
3588     { .name = "SPSR_ABT", .state = ARM_CP_STATE_AA64,
3589       .type = ARM_CP_ALIAS,
3590       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 1,
3591       .access = PL2_RW,
3592       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_ABT]) },
3593     { .name = "SPSR_UND", .state = ARM_CP_STATE_AA64,
3594       .type = ARM_CP_ALIAS,
3595       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 2,
3596       .access = PL2_RW,
3597       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_UND]) },
3598     { .name = "SPSR_FIQ", .state = ARM_CP_STATE_AA64,
3599       .type = ARM_CP_ALIAS,
3600       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 3,
3601       .access = PL2_RW,
3602       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) },
3603     { .name = "MDCR_EL3", .state = ARM_CP_STATE_AA64,
3604       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1,
3605       .resetvalue = 0,
3606       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) },
3607     { .name = "SDCR", .type = ARM_CP_ALIAS,
3608       .cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1,
3609       .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
3610       .writefn = sdcr_write,
3611       .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) },
3612     REGINFO_SENTINEL
3613 };
3614 
3615 /* Used to describe the behaviour of EL2 regs when EL2 does not exist.  */
3616 static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
3617     { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
3618       .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
3619       .access = PL2_RW,
3620       .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
3621     { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
3622       .type = ARM_CP_NO_RAW,
3623       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
3624       .access = PL2_RW,
3625       .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
3626     { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
3627       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
3628       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3629     { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
3630       .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
3631       .access = PL2_RW, .type = ARM_CP_CONST,
3632       .resetvalue = 0 },
3633     { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3634       .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
3635       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3636     { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
3637       .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
3638       .access = PL2_RW, .type = ARM_CP_CONST,
3639       .resetvalue = 0 },
3640     { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3641       .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
3642       .access = PL2_RW, .type = ARM_CP_CONST,
3643       .resetvalue = 0 },
3644     { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
3645       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
3646       .access = PL2_RW, .type = ARM_CP_CONST,
3647       .resetvalue = 0 },
3648     { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
3649       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
3650       .access = PL2_RW, .type = ARM_CP_CONST,
3651       .resetvalue = 0 },
3652     { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
3653       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
3654       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3655     { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH,
3656       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
3657       .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
3658       .type = ARM_CP_CONST, .resetvalue = 0 },
3659     { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
3660       .cp = 15, .opc1 = 6, .crm = 2,
3661       .access = PL2_RW, .accessfn = access_el3_aa32ns,
3662       .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
3663     { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
3664       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
3665       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3666     { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
3667       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
3668       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3669     { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
3670       .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
3671       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3672     { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
3673       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
3674       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3675     { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
3676       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
3677       .resetvalue = 0 },
3678     { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
3679       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
3680       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3681     { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
3682       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
3683       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3684     { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
3685       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
3686       .resetvalue = 0 },
3687     { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
3688       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
3689       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3690     { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
3691       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
3692       .resetvalue = 0 },
3693     { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
3694       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
3695       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3696     { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
3697       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
3698       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3699     { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
3700       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
3701       .access = PL2_RW, .accessfn = access_tda,
3702       .type = ARM_CP_CONST, .resetvalue = 0 },
3703     { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH,
3704       .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
3705       .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
3706       .type = ARM_CP_CONST, .resetvalue = 0 },
3707     { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH,
3708       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3,
3709       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3710     REGINFO_SENTINEL
3711 };
3712 
3713 static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
3714 {
3715     ARMCPU *cpu = arm_env_get_cpu(env);
3716     uint64_t valid_mask = HCR_MASK;
3717 
3718     if (arm_feature(env, ARM_FEATURE_EL3)) {
3719         valid_mask &= ~HCR_HCD;
3720     } else if (cpu->psci_conduit != QEMU_PSCI_CONDUIT_SMC) {
3721         /* Architecturally HCR.TSC is RES0 if EL3 is not implemented.
3722          * However, if we're using the SMC PSCI conduit then QEMU is
3723          * effectively acting like EL3 firmware and so the guest at
3724          * EL2 should retain the ability to prevent EL1 from being
3725          * able to make SMC calls into the ersatz firmware, so in
3726          * that case HCR.TSC should be read/write.
3727          */
3728         valid_mask &= ~HCR_TSC;
3729     }
3730 
3731     /* Clear RES0 bits.  */
3732     value &= valid_mask;
3733 
3734     /* These bits change the MMU setup:
3735      * HCR_VM enables stage 2 translation
3736      * HCR_PTW forbids certain page-table setups
3737      * HCR_DC Disables stage1 and enables stage2 translation
3738      */
3739     if ((raw_read(env, ri) ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) {
3740         tlb_flush(CPU(cpu));
3741     }
3742     raw_write(env, ri, value);
3743 }
3744 
3745 static const ARMCPRegInfo el2_cp_reginfo[] = {
3746     { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
3747       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
3748       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2),
3749       .writefn = hcr_write },
3750     { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64,
3751       .type = ARM_CP_ALIAS,
3752       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1,
3753       .access = PL2_RW,
3754       .fieldoffset = offsetof(CPUARMState, elr_el[2]) },
3755     { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64,
3756       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
3757       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) },
3758     { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64,
3759       .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
3760       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) },
3761     { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64,
3762       .type = ARM_CP_ALIAS,
3763       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0,
3764       .access = PL2_RW,
3765       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_HYP]) },
3766     { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
3767       .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
3768       .access = PL2_RW, .writefn = vbar_write,
3769       .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]),
3770       .resetvalue = 0 },
3771     { .name = "SP_EL2", .state = ARM_CP_STATE_AA64,
3772       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0,
3773       .access = PL3_RW, .type = ARM_CP_ALIAS,
3774       .fieldoffset = offsetof(CPUARMState, sp_el[2]) },
3775     { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
3776       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
3777       .access = PL2_RW, .accessfn = cptr_access, .resetvalue = 0,
3778       .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[2]) },
3779     { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
3780       .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
3781       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[2]),
3782       .resetvalue = 0 },
3783     { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3784       .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
3785       .access = PL2_RW, .type = ARM_CP_ALIAS,
3786       .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el[2]) },
3787     { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
3788       .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
3789       .access = PL2_RW, .type = ARM_CP_CONST,
3790       .resetvalue = 0 },
3791     /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
3792     { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3793       .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
3794       .access = PL2_RW, .type = ARM_CP_CONST,
3795       .resetvalue = 0 },
3796     { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
3797       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
3798       .access = PL2_RW, .type = ARM_CP_CONST,
3799       .resetvalue = 0 },
3800     { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
3801       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
3802       .access = PL2_RW, .type = ARM_CP_CONST,
3803       .resetvalue = 0 },
3804     { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
3805       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
3806       .access = PL2_RW,
3807       /* no .writefn needed as this can't cause an ASID change;
3808        * no .raw_writefn or .resetfn needed as we never use mask/base_mask
3809        */
3810       .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) },
3811     { .name = "VTCR", .state = ARM_CP_STATE_AA32,
3812       .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
3813       .type = ARM_CP_ALIAS,
3814       .access = PL2_RW, .accessfn = access_el3_aa32ns,
3815       .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },
3816     { .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64,
3817       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
3818       .access = PL2_RW,
3819       /* no .writefn needed as this can't cause an ASID change;
3820        * no .raw_writefn or .resetfn needed as we never use mask/base_mask
3821        */
3822       .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },
3823     { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
3824       .cp = 15, .opc1 = 6, .crm = 2,
3825       .type = ARM_CP_64BIT | ARM_CP_ALIAS,
3826       .access = PL2_RW, .accessfn = access_el3_aa32ns,
3827       .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2),
3828       .writefn = vttbr_write },
3829     { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
3830       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
3831       .access = PL2_RW, .writefn = vttbr_write,
3832       .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2) },
3833     { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
3834       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
3835       .access = PL2_RW, .raw_writefn = raw_write, .writefn = sctlr_write,
3836       .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[2]) },
3837     { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
3838       .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
3839       .access = PL2_RW, .resetvalue = 0,
3840       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) },
3841     { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
3842       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
3843       .access = PL2_RW, .resetvalue = 0,
3844       .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },
3845     { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
3846       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
3847       .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },
3848     { .name = "TLBIALLNSNH",
3849       .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
3850       .type = ARM_CP_NO_RAW, .access = PL2_W,
3851       .writefn = tlbiall_nsnh_write },
3852     { .name = "TLBIALLNSNHIS",
3853       .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
3854       .type = ARM_CP_NO_RAW, .access = PL2_W,
3855       .writefn = tlbiall_nsnh_is_write },
3856     { .name = "TLBIALLH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0,
3857       .type = ARM_CP_NO_RAW, .access = PL2_W,
3858       .writefn = tlbiall_hyp_write },
3859     { .name = "TLBIALLHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0,
3860       .type = ARM_CP_NO_RAW, .access = PL2_W,
3861       .writefn = tlbiall_hyp_is_write },
3862     { .name = "TLBIMVAH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1,
3863       .type = ARM_CP_NO_RAW, .access = PL2_W,
3864       .writefn = tlbimva_hyp_write },
3865     { .name = "TLBIMVAHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1,
3866       .type = ARM_CP_NO_RAW, .access = PL2_W,
3867       .writefn = tlbimva_hyp_is_write },
3868     { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64,
3869       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0,
3870       .type = ARM_CP_NO_RAW, .access = PL2_W,
3871       .writefn = tlbi_aa64_alle2_write },
3872     { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64,
3873       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1,
3874       .type = ARM_CP_NO_RAW, .access = PL2_W,
3875       .writefn = tlbi_aa64_vae2_write },
3876     { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64,
3877       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5,
3878       .access = PL2_W, .type = ARM_CP_NO_RAW,
3879       .writefn = tlbi_aa64_vae2_write },
3880     { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64,
3881       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0,
3882       .access = PL2_W, .type = ARM_CP_NO_RAW,
3883       .writefn = tlbi_aa64_alle2is_write },
3884     { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64,
3885       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1,
3886       .type = ARM_CP_NO_RAW, .access = PL2_W,
3887       .writefn = tlbi_aa64_vae2is_write },
3888     { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64,
3889       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5,
3890       .access = PL2_W, .type = ARM_CP_NO_RAW,
3891       .writefn = tlbi_aa64_vae2is_write },
3892 #ifndef CONFIG_USER_ONLY
3893     /* Unlike the other EL2-related AT operations, these must
3894      * UNDEF from EL3 if EL2 is not implemented, which is why we
3895      * define them here rather than with the rest of the AT ops.
3896      */
3897     { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64,
3898       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
3899       .access = PL2_W, .accessfn = at_s1e2_access,
3900       .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3901     { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64,
3902       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
3903       .access = PL2_W, .accessfn = at_s1e2_access,
3904       .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3905     /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
3906      * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
3907      * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
3908      * to behave as if SCR.NS was 1.
3909      */
3910     { .name = "ATS1HR", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
3911       .access = PL2_W,
3912       .writefn = ats1h_write, .type = ARM_CP_NO_RAW },
3913     { .name = "ATS1HW", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
3914       .access = PL2_W,
3915       .writefn = ats1h_write, .type = ARM_CP_NO_RAW },
3916     { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
3917       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
3918       /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
3919        * reset values as IMPDEF. We choose to reset to 3 to comply with
3920        * both ARMv7 and ARMv8.
3921        */
3922       .access = PL2_RW, .resetvalue = 3,
3923       .fieldoffset = offsetof(CPUARMState, cp15.cnthctl_el2) },
3924     { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
3925       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
3926       .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0,
3927       .writefn = gt_cntvoff_write,
3928       .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) },
3929     { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
3930       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS | ARM_CP_IO,
3931       .writefn = gt_cntvoff_write,
3932       .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) },
3933     { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
3934       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
3935       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval),
3936       .type = ARM_CP_IO, .access = PL2_RW,
3937       .writefn = gt_hyp_cval_write, .raw_writefn = raw_write },
3938     { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
3939       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval),
3940       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_IO,
3941       .writefn = gt_hyp_cval_write, .raw_writefn = raw_write },
3942     { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
3943       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
3944       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW,
3945       .resetfn = gt_hyp_timer_reset,
3946       .readfn = gt_hyp_tval_read, .writefn = gt_hyp_tval_write },
3947     { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
3948       .type = ARM_CP_IO,
3949       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
3950       .access = PL2_RW,
3951       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].ctl),
3952       .resetvalue = 0,
3953       .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write },
3954 #endif
3955     /* The only field of MDCR_EL2 that has a defined architectural reset value
3956      * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but we
3957      * don't impelment any PMU event counters, so using zero as a reset
3958      * value for MDCR_EL2 is okay
3959      */
3960     { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
3961       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
3962       .access = PL2_RW, .resetvalue = 0,
3963       .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), },
3964     { .name = "HPFAR", .state = ARM_CP_STATE_AA32,
3965       .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
3966       .access = PL2_RW, .accessfn = access_el3_aa32ns,
3967       .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) },
3968     { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64,
3969       .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
3970       .access = PL2_RW,
3971       .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) },
3972     { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH,
3973       .cp = 15, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3,
3974       .access = PL2_RW,
3975       .fieldoffset = offsetof(CPUARMState, cp15.hstr_el2) },
3976     REGINFO_SENTINEL
3977 };
3978 
3979 static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
3980                                    bool isread)
3981 {
3982     /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
3983      * At Secure EL1 it traps to EL3.
3984      */
3985     if (arm_current_el(env) == 3) {
3986         return CP_ACCESS_OK;
3987     }
3988     if (arm_is_secure_below_el3(env)) {
3989         return CP_ACCESS_TRAP_EL3;
3990     }
3991     /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
3992     if (isread) {
3993         return CP_ACCESS_OK;
3994     }
3995     return CP_ACCESS_TRAP_UNCATEGORIZED;
3996 }
3997 
3998 static const ARMCPRegInfo el3_cp_reginfo[] = {
3999     { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64,
4000       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0,
4001       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3),
4002       .resetvalue = 0, .writefn = scr_write },
4003     { .name = "SCR",  .type = ARM_CP_ALIAS,
4004       .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0,
4005       .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
4006       .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3),
4007       .writefn = scr_write },
4008     { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64,
4009       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1,
4010       .access = PL3_RW, .resetvalue = 0,
4011       .fieldoffset = offsetof(CPUARMState, cp15.sder) },
4012     { .name = "SDER",
4013       .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1,
4014       .access = PL3_RW, .resetvalue = 0,
4015       .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) },
4016     { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
4017       .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
4018       .writefn = vbar_write, .resetvalue = 0,
4019       .fieldoffset = offsetof(CPUARMState, cp15.mvbar) },
4020     { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64,
4021       .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0,
4022       .access = PL3_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
4023       .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) },
4024     { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64,
4025       .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2,
4026       .access = PL3_RW,
4027       /* no .writefn needed as this can't cause an ASID change;
4028        * we must provide a .raw_writefn and .resetfn because we handle
4029        * reset and migration for the AArch32 TTBCR(S), which might be
4030        * using mask and base_mask.
4031        */
4032       .resetfn = vmsa_ttbcr_reset, .raw_writefn = vmsa_ttbcr_raw_write,
4033       .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) },
4034     { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64,
4035       .type = ARM_CP_ALIAS,
4036       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1,
4037       .access = PL3_RW,
4038       .fieldoffset = offsetof(CPUARMState, elr_el[3]) },
4039     { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64,
4040       .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0,
4041       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) },
4042     { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64,
4043       .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0,
4044       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) },
4045     { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64,
4046       .type = ARM_CP_ALIAS,
4047       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,
4048       .access = PL3_RW,
4049       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_MON]) },
4050     { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64,
4051       .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0,
4052       .access = PL3_RW, .writefn = vbar_write,
4053       .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]),
4054       .resetvalue = 0 },
4055     { .name = "CPTR_EL3", .state = ARM_CP_STATE_AA64,
4056       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 2,
4057       .access = PL3_RW, .accessfn = cptr_access, .resetvalue = 0,
4058       .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[3]) },
4059     { .name = "TPIDR_EL3", .state = ARM_CP_STATE_AA64,
4060       .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 2,
4061       .access = PL3_RW, .resetvalue = 0,
4062       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[3]) },
4063     { .name = "AMAIR_EL3", .state = ARM_CP_STATE_AA64,
4064       .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0,
4065       .access = PL3_RW, .type = ARM_CP_CONST,
4066       .resetvalue = 0 },
4067     { .name = "AFSR0_EL3", .state = ARM_CP_STATE_BOTH,
4068       .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 0,
4069       .access = PL3_RW, .type = ARM_CP_CONST,
4070       .resetvalue = 0 },
4071     { .name = "AFSR1_EL3", .state = ARM_CP_STATE_BOTH,
4072       .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 1,
4073       .access = PL3_RW, .type = ARM_CP_CONST,
4074       .resetvalue = 0 },
4075     { .name = "TLBI_ALLE3IS", .state = ARM_CP_STATE_AA64,
4076       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 0,
4077       .access = PL3_W, .type = ARM_CP_NO_RAW,
4078       .writefn = tlbi_aa64_alle3is_write },
4079     { .name = "TLBI_VAE3IS", .state = ARM_CP_STATE_AA64,
4080       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 1,
4081       .access = PL3_W, .type = ARM_CP_NO_RAW,
4082       .writefn = tlbi_aa64_vae3is_write },
4083     { .name = "TLBI_VALE3IS", .state = ARM_CP_STATE_AA64,
4084       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 5,
4085       .access = PL3_W, .type = ARM_CP_NO_RAW,
4086       .writefn = tlbi_aa64_vae3is_write },
4087     { .name = "TLBI_ALLE3", .state = ARM_CP_STATE_AA64,
4088       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 0,
4089       .access = PL3_W, .type = ARM_CP_NO_RAW,
4090       .writefn = tlbi_aa64_alle3_write },
4091     { .name = "TLBI_VAE3", .state = ARM_CP_STATE_AA64,
4092       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 1,
4093       .access = PL3_W, .type = ARM_CP_NO_RAW,
4094       .writefn = tlbi_aa64_vae3_write },
4095     { .name = "TLBI_VALE3", .state = ARM_CP_STATE_AA64,
4096       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5,
4097       .access = PL3_W, .type = ARM_CP_NO_RAW,
4098       .writefn = tlbi_aa64_vae3_write },
4099     REGINFO_SENTINEL
4100 };
4101 
4102 static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri,
4103                                      bool isread)
4104 {
4105     /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
4106      * but the AArch32 CTR has its own reginfo struct)
4107      */
4108     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCT)) {
4109         return CP_ACCESS_TRAP;
4110     }
4111     return CP_ACCESS_OK;
4112 }
4113 
4114 static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri,
4115                         uint64_t value)
4116 {
4117     /* Writes to OSLAR_EL1 may update the OS lock status, which can be
4118      * read via a bit in OSLSR_EL1.
4119      */
4120     int oslock;
4121 
4122     if (ri->state == ARM_CP_STATE_AA32) {
4123         oslock = (value == 0xC5ACCE55);
4124     } else {
4125         oslock = value & 1;
4126     }
4127 
4128     env->cp15.oslsr_el1 = deposit32(env->cp15.oslsr_el1, 1, 1, oslock);
4129 }
4130 
4131 static const ARMCPRegInfo debug_cp_reginfo[] = {
4132     /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
4133      * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
4134      * unlike DBGDRAR it is never accessible from EL0.
4135      * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
4136      * accessor.
4137      */
4138     { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
4139       .access = PL0_R, .accessfn = access_tdra,
4140       .type = ARM_CP_CONST, .resetvalue = 0 },
4141     { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64,
4142       .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
4143       .access = PL1_R, .accessfn = access_tdra,
4144       .type = ARM_CP_CONST, .resetvalue = 0 },
4145     { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
4146       .access = PL0_R, .accessfn = access_tdra,
4147       .type = ARM_CP_CONST, .resetvalue = 0 },
4148     /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
4149     { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH,
4150       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
4151       .access = PL1_RW, .accessfn = access_tda,
4152       .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
4153       .resetvalue = 0 },
4154     /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
4155      * We don't implement the configurable EL0 access.
4156      */
4157     { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH,
4158       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
4159       .type = ARM_CP_ALIAS,
4160       .access = PL1_R, .accessfn = access_tda,
4161       .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), },
4162     { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH,
4163       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
4164       .access = PL1_W, .type = ARM_CP_NO_RAW,
4165       .accessfn = access_tdosa,
4166       .writefn = oslar_write },
4167     { .name = "OSLSR_EL1", .state = ARM_CP_STATE_BOTH,
4168       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 4,
4169       .access = PL1_R, .resetvalue = 10,
4170       .accessfn = access_tdosa,
4171       .fieldoffset = offsetof(CPUARMState, cp15.oslsr_el1) },
4172     /* Dummy OSDLR_EL1: 32-bit Linux will read this */
4173     { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH,
4174       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4,
4175       .access = PL1_RW, .accessfn = access_tdosa,
4176       .type = ARM_CP_NOP },
4177     /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
4178      * implement vector catch debug events yet.
4179      */
4180     { .name = "DBGVCR",
4181       .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
4182       .access = PL1_RW, .accessfn = access_tda,
4183       .type = ARM_CP_NOP },
4184     /* Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor
4185      * to save and restore a 32-bit guest's DBGVCR)
4186      */
4187     { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64,
4188       .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0,
4189       .access = PL2_RW, .accessfn = access_tda,
4190       .type = ARM_CP_NOP },
4191     /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
4192      * Channel but Linux may try to access this register. The 32-bit
4193      * alias is DBGDCCINT.
4194      */
4195     { .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH,
4196       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
4197       .access = PL1_RW, .accessfn = access_tda,
4198       .type = ARM_CP_NOP },
4199     REGINFO_SENTINEL
4200 };
4201 
4202 static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
4203     /* 64 bit access versions of the (dummy) debug registers */
4204     { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
4205       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
4206     { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
4207       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
4208     REGINFO_SENTINEL
4209 };
4210 
4211 void hw_watchpoint_update(ARMCPU *cpu, int n)
4212 {
4213     CPUARMState *env = &cpu->env;
4214     vaddr len = 0;
4215     vaddr wvr = env->cp15.dbgwvr[n];
4216     uint64_t wcr = env->cp15.dbgwcr[n];
4217     int mask;
4218     int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
4219 
4220     if (env->cpu_watchpoint[n]) {
4221         cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]);
4222         env->cpu_watchpoint[n] = NULL;
4223     }
4224 
4225     if (!extract64(wcr, 0, 1)) {
4226         /* E bit clear : watchpoint disabled */
4227         return;
4228     }
4229 
4230     switch (extract64(wcr, 3, 2)) {
4231     case 0:
4232         /* LSC 00 is reserved and must behave as if the wp is disabled */
4233         return;
4234     case 1:
4235         flags |= BP_MEM_READ;
4236         break;
4237     case 2:
4238         flags |= BP_MEM_WRITE;
4239         break;
4240     case 3:
4241         flags |= BP_MEM_ACCESS;
4242         break;
4243     }
4244 
4245     /* Attempts to use both MASK and BAS fields simultaneously are
4246      * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
4247      * thus generating a watchpoint for every byte in the masked region.
4248      */
4249     mask = extract64(wcr, 24, 4);
4250     if (mask == 1 || mask == 2) {
4251         /* Reserved values of MASK; we must act as if the mask value was
4252          * some non-reserved value, or as if the watchpoint were disabled.
4253          * We choose the latter.
4254          */
4255         return;
4256     } else if (mask) {
4257         /* Watchpoint covers an aligned area up to 2GB in size */
4258         len = 1ULL << mask;
4259         /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
4260          * whether the watchpoint fires when the unmasked bits match; we opt
4261          * to generate the exceptions.
4262          */
4263         wvr &= ~(len - 1);
4264     } else {
4265         /* Watchpoint covers bytes defined by the byte address select bits */
4266         int bas = extract64(wcr, 5, 8);
4267         int basstart;
4268 
4269         if (bas == 0) {
4270             /* This must act as if the watchpoint is disabled */
4271             return;
4272         }
4273 
4274         if (extract64(wvr, 2, 1)) {
4275             /* Deprecated case of an only 4-aligned address. BAS[7:4] are
4276              * ignored, and BAS[3:0] define which bytes to watch.
4277              */
4278             bas &= 0xf;
4279         }
4280         /* The BAS bits are supposed to be programmed to indicate a contiguous
4281          * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
4282          * we fire for each byte in the word/doubleword addressed by the WVR.
4283          * We choose to ignore any non-zero bits after the first range of 1s.
4284          */
4285         basstart = ctz32(bas);
4286         len = cto32(bas >> basstart);
4287         wvr += basstart;
4288     }
4289 
4290     cpu_watchpoint_insert(CPU(cpu), wvr, len, flags,
4291                           &env->cpu_watchpoint[n]);
4292 }
4293 
4294 void hw_watchpoint_update_all(ARMCPU *cpu)
4295 {
4296     int i;
4297     CPUARMState *env = &cpu->env;
4298 
4299     /* Completely clear out existing QEMU watchpoints and our array, to
4300      * avoid possible stale entries following migration load.
4301      */
4302     cpu_watchpoint_remove_all(CPU(cpu), BP_CPU);
4303     memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint));
4304 
4305     for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) {
4306         hw_watchpoint_update(cpu, i);
4307     }
4308 }
4309 
4310 static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4311                          uint64_t value)
4312 {
4313     ARMCPU *cpu = arm_env_get_cpu(env);
4314     int i = ri->crm;
4315 
4316     /* Bits [63:49] are hardwired to the value of bit [48]; that is, the
4317      * register reads and behaves as if values written are sign extended.
4318      * Bits [1:0] are RES0.
4319      */
4320     value = sextract64(value, 0, 49) & ~3ULL;
4321 
4322     raw_write(env, ri, value);
4323     hw_watchpoint_update(cpu, i);
4324 }
4325 
4326 static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4327                          uint64_t value)
4328 {
4329     ARMCPU *cpu = arm_env_get_cpu(env);
4330     int i = ri->crm;
4331 
4332     raw_write(env, ri, value);
4333     hw_watchpoint_update(cpu, i);
4334 }
4335 
4336 void hw_breakpoint_update(ARMCPU *cpu, int n)
4337 {
4338     CPUARMState *env = &cpu->env;
4339     uint64_t bvr = env->cp15.dbgbvr[n];
4340     uint64_t bcr = env->cp15.dbgbcr[n];
4341     vaddr addr;
4342     int bt;
4343     int flags = BP_CPU;
4344 
4345     if (env->cpu_breakpoint[n]) {
4346         cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]);
4347         env->cpu_breakpoint[n] = NULL;
4348     }
4349 
4350     if (!extract64(bcr, 0, 1)) {
4351         /* E bit clear : watchpoint disabled */
4352         return;
4353     }
4354 
4355     bt = extract64(bcr, 20, 4);
4356 
4357     switch (bt) {
4358     case 4: /* unlinked address mismatch (reserved if AArch64) */
4359     case 5: /* linked address mismatch (reserved if AArch64) */
4360         qemu_log_mask(LOG_UNIMP,
4361                       "arm: address mismatch breakpoint types not implemented");
4362         return;
4363     case 0: /* unlinked address match */
4364     case 1: /* linked address match */
4365     {
4366         /* Bits [63:49] are hardwired to the value of bit [48]; that is,
4367          * we behave as if the register was sign extended. Bits [1:0] are
4368          * RES0. The BAS field is used to allow setting breakpoints on 16
4369          * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether
4370          * a bp will fire if the addresses covered by the bp and the addresses
4371          * covered by the insn overlap but the insn doesn't start at the
4372          * start of the bp address range. We choose to require the insn and
4373          * the bp to have the same address. The constraints on writing to
4374          * BAS enforced in dbgbcr_write mean we have only four cases:
4375          *  0b0000  => no breakpoint
4376          *  0b0011  => breakpoint on addr
4377          *  0b1100  => breakpoint on addr + 2
4378          *  0b1111  => breakpoint on addr
4379          * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
4380          */
4381         int bas = extract64(bcr, 5, 4);
4382         addr = sextract64(bvr, 0, 49) & ~3ULL;
4383         if (bas == 0) {
4384             return;
4385         }
4386         if (bas == 0xc) {
4387             addr += 2;
4388         }
4389         break;
4390     }
4391     case 2: /* unlinked context ID match */
4392     case 8: /* unlinked VMID match (reserved if no EL2) */
4393     case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
4394         qemu_log_mask(LOG_UNIMP,
4395                       "arm: unlinked context breakpoint types not implemented");
4396         return;
4397     case 9: /* linked VMID match (reserved if no EL2) */
4398     case 11: /* linked context ID and VMID match (reserved if no EL2) */
4399     case 3: /* linked context ID match */
4400     default:
4401         /* We must generate no events for Linked context matches (unless
4402          * they are linked to by some other bp/wp, which is handled in
4403          * updates for the linking bp/wp). We choose to also generate no events
4404          * for reserved values.
4405          */
4406         return;
4407     }
4408 
4409     cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]);
4410 }
4411 
4412 void hw_breakpoint_update_all(ARMCPU *cpu)
4413 {
4414     int i;
4415     CPUARMState *env = &cpu->env;
4416 
4417     /* Completely clear out existing QEMU breakpoints and our array, to
4418      * avoid possible stale entries following migration load.
4419      */
4420     cpu_breakpoint_remove_all(CPU(cpu), BP_CPU);
4421     memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint));
4422 
4423     for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) {
4424         hw_breakpoint_update(cpu, i);
4425     }
4426 }
4427 
4428 static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4429                          uint64_t value)
4430 {
4431     ARMCPU *cpu = arm_env_get_cpu(env);
4432     int i = ri->crm;
4433 
4434     raw_write(env, ri, value);
4435     hw_breakpoint_update(cpu, i);
4436 }
4437 
4438 static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4439                          uint64_t value)
4440 {
4441     ARMCPU *cpu = arm_env_get_cpu(env);
4442     int i = ri->crm;
4443 
4444     /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
4445      * copy of BAS[0].
4446      */
4447     value = deposit64(value, 6, 1, extract64(value, 5, 1));
4448     value = deposit64(value, 8, 1, extract64(value, 7, 1));
4449 
4450     raw_write(env, ri, value);
4451     hw_breakpoint_update(cpu, i);
4452 }
4453 
4454 static void define_debug_regs(ARMCPU *cpu)
4455 {
4456     /* Define v7 and v8 architectural debug registers.
4457      * These are just dummy implementations for now.
4458      */
4459     int i;
4460     int wrps, brps, ctx_cmps;
4461     ARMCPRegInfo dbgdidr = {
4462         .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
4463         .access = PL0_R, .accessfn = access_tda,
4464         .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr,
4465     };
4466 
4467     /* Note that all these register fields hold "number of Xs minus 1". */
4468     brps = extract32(cpu->dbgdidr, 24, 4);
4469     wrps = extract32(cpu->dbgdidr, 28, 4);
4470     ctx_cmps = extract32(cpu->dbgdidr, 20, 4);
4471 
4472     assert(ctx_cmps <= brps);
4473 
4474     /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties
4475      * of the debug registers such as number of breakpoints;
4476      * check that if they both exist then they agree.
4477      */
4478     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
4479         assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps);
4480         assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps);
4481         assert(extract32(cpu->id_aa64dfr0, 28, 4) == ctx_cmps);
4482     }
4483 
4484     define_one_arm_cp_reg(cpu, &dbgdidr);
4485     define_arm_cp_regs(cpu, debug_cp_reginfo);
4486 
4487     if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) {
4488         define_arm_cp_regs(cpu, debug_lpae_cp_reginfo);
4489     }
4490 
4491     for (i = 0; i < brps + 1; i++) {
4492         ARMCPRegInfo dbgregs[] = {
4493             { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH,
4494               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
4495               .access = PL1_RW, .accessfn = access_tda,
4496               .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]),
4497               .writefn = dbgbvr_write, .raw_writefn = raw_write
4498             },
4499             { .name = "DBGBCR", .state = ARM_CP_STATE_BOTH,
4500               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
4501               .access = PL1_RW, .accessfn = access_tda,
4502               .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]),
4503               .writefn = dbgbcr_write, .raw_writefn = raw_write
4504             },
4505             REGINFO_SENTINEL
4506         };
4507         define_arm_cp_regs(cpu, dbgregs);
4508     }
4509 
4510     for (i = 0; i < wrps + 1; i++) {
4511         ARMCPRegInfo dbgregs[] = {
4512             { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH,
4513               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
4514               .access = PL1_RW, .accessfn = access_tda,
4515               .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]),
4516               .writefn = dbgwvr_write, .raw_writefn = raw_write
4517             },
4518             { .name = "DBGWCR", .state = ARM_CP_STATE_BOTH,
4519               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
4520               .access = PL1_RW, .accessfn = access_tda,
4521               .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]),
4522               .writefn = dbgwcr_write, .raw_writefn = raw_write
4523             },
4524             REGINFO_SENTINEL
4525         };
4526         define_arm_cp_regs(cpu, dbgregs);
4527     }
4528 }
4529 
4530 void register_cp_regs_for_features(ARMCPU *cpu)
4531 {
4532     /* Register all the coprocessor registers based on feature bits */
4533     CPUARMState *env = &cpu->env;
4534     if (arm_feature(env, ARM_FEATURE_M)) {
4535         /* M profile has no coprocessor registers */
4536         return;
4537     }
4538 
4539     define_arm_cp_regs(cpu, cp_reginfo);
4540     if (!arm_feature(env, ARM_FEATURE_V8)) {
4541         /* Must go early as it is full of wildcards that may be
4542          * overridden by later definitions.
4543          */
4544         define_arm_cp_regs(cpu, not_v8_cp_reginfo);
4545     }
4546 
4547     if (arm_feature(env, ARM_FEATURE_V6)) {
4548         /* The ID registers all have impdef reset values */
4549         ARMCPRegInfo v6_idregs[] = {
4550             { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH,
4551               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
4552               .access = PL1_R, .type = ARM_CP_CONST,
4553               .resetvalue = cpu->id_pfr0 },
4554             { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
4555               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
4556               .access = PL1_R, .type = ARM_CP_CONST,
4557               .resetvalue = cpu->id_pfr1 },
4558             { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
4559               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
4560               .access = PL1_R, .type = ARM_CP_CONST,
4561               .resetvalue = cpu->id_dfr0 },
4562             { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
4563               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
4564               .access = PL1_R, .type = ARM_CP_CONST,
4565               .resetvalue = cpu->id_afr0 },
4566             { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH,
4567               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
4568               .access = PL1_R, .type = ARM_CP_CONST,
4569               .resetvalue = cpu->id_mmfr0 },
4570             { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
4571               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
4572               .access = PL1_R, .type = ARM_CP_CONST,
4573               .resetvalue = cpu->id_mmfr1 },
4574             { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
4575               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
4576               .access = PL1_R, .type = ARM_CP_CONST,
4577               .resetvalue = cpu->id_mmfr2 },
4578             { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
4579               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
4580               .access = PL1_R, .type = ARM_CP_CONST,
4581               .resetvalue = cpu->id_mmfr3 },
4582             { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
4583               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
4584               .access = PL1_R, .type = ARM_CP_CONST,
4585               .resetvalue = cpu->id_isar0 },
4586             { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
4587               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
4588               .access = PL1_R, .type = ARM_CP_CONST,
4589               .resetvalue = cpu->id_isar1 },
4590             { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
4591               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
4592               .access = PL1_R, .type = ARM_CP_CONST,
4593               .resetvalue = cpu->id_isar2 },
4594             { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
4595               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
4596               .access = PL1_R, .type = ARM_CP_CONST,
4597               .resetvalue = cpu->id_isar3 },
4598             { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
4599               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
4600               .access = PL1_R, .type = ARM_CP_CONST,
4601               .resetvalue = cpu->id_isar4 },
4602             { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
4603               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
4604               .access = PL1_R, .type = ARM_CP_CONST,
4605               .resetvalue = cpu->id_isar5 },
4606             { .name = "ID_MMFR4", .state = ARM_CP_STATE_BOTH,
4607               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6,
4608               .access = PL1_R, .type = ARM_CP_CONST,
4609               .resetvalue = cpu->id_mmfr4 },
4610             /* 7 is as yet unallocated and must RAZ */
4611             { .name = "ID_ISAR7_RESERVED", .state = ARM_CP_STATE_BOTH,
4612               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7,
4613               .access = PL1_R, .type = ARM_CP_CONST,
4614               .resetvalue = 0 },
4615             REGINFO_SENTINEL
4616         };
4617         define_arm_cp_regs(cpu, v6_idregs);
4618         define_arm_cp_regs(cpu, v6_cp_reginfo);
4619     } else {
4620         define_arm_cp_regs(cpu, not_v6_cp_reginfo);
4621     }
4622     if (arm_feature(env, ARM_FEATURE_V6K)) {
4623         define_arm_cp_regs(cpu, v6k_cp_reginfo);
4624     }
4625     if (arm_feature(env, ARM_FEATURE_V7MP) &&
4626         !arm_feature(env, ARM_FEATURE_PMSA)) {
4627         define_arm_cp_regs(cpu, v7mp_cp_reginfo);
4628     }
4629     if (arm_feature(env, ARM_FEATURE_V7)) {
4630         /* v7 performance monitor control register: same implementor
4631          * field as main ID register, and we implement only the cycle
4632          * count register.
4633          */
4634 #ifndef CONFIG_USER_ONLY
4635         ARMCPRegInfo pmcr = {
4636             .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
4637             .access = PL0_RW,
4638             .type = ARM_CP_IO | ARM_CP_ALIAS,
4639             .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr),
4640             .accessfn = pmreg_access, .writefn = pmcr_write,
4641             .raw_writefn = raw_write,
4642         };
4643         ARMCPRegInfo pmcr64 = {
4644             .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64,
4645             .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0,
4646             .access = PL0_RW, .accessfn = pmreg_access,
4647             .type = ARM_CP_IO,
4648             .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
4649             .resetvalue = cpu->midr & 0xff000000,
4650             .writefn = pmcr_write, .raw_writefn = raw_write,
4651         };
4652         define_one_arm_cp_reg(cpu, &pmcr);
4653         define_one_arm_cp_reg(cpu, &pmcr64);
4654 #endif
4655         ARMCPRegInfo clidr = {
4656             .name = "CLIDR", .state = ARM_CP_STATE_BOTH,
4657             .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
4658             .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
4659         };
4660         define_one_arm_cp_reg(cpu, &clidr);
4661         define_arm_cp_regs(cpu, v7_cp_reginfo);
4662         define_debug_regs(cpu);
4663     } else {
4664         define_arm_cp_regs(cpu, not_v7_cp_reginfo);
4665     }
4666     if (arm_feature(env, ARM_FEATURE_V8)) {
4667         /* AArch64 ID registers, which all have impdef reset values.
4668          * Note that within the ID register ranges the unused slots
4669          * must all RAZ, not UNDEF; future architecture versions may
4670          * define new registers here.
4671          */
4672         ARMCPRegInfo v8_idregs[] = {
4673             { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
4674               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
4675               .access = PL1_R, .type = ARM_CP_CONST,
4676               .resetvalue = cpu->id_aa64pfr0 },
4677             { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
4678               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
4679               .access = PL1_R, .type = ARM_CP_CONST,
4680               .resetvalue = cpu->id_aa64pfr1},
4681             { .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4682               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2,
4683               .access = PL1_R, .type = ARM_CP_CONST,
4684               .resetvalue = 0 },
4685             { .name = "ID_AA64PFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4686               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3,
4687               .access = PL1_R, .type = ARM_CP_CONST,
4688               .resetvalue = 0 },
4689             { .name = "ID_AA64PFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4690               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4,
4691               .access = PL1_R, .type = ARM_CP_CONST,
4692               .resetvalue = 0 },
4693             { .name = "ID_AA64PFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4694               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5,
4695               .access = PL1_R, .type = ARM_CP_CONST,
4696               .resetvalue = 0 },
4697             { .name = "ID_AA64PFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4698               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6,
4699               .access = PL1_R, .type = ARM_CP_CONST,
4700               .resetvalue = 0 },
4701             { .name = "ID_AA64PFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4702               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 7,
4703               .access = PL1_R, .type = ARM_CP_CONST,
4704               .resetvalue = 0 },
4705             { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
4706               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
4707               .access = PL1_R, .type = ARM_CP_CONST,
4708               .resetvalue = cpu->id_aa64dfr0 },
4709             { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
4710               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
4711               .access = PL1_R, .type = ARM_CP_CONST,
4712               .resetvalue = cpu->id_aa64dfr1 },
4713             { .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4714               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2,
4715               .access = PL1_R, .type = ARM_CP_CONST,
4716               .resetvalue = 0 },
4717             { .name = "ID_AA64DFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4718               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 3,
4719               .access = PL1_R, .type = ARM_CP_CONST,
4720               .resetvalue = 0 },
4721             { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
4722               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
4723               .access = PL1_R, .type = ARM_CP_CONST,
4724               .resetvalue = cpu->id_aa64afr0 },
4725             { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
4726               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
4727               .access = PL1_R, .type = ARM_CP_CONST,
4728               .resetvalue = cpu->id_aa64afr1 },
4729             { .name = "ID_AA64AFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4730               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 6,
4731               .access = PL1_R, .type = ARM_CP_CONST,
4732               .resetvalue = 0 },
4733             { .name = "ID_AA64AFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4734               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 7,
4735               .access = PL1_R, .type = ARM_CP_CONST,
4736               .resetvalue = 0 },
4737             { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
4738               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
4739               .access = PL1_R, .type = ARM_CP_CONST,
4740               .resetvalue = cpu->id_aa64isar0 },
4741             { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
4742               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
4743               .access = PL1_R, .type = ARM_CP_CONST,
4744               .resetvalue = cpu->id_aa64isar1 },
4745             { .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4746               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2,
4747               .access = PL1_R, .type = ARM_CP_CONST,
4748               .resetvalue = 0 },
4749             { .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4750               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3,
4751               .access = PL1_R, .type = ARM_CP_CONST,
4752               .resetvalue = 0 },
4753             { .name = "ID_AA64ISAR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4754               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 4,
4755               .access = PL1_R, .type = ARM_CP_CONST,
4756               .resetvalue = 0 },
4757             { .name = "ID_AA64ISAR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4758               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 5,
4759               .access = PL1_R, .type = ARM_CP_CONST,
4760               .resetvalue = 0 },
4761             { .name = "ID_AA64ISAR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4762               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 6,
4763               .access = PL1_R, .type = ARM_CP_CONST,
4764               .resetvalue = 0 },
4765             { .name = "ID_AA64ISAR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4766               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 7,
4767               .access = PL1_R, .type = ARM_CP_CONST,
4768               .resetvalue = 0 },
4769             { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
4770               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
4771               .access = PL1_R, .type = ARM_CP_CONST,
4772               .resetvalue = cpu->id_aa64mmfr0 },
4773             { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
4774               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
4775               .access = PL1_R, .type = ARM_CP_CONST,
4776               .resetvalue = cpu->id_aa64mmfr1 },
4777             { .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4778               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2,
4779               .access = PL1_R, .type = ARM_CP_CONST,
4780               .resetvalue = 0 },
4781             { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4782               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3,
4783               .access = PL1_R, .type = ARM_CP_CONST,
4784               .resetvalue = 0 },
4785             { .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4786               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4,
4787               .access = PL1_R, .type = ARM_CP_CONST,
4788               .resetvalue = 0 },
4789             { .name = "ID_AA64MMFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4790               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5,
4791               .access = PL1_R, .type = ARM_CP_CONST,
4792               .resetvalue = 0 },
4793             { .name = "ID_AA64MMFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4794               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 6,
4795               .access = PL1_R, .type = ARM_CP_CONST,
4796               .resetvalue = 0 },
4797             { .name = "ID_AA64MMFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4798               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 7,
4799               .access = PL1_R, .type = ARM_CP_CONST,
4800               .resetvalue = 0 },
4801             { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64,
4802               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0,
4803               .access = PL1_R, .type = ARM_CP_CONST,
4804               .resetvalue = cpu->mvfr0 },
4805             { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64,
4806               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1,
4807               .access = PL1_R, .type = ARM_CP_CONST,
4808               .resetvalue = cpu->mvfr1 },
4809             { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64,
4810               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
4811               .access = PL1_R, .type = ARM_CP_CONST,
4812               .resetvalue = cpu->mvfr2 },
4813             { .name = "MVFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4814               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3,
4815               .access = PL1_R, .type = ARM_CP_CONST,
4816               .resetvalue = 0 },
4817             { .name = "MVFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4818               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4,
4819               .access = PL1_R, .type = ARM_CP_CONST,
4820               .resetvalue = 0 },
4821             { .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4822               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5,
4823               .access = PL1_R, .type = ARM_CP_CONST,
4824               .resetvalue = 0 },
4825             { .name = "MVFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4826               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6,
4827               .access = PL1_R, .type = ARM_CP_CONST,
4828               .resetvalue = 0 },
4829             { .name = "MVFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4830               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7,
4831               .access = PL1_R, .type = ARM_CP_CONST,
4832               .resetvalue = 0 },
4833             { .name = "PMCEID0", .state = ARM_CP_STATE_AA32,
4834               .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6,
4835               .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
4836               .resetvalue = cpu->pmceid0 },
4837             { .name = "PMCEID0_EL0", .state = ARM_CP_STATE_AA64,
4838               .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 6,
4839               .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
4840               .resetvalue = cpu->pmceid0 },
4841             { .name = "PMCEID1", .state = ARM_CP_STATE_AA32,
4842               .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 7,
4843               .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
4844               .resetvalue = cpu->pmceid1 },
4845             { .name = "PMCEID1_EL0", .state = ARM_CP_STATE_AA64,
4846               .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7,
4847               .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
4848               .resetvalue = cpu->pmceid1 },
4849             REGINFO_SENTINEL
4850         };
4851         /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
4852         if (!arm_feature(env, ARM_FEATURE_EL3) &&
4853             !arm_feature(env, ARM_FEATURE_EL2)) {
4854             ARMCPRegInfo rvbar = {
4855                 .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
4856                 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
4857                 .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar
4858             };
4859             define_one_arm_cp_reg(cpu, &rvbar);
4860         }
4861         define_arm_cp_regs(cpu, v8_idregs);
4862         define_arm_cp_regs(cpu, v8_cp_reginfo);
4863     }
4864     if (arm_feature(env, ARM_FEATURE_EL2)) {
4865         uint64_t vmpidr_def = mpidr_read_val(env);
4866         ARMCPRegInfo vpidr_regs[] = {
4867             { .name = "VPIDR", .state = ARM_CP_STATE_AA32,
4868               .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
4869               .access = PL2_RW, .accessfn = access_el3_aa32ns,
4870               .resetvalue = cpu->midr,
4871               .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
4872             { .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64,
4873               .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
4874               .access = PL2_RW, .resetvalue = cpu->midr,
4875               .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
4876             { .name = "VMPIDR", .state = ARM_CP_STATE_AA32,
4877               .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
4878               .access = PL2_RW, .accessfn = access_el3_aa32ns,
4879               .resetvalue = vmpidr_def,
4880               .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
4881             { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64,
4882               .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
4883               .access = PL2_RW,
4884               .resetvalue = vmpidr_def,
4885               .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
4886             REGINFO_SENTINEL
4887         };
4888         define_arm_cp_regs(cpu, vpidr_regs);
4889         define_arm_cp_regs(cpu, el2_cp_reginfo);
4890         /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
4891         if (!arm_feature(env, ARM_FEATURE_EL3)) {
4892             ARMCPRegInfo rvbar = {
4893                 .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64,
4894                 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1,
4895                 .type = ARM_CP_CONST, .access = PL2_R, .resetvalue = cpu->rvbar
4896             };
4897             define_one_arm_cp_reg(cpu, &rvbar);
4898         }
4899     } else {
4900         /* If EL2 is missing but higher ELs are enabled, we need to
4901          * register the no_el2 reginfos.
4902          */
4903         if (arm_feature(env, ARM_FEATURE_EL3)) {
4904             /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
4905              * of MIDR_EL1 and MPIDR_EL1.
4906              */
4907             ARMCPRegInfo vpidr_regs[] = {
4908                 { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH,
4909                   .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
4910                   .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
4911                   .type = ARM_CP_CONST, .resetvalue = cpu->midr,
4912                   .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
4913                 { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH,
4914                   .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
4915                   .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
4916                   .type = ARM_CP_NO_RAW,
4917                   .writefn = arm_cp_write_ignore, .readfn = mpidr_read },
4918                 REGINFO_SENTINEL
4919             };
4920             define_arm_cp_regs(cpu, vpidr_regs);
4921             define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo);
4922         }
4923     }
4924     if (arm_feature(env, ARM_FEATURE_EL3)) {
4925         define_arm_cp_regs(cpu, el3_cp_reginfo);
4926         ARMCPRegInfo el3_regs[] = {
4927             { .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64,
4928               .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1,
4929               .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar },
4930             { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64,
4931               .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0,
4932               .access = PL3_RW,
4933               .raw_writefn = raw_write, .writefn = sctlr_write,
4934               .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]),
4935               .resetvalue = cpu->reset_sctlr },
4936             REGINFO_SENTINEL
4937         };
4938 
4939         define_arm_cp_regs(cpu, el3_regs);
4940     }
4941     /* The behaviour of NSACR is sufficiently various that we don't
4942      * try to describe it in a single reginfo:
4943      *  if EL3 is 64 bit, then trap to EL3 from S EL1,
4944      *     reads as constant 0xc00 from NS EL1 and NS EL2
4945      *  if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2
4946      *  if v7 without EL3, register doesn't exist
4947      *  if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2
4948      */
4949     if (arm_feature(env, ARM_FEATURE_EL3)) {
4950         if (arm_feature(env, ARM_FEATURE_AARCH64)) {
4951             ARMCPRegInfo nsacr = {
4952                 .name = "NSACR", .type = ARM_CP_CONST,
4953                 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
4954                 .access = PL1_RW, .accessfn = nsacr_access,
4955                 .resetvalue = 0xc00
4956             };
4957             define_one_arm_cp_reg(cpu, &nsacr);
4958         } else {
4959             ARMCPRegInfo nsacr = {
4960                 .name = "NSACR",
4961                 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
4962                 .access = PL3_RW | PL1_R,
4963                 .resetvalue = 0,
4964                 .fieldoffset = offsetof(CPUARMState, cp15.nsacr)
4965             };
4966             define_one_arm_cp_reg(cpu, &nsacr);
4967         }
4968     } else {
4969         if (arm_feature(env, ARM_FEATURE_V8)) {
4970             ARMCPRegInfo nsacr = {
4971                 .name = "NSACR", .type = ARM_CP_CONST,
4972                 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
4973                 .access = PL1_R,
4974                 .resetvalue = 0xc00
4975             };
4976             define_one_arm_cp_reg(cpu, &nsacr);
4977         }
4978     }
4979 
4980     if (arm_feature(env, ARM_FEATURE_PMSA)) {
4981         if (arm_feature(env, ARM_FEATURE_V6)) {
4982             /* PMSAv6 not implemented */
4983             assert(arm_feature(env, ARM_FEATURE_V7));
4984             define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
4985             define_arm_cp_regs(cpu, pmsav7_cp_reginfo);
4986         } else {
4987             define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
4988         }
4989     } else {
4990         define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
4991         define_arm_cp_regs(cpu, vmsa_cp_reginfo);
4992     }
4993     if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
4994         define_arm_cp_regs(cpu, t2ee_cp_reginfo);
4995     }
4996     if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
4997         define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
4998     }
4999     if (arm_feature(env, ARM_FEATURE_VAPA)) {
5000         define_arm_cp_regs(cpu, vapa_cp_reginfo);
5001     }
5002     if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
5003         define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
5004     }
5005     if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
5006         define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
5007     }
5008     if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
5009         define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
5010     }
5011     if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
5012         define_arm_cp_regs(cpu, omap_cp_reginfo);
5013     }
5014     if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
5015         define_arm_cp_regs(cpu, strongarm_cp_reginfo);
5016     }
5017     if (arm_feature(env, ARM_FEATURE_XSCALE)) {
5018         define_arm_cp_regs(cpu, xscale_cp_reginfo);
5019     }
5020     if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
5021         define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
5022     }
5023     if (arm_feature(env, ARM_FEATURE_LPAE)) {
5024         define_arm_cp_regs(cpu, lpae_cp_reginfo);
5025     }
5026     /* Slightly awkwardly, the OMAP and StrongARM cores need all of
5027      * cp15 crn=0 to be writes-ignored, whereas for other cores they should
5028      * be read-only (ie write causes UNDEF exception).
5029      */
5030     {
5031         ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = {
5032             /* Pre-v8 MIDR space.
5033              * Note that the MIDR isn't a simple constant register because
5034              * of the TI925 behaviour where writes to another register can
5035              * cause the MIDR value to change.
5036              *
5037              * Unimplemented registers in the c15 0 0 0 space default to
5038              * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
5039              * and friends override accordingly.
5040              */
5041             { .name = "MIDR",
5042               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
5043               .access = PL1_R, .resetvalue = cpu->midr,
5044               .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
5045               .readfn = midr_read,
5046               .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
5047               .type = ARM_CP_OVERRIDE },
5048             /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
5049             { .name = "DUMMY",
5050               .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
5051               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
5052             { .name = "DUMMY",
5053               .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
5054               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
5055             { .name = "DUMMY",
5056               .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
5057               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
5058             { .name = "DUMMY",
5059               .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
5060               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
5061             { .name = "DUMMY",
5062               .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
5063               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
5064             REGINFO_SENTINEL
5065         };
5066         ARMCPRegInfo id_v8_midr_cp_reginfo[] = {
5067             { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
5068               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0,
5069               .access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr,
5070               .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
5071               .readfn = midr_read },
5072             /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
5073             { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
5074               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
5075               .access = PL1_R, .resetvalue = cpu->midr },
5076             { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
5077               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7,
5078               .access = PL1_R, .resetvalue = cpu->midr },
5079             { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH,
5080               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6,
5081               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->revidr },
5082             REGINFO_SENTINEL
5083         };
5084         ARMCPRegInfo id_cp_reginfo[] = {
5085             /* These are common to v8 and pre-v8 */
5086             { .name = "CTR",
5087               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
5088               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
5089             { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
5090               .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
5091               .access = PL0_R, .accessfn = ctr_el0_access,
5092               .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
5093             /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
5094             { .name = "TCMTR",
5095               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
5096               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
5097             REGINFO_SENTINEL
5098         };
5099         /* TLBTR is specific to VMSA */
5100         ARMCPRegInfo id_tlbtr_reginfo = {
5101               .name = "TLBTR",
5102               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
5103               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0,
5104         };
5105         /* MPUIR is specific to PMSA V6+ */
5106         ARMCPRegInfo id_mpuir_reginfo = {
5107               .name = "MPUIR",
5108               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
5109               .access = PL1_R, .type = ARM_CP_CONST,
5110               .resetvalue = cpu->pmsav7_dregion << 8
5111         };
5112         ARMCPRegInfo crn0_wi_reginfo = {
5113             .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
5114             .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
5115             .type = ARM_CP_NOP | ARM_CP_OVERRIDE
5116         };
5117         if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
5118             arm_feature(env, ARM_FEATURE_STRONGARM)) {
5119             ARMCPRegInfo *r;
5120             /* Register the blanket "writes ignored" value first to cover the
5121              * whole space. Then update the specific ID registers to allow write
5122              * access, so that they ignore writes rather than causing them to
5123              * UNDEF.
5124              */
5125             define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
5126             for (r = id_pre_v8_midr_cp_reginfo;
5127                  r->type != ARM_CP_SENTINEL; r++) {
5128                 r->access = PL1_RW;
5129             }
5130             for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
5131                 r->access = PL1_RW;
5132             }
5133             id_tlbtr_reginfo.access = PL1_RW;
5134             id_tlbtr_reginfo.access = PL1_RW;
5135         }
5136         if (arm_feature(env, ARM_FEATURE_V8)) {
5137             define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo);
5138         } else {
5139             define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo);
5140         }
5141         define_arm_cp_regs(cpu, id_cp_reginfo);
5142         if (!arm_feature(env, ARM_FEATURE_PMSA)) {
5143             define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo);
5144         } else if (arm_feature(env, ARM_FEATURE_V7)) {
5145             define_one_arm_cp_reg(cpu, &id_mpuir_reginfo);
5146         }
5147     }
5148 
5149     if (arm_feature(env, ARM_FEATURE_MPIDR)) {
5150         define_arm_cp_regs(cpu, mpidr_cp_reginfo);
5151     }
5152 
5153     if (arm_feature(env, ARM_FEATURE_AUXCR)) {
5154         ARMCPRegInfo auxcr_reginfo[] = {
5155             { .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH,
5156               .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1,
5157               .access = PL1_RW, .type = ARM_CP_CONST,
5158               .resetvalue = cpu->reset_auxcr },
5159             { .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH,
5160               .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1,
5161               .access = PL2_RW, .type = ARM_CP_CONST,
5162               .resetvalue = 0 },
5163             { .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64,
5164               .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1,
5165               .access = PL3_RW, .type = ARM_CP_CONST,
5166               .resetvalue = 0 },
5167             REGINFO_SENTINEL
5168         };
5169         define_arm_cp_regs(cpu, auxcr_reginfo);
5170     }
5171 
5172     if (arm_feature(env, ARM_FEATURE_CBAR)) {
5173         if (arm_feature(env, ARM_FEATURE_AARCH64)) {
5174             /* 32 bit view is [31:18] 0...0 [43:32]. */
5175             uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18)
5176                 | extract64(cpu->reset_cbar, 32, 12);
5177             ARMCPRegInfo cbar_reginfo[] = {
5178                 { .name = "CBAR",
5179                   .type = ARM_CP_CONST,
5180                   .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
5181                   .access = PL1_R, .resetvalue = cpu->reset_cbar },
5182                 { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64,
5183                   .type = ARM_CP_CONST,
5184                   .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0,
5185                   .access = PL1_R, .resetvalue = cbar32 },
5186                 REGINFO_SENTINEL
5187             };
5188             /* We don't implement a r/w 64 bit CBAR currently */
5189             assert(arm_feature(env, ARM_FEATURE_CBAR_RO));
5190             define_arm_cp_regs(cpu, cbar_reginfo);
5191         } else {
5192             ARMCPRegInfo cbar = {
5193                 .name = "CBAR",
5194                 .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
5195                 .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
5196                 .fieldoffset = offsetof(CPUARMState,
5197                                         cp15.c15_config_base_address)
5198             };
5199             if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
5200                 cbar.access = PL1_R;
5201                 cbar.fieldoffset = 0;
5202                 cbar.type = ARM_CP_CONST;
5203             }
5204             define_one_arm_cp_reg(cpu, &cbar);
5205         }
5206     }
5207 
5208     if (arm_feature(env, ARM_FEATURE_VBAR)) {
5209         ARMCPRegInfo vbar_cp_reginfo[] = {
5210             { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
5211               .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
5212               .access = PL1_RW, .writefn = vbar_write,
5213               .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s),
5214                                      offsetof(CPUARMState, cp15.vbar_ns) },
5215               .resetvalue = 0 },
5216             REGINFO_SENTINEL
5217         };
5218         define_arm_cp_regs(cpu, vbar_cp_reginfo);
5219     }
5220 
5221     /* Generic registers whose values depend on the implementation */
5222     {
5223         ARMCPRegInfo sctlr = {
5224             .name = "SCTLR", .state = ARM_CP_STATE_BOTH,
5225             .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
5226             .access = PL1_RW,
5227             .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s),
5228                                    offsetof(CPUARMState, cp15.sctlr_ns) },
5229             .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
5230             .raw_writefn = raw_write,
5231         };
5232         if (arm_feature(env, ARM_FEATURE_XSCALE)) {
5233             /* Normally we would always end the TB on an SCTLR write, but Linux
5234              * arch/arm/mach-pxa/sleep.S expects two instructions following
5235              * an MMU enable to execute from cache.  Imitate this behaviour.
5236              */
5237             sctlr.type |= ARM_CP_SUPPRESS_TB_END;
5238         }
5239         define_one_arm_cp_reg(cpu, &sctlr);
5240     }
5241 }
5242 
5243 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
5244 {
5245     CPUState *cs = CPU(cpu);
5246     CPUARMState *env = &cpu->env;
5247 
5248     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
5249         gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
5250                                  aarch64_fpu_gdb_set_reg,
5251                                  34, "aarch64-fpu.xml", 0);
5252     } else if (arm_feature(env, ARM_FEATURE_NEON)) {
5253         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
5254                                  51, "arm-neon.xml", 0);
5255     } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
5256         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
5257                                  35, "arm-vfp3.xml", 0);
5258     } else if (arm_feature(env, ARM_FEATURE_VFP)) {
5259         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
5260                                  19, "arm-vfp.xml", 0);
5261     }
5262 }
5263 
5264 /* Sort alphabetically by type name, except for "any". */
5265 static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
5266 {
5267     ObjectClass *class_a = (ObjectClass *)a;
5268     ObjectClass *class_b = (ObjectClass *)b;
5269     const char *name_a, *name_b;
5270 
5271     name_a = object_class_get_name(class_a);
5272     name_b = object_class_get_name(class_b);
5273     if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) {
5274         return 1;
5275     } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) {
5276         return -1;
5277     } else {
5278         return strcmp(name_a, name_b);
5279     }
5280 }
5281 
5282 static void arm_cpu_list_entry(gpointer data, gpointer user_data)
5283 {
5284     ObjectClass *oc = data;
5285     CPUListState *s = user_data;
5286     const char *typename;
5287     char *name;
5288 
5289     typename = object_class_get_name(oc);
5290     name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
5291     (*s->cpu_fprintf)(s->file, "  %s\n",
5292                       name);
5293     g_free(name);
5294 }
5295 
5296 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
5297 {
5298     CPUListState s = {
5299         .file = f,
5300         .cpu_fprintf = cpu_fprintf,
5301     };
5302     GSList *list;
5303 
5304     list = object_class_get_list(TYPE_ARM_CPU, false);
5305     list = g_slist_sort(list, arm_cpu_list_compare);
5306     (*cpu_fprintf)(f, "Available CPUs:\n");
5307     g_slist_foreach(list, arm_cpu_list_entry, &s);
5308     g_slist_free(list);
5309 #ifdef CONFIG_KVM
5310     /* The 'host' CPU type is dynamically registered only if KVM is
5311      * enabled, so we have to special-case it here:
5312      */
5313     (*cpu_fprintf)(f, "  host (only available in KVM mode)\n");
5314 #endif
5315 }
5316 
5317 static void arm_cpu_add_definition(gpointer data, gpointer user_data)
5318 {
5319     ObjectClass *oc = data;
5320     CpuDefinitionInfoList **cpu_list = user_data;
5321     CpuDefinitionInfoList *entry;
5322     CpuDefinitionInfo *info;
5323     const char *typename;
5324 
5325     typename = object_class_get_name(oc);
5326     info = g_malloc0(sizeof(*info));
5327     info->name = g_strndup(typename,
5328                            strlen(typename) - strlen("-" TYPE_ARM_CPU));
5329     info->q_typename = g_strdup(typename);
5330 
5331     entry = g_malloc0(sizeof(*entry));
5332     entry->value = info;
5333     entry->next = *cpu_list;
5334     *cpu_list = entry;
5335 }
5336 
5337 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
5338 {
5339     CpuDefinitionInfoList *cpu_list = NULL;
5340     GSList *list;
5341 
5342     list = object_class_get_list(TYPE_ARM_CPU, false);
5343     g_slist_foreach(list, arm_cpu_add_definition, &cpu_list);
5344     g_slist_free(list);
5345 
5346     return cpu_list;
5347 }
5348 
5349 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
5350                                    void *opaque, int state, int secstate,
5351                                    int crm, int opc1, int opc2)
5352 {
5353     /* Private utility function for define_one_arm_cp_reg_with_opaque():
5354      * add a single reginfo struct to the hash table.
5355      */
5356     uint32_t *key = g_new(uint32_t, 1);
5357     ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
5358     int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
5359     int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
5360 
5361     /* Reset the secure state to the specific incoming state.  This is
5362      * necessary as the register may have been defined with both states.
5363      */
5364     r2->secure = secstate;
5365 
5366     if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
5367         /* Register is banked (using both entries in array).
5368          * Overwriting fieldoffset as the array is only used to define
5369          * banked registers but later only fieldoffset is used.
5370          */
5371         r2->fieldoffset = r->bank_fieldoffsets[ns];
5372     }
5373 
5374     if (state == ARM_CP_STATE_AA32) {
5375         if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
5376             /* If the register is banked then we don't need to migrate or
5377              * reset the 32-bit instance in certain cases:
5378              *
5379              * 1) If the register has both 32-bit and 64-bit instances then we
5380              *    can count on the 64-bit instance taking care of the
5381              *    non-secure bank.
5382              * 2) If ARMv8 is enabled then we can count on a 64-bit version
5383              *    taking care of the secure bank.  This requires that separate
5384              *    32 and 64-bit definitions are provided.
5385              */
5386             if ((r->state == ARM_CP_STATE_BOTH && ns) ||
5387                 (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) {
5388                 r2->type |= ARM_CP_ALIAS;
5389             }
5390         } else if ((secstate != r->secure) && !ns) {
5391             /* The register is not banked so we only want to allow migration of
5392              * the non-secure instance.
5393              */
5394             r2->type |= ARM_CP_ALIAS;
5395         }
5396 
5397         if (r->state == ARM_CP_STATE_BOTH) {
5398             /* We assume it is a cp15 register if the .cp field is left unset.
5399              */
5400             if (r2->cp == 0) {
5401                 r2->cp = 15;
5402             }
5403 
5404 #ifdef HOST_WORDS_BIGENDIAN
5405             if (r2->fieldoffset) {
5406                 r2->fieldoffset += sizeof(uint32_t);
5407             }
5408 #endif
5409         }
5410     }
5411     if (state == ARM_CP_STATE_AA64) {
5412         /* To allow abbreviation of ARMCPRegInfo
5413          * definitions, we treat cp == 0 as equivalent to
5414          * the value for "standard guest-visible sysreg".
5415          * STATE_BOTH definitions are also always "standard
5416          * sysreg" in their AArch64 view (the .cp value may
5417          * be non-zero for the benefit of the AArch32 view).
5418          */
5419         if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) {
5420             r2->cp = CP_REG_ARM64_SYSREG_CP;
5421         }
5422         *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
5423                                   r2->opc0, opc1, opc2);
5424     } else {
5425         *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2);
5426     }
5427     if (opaque) {
5428         r2->opaque = opaque;
5429     }
5430     /* reginfo passed to helpers is correct for the actual access,
5431      * and is never ARM_CP_STATE_BOTH:
5432      */
5433     r2->state = state;
5434     /* Make sure reginfo passed to helpers for wildcarded regs
5435      * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
5436      */
5437     r2->crm = crm;
5438     r2->opc1 = opc1;
5439     r2->opc2 = opc2;
5440     /* By convention, for wildcarded registers only the first
5441      * entry is used for migration; the others are marked as
5442      * ALIAS so we don't try to transfer the register
5443      * multiple times. Special registers (ie NOP/WFI) are
5444      * never migratable and not even raw-accessible.
5445      */
5446     if ((r->type & ARM_CP_SPECIAL)) {
5447         r2->type |= ARM_CP_NO_RAW;
5448     }
5449     if (((r->crm == CP_ANY) && crm != 0) ||
5450         ((r->opc1 == CP_ANY) && opc1 != 0) ||
5451         ((r->opc2 == CP_ANY) && opc2 != 0)) {
5452         r2->type |= ARM_CP_ALIAS;
5453     }
5454 
5455     /* Check that raw accesses are either forbidden or handled. Note that
5456      * we can't assert this earlier because the setup of fieldoffset for
5457      * banked registers has to be done first.
5458      */
5459     if (!(r2->type & ARM_CP_NO_RAW)) {
5460         assert(!raw_accessors_invalid(r2));
5461     }
5462 
5463     /* Overriding of an existing definition must be explicitly
5464      * requested.
5465      */
5466     if (!(r->type & ARM_CP_OVERRIDE)) {
5467         ARMCPRegInfo *oldreg;
5468         oldreg = g_hash_table_lookup(cpu->cp_regs, key);
5469         if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
5470             fprintf(stderr, "Register redefined: cp=%d %d bit "
5471                     "crn=%d crm=%d opc1=%d opc2=%d, "
5472                     "was %s, now %s\n", r2->cp, 32 + 32 * is64,
5473                     r2->crn, r2->crm, r2->opc1, r2->opc2,
5474                     oldreg->name, r2->name);
5475             g_assert_not_reached();
5476         }
5477     }
5478     g_hash_table_insert(cpu->cp_regs, key, r2);
5479 }
5480 
5481 
5482 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
5483                                        const ARMCPRegInfo *r, void *opaque)
5484 {
5485     /* Define implementations of coprocessor registers.
5486      * We store these in a hashtable because typically
5487      * there are less than 150 registers in a space which
5488      * is 16*16*16*8*8 = 262144 in size.
5489      * Wildcarding is supported for the crm, opc1 and opc2 fields.
5490      * If a register is defined twice then the second definition is
5491      * used, so this can be used to define some generic registers and
5492      * then override them with implementation specific variations.
5493      * At least one of the original and the second definition should
5494      * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
5495      * against accidental use.
5496      *
5497      * The state field defines whether the register is to be
5498      * visible in the AArch32 or AArch64 execution state. If the
5499      * state is set to ARM_CP_STATE_BOTH then we synthesise a
5500      * reginfo structure for the AArch32 view, which sees the lower
5501      * 32 bits of the 64 bit register.
5502      *
5503      * Only registers visible in AArch64 may set r->opc0; opc0 cannot
5504      * be wildcarded. AArch64 registers are always considered to be 64
5505      * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
5506      * the register, if any.
5507      */
5508     int crm, opc1, opc2, state;
5509     int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
5510     int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
5511     int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
5512     int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
5513     int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
5514     int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
5515     /* 64 bit registers have only CRm and Opc1 fields */
5516     assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
5517     /* op0 only exists in the AArch64 encodings */
5518     assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0));
5519     /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
5520     assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT));
5521     /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
5522      * encodes a minimum access level for the register. We roll this
5523      * runtime check into our general permission check code, so check
5524      * here that the reginfo's specified permissions are strict enough
5525      * to encompass the generic architectural permission check.
5526      */
5527     if (r->state != ARM_CP_STATE_AA32) {
5528         int mask = 0;
5529         switch (r->opc1) {
5530         case 0: case 1: case 2:
5531             /* min_EL EL1 */
5532             mask = PL1_RW;
5533             break;
5534         case 3:
5535             /* min_EL EL0 */
5536             mask = PL0_RW;
5537             break;
5538         case 4:
5539             /* min_EL EL2 */
5540             mask = PL2_RW;
5541             break;
5542         case 5:
5543             /* unallocated encoding, so not possible */
5544             assert(false);
5545             break;
5546         case 6:
5547             /* min_EL EL3 */
5548             mask = PL3_RW;
5549             break;
5550         case 7:
5551             /* min_EL EL1, secure mode only (we don't check the latter) */
5552             mask = PL1_RW;
5553             break;
5554         default:
5555             /* broken reginfo with out-of-range opc1 */
5556             assert(false);
5557             break;
5558         }
5559         /* assert our permissions are not too lax (stricter is fine) */
5560         assert((r->access & ~mask) == 0);
5561     }
5562 
5563     /* Check that the register definition has enough info to handle
5564      * reads and writes if they are permitted.
5565      */
5566     if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
5567         if (r->access & PL3_R) {
5568             assert((r->fieldoffset ||
5569                    (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
5570                    r->readfn);
5571         }
5572         if (r->access & PL3_W) {
5573             assert((r->fieldoffset ||
5574                    (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
5575                    r->writefn);
5576         }
5577     }
5578     /* Bad type field probably means missing sentinel at end of reg list */
5579     assert(cptype_valid(r->type));
5580     for (crm = crmmin; crm <= crmmax; crm++) {
5581         for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
5582             for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
5583                 for (state = ARM_CP_STATE_AA32;
5584                      state <= ARM_CP_STATE_AA64; state++) {
5585                     if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
5586                         continue;
5587                     }
5588                     if (state == ARM_CP_STATE_AA32) {
5589                         /* Under AArch32 CP registers can be common
5590                          * (same for secure and non-secure world) or banked.
5591                          */
5592                         switch (r->secure) {
5593                         case ARM_CP_SECSTATE_S:
5594                         case ARM_CP_SECSTATE_NS:
5595                             add_cpreg_to_hashtable(cpu, r, opaque, state,
5596                                                    r->secure, crm, opc1, opc2);
5597                             break;
5598                         default:
5599                             add_cpreg_to_hashtable(cpu, r, opaque, state,
5600                                                    ARM_CP_SECSTATE_S,
5601                                                    crm, opc1, opc2);
5602                             add_cpreg_to_hashtable(cpu, r, opaque, state,
5603                                                    ARM_CP_SECSTATE_NS,
5604                                                    crm, opc1, opc2);
5605                             break;
5606                         }
5607                     } else {
5608                         /* AArch64 registers get mapped to non-secure instance
5609                          * of AArch32 */
5610                         add_cpreg_to_hashtable(cpu, r, opaque, state,
5611                                                ARM_CP_SECSTATE_NS,
5612                                                crm, opc1, opc2);
5613                     }
5614                 }
5615             }
5616         }
5617     }
5618 }
5619 
5620 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
5621                                     const ARMCPRegInfo *regs, void *opaque)
5622 {
5623     /* Define a whole list of registers */
5624     const ARMCPRegInfo *r;
5625     for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
5626         define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
5627     }
5628 }
5629 
5630 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
5631 {
5632     return g_hash_table_lookup(cpregs, &encoded_cp);
5633 }
5634 
5635 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
5636                          uint64_t value)
5637 {
5638     /* Helper coprocessor write function for write-ignore registers */
5639 }
5640 
5641 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri)
5642 {
5643     /* Helper coprocessor write function for read-as-zero registers */
5644     return 0;
5645 }
5646 
5647 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
5648 {
5649     /* Helper coprocessor reset function for do-nothing-on-reset registers */
5650 }
5651 
5652 static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type)
5653 {
5654     /* Return true if it is not valid for us to switch to
5655      * this CPU mode (ie all the UNPREDICTABLE cases in
5656      * the ARM ARM CPSRWriteByInstr pseudocode).
5657      */
5658 
5659     /* Changes to or from Hyp via MSR and CPS are illegal. */
5660     if (write_type == CPSRWriteByInstr &&
5661         ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_HYP ||
5662          mode == ARM_CPU_MODE_HYP)) {
5663         return 1;
5664     }
5665 
5666     switch (mode) {
5667     case ARM_CPU_MODE_USR:
5668         return 0;
5669     case ARM_CPU_MODE_SYS:
5670     case ARM_CPU_MODE_SVC:
5671     case ARM_CPU_MODE_ABT:
5672     case ARM_CPU_MODE_UND:
5673     case ARM_CPU_MODE_IRQ:
5674     case ARM_CPU_MODE_FIQ:
5675         /* Note that we don't implement the IMPDEF NSACR.RFR which in v7
5676          * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
5677          */
5678         /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
5679          * and CPS are treated as illegal mode changes.
5680          */
5681         if (write_type == CPSRWriteByInstr &&
5682             (env->cp15.hcr_el2 & HCR_TGE) &&
5683             (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON &&
5684             !arm_is_secure_below_el3(env)) {
5685             return 1;
5686         }
5687         return 0;
5688     case ARM_CPU_MODE_HYP:
5689         return !arm_feature(env, ARM_FEATURE_EL2)
5690             || arm_current_el(env) < 2 || arm_is_secure(env);
5691     case ARM_CPU_MODE_MON:
5692         return arm_current_el(env) < 3;
5693     default:
5694         return 1;
5695     }
5696 }
5697 
5698 uint32_t cpsr_read(CPUARMState *env)
5699 {
5700     int ZF;
5701     ZF = (env->ZF == 0);
5702     return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
5703         (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
5704         | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
5705         | ((env->condexec_bits & 0xfc) << 8)
5706         | (env->GE << 16) | (env->daif & CPSR_AIF);
5707 }
5708 
5709 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
5710                 CPSRWriteType write_type)
5711 {
5712     uint32_t changed_daif;
5713 
5714     if (mask & CPSR_NZCV) {
5715         env->ZF = (~val) & CPSR_Z;
5716         env->NF = val;
5717         env->CF = (val >> 29) & 1;
5718         env->VF = (val << 3) & 0x80000000;
5719     }
5720     if (mask & CPSR_Q)
5721         env->QF = ((val & CPSR_Q) != 0);
5722     if (mask & CPSR_T)
5723         env->thumb = ((val & CPSR_T) != 0);
5724     if (mask & CPSR_IT_0_1) {
5725         env->condexec_bits &= ~3;
5726         env->condexec_bits |= (val >> 25) & 3;
5727     }
5728     if (mask & CPSR_IT_2_7) {
5729         env->condexec_bits &= 3;
5730         env->condexec_bits |= (val >> 8) & 0xfc;
5731     }
5732     if (mask & CPSR_GE) {
5733         env->GE = (val >> 16) & 0xf;
5734     }
5735 
5736     /* In a V7 implementation that includes the security extensions but does
5737      * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
5738      * whether non-secure software is allowed to change the CPSR_F and CPSR_A
5739      * bits respectively.
5740      *
5741      * In a V8 implementation, it is permitted for privileged software to
5742      * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
5743      */
5744     if (write_type != CPSRWriteRaw && !arm_feature(env, ARM_FEATURE_V8) &&
5745         arm_feature(env, ARM_FEATURE_EL3) &&
5746         !arm_feature(env, ARM_FEATURE_EL2) &&
5747         !arm_is_secure(env)) {
5748 
5749         changed_daif = (env->daif ^ val) & mask;
5750 
5751         if (changed_daif & CPSR_A) {
5752             /* Check to see if we are allowed to change the masking of async
5753              * abort exceptions from a non-secure state.
5754              */
5755             if (!(env->cp15.scr_el3 & SCR_AW)) {
5756                 qemu_log_mask(LOG_GUEST_ERROR,
5757                               "Ignoring attempt to switch CPSR_A flag from "
5758                               "non-secure world with SCR.AW bit clear\n");
5759                 mask &= ~CPSR_A;
5760             }
5761         }
5762 
5763         if (changed_daif & CPSR_F) {
5764             /* Check to see if we are allowed to change the masking of FIQ
5765              * exceptions from a non-secure state.
5766              */
5767             if (!(env->cp15.scr_el3 & SCR_FW)) {
5768                 qemu_log_mask(LOG_GUEST_ERROR,
5769                               "Ignoring attempt to switch CPSR_F flag from "
5770                               "non-secure world with SCR.FW bit clear\n");
5771                 mask &= ~CPSR_F;
5772             }
5773 
5774             /* Check whether non-maskable FIQ (NMFI) support is enabled.
5775              * If this bit is set software is not allowed to mask
5776              * FIQs, but is allowed to set CPSR_F to 0.
5777              */
5778             if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) &&
5779                 (val & CPSR_F)) {
5780                 qemu_log_mask(LOG_GUEST_ERROR,
5781                               "Ignoring attempt to enable CPSR_F flag "
5782                               "(non-maskable FIQ [NMFI] support enabled)\n");
5783                 mask &= ~CPSR_F;
5784             }
5785         }
5786     }
5787 
5788     env->daif &= ~(CPSR_AIF & mask);
5789     env->daif |= val & CPSR_AIF & mask;
5790 
5791     if (write_type != CPSRWriteRaw &&
5792         ((env->uncached_cpsr ^ val) & mask & CPSR_M)) {
5793         if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR) {
5794             /* Note that we can only get here in USR mode if this is a
5795              * gdb stub write; for this case we follow the architectural
5796              * behaviour for guest writes in USR mode of ignoring an attempt
5797              * to switch mode. (Those are caught by translate.c for writes
5798              * triggered by guest instructions.)
5799              */
5800             mask &= ~CPSR_M;
5801         } else if (bad_mode_switch(env, val & CPSR_M, write_type)) {
5802             /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in
5803              * v7, and has defined behaviour in v8:
5804              *  + leave CPSR.M untouched
5805              *  + allow changes to the other CPSR fields
5806              *  + set PSTATE.IL
5807              * For user changes via the GDB stub, we don't set PSTATE.IL,
5808              * as this would be unnecessarily harsh for a user error.
5809              */
5810             mask &= ~CPSR_M;
5811             if (write_type != CPSRWriteByGDBStub &&
5812                 arm_feature(env, ARM_FEATURE_V8)) {
5813                 mask |= CPSR_IL;
5814                 val |= CPSR_IL;
5815             }
5816         } else {
5817             switch_mode(env, val & CPSR_M);
5818         }
5819     }
5820     mask &= ~CACHED_CPSR_BITS;
5821     env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
5822 }
5823 
5824 /* Sign/zero extend */
5825 uint32_t HELPER(sxtb16)(uint32_t x)
5826 {
5827     uint32_t res;
5828     res = (uint16_t)(int8_t)x;
5829     res |= (uint32_t)(int8_t)(x >> 16) << 16;
5830     return res;
5831 }
5832 
5833 uint32_t HELPER(uxtb16)(uint32_t x)
5834 {
5835     uint32_t res;
5836     res = (uint16_t)(uint8_t)x;
5837     res |= (uint32_t)(uint8_t)(x >> 16) << 16;
5838     return res;
5839 }
5840 
5841 int32_t HELPER(sdiv)(int32_t num, int32_t den)
5842 {
5843     if (den == 0)
5844       return 0;
5845     if (num == INT_MIN && den == -1)
5846       return INT_MIN;
5847     return num / den;
5848 }
5849 
5850 uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
5851 {
5852     if (den == 0)
5853       return 0;
5854     return num / den;
5855 }
5856 
5857 uint32_t HELPER(rbit)(uint32_t x)
5858 {
5859     return revbit32(x);
5860 }
5861 
5862 #if defined(CONFIG_USER_ONLY)
5863 
5864 /* These should probably raise undefined insn exceptions.  */
5865 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
5866 {
5867     ARMCPU *cpu = arm_env_get_cpu(env);
5868 
5869     cpu_abort(CPU(cpu), "v7m_msr %d\n", reg);
5870 }
5871 
5872 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
5873 {
5874     ARMCPU *cpu = arm_env_get_cpu(env);
5875 
5876     cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg);
5877     return 0;
5878 }
5879 
5880 void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)
5881 {
5882     /* translate.c should never generate calls here in user-only mode */
5883     g_assert_not_reached();
5884 }
5885 
5886 void switch_mode(CPUARMState *env, int mode)
5887 {
5888     ARMCPU *cpu = arm_env_get_cpu(env);
5889 
5890     if (mode != ARM_CPU_MODE_USR) {
5891         cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
5892     }
5893 }
5894 
5895 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
5896                                  uint32_t cur_el, bool secure)
5897 {
5898     return 1;
5899 }
5900 
5901 void aarch64_sync_64_to_32(CPUARMState *env)
5902 {
5903     g_assert_not_reached();
5904 }
5905 
5906 #else
5907 
5908 void switch_mode(CPUARMState *env, int mode)
5909 {
5910     int old_mode;
5911     int i;
5912 
5913     old_mode = env->uncached_cpsr & CPSR_M;
5914     if (mode == old_mode)
5915         return;
5916 
5917     if (old_mode == ARM_CPU_MODE_FIQ) {
5918         memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
5919         memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
5920     } else if (mode == ARM_CPU_MODE_FIQ) {
5921         memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
5922         memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
5923     }
5924 
5925     i = bank_number(old_mode);
5926     env->banked_r13[i] = env->regs[13];
5927     env->banked_r14[i] = env->regs[14];
5928     env->banked_spsr[i] = env->spsr;
5929 
5930     i = bank_number(mode);
5931     env->regs[13] = env->banked_r13[i];
5932     env->regs[14] = env->banked_r14[i];
5933     env->spsr = env->banked_spsr[i];
5934 }
5935 
5936 /* Physical Interrupt Target EL Lookup Table
5937  *
5938  * [ From ARM ARM section G1.13.4 (Table G1-15) ]
5939  *
5940  * The below multi-dimensional table is used for looking up the target
5941  * exception level given numerous condition criteria.  Specifically, the
5942  * target EL is based on SCR and HCR routing controls as well as the
5943  * currently executing EL and secure state.
5944  *
5945  *    Dimensions:
5946  *    target_el_table[2][2][2][2][2][4]
5947  *                    |  |  |  |  |  +--- Current EL
5948  *                    |  |  |  |  +------ Non-secure(0)/Secure(1)
5949  *                    |  |  |  +--------- HCR mask override
5950  *                    |  |  +------------ SCR exec state control
5951  *                    |  +--------------- SCR mask override
5952  *                    +------------------ 32-bit(0)/64-bit(1) EL3
5953  *
5954  *    The table values are as such:
5955  *    0-3 = EL0-EL3
5956  *     -1 = Cannot occur
5957  *
5958  * The ARM ARM target EL table includes entries indicating that an "exception
5959  * is not taken".  The two cases where this is applicable are:
5960  *    1) An exception is taken from EL3 but the SCR does not have the exception
5961  *    routed to EL3.
5962  *    2) An exception is taken from EL2 but the HCR does not have the exception
5963  *    routed to EL2.
5964  * In these two cases, the below table contain a target of EL1.  This value is
5965  * returned as it is expected that the consumer of the table data will check
5966  * for "target EL >= current EL" to ensure the exception is not taken.
5967  *
5968  *            SCR     HCR
5969  *         64  EA     AMO                 From
5970  *        BIT IRQ     IMO      Non-secure         Secure
5971  *        EL3 FIQ  RW FMO   EL0 EL1 EL2 EL3   EL0 EL1 EL2 EL3
5972  */
5973 static const int8_t target_el_table[2][2][2][2][2][4] = {
5974     {{{{/* 0   0   0   0 */{ 1,  1,  2, -1 },{ 3, -1, -1,  3 },},
5975        {/* 0   0   0   1 */{ 2,  2,  2, -1 },{ 3, -1, -1,  3 },},},
5976       {{/* 0   0   1   0 */{ 1,  1,  2, -1 },{ 3, -1, -1,  3 },},
5977        {/* 0   0   1   1 */{ 2,  2,  2, -1 },{ 3, -1, -1,  3 },},},},
5978      {{{/* 0   1   0   0 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},
5979        {/* 0   1   0   1 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},},
5980       {{/* 0   1   1   0 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},
5981        {/* 0   1   1   1 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},},},},
5982     {{{{/* 1   0   0   0 */{ 1,  1,  2, -1 },{ 1,  1, -1,  1 },},
5983        {/* 1   0   0   1 */{ 2,  2,  2, -1 },{ 1,  1, -1,  1 },},},
5984       {{/* 1   0   1   0 */{ 1,  1,  1, -1 },{ 1,  1, -1,  1 },},
5985        {/* 1   0   1   1 */{ 2,  2,  2, -1 },{ 1,  1, -1,  1 },},},},
5986      {{{/* 1   1   0   0 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},
5987        {/* 1   1   0   1 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},},
5988       {{/* 1   1   1   0 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},
5989        {/* 1   1   1   1 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},},},},
5990 };
5991 
5992 /*
5993  * Determine the target EL for physical exceptions
5994  */
5995 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
5996                                  uint32_t cur_el, bool secure)
5997 {
5998     CPUARMState *env = cs->env_ptr;
5999     int rw;
6000     int scr;
6001     int hcr;
6002     int target_el;
6003     /* Is the highest EL AArch64? */
6004     int is64 = arm_feature(env, ARM_FEATURE_AARCH64);
6005 
6006     if (arm_feature(env, ARM_FEATURE_EL3)) {
6007         rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW);
6008     } else {
6009         /* Either EL2 is the highest EL (and so the EL2 register width
6010          * is given by is64); or there is no EL2 or EL3, in which case
6011          * the value of 'rw' does not affect the table lookup anyway.
6012          */
6013         rw = is64;
6014     }
6015 
6016     switch (excp_idx) {
6017     case EXCP_IRQ:
6018         scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ);
6019         hcr = ((env->cp15.hcr_el2 & HCR_IMO) == HCR_IMO);
6020         break;
6021     case EXCP_FIQ:
6022         scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ);
6023         hcr = ((env->cp15.hcr_el2 & HCR_FMO) == HCR_FMO);
6024         break;
6025     default:
6026         scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA);
6027         hcr = ((env->cp15.hcr_el2 & HCR_AMO) == HCR_AMO);
6028         break;
6029     };
6030 
6031     /* If HCR.TGE is set then HCR is treated as being 1 */
6032     hcr |= ((env->cp15.hcr_el2 & HCR_TGE) == HCR_TGE);
6033 
6034     /* Perform a table-lookup for the target EL given the current state */
6035     target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el];
6036 
6037     assert(target_el > 0);
6038 
6039     return target_el;
6040 }
6041 
6042 static void v7m_push(CPUARMState *env, uint32_t val)
6043 {
6044     CPUState *cs = CPU(arm_env_get_cpu(env));
6045 
6046     env->regs[13] -= 4;
6047     stl_phys(cs->as, env->regs[13], val);
6048 }
6049 
6050 /* Return true if we're using the process stack pointer (not the MSP) */
6051 static bool v7m_using_psp(CPUARMState *env)
6052 {
6053     /* Handler mode always uses the main stack; for thread mode
6054      * the CONTROL.SPSEL bit determines the answer.
6055      * Note that in v7M it is not possible to be in Handler mode with
6056      * CONTROL.SPSEL non-zero, but in v8M it is, so we must check both.
6057      */
6058     return !arm_v7m_is_handler_mode(env) &&
6059         env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK;
6060 }
6061 
6062 /* Write to v7M CONTROL.SPSEL bit for the specified security bank.
6063  * This may change the current stack pointer between Main and Process
6064  * stack pointers if it is done for the CONTROL register for the current
6065  * security state.
6066  */
6067 static void write_v7m_control_spsel_for_secstate(CPUARMState *env,
6068                                                  bool new_spsel,
6069                                                  bool secstate)
6070 {
6071     bool old_is_psp = v7m_using_psp(env);
6072 
6073     env->v7m.control[secstate] =
6074         deposit32(env->v7m.control[secstate],
6075                   R_V7M_CONTROL_SPSEL_SHIFT,
6076                   R_V7M_CONTROL_SPSEL_LENGTH, new_spsel);
6077 
6078     if (secstate == env->v7m.secure) {
6079         bool new_is_psp = v7m_using_psp(env);
6080         uint32_t tmp;
6081 
6082         if (old_is_psp != new_is_psp) {
6083             tmp = env->v7m.other_sp;
6084             env->v7m.other_sp = env->regs[13];
6085             env->regs[13] = tmp;
6086         }
6087     }
6088 }
6089 
6090 /* Write to v7M CONTROL.SPSEL bit. This may change the current
6091  * stack pointer between Main and Process stack pointers.
6092  */
6093 static void write_v7m_control_spsel(CPUARMState *env, bool new_spsel)
6094 {
6095     write_v7m_control_spsel_for_secstate(env, new_spsel, env->v7m.secure);
6096 }
6097 
6098 void write_v7m_exception(CPUARMState *env, uint32_t new_exc)
6099 {
6100     /* Write a new value to v7m.exception, thus transitioning into or out
6101      * of Handler mode; this may result in a change of active stack pointer.
6102      */
6103     bool new_is_psp, old_is_psp = v7m_using_psp(env);
6104     uint32_t tmp;
6105 
6106     env->v7m.exception = new_exc;
6107 
6108     new_is_psp = v7m_using_psp(env);
6109 
6110     if (old_is_psp != new_is_psp) {
6111         tmp = env->v7m.other_sp;
6112         env->v7m.other_sp = env->regs[13];
6113         env->regs[13] = tmp;
6114     }
6115 }
6116 
6117 /* Switch M profile security state between NS and S */
6118 static void switch_v7m_security_state(CPUARMState *env, bool new_secstate)
6119 {
6120     uint32_t new_ss_msp, new_ss_psp;
6121 
6122     if (env->v7m.secure == new_secstate) {
6123         return;
6124     }
6125 
6126     /* All the banked state is accessed by looking at env->v7m.secure
6127      * except for the stack pointer; rearrange the SP appropriately.
6128      */
6129     new_ss_msp = env->v7m.other_ss_msp;
6130     new_ss_psp = env->v7m.other_ss_psp;
6131 
6132     if (v7m_using_psp(env)) {
6133         env->v7m.other_ss_psp = env->regs[13];
6134         env->v7m.other_ss_msp = env->v7m.other_sp;
6135     } else {
6136         env->v7m.other_ss_msp = env->regs[13];
6137         env->v7m.other_ss_psp = env->v7m.other_sp;
6138     }
6139 
6140     env->v7m.secure = new_secstate;
6141 
6142     if (v7m_using_psp(env)) {
6143         env->regs[13] = new_ss_psp;
6144         env->v7m.other_sp = new_ss_msp;
6145     } else {
6146         env->regs[13] = new_ss_msp;
6147         env->v7m.other_sp = new_ss_psp;
6148     }
6149 }
6150 
6151 void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)
6152 {
6153     /* Handle v7M BXNS:
6154      *  - if the return value is a magic value, do exception return (like BX)
6155      *  - otherwise bit 0 of the return value is the target security state
6156      */
6157     if (dest >= 0xff000000) {
6158         /* This is an exception return magic value; put it where
6159          * do_v7m_exception_exit() expects and raise EXCEPTION_EXIT.
6160          * Note that if we ever add gen_ss_advance() singlestep support to
6161          * M profile this should count as an "instruction execution complete"
6162          * event (compare gen_bx_excret_final_code()).
6163          */
6164         env->regs[15] = dest & ~1;
6165         env->thumb = dest & 1;
6166         HELPER(exception_internal)(env, EXCP_EXCEPTION_EXIT);
6167         /* notreached */
6168     }
6169 
6170     /* translate.c should have made BXNS UNDEF unless we're secure */
6171     assert(env->v7m.secure);
6172 
6173     switch_v7m_security_state(env, dest & 1);
6174     env->thumb = 1;
6175     env->regs[15] = dest & ~1;
6176 }
6177 
6178 static uint32_t *get_v7m_sp_ptr(CPUARMState *env, bool secure, bool threadmode,
6179                                 bool spsel)
6180 {
6181     /* Return a pointer to the location where we currently store the
6182      * stack pointer for the requested security state and thread mode.
6183      * This pointer will become invalid if the CPU state is updated
6184      * such that the stack pointers are switched around (eg changing
6185      * the SPSEL control bit).
6186      * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode().
6187      * Unlike that pseudocode, we require the caller to pass us in the
6188      * SPSEL control bit value; this is because we also use this
6189      * function in handling of pushing of the callee-saves registers
6190      * part of the v8M stack frame (pseudocode PushCalleeStack()),
6191      * and in the tailchain codepath the SPSEL bit comes from the exception
6192      * return magic LR value from the previous exception. The pseudocode
6193      * opencodes the stack-selection in PushCalleeStack(), but we prefer
6194      * to make this utility function generic enough to do the job.
6195      */
6196     bool want_psp = threadmode && spsel;
6197 
6198     if (secure == env->v7m.secure) {
6199         if (want_psp == v7m_using_psp(env)) {
6200             return &env->regs[13];
6201         } else {
6202             return &env->v7m.other_sp;
6203         }
6204     } else {
6205         if (want_psp) {
6206             return &env->v7m.other_ss_psp;
6207         } else {
6208             return &env->v7m.other_ss_msp;
6209         }
6210     }
6211 }
6212 
6213 static uint32_t arm_v7m_load_vector(ARMCPU *cpu)
6214 {
6215     CPUState *cs = CPU(cpu);
6216     CPUARMState *env = &cpu->env;
6217     MemTxResult result;
6218     hwaddr vec = env->v7m.vecbase[env->v7m.secure] + env->v7m.exception * 4;
6219     uint32_t addr;
6220 
6221     addr = address_space_ldl(cs->as, vec,
6222                              MEMTXATTRS_UNSPECIFIED, &result);
6223     if (result != MEMTX_OK) {
6224         /* Architecturally this should cause a HardFault setting HSFR.VECTTBL,
6225          * which would then be immediately followed by our failing to load
6226          * the entry vector for that HardFault, which is a Lockup case.
6227          * Since we don't model Lockup, we just report this guest error
6228          * via cpu_abort().
6229          */
6230         cpu_abort(cs, "Failed to read from exception vector table "
6231                   "entry %08x\n", (unsigned)vec);
6232     }
6233     return addr;
6234 }
6235 
6236 static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr)
6237 {
6238     /* Do the "take the exception" parts of exception entry,
6239      * but not the pushing of state to the stack. This is
6240      * similar to the pseudocode ExceptionTaken() function.
6241      */
6242     CPUARMState *env = &cpu->env;
6243     uint32_t addr;
6244 
6245     armv7m_nvic_acknowledge_irq(env->nvic);
6246     write_v7m_control_spsel(env, 0);
6247     arm_clear_exclusive(env);
6248     /* Clear IT bits */
6249     env->condexec_bits = 0;
6250     env->regs[14] = lr;
6251     addr = arm_v7m_load_vector(cpu);
6252     env->regs[15] = addr & 0xfffffffe;
6253     env->thumb = addr & 1;
6254 }
6255 
6256 static void v7m_push_stack(ARMCPU *cpu)
6257 {
6258     /* Do the "set up stack frame" part of exception entry,
6259      * similar to pseudocode PushStack().
6260      */
6261     CPUARMState *env = &cpu->env;
6262     uint32_t xpsr = xpsr_read(env);
6263 
6264     /* Align stack pointer if the guest wants that */
6265     if ((env->regs[13] & 4) &&
6266         (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKALIGN_MASK)) {
6267         env->regs[13] -= 4;
6268         xpsr |= XPSR_SPREALIGN;
6269     }
6270     /* Switch to the handler mode.  */
6271     v7m_push(env, xpsr);
6272     v7m_push(env, env->regs[15]);
6273     v7m_push(env, env->regs[14]);
6274     v7m_push(env, env->regs[12]);
6275     v7m_push(env, env->regs[3]);
6276     v7m_push(env, env->regs[2]);
6277     v7m_push(env, env->regs[1]);
6278     v7m_push(env, env->regs[0]);
6279 }
6280 
6281 static void do_v7m_exception_exit(ARMCPU *cpu)
6282 {
6283     CPUARMState *env = &cpu->env;
6284     CPUState *cs = CPU(cpu);
6285     uint32_t excret;
6286     uint32_t xpsr;
6287     bool ufault = false;
6288     bool return_to_sp_process = false;
6289     bool return_to_handler = false;
6290     bool rettobase = false;
6291     bool exc_secure = false;
6292     bool return_to_secure;
6293 
6294     /* We can only get here from an EXCP_EXCEPTION_EXIT, and
6295      * gen_bx_excret() enforces the architectural rule
6296      * that jumps to magic addresses don't have magic behaviour unless
6297      * we're in Handler mode (compare pseudocode BXWritePC()).
6298      */
6299     assert(arm_v7m_is_handler_mode(env));
6300 
6301     /* In the spec pseudocode ExceptionReturn() is called directly
6302      * from BXWritePC() and gets the full target PC value including
6303      * bit zero. In QEMU's implementation we treat it as a normal
6304      * jump-to-register (which is then caught later on), and so split
6305      * the target value up between env->regs[15] and env->thumb in
6306      * gen_bx(). Reconstitute it.
6307      */
6308     excret = env->regs[15];
6309     if (env->thumb) {
6310         excret |= 1;
6311     }
6312 
6313     qemu_log_mask(CPU_LOG_INT, "Exception return: magic PC %" PRIx32
6314                   " previous exception %d\n",
6315                   excret, env->v7m.exception);
6316 
6317     if ((excret & R_V7M_EXCRET_RES1_MASK) != R_V7M_EXCRET_RES1_MASK) {
6318         qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero high bits in exception "
6319                       "exit PC value 0x%" PRIx32 " are UNPREDICTABLE\n",
6320                       excret);
6321     }
6322 
6323     if (env->v7m.exception != ARMV7M_EXCP_NMI) {
6324         /* Auto-clear FAULTMASK on return from other than NMI.
6325          * If the security extension is implemented then this only
6326          * happens if the raw execution priority is >= 0; the
6327          * value of the ES bit in the exception return value indicates
6328          * which security state's faultmask to clear. (v8M ARM ARM R_KBNF.)
6329          */
6330         if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
6331             exc_secure = excret & R_V7M_EXCRET_ES_MASK;
6332             if (armv7m_nvic_raw_execution_priority(env->nvic) >= 0) {
6333                 env->v7m.faultmask[exc_secure] = 0;
6334             }
6335         } else {
6336             env->v7m.faultmask[M_REG_NS] = 0;
6337         }
6338     }
6339 
6340     switch (armv7m_nvic_complete_irq(env->nvic, env->v7m.exception,
6341                                      exc_secure)) {
6342     case -1:
6343         /* attempt to exit an exception that isn't active */
6344         ufault = true;
6345         break;
6346     case 0:
6347         /* still an irq active now */
6348         break;
6349     case 1:
6350         /* we returned to base exception level, no nesting.
6351          * (In the pseudocode this is written using "NestedActivation != 1"
6352          * where we have 'rettobase == false'.)
6353          */
6354         rettobase = true;
6355         break;
6356     default:
6357         g_assert_not_reached();
6358     }
6359 
6360     return_to_secure = arm_feature(env, ARM_FEATURE_M_SECURITY) &&
6361         (excret & R_V7M_EXCRET_S_MASK);
6362 
6363     switch (excret & 0xf) {
6364     case 1: /* Return to Handler */
6365         return_to_handler = true;
6366         break;
6367     case 13: /* Return to Thread using Process stack */
6368         return_to_sp_process = true;
6369         /* fall through */
6370     case 9: /* Return to Thread using Main stack */
6371         if (!rettobase &&
6372             !(env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_NONBASETHRDENA_MASK)) {
6373             ufault = true;
6374         }
6375         break;
6376     default:
6377         ufault = true;
6378     }
6379 
6380     if (ufault) {
6381         /* Bad exception return: instead of popping the exception
6382          * stack, directly take a usage fault on the current stack.
6383          */
6384         env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK;
6385         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);
6386         v7m_exception_taken(cpu, excret);
6387         qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing "
6388                       "stackframe: failed exception return integrity check\n");
6389         return;
6390     }
6391 
6392     /* Set CONTROL.SPSEL from excret.SPSEL. Since we're still in
6393      * Handler mode (and will be until we write the new XPSR.Interrupt
6394      * field) this does not switch around the current stack pointer.
6395      */
6396     write_v7m_control_spsel_for_secstate(env, return_to_sp_process, exc_secure);
6397 
6398     switch_v7m_security_state(env, return_to_secure);
6399 
6400     {
6401         /* The stack pointer we should be reading the exception frame from
6402          * depends on bits in the magic exception return type value (and
6403          * for v8M isn't necessarily the stack pointer we will eventually
6404          * end up resuming execution with). Get a pointer to the location
6405          * in the CPU state struct where the SP we need is currently being
6406          * stored; we will use and modify it in place.
6407          * We use this limited C variable scope so we don't accidentally
6408          * use 'frame_sp_p' after we do something that makes it invalid.
6409          */
6410         uint32_t *frame_sp_p = get_v7m_sp_ptr(env,
6411                                               return_to_secure,
6412                                               !return_to_handler,
6413                                               return_to_sp_process);
6414         uint32_t frameptr = *frame_sp_p;
6415 
6416         if (!QEMU_IS_ALIGNED(frameptr, 8) &&
6417             arm_feature(env, ARM_FEATURE_V8)) {
6418             qemu_log_mask(LOG_GUEST_ERROR,
6419                           "M profile exception return with non-8-aligned SP "
6420                           "for destination state is UNPREDICTABLE\n");
6421         }
6422 
6423         /* Pop registers. TODO: make these accesses use the correct
6424          * attributes and address space (S/NS, priv/unpriv) and handle
6425          * memory transaction failures.
6426          */
6427         env->regs[0] = ldl_phys(cs->as, frameptr);
6428         env->regs[1] = ldl_phys(cs->as, frameptr + 0x4);
6429         env->regs[2] = ldl_phys(cs->as, frameptr + 0x8);
6430         env->regs[3] = ldl_phys(cs->as, frameptr + 0xc);
6431         env->regs[12] = ldl_phys(cs->as, frameptr + 0x10);
6432         env->regs[14] = ldl_phys(cs->as, frameptr + 0x14);
6433         env->regs[15] = ldl_phys(cs->as, frameptr + 0x18);
6434 
6435         /* Returning from an exception with a PC with bit 0 set is defined
6436          * behaviour on v8M (bit 0 is ignored), but for v7M it was specified
6437          * to be UNPREDICTABLE. In practice actual v7M hardware seems to ignore
6438          * the lsbit, and there are several RTOSes out there which incorrectly
6439          * assume the r15 in the stack frame should be a Thumb-style "lsbit
6440          * indicates ARM/Thumb" value, so ignore the bit on v7M as well, but
6441          * complain about the badly behaved guest.
6442          */
6443         if (env->regs[15] & 1) {
6444             env->regs[15] &= ~1U;
6445             if (!arm_feature(env, ARM_FEATURE_V8)) {
6446                 qemu_log_mask(LOG_GUEST_ERROR,
6447                               "M profile return from interrupt with misaligned "
6448                               "PC is UNPREDICTABLE on v7M\n");
6449             }
6450         }
6451 
6452         xpsr = ldl_phys(cs->as, frameptr + 0x1c);
6453 
6454         if (arm_feature(env, ARM_FEATURE_V8)) {
6455             /* For v8M we have to check whether the xPSR exception field
6456              * matches the EXCRET value for return to handler/thread
6457              * before we commit to changing the SP and xPSR.
6458              */
6459             bool will_be_handler = (xpsr & XPSR_EXCP) != 0;
6460             if (return_to_handler != will_be_handler) {
6461                 /* Take an INVPC UsageFault on the current stack.
6462                  * By this point we will have switched to the security state
6463                  * for the background state, so this UsageFault will target
6464                  * that state.
6465                  */
6466                 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE,
6467                                         env->v7m.secure);
6468                 env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK;
6469                 v7m_exception_taken(cpu, excret);
6470                 qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing "
6471                               "stackframe: failed exception return integrity "
6472                               "check\n");
6473                 return;
6474             }
6475         }
6476 
6477         /* Commit to consuming the stack frame */
6478         frameptr += 0x20;
6479         /* Undo stack alignment (the SPREALIGN bit indicates that the original
6480          * pre-exception SP was not 8-aligned and we added a padding word to
6481          * align it, so we undo this by ORing in the bit that increases it
6482          * from the current 8-aligned value to the 8-unaligned value. (Adding 4
6483          * would work too but a logical OR is how the pseudocode specifies it.)
6484          */
6485         if (xpsr & XPSR_SPREALIGN) {
6486             frameptr |= 4;
6487         }
6488         *frame_sp_p = frameptr;
6489     }
6490     /* This xpsr_write() will invalidate frame_sp_p as it may switch stack */
6491     xpsr_write(env, xpsr, ~XPSR_SPREALIGN);
6492 
6493     /* The restored xPSR exception field will be zero if we're
6494      * resuming in Thread mode. If that doesn't match what the
6495      * exception return excret specified then this is a UsageFault.
6496      * v7M requires we make this check here; v8M did it earlier.
6497      */
6498     if (return_to_handler != arm_v7m_is_handler_mode(env)) {
6499         /* Take an INVPC UsageFault by pushing the stack again;
6500          * we know we're v7M so this is never a Secure UsageFault.
6501          */
6502         assert(!arm_feature(env, ARM_FEATURE_V8));
6503         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, false);
6504         env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK;
6505         v7m_push_stack(cpu);
6506         v7m_exception_taken(cpu, excret);
6507         qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on new stackframe: "
6508                       "failed exception return integrity check\n");
6509         return;
6510     }
6511 
6512     /* Otherwise, we have a successful exception exit. */
6513     arm_clear_exclusive(env);
6514     qemu_log_mask(CPU_LOG_INT, "...successful exception return\n");
6515 }
6516 
6517 static void arm_log_exception(int idx)
6518 {
6519     if (qemu_loglevel_mask(CPU_LOG_INT)) {
6520         const char *exc = NULL;
6521         static const char * const excnames[] = {
6522             [EXCP_UDEF] = "Undefined Instruction",
6523             [EXCP_SWI] = "SVC",
6524             [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
6525             [EXCP_DATA_ABORT] = "Data Abort",
6526             [EXCP_IRQ] = "IRQ",
6527             [EXCP_FIQ] = "FIQ",
6528             [EXCP_BKPT] = "Breakpoint",
6529             [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
6530             [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
6531             [EXCP_HVC] = "Hypervisor Call",
6532             [EXCP_HYP_TRAP] = "Hypervisor Trap",
6533             [EXCP_SMC] = "Secure Monitor Call",
6534             [EXCP_VIRQ] = "Virtual IRQ",
6535             [EXCP_VFIQ] = "Virtual FIQ",
6536             [EXCP_SEMIHOST] = "Semihosting call",
6537             [EXCP_NOCP] = "v7M NOCP UsageFault",
6538             [EXCP_INVSTATE] = "v7M INVSTATE UsageFault",
6539         };
6540 
6541         if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
6542             exc = excnames[idx];
6543         }
6544         if (!exc) {
6545             exc = "unknown";
6546         }
6547         qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc);
6548     }
6549 }
6550 
6551 void arm_v7m_cpu_do_interrupt(CPUState *cs)
6552 {
6553     ARMCPU *cpu = ARM_CPU(cs);
6554     CPUARMState *env = &cpu->env;
6555     uint32_t lr;
6556 
6557     arm_log_exception(cs->exception_index);
6558 
6559     /* For exceptions we just mark as pending on the NVIC, and let that
6560        handle it.  */
6561     switch (cs->exception_index) {
6562     case EXCP_UDEF:
6563         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);
6564         env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_UNDEFINSTR_MASK;
6565         break;
6566     case EXCP_NOCP:
6567         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);
6568         env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_NOCP_MASK;
6569         break;
6570     case EXCP_INVSTATE:
6571         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);
6572         env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVSTATE_MASK;
6573         break;
6574     case EXCP_SWI:
6575         /* The PC already points to the next instruction.  */
6576         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC, env->v7m.secure);
6577         break;
6578     case EXCP_PREFETCH_ABORT:
6579     case EXCP_DATA_ABORT:
6580         /* Note that for M profile we don't have a guest facing FSR, but
6581          * the env->exception.fsr will be populated by the code that
6582          * raises the fault, in the A profile short-descriptor format.
6583          */
6584         switch (env->exception.fsr & 0xf) {
6585         case 0x8: /* External Abort */
6586             switch (cs->exception_index) {
6587             case EXCP_PREFETCH_ABORT:
6588                 env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_IBUSERR_MASK;
6589                 qemu_log_mask(CPU_LOG_INT, "...with CFSR.IBUSERR\n");
6590                 break;
6591             case EXCP_DATA_ABORT:
6592                 env->v7m.cfsr[M_REG_NS] |=
6593                     (R_V7M_CFSR_PRECISERR_MASK | R_V7M_CFSR_BFARVALID_MASK);
6594                 env->v7m.bfar = env->exception.vaddress;
6595                 qemu_log_mask(CPU_LOG_INT,
6596                               "...with CFSR.PRECISERR and BFAR 0x%x\n",
6597                               env->v7m.bfar);
6598                 break;
6599             }
6600             armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false);
6601             break;
6602         default:
6603             /* All other FSR values are either MPU faults or "can't happen
6604              * for M profile" cases.
6605              */
6606             switch (cs->exception_index) {
6607             case EXCP_PREFETCH_ABORT:
6608                 env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_IACCVIOL_MASK;
6609                 qemu_log_mask(CPU_LOG_INT, "...with CFSR.IACCVIOL\n");
6610                 break;
6611             case EXCP_DATA_ABORT:
6612                 env->v7m.cfsr[env->v7m.secure] |=
6613                     (R_V7M_CFSR_DACCVIOL_MASK | R_V7M_CFSR_MMARVALID_MASK);
6614                 env->v7m.mmfar[env->v7m.secure] = env->exception.vaddress;
6615                 qemu_log_mask(CPU_LOG_INT,
6616                               "...with CFSR.DACCVIOL and MMFAR 0x%x\n",
6617                               env->v7m.mmfar[env->v7m.secure]);
6618                 break;
6619             }
6620             armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM,
6621                                     env->v7m.secure);
6622             break;
6623         }
6624         break;
6625     case EXCP_BKPT:
6626         if (semihosting_enabled()) {
6627             int nr;
6628             nr = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env)) & 0xff;
6629             if (nr == 0xab) {
6630                 env->regs[15] += 2;
6631                 qemu_log_mask(CPU_LOG_INT,
6632                               "...handling as semihosting call 0x%x\n",
6633                               env->regs[0]);
6634                 env->regs[0] = do_arm_semihosting(env);
6635                 return;
6636             }
6637         }
6638         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG, false);
6639         break;
6640     case EXCP_IRQ:
6641         break;
6642     case EXCP_EXCEPTION_EXIT:
6643         do_v7m_exception_exit(cpu);
6644         return;
6645     default:
6646         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
6647         return; /* Never happens.  Keep compiler happy.  */
6648     }
6649 
6650     lr = R_V7M_EXCRET_RES1_MASK |
6651         R_V7M_EXCRET_S_MASK |
6652         R_V7M_EXCRET_DCRS_MASK |
6653         R_V7M_EXCRET_FTYPE_MASK |
6654         R_V7M_EXCRET_ES_MASK;
6655     if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) {
6656         lr |= R_V7M_EXCRET_SPSEL_MASK;
6657     }
6658     if (!arm_v7m_is_handler_mode(env)) {
6659         lr |= R_V7M_EXCRET_MODE_MASK;
6660     }
6661 
6662     v7m_push_stack(cpu);
6663     v7m_exception_taken(cpu, lr);
6664     qemu_log_mask(CPU_LOG_INT, "... as %d\n", env->v7m.exception);
6665 }
6666 
6667 /* Function used to synchronize QEMU's AArch64 register set with AArch32
6668  * register set.  This is necessary when switching between AArch32 and AArch64
6669  * execution state.
6670  */
6671 void aarch64_sync_32_to_64(CPUARMState *env)
6672 {
6673     int i;
6674     uint32_t mode = env->uncached_cpsr & CPSR_M;
6675 
6676     /* We can blanket copy R[0:7] to X[0:7] */
6677     for (i = 0; i < 8; i++) {
6678         env->xregs[i] = env->regs[i];
6679     }
6680 
6681     /* Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
6682      * Otherwise, they come from the banked user regs.
6683      */
6684     if (mode == ARM_CPU_MODE_FIQ) {
6685         for (i = 8; i < 13; i++) {
6686             env->xregs[i] = env->usr_regs[i - 8];
6687         }
6688     } else {
6689         for (i = 8; i < 13; i++) {
6690             env->xregs[i] = env->regs[i];
6691         }
6692     }
6693 
6694     /* Registers x13-x23 are the various mode SP and FP registers. Registers
6695      * r13 and r14 are only copied if we are in that mode, otherwise we copy
6696      * from the mode banked register.
6697      */
6698     if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
6699         env->xregs[13] = env->regs[13];
6700         env->xregs[14] = env->regs[14];
6701     } else {
6702         env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)];
6703         /* HYP is an exception in that it is copied from r14 */
6704         if (mode == ARM_CPU_MODE_HYP) {
6705             env->xregs[14] = env->regs[14];
6706         } else {
6707             env->xregs[14] = env->banked_r14[bank_number(ARM_CPU_MODE_USR)];
6708         }
6709     }
6710 
6711     if (mode == ARM_CPU_MODE_HYP) {
6712         env->xregs[15] = env->regs[13];
6713     } else {
6714         env->xregs[15] = env->banked_r13[bank_number(ARM_CPU_MODE_HYP)];
6715     }
6716 
6717     if (mode == ARM_CPU_MODE_IRQ) {
6718         env->xregs[16] = env->regs[14];
6719         env->xregs[17] = env->regs[13];
6720     } else {
6721         env->xregs[16] = env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)];
6722         env->xregs[17] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)];
6723     }
6724 
6725     if (mode == ARM_CPU_MODE_SVC) {
6726         env->xregs[18] = env->regs[14];
6727         env->xregs[19] = env->regs[13];
6728     } else {
6729         env->xregs[18] = env->banked_r14[bank_number(ARM_CPU_MODE_SVC)];
6730         env->xregs[19] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)];
6731     }
6732 
6733     if (mode == ARM_CPU_MODE_ABT) {
6734         env->xregs[20] = env->regs[14];
6735         env->xregs[21] = env->regs[13];
6736     } else {
6737         env->xregs[20] = env->banked_r14[bank_number(ARM_CPU_MODE_ABT)];
6738         env->xregs[21] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)];
6739     }
6740 
6741     if (mode == ARM_CPU_MODE_UND) {
6742         env->xregs[22] = env->regs[14];
6743         env->xregs[23] = env->regs[13];
6744     } else {
6745         env->xregs[22] = env->banked_r14[bank_number(ARM_CPU_MODE_UND)];
6746         env->xregs[23] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)];
6747     }
6748 
6749     /* Registers x24-x30 are mapped to r8-r14 in FIQ mode.  If we are in FIQ
6750      * mode, then we can copy from r8-r14.  Otherwise, we copy from the
6751      * FIQ bank for r8-r14.
6752      */
6753     if (mode == ARM_CPU_MODE_FIQ) {
6754         for (i = 24; i < 31; i++) {
6755             env->xregs[i] = env->regs[i - 16];   /* X[24:30] <- R[8:14] */
6756         }
6757     } else {
6758         for (i = 24; i < 29; i++) {
6759             env->xregs[i] = env->fiq_regs[i - 24];
6760         }
6761         env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)];
6762         env->xregs[30] = env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)];
6763     }
6764 
6765     env->pc = env->regs[15];
6766 }
6767 
6768 /* Function used to synchronize QEMU's AArch32 register set with AArch64
6769  * register set.  This is necessary when switching between AArch32 and AArch64
6770  * execution state.
6771  */
6772 void aarch64_sync_64_to_32(CPUARMState *env)
6773 {
6774     int i;
6775     uint32_t mode = env->uncached_cpsr & CPSR_M;
6776 
6777     /* We can blanket copy X[0:7] to R[0:7] */
6778     for (i = 0; i < 8; i++) {
6779         env->regs[i] = env->xregs[i];
6780     }
6781 
6782     /* Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
6783      * Otherwise, we copy x8-x12 into the banked user regs.
6784      */
6785     if (mode == ARM_CPU_MODE_FIQ) {
6786         for (i = 8; i < 13; i++) {
6787             env->usr_regs[i - 8] = env->xregs[i];
6788         }
6789     } else {
6790         for (i = 8; i < 13; i++) {
6791             env->regs[i] = env->xregs[i];
6792         }
6793     }
6794 
6795     /* Registers r13 & r14 depend on the current mode.
6796      * If we are in a given mode, we copy the corresponding x registers to r13
6797      * and r14.  Otherwise, we copy the x register to the banked r13 and r14
6798      * for the mode.
6799      */
6800     if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
6801         env->regs[13] = env->xregs[13];
6802         env->regs[14] = env->xregs[14];
6803     } else {
6804         env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13];
6805 
6806         /* HYP is an exception in that it does not have its own banked r14 but
6807          * shares the USR r14
6808          */
6809         if (mode == ARM_CPU_MODE_HYP) {
6810             env->regs[14] = env->xregs[14];
6811         } else {
6812             env->banked_r14[bank_number(ARM_CPU_MODE_USR)] = env->xregs[14];
6813         }
6814     }
6815 
6816     if (mode == ARM_CPU_MODE_HYP) {
6817         env->regs[13] = env->xregs[15];
6818     } else {
6819         env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] = env->xregs[15];
6820     }
6821 
6822     if (mode == ARM_CPU_MODE_IRQ) {
6823         env->regs[14] = env->xregs[16];
6824         env->regs[13] = env->xregs[17];
6825     } else {
6826         env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16];
6827         env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17];
6828     }
6829 
6830     if (mode == ARM_CPU_MODE_SVC) {
6831         env->regs[14] = env->xregs[18];
6832         env->regs[13] = env->xregs[19];
6833     } else {
6834         env->banked_r14[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18];
6835         env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19];
6836     }
6837 
6838     if (mode == ARM_CPU_MODE_ABT) {
6839         env->regs[14] = env->xregs[20];
6840         env->regs[13] = env->xregs[21];
6841     } else {
6842         env->banked_r14[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20];
6843         env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21];
6844     }
6845 
6846     if (mode == ARM_CPU_MODE_UND) {
6847         env->regs[14] = env->xregs[22];
6848         env->regs[13] = env->xregs[23];
6849     } else {
6850         env->banked_r14[bank_number(ARM_CPU_MODE_UND)] = env->xregs[22];
6851         env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23];
6852     }
6853 
6854     /* Registers x24-x30 are mapped to r8-r14 in FIQ mode.  If we are in FIQ
6855      * mode, then we can copy to r8-r14.  Otherwise, we copy to the
6856      * FIQ bank for r8-r14.
6857      */
6858     if (mode == ARM_CPU_MODE_FIQ) {
6859         for (i = 24; i < 31; i++) {
6860             env->regs[i - 16] = env->xregs[i];   /* X[24:30] -> R[8:14] */
6861         }
6862     } else {
6863         for (i = 24; i < 29; i++) {
6864             env->fiq_regs[i - 24] = env->xregs[i];
6865         }
6866         env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29];
6867         env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30];
6868     }
6869 
6870     env->regs[15] = env->pc;
6871 }
6872 
6873 static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
6874 {
6875     ARMCPU *cpu = ARM_CPU(cs);
6876     CPUARMState *env = &cpu->env;
6877     uint32_t addr;
6878     uint32_t mask;
6879     int new_mode;
6880     uint32_t offset;
6881     uint32_t moe;
6882 
6883     /* If this is a debug exception we must update the DBGDSCR.MOE bits */
6884     switch (env->exception.syndrome >> ARM_EL_EC_SHIFT) {
6885     case EC_BREAKPOINT:
6886     case EC_BREAKPOINT_SAME_EL:
6887         moe = 1;
6888         break;
6889     case EC_WATCHPOINT:
6890     case EC_WATCHPOINT_SAME_EL:
6891         moe = 10;
6892         break;
6893     case EC_AA32_BKPT:
6894         moe = 3;
6895         break;
6896     case EC_VECTORCATCH:
6897         moe = 5;
6898         break;
6899     default:
6900         moe = 0;
6901         break;
6902     }
6903 
6904     if (moe) {
6905         env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe);
6906     }
6907 
6908     /* TODO: Vectored interrupt controller.  */
6909     switch (cs->exception_index) {
6910     case EXCP_UDEF:
6911         new_mode = ARM_CPU_MODE_UND;
6912         addr = 0x04;
6913         mask = CPSR_I;
6914         if (env->thumb)
6915             offset = 2;
6916         else
6917             offset = 4;
6918         break;
6919     case EXCP_SWI:
6920         new_mode = ARM_CPU_MODE_SVC;
6921         addr = 0x08;
6922         mask = CPSR_I;
6923         /* The PC already points to the next instruction.  */
6924         offset = 0;
6925         break;
6926     case EXCP_BKPT:
6927         env->exception.fsr = 2;
6928         /* Fall through to prefetch abort.  */
6929     case EXCP_PREFETCH_ABORT:
6930         A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr);
6931         A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress);
6932         qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",
6933                       env->exception.fsr, (uint32_t)env->exception.vaddress);
6934         new_mode = ARM_CPU_MODE_ABT;
6935         addr = 0x0c;
6936         mask = CPSR_A | CPSR_I;
6937         offset = 4;
6938         break;
6939     case EXCP_DATA_ABORT:
6940         A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr);
6941         A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress);
6942         qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
6943                       env->exception.fsr,
6944                       (uint32_t)env->exception.vaddress);
6945         new_mode = ARM_CPU_MODE_ABT;
6946         addr = 0x10;
6947         mask = CPSR_A | CPSR_I;
6948         offset = 8;
6949         break;
6950     case EXCP_IRQ:
6951         new_mode = ARM_CPU_MODE_IRQ;
6952         addr = 0x18;
6953         /* Disable IRQ and imprecise data aborts.  */
6954         mask = CPSR_A | CPSR_I;
6955         offset = 4;
6956         if (env->cp15.scr_el3 & SCR_IRQ) {
6957             /* IRQ routed to monitor mode */
6958             new_mode = ARM_CPU_MODE_MON;
6959             mask |= CPSR_F;
6960         }
6961         break;
6962     case EXCP_FIQ:
6963         new_mode = ARM_CPU_MODE_FIQ;
6964         addr = 0x1c;
6965         /* Disable FIQ, IRQ and imprecise data aborts.  */
6966         mask = CPSR_A | CPSR_I | CPSR_F;
6967         if (env->cp15.scr_el3 & SCR_FIQ) {
6968             /* FIQ routed to monitor mode */
6969             new_mode = ARM_CPU_MODE_MON;
6970         }
6971         offset = 4;
6972         break;
6973     case EXCP_VIRQ:
6974         new_mode = ARM_CPU_MODE_IRQ;
6975         addr = 0x18;
6976         /* Disable IRQ and imprecise data aborts.  */
6977         mask = CPSR_A | CPSR_I;
6978         offset = 4;
6979         break;
6980     case EXCP_VFIQ:
6981         new_mode = ARM_CPU_MODE_FIQ;
6982         addr = 0x1c;
6983         /* Disable FIQ, IRQ and imprecise data aborts.  */
6984         mask = CPSR_A | CPSR_I | CPSR_F;
6985         offset = 4;
6986         break;
6987     case EXCP_SMC:
6988         new_mode = ARM_CPU_MODE_MON;
6989         addr = 0x08;
6990         mask = CPSR_A | CPSR_I | CPSR_F;
6991         offset = 0;
6992         break;
6993     default:
6994         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
6995         return; /* Never happens.  Keep compiler happy.  */
6996     }
6997 
6998     if (new_mode == ARM_CPU_MODE_MON) {
6999         addr += env->cp15.mvbar;
7000     } else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
7001         /* High vectors. When enabled, base address cannot be remapped. */
7002         addr += 0xffff0000;
7003     } else {
7004         /* ARM v7 architectures provide a vector base address register to remap
7005          * the interrupt vector table.
7006          * This register is only followed in non-monitor mode, and is banked.
7007          * Note: only bits 31:5 are valid.
7008          */
7009         addr += A32_BANKED_CURRENT_REG_GET(env, vbar);
7010     }
7011 
7012     if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
7013         env->cp15.scr_el3 &= ~SCR_NS;
7014     }
7015 
7016     switch_mode (env, new_mode);
7017     /* For exceptions taken to AArch32 we must clear the SS bit in both
7018      * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
7019      */
7020     env->uncached_cpsr &= ~PSTATE_SS;
7021     env->spsr = cpsr_read(env);
7022     /* Clear IT bits.  */
7023     env->condexec_bits = 0;
7024     /* Switch to the new mode, and to the correct instruction set.  */
7025     env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
7026     /* Set new mode endianness */
7027     env->uncached_cpsr &= ~CPSR_E;
7028     if (env->cp15.sctlr_el[arm_current_el(env)] & SCTLR_EE) {
7029         env->uncached_cpsr |= CPSR_E;
7030     }
7031     env->daif |= mask;
7032     /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
7033      * and we should just guard the thumb mode on V4 */
7034     if (arm_feature(env, ARM_FEATURE_V4T)) {
7035         env->thumb = (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) != 0;
7036     }
7037     env->regs[14] = env->regs[15] + offset;
7038     env->regs[15] = addr;
7039 }
7040 
7041 /* Handle exception entry to a target EL which is using AArch64 */
7042 static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
7043 {
7044     ARMCPU *cpu = ARM_CPU(cs);
7045     CPUARMState *env = &cpu->env;
7046     unsigned int new_el = env->exception.target_el;
7047     target_ulong addr = env->cp15.vbar_el[new_el];
7048     unsigned int new_mode = aarch64_pstate_mode(new_el, true);
7049 
7050     if (arm_current_el(env) < new_el) {
7051         /* Entry vector offset depends on whether the implemented EL
7052          * immediately lower than the target level is using AArch32 or AArch64
7053          */
7054         bool is_aa64;
7055 
7056         switch (new_el) {
7057         case 3:
7058             is_aa64 = (env->cp15.scr_el3 & SCR_RW) != 0;
7059             break;
7060         case 2:
7061             is_aa64 = (env->cp15.hcr_el2 & HCR_RW) != 0;
7062             break;
7063         case 1:
7064             is_aa64 = is_a64(env);
7065             break;
7066         default:
7067             g_assert_not_reached();
7068         }
7069 
7070         if (is_aa64) {
7071             addr += 0x400;
7072         } else {
7073             addr += 0x600;
7074         }
7075     } else if (pstate_read(env) & PSTATE_SP) {
7076         addr += 0x200;
7077     }
7078 
7079     switch (cs->exception_index) {
7080     case EXCP_PREFETCH_ABORT:
7081     case EXCP_DATA_ABORT:
7082         env->cp15.far_el[new_el] = env->exception.vaddress;
7083         qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n",
7084                       env->cp15.far_el[new_el]);
7085         /* fall through */
7086     case EXCP_BKPT:
7087     case EXCP_UDEF:
7088     case EXCP_SWI:
7089     case EXCP_HVC:
7090     case EXCP_HYP_TRAP:
7091     case EXCP_SMC:
7092         env->cp15.esr_el[new_el] = env->exception.syndrome;
7093         break;
7094     case EXCP_IRQ:
7095     case EXCP_VIRQ:
7096         addr += 0x80;
7097         break;
7098     case EXCP_FIQ:
7099     case EXCP_VFIQ:
7100         addr += 0x100;
7101         break;
7102     case EXCP_SEMIHOST:
7103         qemu_log_mask(CPU_LOG_INT,
7104                       "...handling as semihosting call 0x%" PRIx64 "\n",
7105                       env->xregs[0]);
7106         env->xregs[0] = do_arm_semihosting(env);
7107         return;
7108     default:
7109         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
7110     }
7111 
7112     if (is_a64(env)) {
7113         env->banked_spsr[aarch64_banked_spsr_index(new_el)] = pstate_read(env);
7114         aarch64_save_sp(env, arm_current_el(env));
7115         env->elr_el[new_el] = env->pc;
7116     } else {
7117         env->banked_spsr[aarch64_banked_spsr_index(new_el)] = cpsr_read(env);
7118         env->elr_el[new_el] = env->regs[15];
7119 
7120         aarch64_sync_32_to_64(env);
7121 
7122         env->condexec_bits = 0;
7123     }
7124     qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n",
7125                   env->elr_el[new_el]);
7126 
7127     pstate_write(env, PSTATE_DAIF | new_mode);
7128     env->aarch64 = 1;
7129     aarch64_restore_sp(env, new_el);
7130 
7131     env->pc = addr;
7132 
7133     qemu_log_mask(CPU_LOG_INT, "...to EL%d PC 0x%" PRIx64 " PSTATE 0x%x\n",
7134                   new_el, env->pc, pstate_read(env));
7135 }
7136 
7137 static inline bool check_for_semihosting(CPUState *cs)
7138 {
7139     /* Check whether this exception is a semihosting call; if so
7140      * then handle it and return true; otherwise return false.
7141      */
7142     ARMCPU *cpu = ARM_CPU(cs);
7143     CPUARMState *env = &cpu->env;
7144 
7145     if (is_a64(env)) {
7146         if (cs->exception_index == EXCP_SEMIHOST) {
7147             /* This is always the 64-bit semihosting exception.
7148              * The "is this usermode" and "is semihosting enabled"
7149              * checks have been done at translate time.
7150              */
7151             qemu_log_mask(CPU_LOG_INT,
7152                           "...handling as semihosting call 0x%" PRIx64 "\n",
7153                           env->xregs[0]);
7154             env->xregs[0] = do_arm_semihosting(env);
7155             return true;
7156         }
7157         return false;
7158     } else {
7159         uint32_t imm;
7160 
7161         /* Only intercept calls from privileged modes, to provide some
7162          * semblance of security.
7163          */
7164         if (cs->exception_index != EXCP_SEMIHOST &&
7165             (!semihosting_enabled() ||
7166              ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR))) {
7167             return false;
7168         }
7169 
7170         switch (cs->exception_index) {
7171         case EXCP_SEMIHOST:
7172             /* This is always a semihosting call; the "is this usermode"
7173              * and "is semihosting enabled" checks have been done at
7174              * translate time.
7175              */
7176             break;
7177         case EXCP_SWI:
7178             /* Check for semihosting interrupt.  */
7179             if (env->thumb) {
7180                 imm = arm_lduw_code(env, env->regs[15] - 2, arm_sctlr_b(env))
7181                     & 0xff;
7182                 if (imm == 0xab) {
7183                     break;
7184                 }
7185             } else {
7186                 imm = arm_ldl_code(env, env->regs[15] - 4, arm_sctlr_b(env))
7187                     & 0xffffff;
7188                 if (imm == 0x123456) {
7189                     break;
7190                 }
7191             }
7192             return false;
7193         case EXCP_BKPT:
7194             /* See if this is a semihosting syscall.  */
7195             if (env->thumb) {
7196                 imm = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env))
7197                     & 0xff;
7198                 if (imm == 0xab) {
7199                     env->regs[15] += 2;
7200                     break;
7201                 }
7202             }
7203             return false;
7204         default:
7205             return false;
7206         }
7207 
7208         qemu_log_mask(CPU_LOG_INT,
7209                       "...handling as semihosting call 0x%x\n",
7210                       env->regs[0]);
7211         env->regs[0] = do_arm_semihosting(env);
7212         return true;
7213     }
7214 }
7215 
7216 /* Handle a CPU exception for A and R profile CPUs.
7217  * Do any appropriate logging, handle PSCI calls, and then hand off
7218  * to the AArch64-entry or AArch32-entry function depending on the
7219  * target exception level's register width.
7220  */
7221 void arm_cpu_do_interrupt(CPUState *cs)
7222 {
7223     ARMCPU *cpu = ARM_CPU(cs);
7224     CPUARMState *env = &cpu->env;
7225     unsigned int new_el = env->exception.target_el;
7226 
7227     assert(!arm_feature(env, ARM_FEATURE_M));
7228 
7229     arm_log_exception(cs->exception_index);
7230     qemu_log_mask(CPU_LOG_INT, "...from EL%d to EL%d\n", arm_current_el(env),
7231                   new_el);
7232     if (qemu_loglevel_mask(CPU_LOG_INT)
7233         && !excp_is_internal(cs->exception_index)) {
7234         qemu_log_mask(CPU_LOG_INT, "...with ESR 0x%x/0x%" PRIx32 "\n",
7235                       env->exception.syndrome >> ARM_EL_EC_SHIFT,
7236                       env->exception.syndrome);
7237     }
7238 
7239     if (arm_is_psci_call(cpu, cs->exception_index)) {
7240         arm_handle_psci_call(cpu);
7241         qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n");
7242         return;
7243     }
7244 
7245     /* Semihosting semantics depend on the register width of the
7246      * code that caused the exception, not the target exception level,
7247      * so must be handled here.
7248      */
7249     if (check_for_semihosting(cs)) {
7250         return;
7251     }
7252 
7253     assert(!excp_is_internal(cs->exception_index));
7254     if (arm_el_is_aa64(env, new_el)) {
7255         arm_cpu_do_interrupt_aarch64(cs);
7256     } else {
7257         arm_cpu_do_interrupt_aarch32(cs);
7258     }
7259 
7260     /* Hooks may change global state so BQL should be held, also the
7261      * BQL needs to be held for any modification of
7262      * cs->interrupt_request.
7263      */
7264     g_assert(qemu_mutex_iothread_locked());
7265 
7266     arm_call_el_change_hook(cpu);
7267 
7268     if (!kvm_enabled()) {
7269         cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
7270     }
7271 }
7272 
7273 /* Return the exception level which controls this address translation regime */
7274 static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
7275 {
7276     switch (mmu_idx) {
7277     case ARMMMUIdx_S2NS:
7278     case ARMMMUIdx_S1E2:
7279         return 2;
7280     case ARMMMUIdx_S1E3:
7281         return 3;
7282     case ARMMMUIdx_S1SE0:
7283         return arm_el_is_aa64(env, 3) ? 1 : 3;
7284     case ARMMMUIdx_S1SE1:
7285     case ARMMMUIdx_S1NSE0:
7286     case ARMMMUIdx_S1NSE1:
7287     case ARMMMUIdx_MPriv:
7288     case ARMMMUIdx_MNegPri:
7289     case ARMMMUIdx_MUser:
7290     case ARMMMUIdx_MSPriv:
7291     case ARMMMUIdx_MSNegPri:
7292     case ARMMMUIdx_MSUser:
7293         return 1;
7294     default:
7295         g_assert_not_reached();
7296     }
7297 }
7298 
7299 /* Return the SCTLR value which controls this address translation regime */
7300 static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx)
7301 {
7302     return env->cp15.sctlr_el[regime_el(env, mmu_idx)];
7303 }
7304 
7305 /* Return true if the specified stage of address translation is disabled */
7306 static inline bool regime_translation_disabled(CPUARMState *env,
7307                                                ARMMMUIdx mmu_idx)
7308 {
7309     if (arm_feature(env, ARM_FEATURE_M)) {
7310         switch (env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] &
7311                 (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK)) {
7312         case R_V7M_MPU_CTRL_ENABLE_MASK:
7313             /* Enabled, but not for HardFault and NMI */
7314             return mmu_idx == ARMMMUIdx_MNegPri ||
7315                 mmu_idx == ARMMMUIdx_MSNegPri;
7316         case R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK:
7317             /* Enabled for all cases */
7318             return false;
7319         case 0:
7320         default:
7321             /* HFNMIENA set and ENABLE clear is UNPREDICTABLE, but
7322              * we warned about that in armv7m_nvic.c when the guest set it.
7323              */
7324             return true;
7325         }
7326     }
7327 
7328     if (mmu_idx == ARMMMUIdx_S2NS) {
7329         return (env->cp15.hcr_el2 & HCR_VM) == 0;
7330     }
7331     return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0;
7332 }
7333 
7334 static inline bool regime_translation_big_endian(CPUARMState *env,
7335                                                  ARMMMUIdx mmu_idx)
7336 {
7337     return (regime_sctlr(env, mmu_idx) & SCTLR_EE) != 0;
7338 }
7339 
7340 /* Return the TCR controlling this translation regime */
7341 static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
7342 {
7343     if (mmu_idx == ARMMMUIdx_S2NS) {
7344         return &env->cp15.vtcr_el2;
7345     }
7346     return &env->cp15.tcr_el[regime_el(env, mmu_idx)];
7347 }
7348 
7349 /* Convert a possible stage1+2 MMU index into the appropriate
7350  * stage 1 MMU index
7351  */
7352 static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx)
7353 {
7354     if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
7355         mmu_idx += (ARMMMUIdx_S1NSE0 - ARMMMUIdx_S12NSE0);
7356     }
7357     return mmu_idx;
7358 }
7359 
7360 /* Returns TBI0 value for current regime el */
7361 uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx)
7362 {
7363     TCR *tcr;
7364     uint32_t el;
7365 
7366     /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert
7367      * a stage 1+2 mmu index into the appropriate stage 1 mmu index.
7368      */
7369     mmu_idx = stage_1_mmu_idx(mmu_idx);
7370 
7371     tcr = regime_tcr(env, mmu_idx);
7372     el = regime_el(env, mmu_idx);
7373 
7374     if (el > 1) {
7375         return extract64(tcr->raw_tcr, 20, 1);
7376     } else {
7377         return extract64(tcr->raw_tcr, 37, 1);
7378     }
7379 }
7380 
7381 /* Returns TBI1 value for current regime el */
7382 uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx)
7383 {
7384     TCR *tcr;
7385     uint32_t el;
7386 
7387     /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert
7388      * a stage 1+2 mmu index into the appropriate stage 1 mmu index.
7389      */
7390     mmu_idx = stage_1_mmu_idx(mmu_idx);
7391 
7392     tcr = regime_tcr(env, mmu_idx);
7393     el = regime_el(env, mmu_idx);
7394 
7395     if (el > 1) {
7396         return 0;
7397     } else {
7398         return extract64(tcr->raw_tcr, 38, 1);
7399     }
7400 }
7401 
7402 /* Return the TTBR associated with this translation regime */
7403 static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx,
7404                                    int ttbrn)
7405 {
7406     if (mmu_idx == ARMMMUIdx_S2NS) {
7407         return env->cp15.vttbr_el2;
7408     }
7409     if (ttbrn == 0) {
7410         return env->cp15.ttbr0_el[regime_el(env, mmu_idx)];
7411     } else {
7412         return env->cp15.ttbr1_el[regime_el(env, mmu_idx)];
7413     }
7414 }
7415 
7416 /* Return true if the translation regime is using LPAE format page tables */
7417 static inline bool regime_using_lpae_format(CPUARMState *env,
7418                                             ARMMMUIdx mmu_idx)
7419 {
7420     int el = regime_el(env, mmu_idx);
7421     if (el == 2 || arm_el_is_aa64(env, el)) {
7422         return true;
7423     }
7424     if (arm_feature(env, ARM_FEATURE_LPAE)
7425         && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) {
7426         return true;
7427     }
7428     return false;
7429 }
7430 
7431 /* Returns true if the stage 1 translation regime is using LPAE format page
7432  * tables. Used when raising alignment exceptions, whose FSR changes depending
7433  * on whether the long or short descriptor format is in use. */
7434 bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx)
7435 {
7436     mmu_idx = stage_1_mmu_idx(mmu_idx);
7437 
7438     return regime_using_lpae_format(env, mmu_idx);
7439 }
7440 
7441 static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx)
7442 {
7443     switch (mmu_idx) {
7444     case ARMMMUIdx_S1SE0:
7445     case ARMMMUIdx_S1NSE0:
7446     case ARMMMUIdx_MUser:
7447         return true;
7448     default:
7449         return false;
7450     case ARMMMUIdx_S12NSE0:
7451     case ARMMMUIdx_S12NSE1:
7452         g_assert_not_reached();
7453     }
7454 }
7455 
7456 /* Translate section/page access permissions to page
7457  * R/W protection flags
7458  *
7459  * @env:         CPUARMState
7460  * @mmu_idx:     MMU index indicating required translation regime
7461  * @ap:          The 3-bit access permissions (AP[2:0])
7462  * @domain_prot: The 2-bit domain access permissions
7463  */
7464 static inline int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx,
7465                                 int ap, int domain_prot)
7466 {
7467     bool is_user = regime_is_user(env, mmu_idx);
7468 
7469     if (domain_prot == 3) {
7470         return PAGE_READ | PAGE_WRITE;
7471     }
7472 
7473     switch (ap) {
7474     case 0:
7475         if (arm_feature(env, ARM_FEATURE_V7)) {
7476             return 0;
7477         }
7478         switch (regime_sctlr(env, mmu_idx) & (SCTLR_S | SCTLR_R)) {
7479         case SCTLR_S:
7480             return is_user ? 0 : PAGE_READ;
7481         case SCTLR_R:
7482             return PAGE_READ;
7483         default:
7484             return 0;
7485         }
7486     case 1:
7487         return is_user ? 0 : PAGE_READ | PAGE_WRITE;
7488     case 2:
7489         if (is_user) {
7490             return PAGE_READ;
7491         } else {
7492             return PAGE_READ | PAGE_WRITE;
7493         }
7494     case 3:
7495         return PAGE_READ | PAGE_WRITE;
7496     case 4: /* Reserved.  */
7497         return 0;
7498     case 5:
7499         return is_user ? 0 : PAGE_READ;
7500     case 6:
7501         return PAGE_READ;
7502     case 7:
7503         if (!arm_feature(env, ARM_FEATURE_V6K)) {
7504             return 0;
7505         }
7506         return PAGE_READ;
7507     default:
7508         g_assert_not_reached();
7509     }
7510 }
7511 
7512 /* Translate section/page access permissions to page
7513  * R/W protection flags.
7514  *
7515  * @ap:      The 2-bit simple AP (AP[2:1])
7516  * @is_user: TRUE if accessing from PL0
7517  */
7518 static inline int simple_ap_to_rw_prot_is_user(int ap, bool is_user)
7519 {
7520     switch (ap) {
7521     case 0:
7522         return is_user ? 0 : PAGE_READ | PAGE_WRITE;
7523     case 1:
7524         return PAGE_READ | PAGE_WRITE;
7525     case 2:
7526         return is_user ? 0 : PAGE_READ;
7527     case 3:
7528         return PAGE_READ;
7529     default:
7530         g_assert_not_reached();
7531     }
7532 }
7533 
7534 static inline int
7535 simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap)
7536 {
7537     return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx));
7538 }
7539 
7540 /* Translate S2 section/page access permissions to protection flags
7541  *
7542  * @env:     CPUARMState
7543  * @s2ap:    The 2-bit stage2 access permissions (S2AP)
7544  * @xn:      XN (execute-never) bit
7545  */
7546 static int get_S2prot(CPUARMState *env, int s2ap, int xn)
7547 {
7548     int prot = 0;
7549 
7550     if (s2ap & 1) {
7551         prot |= PAGE_READ;
7552     }
7553     if (s2ap & 2) {
7554         prot |= PAGE_WRITE;
7555     }
7556     if (!xn) {
7557         if (arm_el_is_aa64(env, 2) || prot & PAGE_READ) {
7558             prot |= PAGE_EXEC;
7559         }
7560     }
7561     return prot;
7562 }
7563 
7564 /* Translate section/page access permissions to protection flags
7565  *
7566  * @env:     CPUARMState
7567  * @mmu_idx: MMU index indicating required translation regime
7568  * @is_aa64: TRUE if AArch64
7569  * @ap:      The 2-bit simple AP (AP[2:1])
7570  * @ns:      NS (non-secure) bit
7571  * @xn:      XN (execute-never) bit
7572  * @pxn:     PXN (privileged execute-never) bit
7573  */
7574 static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64,
7575                       int ap, int ns, int xn, int pxn)
7576 {
7577     bool is_user = regime_is_user(env, mmu_idx);
7578     int prot_rw, user_rw;
7579     bool have_wxn;
7580     int wxn = 0;
7581 
7582     assert(mmu_idx != ARMMMUIdx_S2NS);
7583 
7584     user_rw = simple_ap_to_rw_prot_is_user(ap, true);
7585     if (is_user) {
7586         prot_rw = user_rw;
7587     } else {
7588         prot_rw = simple_ap_to_rw_prot_is_user(ap, false);
7589     }
7590 
7591     if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) {
7592         return prot_rw;
7593     }
7594 
7595     /* TODO have_wxn should be replaced with
7596      *   ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2)
7597      * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE
7598      * compatible processors have EL2, which is required for [U]WXN.
7599      */
7600     have_wxn = arm_feature(env, ARM_FEATURE_LPAE);
7601 
7602     if (have_wxn) {
7603         wxn = regime_sctlr(env, mmu_idx) & SCTLR_WXN;
7604     }
7605 
7606     if (is_aa64) {
7607         switch (regime_el(env, mmu_idx)) {
7608         case 1:
7609             if (!is_user) {
7610                 xn = pxn || (user_rw & PAGE_WRITE);
7611             }
7612             break;
7613         case 2:
7614         case 3:
7615             break;
7616         }
7617     } else if (arm_feature(env, ARM_FEATURE_V7)) {
7618         switch (regime_el(env, mmu_idx)) {
7619         case 1:
7620         case 3:
7621             if (is_user) {
7622                 xn = xn || !(user_rw & PAGE_READ);
7623             } else {
7624                 int uwxn = 0;
7625                 if (have_wxn) {
7626                     uwxn = regime_sctlr(env, mmu_idx) & SCTLR_UWXN;
7627                 }
7628                 xn = xn || !(prot_rw & PAGE_READ) || pxn ||
7629                      (uwxn && (user_rw & PAGE_WRITE));
7630             }
7631             break;
7632         case 2:
7633             break;
7634         }
7635     } else {
7636         xn = wxn = 0;
7637     }
7638 
7639     if (xn || (wxn && (prot_rw & PAGE_WRITE))) {
7640         return prot_rw;
7641     }
7642     return prot_rw | PAGE_EXEC;
7643 }
7644 
7645 static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx,
7646                                      uint32_t *table, uint32_t address)
7647 {
7648     /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
7649     TCR *tcr = regime_tcr(env, mmu_idx);
7650 
7651     if (address & tcr->mask) {
7652         if (tcr->raw_tcr & TTBCR_PD1) {
7653             /* Translation table walk disabled for TTBR1 */
7654             return false;
7655         }
7656         *table = regime_ttbr(env, mmu_idx, 1) & 0xffffc000;
7657     } else {
7658         if (tcr->raw_tcr & TTBCR_PD0) {
7659             /* Translation table walk disabled for TTBR0 */
7660             return false;
7661         }
7662         *table = regime_ttbr(env, mmu_idx, 0) & tcr->base_mask;
7663     }
7664     *table |= (address >> 18) & 0x3ffc;
7665     return true;
7666 }
7667 
7668 /* Translate a S1 pagetable walk through S2 if needed.  */
7669 static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
7670                                hwaddr addr, MemTxAttrs txattrs,
7671                                uint32_t *fsr,
7672                                ARMMMUFaultInfo *fi)
7673 {
7674     if ((mmu_idx == ARMMMUIdx_S1NSE0 || mmu_idx == ARMMMUIdx_S1NSE1) &&
7675         !regime_translation_disabled(env, ARMMMUIdx_S2NS)) {
7676         target_ulong s2size;
7677         hwaddr s2pa;
7678         int s2prot;
7679         int ret;
7680 
7681         ret = get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_S2NS, &s2pa,
7682                                  &txattrs, &s2prot, &s2size, fsr, fi);
7683         if (ret) {
7684             fi->s2addr = addr;
7685             fi->stage2 = true;
7686             fi->s1ptw = true;
7687             return ~0;
7688         }
7689         addr = s2pa;
7690     }
7691     return addr;
7692 }
7693 
7694 /* All loads done in the course of a page table walk go through here.
7695  * TODO: rather than ignoring errors from physical memory reads (which
7696  * are external aborts in ARM terminology) we should propagate this
7697  * error out so that we can turn it into a Data Abort if this walk
7698  * was being done for a CPU load/store or an address translation instruction
7699  * (but not if it was for a debug access).
7700  */
7701 static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure,
7702                             ARMMMUIdx mmu_idx, uint32_t *fsr,
7703                             ARMMMUFaultInfo *fi)
7704 {
7705     ARMCPU *cpu = ARM_CPU(cs);
7706     CPUARMState *env = &cpu->env;
7707     MemTxAttrs attrs = {};
7708     AddressSpace *as;
7709 
7710     attrs.secure = is_secure;
7711     as = arm_addressspace(cs, attrs);
7712     addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi);
7713     if (fi->s1ptw) {
7714         return 0;
7715     }
7716     if (regime_translation_big_endian(env, mmu_idx)) {
7717         return address_space_ldl_be(as, addr, attrs, NULL);
7718     } else {
7719         return address_space_ldl_le(as, addr, attrs, NULL);
7720     }
7721 }
7722 
7723 static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure,
7724                             ARMMMUIdx mmu_idx, uint32_t *fsr,
7725                             ARMMMUFaultInfo *fi)
7726 {
7727     ARMCPU *cpu = ARM_CPU(cs);
7728     CPUARMState *env = &cpu->env;
7729     MemTxAttrs attrs = {};
7730     AddressSpace *as;
7731 
7732     attrs.secure = is_secure;
7733     as = arm_addressspace(cs, attrs);
7734     addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi);
7735     if (fi->s1ptw) {
7736         return 0;
7737     }
7738     if (regime_translation_big_endian(env, mmu_idx)) {
7739         return address_space_ldq_be(as, addr, attrs, NULL);
7740     } else {
7741         return address_space_ldq_le(as, addr, attrs, NULL);
7742     }
7743 }
7744 
7745 static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
7746                              MMUAccessType access_type, ARMMMUIdx mmu_idx,
7747                              hwaddr *phys_ptr, int *prot,
7748                              target_ulong *page_size, uint32_t *fsr,
7749                              ARMMMUFaultInfo *fi)
7750 {
7751     CPUState *cs = CPU(arm_env_get_cpu(env));
7752     int code;
7753     uint32_t table;
7754     uint32_t desc;
7755     int type;
7756     int ap;
7757     int domain = 0;
7758     int domain_prot;
7759     hwaddr phys_addr;
7760     uint32_t dacr;
7761 
7762     /* Pagetable walk.  */
7763     /* Lookup l1 descriptor.  */
7764     if (!get_level1_table_address(env, mmu_idx, &table, address)) {
7765         /* Section translation fault if page walk is disabled by PD0 or PD1 */
7766         code = 5;
7767         goto do_fault;
7768     }
7769     desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
7770                        mmu_idx, fsr, fi);
7771     type = (desc & 3);
7772     domain = (desc >> 5) & 0x0f;
7773     if (regime_el(env, mmu_idx) == 1) {
7774         dacr = env->cp15.dacr_ns;
7775     } else {
7776         dacr = env->cp15.dacr_s;
7777     }
7778     domain_prot = (dacr >> (domain * 2)) & 3;
7779     if (type == 0) {
7780         /* Section translation fault.  */
7781         code = 5;
7782         goto do_fault;
7783     }
7784     if (domain_prot == 0 || domain_prot == 2) {
7785         if (type == 2)
7786             code = 9; /* Section domain fault.  */
7787         else
7788             code = 11; /* Page domain fault.  */
7789         goto do_fault;
7790     }
7791     if (type == 2) {
7792         /* 1Mb section.  */
7793         phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
7794         ap = (desc >> 10) & 3;
7795         code = 13;
7796         *page_size = 1024 * 1024;
7797     } else {
7798         /* Lookup l2 entry.  */
7799         if (type == 1) {
7800             /* Coarse pagetable.  */
7801             table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
7802         } else {
7803             /* Fine pagetable.  */
7804             table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
7805         }
7806         desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
7807                            mmu_idx, fsr, fi);
7808         switch (desc & 3) {
7809         case 0: /* Page translation fault.  */
7810             code = 7;
7811             goto do_fault;
7812         case 1: /* 64k page.  */
7813             phys_addr = (desc & 0xffff0000) | (address & 0xffff);
7814             ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
7815             *page_size = 0x10000;
7816             break;
7817         case 2: /* 4k page.  */
7818             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
7819             ap = (desc >> (4 + ((address >> 9) & 6))) & 3;
7820             *page_size = 0x1000;
7821             break;
7822         case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
7823             if (type == 1) {
7824                 /* ARMv6/XScale extended small page format */
7825                 if (arm_feature(env, ARM_FEATURE_XSCALE)
7826                     || arm_feature(env, ARM_FEATURE_V6)) {
7827                     phys_addr = (desc & 0xfffff000) | (address & 0xfff);
7828                     *page_size = 0x1000;
7829                 } else {
7830                     /* UNPREDICTABLE in ARMv5; we choose to take a
7831                      * page translation fault.
7832                      */
7833                     code = 7;
7834                     goto do_fault;
7835                 }
7836             } else {
7837                 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
7838                 *page_size = 0x400;
7839             }
7840             ap = (desc >> 4) & 3;
7841             break;
7842         default:
7843             /* Never happens, but compiler isn't smart enough to tell.  */
7844             abort();
7845         }
7846         code = 15;
7847     }
7848     *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
7849     *prot |= *prot ? PAGE_EXEC : 0;
7850     if (!(*prot & (1 << access_type))) {
7851         /* Access permission fault.  */
7852         goto do_fault;
7853     }
7854     *phys_ptr = phys_addr;
7855     return false;
7856 do_fault:
7857     *fsr = code | (domain << 4);
7858     return true;
7859 }
7860 
7861 static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
7862                              MMUAccessType access_type, ARMMMUIdx mmu_idx,
7863                              hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
7864                              target_ulong *page_size, uint32_t *fsr,
7865                              ARMMMUFaultInfo *fi)
7866 {
7867     CPUState *cs = CPU(arm_env_get_cpu(env));
7868     int code;
7869     uint32_t table;
7870     uint32_t desc;
7871     uint32_t xn;
7872     uint32_t pxn = 0;
7873     int type;
7874     int ap;
7875     int domain = 0;
7876     int domain_prot;
7877     hwaddr phys_addr;
7878     uint32_t dacr;
7879     bool ns;
7880 
7881     /* Pagetable walk.  */
7882     /* Lookup l1 descriptor.  */
7883     if (!get_level1_table_address(env, mmu_idx, &table, address)) {
7884         /* Section translation fault if page walk is disabled by PD0 or PD1 */
7885         code = 5;
7886         goto do_fault;
7887     }
7888     desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
7889                        mmu_idx, fsr, fi);
7890     type = (desc & 3);
7891     if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
7892         /* Section translation fault, or attempt to use the encoding
7893          * which is Reserved on implementations without PXN.
7894          */
7895         code = 5;
7896         goto do_fault;
7897     }
7898     if ((type == 1) || !(desc & (1 << 18))) {
7899         /* Page or Section.  */
7900         domain = (desc >> 5) & 0x0f;
7901     }
7902     if (regime_el(env, mmu_idx) == 1) {
7903         dacr = env->cp15.dacr_ns;
7904     } else {
7905         dacr = env->cp15.dacr_s;
7906     }
7907     domain_prot = (dacr >> (domain * 2)) & 3;
7908     if (domain_prot == 0 || domain_prot == 2) {
7909         if (type != 1) {
7910             code = 9; /* Section domain fault.  */
7911         } else {
7912             code = 11; /* Page domain fault.  */
7913         }
7914         goto do_fault;
7915     }
7916     if (type != 1) {
7917         if (desc & (1 << 18)) {
7918             /* Supersection.  */
7919             phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
7920             phys_addr |= (uint64_t)extract32(desc, 20, 4) << 32;
7921             phys_addr |= (uint64_t)extract32(desc, 5, 4) << 36;
7922             *page_size = 0x1000000;
7923         } else {
7924             /* Section.  */
7925             phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
7926             *page_size = 0x100000;
7927         }
7928         ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
7929         xn = desc & (1 << 4);
7930         pxn = desc & 1;
7931         code = 13;
7932         ns = extract32(desc, 19, 1);
7933     } else {
7934         if (arm_feature(env, ARM_FEATURE_PXN)) {
7935             pxn = (desc >> 2) & 1;
7936         }
7937         ns = extract32(desc, 3, 1);
7938         /* Lookup l2 entry.  */
7939         table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
7940         desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
7941                            mmu_idx, fsr, fi);
7942         ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
7943         switch (desc & 3) {
7944         case 0: /* Page translation fault.  */
7945             code = 7;
7946             goto do_fault;
7947         case 1: /* 64k page.  */
7948             phys_addr = (desc & 0xffff0000) | (address & 0xffff);
7949             xn = desc & (1 << 15);
7950             *page_size = 0x10000;
7951             break;
7952         case 2: case 3: /* 4k page.  */
7953             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
7954             xn = desc & 1;
7955             *page_size = 0x1000;
7956             break;
7957         default:
7958             /* Never happens, but compiler isn't smart enough to tell.  */
7959             abort();
7960         }
7961         code = 15;
7962     }
7963     if (domain_prot == 3) {
7964         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
7965     } else {
7966         if (pxn && !regime_is_user(env, mmu_idx)) {
7967             xn = 1;
7968         }
7969         if (xn && access_type == MMU_INST_FETCH)
7970             goto do_fault;
7971 
7972         if (arm_feature(env, ARM_FEATURE_V6K) &&
7973                 (regime_sctlr(env, mmu_idx) & SCTLR_AFE)) {
7974             /* The simplified model uses AP[0] as an access control bit.  */
7975             if ((ap & 1) == 0) {
7976                 /* Access flag fault.  */
7977                 code = (code == 15) ? 6 : 3;
7978                 goto do_fault;
7979             }
7980             *prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1);
7981         } else {
7982             *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
7983         }
7984         if (*prot && !xn) {
7985             *prot |= PAGE_EXEC;
7986         }
7987         if (!(*prot & (1 << access_type))) {
7988             /* Access permission fault.  */
7989             goto do_fault;
7990         }
7991     }
7992     if (ns) {
7993         /* The NS bit will (as required by the architecture) have no effect if
7994          * the CPU doesn't support TZ or this is a non-secure translation
7995          * regime, because the attribute will already be non-secure.
7996          */
7997         attrs->secure = false;
7998     }
7999     *phys_ptr = phys_addr;
8000     return false;
8001 do_fault:
8002     *fsr = code | (domain << 4);
8003     return true;
8004 }
8005 
8006 /* Fault type for long-descriptor MMU fault reporting; this corresponds
8007  * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
8008  */
8009 typedef enum {
8010     translation_fault = 1,
8011     access_fault = 2,
8012     permission_fault = 3,
8013 } MMUFaultType;
8014 
8015 /*
8016  * check_s2_mmu_setup
8017  * @cpu:        ARMCPU
8018  * @is_aa64:    True if the translation regime is in AArch64 state
8019  * @startlevel: Suggested starting level
8020  * @inputsize:  Bitsize of IPAs
8021  * @stride:     Page-table stride (See the ARM ARM)
8022  *
8023  * Returns true if the suggested S2 translation parameters are OK and
8024  * false otherwise.
8025  */
8026 static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,
8027                                int inputsize, int stride)
8028 {
8029     const int grainsize = stride + 3;
8030     int startsizecheck;
8031 
8032     /* Negative levels are never allowed.  */
8033     if (level < 0) {
8034         return false;
8035     }
8036 
8037     startsizecheck = inputsize - ((3 - level) * stride + grainsize);
8038     if (startsizecheck < 1 || startsizecheck > stride + 4) {
8039         return false;
8040     }
8041 
8042     if (is_aa64) {
8043         CPUARMState *env = &cpu->env;
8044         unsigned int pamax = arm_pamax(cpu);
8045 
8046         switch (stride) {
8047         case 13: /* 64KB Pages.  */
8048             if (level == 0 || (level == 1 && pamax <= 42)) {
8049                 return false;
8050             }
8051             break;
8052         case 11: /* 16KB Pages.  */
8053             if (level == 0 || (level == 1 && pamax <= 40)) {
8054                 return false;
8055             }
8056             break;
8057         case 9: /* 4KB Pages.  */
8058             if (level == 0 && pamax <= 42) {
8059                 return false;
8060             }
8061             break;
8062         default:
8063             g_assert_not_reached();
8064         }
8065 
8066         /* Inputsize checks.  */
8067         if (inputsize > pamax &&
8068             (arm_el_is_aa64(env, 1) || inputsize > 40)) {
8069             /* This is CONSTRAINED UNPREDICTABLE and we choose to fault.  */
8070             return false;
8071         }
8072     } else {
8073         /* AArch32 only supports 4KB pages. Assert on that.  */
8074         assert(stride == 9);
8075 
8076         if (level == 0) {
8077             return false;
8078         }
8079     }
8080     return true;
8081 }
8082 
8083 static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
8084                                MMUAccessType access_type, ARMMMUIdx mmu_idx,
8085                                hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
8086                                target_ulong *page_size_ptr, uint32_t *fsr,
8087                                ARMMMUFaultInfo *fi)
8088 {
8089     ARMCPU *cpu = arm_env_get_cpu(env);
8090     CPUState *cs = CPU(cpu);
8091     /* Read an LPAE long-descriptor translation table. */
8092     MMUFaultType fault_type = translation_fault;
8093     uint32_t level;
8094     uint32_t epd = 0;
8095     int32_t t0sz, t1sz;
8096     uint32_t tg;
8097     uint64_t ttbr;
8098     int ttbr_select;
8099     hwaddr descaddr, indexmask, indexmask_grainsize;
8100     uint32_t tableattrs;
8101     target_ulong page_size;
8102     uint32_t attrs;
8103     int32_t stride = 9;
8104     int32_t addrsize;
8105     int inputsize;
8106     int32_t tbi = 0;
8107     TCR *tcr = regime_tcr(env, mmu_idx);
8108     int ap, ns, xn, pxn;
8109     uint32_t el = regime_el(env, mmu_idx);
8110     bool ttbr1_valid = true;
8111     uint64_t descaddrmask;
8112     bool aarch64 = arm_el_is_aa64(env, el);
8113 
8114     /* TODO:
8115      * This code does not handle the different format TCR for VTCR_EL2.
8116      * This code also does not support shareability levels.
8117      * Attribute and permission bit handling should also be checked when adding
8118      * support for those page table walks.
8119      */
8120     if (aarch64) {
8121         level = 0;
8122         addrsize = 64;
8123         if (el > 1) {
8124             if (mmu_idx != ARMMMUIdx_S2NS) {
8125                 tbi = extract64(tcr->raw_tcr, 20, 1);
8126             }
8127         } else {
8128             if (extract64(address, 55, 1)) {
8129                 tbi = extract64(tcr->raw_tcr, 38, 1);
8130             } else {
8131                 tbi = extract64(tcr->raw_tcr, 37, 1);
8132             }
8133         }
8134         tbi *= 8;
8135 
8136         /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it
8137          * invalid.
8138          */
8139         if (el > 1) {
8140             ttbr1_valid = false;
8141         }
8142     } else {
8143         level = 1;
8144         addrsize = 32;
8145         /* There is no TTBR1 for EL2 */
8146         if (el == 2) {
8147             ttbr1_valid = false;
8148         }
8149     }
8150 
8151     /* Determine whether this address is in the region controlled by
8152      * TTBR0 or TTBR1 (or if it is in neither region and should fault).
8153      * This is a Non-secure PL0/1 stage 1 translation, so controlled by
8154      * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
8155      */
8156     if (aarch64) {
8157         /* AArch64 translation.  */
8158         t0sz = extract32(tcr->raw_tcr, 0, 6);
8159         t0sz = MIN(t0sz, 39);
8160         t0sz = MAX(t0sz, 16);
8161     } else if (mmu_idx != ARMMMUIdx_S2NS) {
8162         /* AArch32 stage 1 translation.  */
8163         t0sz = extract32(tcr->raw_tcr, 0, 3);
8164     } else {
8165         /* AArch32 stage 2 translation.  */
8166         bool sext = extract32(tcr->raw_tcr, 4, 1);
8167         bool sign = extract32(tcr->raw_tcr, 3, 1);
8168         /* Address size is 40-bit for a stage 2 translation,
8169          * and t0sz can be negative (from -8 to 7),
8170          * so we need to adjust it to use the TTBR selecting logic below.
8171          */
8172         addrsize = 40;
8173         t0sz = sextract32(tcr->raw_tcr, 0, 4) + 8;
8174 
8175         /* If the sign-extend bit is not the same as t0sz[3], the result
8176          * is unpredictable. Flag this as a guest error.  */
8177         if (sign != sext) {
8178             qemu_log_mask(LOG_GUEST_ERROR,
8179                           "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n");
8180         }
8181     }
8182     t1sz = extract32(tcr->raw_tcr, 16, 6);
8183     if (aarch64) {
8184         t1sz = MIN(t1sz, 39);
8185         t1sz = MAX(t1sz, 16);
8186     }
8187     if (t0sz && !extract64(address, addrsize - t0sz, t0sz - tbi)) {
8188         /* there is a ttbr0 region and we are in it (high bits all zero) */
8189         ttbr_select = 0;
8190     } else if (ttbr1_valid && t1sz &&
8191                !extract64(~address, addrsize - t1sz, t1sz - tbi)) {
8192         /* there is a ttbr1 region and we are in it (high bits all one) */
8193         ttbr_select = 1;
8194     } else if (!t0sz) {
8195         /* ttbr0 region is "everything not in the ttbr1 region" */
8196         ttbr_select = 0;
8197     } else if (!t1sz && ttbr1_valid) {
8198         /* ttbr1 region is "everything not in the ttbr0 region" */
8199         ttbr_select = 1;
8200     } else {
8201         /* in the gap between the two regions, this is a Translation fault */
8202         fault_type = translation_fault;
8203         goto do_fault;
8204     }
8205 
8206     /* Note that QEMU ignores shareability and cacheability attributes,
8207      * so we don't need to do anything with the SH, ORGN, IRGN fields
8208      * in the TTBCR.  Similarly, TTBCR:A1 selects whether we get the
8209      * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
8210      * implement any ASID-like capability so we can ignore it (instead
8211      * we will always flush the TLB any time the ASID is changed).
8212      */
8213     if (ttbr_select == 0) {
8214         ttbr = regime_ttbr(env, mmu_idx, 0);
8215         if (el < 2) {
8216             epd = extract32(tcr->raw_tcr, 7, 1);
8217         }
8218         inputsize = addrsize - t0sz;
8219 
8220         tg = extract32(tcr->raw_tcr, 14, 2);
8221         if (tg == 1) { /* 64KB pages */
8222             stride = 13;
8223         }
8224         if (tg == 2) { /* 16KB pages */
8225             stride = 11;
8226         }
8227     } else {
8228         /* We should only be here if TTBR1 is valid */
8229         assert(ttbr1_valid);
8230 
8231         ttbr = regime_ttbr(env, mmu_idx, 1);
8232         epd = extract32(tcr->raw_tcr, 23, 1);
8233         inputsize = addrsize - t1sz;
8234 
8235         tg = extract32(tcr->raw_tcr, 30, 2);
8236         if (tg == 3)  { /* 64KB pages */
8237             stride = 13;
8238         }
8239         if (tg == 1) { /* 16KB pages */
8240             stride = 11;
8241         }
8242     }
8243 
8244     /* Here we should have set up all the parameters for the translation:
8245      * inputsize, ttbr, epd, stride, tbi
8246      */
8247 
8248     if (epd) {
8249         /* Translation table walk disabled => Translation fault on TLB miss
8250          * Note: This is always 0 on 64-bit EL2 and EL3.
8251          */
8252         goto do_fault;
8253     }
8254 
8255     if (mmu_idx != ARMMMUIdx_S2NS) {
8256         /* The starting level depends on the virtual address size (which can
8257          * be up to 48 bits) and the translation granule size. It indicates
8258          * the number of strides (stride bits at a time) needed to
8259          * consume the bits of the input address. In the pseudocode this is:
8260          *  level = 4 - RoundUp((inputsize - grainsize) / stride)
8261          * where their 'inputsize' is our 'inputsize', 'grainsize' is
8262          * our 'stride + 3' and 'stride' is our 'stride'.
8263          * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
8264          * = 4 - (inputsize - stride - 3 + stride - 1) / stride
8265          * = 4 - (inputsize - 4) / stride;
8266          */
8267         level = 4 - (inputsize - 4) / stride;
8268     } else {
8269         /* For stage 2 translations the starting level is specified by the
8270          * VTCR_EL2.SL0 field (whose interpretation depends on the page size)
8271          */
8272         uint32_t sl0 = extract32(tcr->raw_tcr, 6, 2);
8273         uint32_t startlevel;
8274         bool ok;
8275 
8276         if (!aarch64 || stride == 9) {
8277             /* AArch32 or 4KB pages */
8278             startlevel = 2 - sl0;
8279         } else {
8280             /* 16KB or 64KB pages */
8281             startlevel = 3 - sl0;
8282         }
8283 
8284         /* Check that the starting level is valid. */
8285         ok = check_s2_mmu_setup(cpu, aarch64, startlevel,
8286                                 inputsize, stride);
8287         if (!ok) {
8288             fault_type = translation_fault;
8289             goto do_fault;
8290         }
8291         level = startlevel;
8292     }
8293 
8294     indexmask_grainsize = (1ULL << (stride + 3)) - 1;
8295     indexmask = (1ULL << (inputsize - (stride * (4 - level)))) - 1;
8296 
8297     /* Now we can extract the actual base address from the TTBR */
8298     descaddr = extract64(ttbr, 0, 48);
8299     descaddr &= ~indexmask;
8300 
8301     /* The address field in the descriptor goes up to bit 39 for ARMv7
8302      * but up to bit 47 for ARMv8, but we use the descaddrmask
8303      * up to bit 39 for AArch32, because we don't need other bits in that case
8304      * to construct next descriptor address (anyway they should be all zeroes).
8305      */
8306     descaddrmask = ((1ull << (aarch64 ? 48 : 40)) - 1) &
8307                    ~indexmask_grainsize;
8308 
8309     /* Secure accesses start with the page table in secure memory and
8310      * can be downgraded to non-secure at any step. Non-secure accesses
8311      * remain non-secure. We implement this by just ORing in the NSTable/NS
8312      * bits at each step.
8313      */
8314     tableattrs = regime_is_secure(env, mmu_idx) ? 0 : (1 << 4);
8315     for (;;) {
8316         uint64_t descriptor;
8317         bool nstable;
8318 
8319         descaddr |= (address >> (stride * (4 - level))) & indexmask;
8320         descaddr &= ~7ULL;
8321         nstable = extract32(tableattrs, 4, 1);
8322         descriptor = arm_ldq_ptw(cs, descaddr, !nstable, mmu_idx, fsr, fi);
8323         if (fi->s1ptw) {
8324             goto do_fault;
8325         }
8326 
8327         if (!(descriptor & 1) ||
8328             (!(descriptor & 2) && (level == 3))) {
8329             /* Invalid, or the Reserved level 3 encoding */
8330             goto do_fault;
8331         }
8332         descaddr = descriptor & descaddrmask;
8333 
8334         if ((descriptor & 2) && (level < 3)) {
8335             /* Table entry. The top five bits are attributes which  may
8336              * propagate down through lower levels of the table (and
8337              * which are all arranged so that 0 means "no effect", so
8338              * we can gather them up by ORing in the bits at each level).
8339              */
8340             tableattrs |= extract64(descriptor, 59, 5);
8341             level++;
8342             indexmask = indexmask_grainsize;
8343             continue;
8344         }
8345         /* Block entry at level 1 or 2, or page entry at level 3.
8346          * These are basically the same thing, although the number
8347          * of bits we pull in from the vaddr varies.
8348          */
8349         page_size = (1ULL << ((stride * (4 - level)) + 3));
8350         descaddr |= (address & (page_size - 1));
8351         /* Extract attributes from the descriptor */
8352         attrs = extract64(descriptor, 2, 10)
8353             | (extract64(descriptor, 52, 12) << 10);
8354 
8355         if (mmu_idx == ARMMMUIdx_S2NS) {
8356             /* Stage 2 table descriptors do not include any attribute fields */
8357             break;
8358         }
8359         /* Merge in attributes from table descriptors */
8360         attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
8361         attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
8362         /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
8363          * means "force PL1 access only", which means forcing AP[1] to 0.
8364          */
8365         if (extract32(tableattrs, 2, 1)) {
8366             attrs &= ~(1 << 4);
8367         }
8368         attrs |= nstable << 3; /* NS */
8369         break;
8370     }
8371     /* Here descaddr is the final physical address, and attributes
8372      * are all in attrs.
8373      */
8374     fault_type = access_fault;
8375     if ((attrs & (1 << 8)) == 0) {
8376         /* Access flag */
8377         goto do_fault;
8378     }
8379 
8380     ap = extract32(attrs, 4, 2);
8381     xn = extract32(attrs, 12, 1);
8382 
8383     if (mmu_idx == ARMMMUIdx_S2NS) {
8384         ns = true;
8385         *prot = get_S2prot(env, ap, xn);
8386     } else {
8387         ns = extract32(attrs, 3, 1);
8388         pxn = extract32(attrs, 11, 1);
8389         *prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn);
8390     }
8391 
8392     fault_type = permission_fault;
8393     if (!(*prot & (1 << access_type))) {
8394         goto do_fault;
8395     }
8396 
8397     if (ns) {
8398         /* The NS bit will (as required by the architecture) have no effect if
8399          * the CPU doesn't support TZ or this is a non-secure translation
8400          * regime, because the attribute will already be non-secure.
8401          */
8402         txattrs->secure = false;
8403     }
8404     *phys_ptr = descaddr;
8405     *page_size_ptr = page_size;
8406     return false;
8407 
8408 do_fault:
8409     /* Long-descriptor format IFSR/DFSR value */
8410     *fsr = (1 << 9) | (fault_type << 2) | level;
8411     /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2.  */
8412     fi->stage2 = fi->s1ptw || (mmu_idx == ARMMMUIdx_S2NS);
8413     return true;
8414 }
8415 
8416 static inline void get_phys_addr_pmsav7_default(CPUARMState *env,
8417                                                 ARMMMUIdx mmu_idx,
8418                                                 int32_t address, int *prot)
8419 {
8420     if (!arm_feature(env, ARM_FEATURE_M)) {
8421         *prot = PAGE_READ | PAGE_WRITE;
8422         switch (address) {
8423         case 0xF0000000 ... 0xFFFFFFFF:
8424             if (regime_sctlr(env, mmu_idx) & SCTLR_V) {
8425                 /* hivecs execing is ok */
8426                 *prot |= PAGE_EXEC;
8427             }
8428             break;
8429         case 0x00000000 ... 0x7FFFFFFF:
8430             *prot |= PAGE_EXEC;
8431             break;
8432         }
8433     } else {
8434         /* Default system address map for M profile cores.
8435          * The architecture specifies which regions are execute-never;
8436          * at the MPU level no other checks are defined.
8437          */
8438         switch (address) {
8439         case 0x00000000 ... 0x1fffffff: /* ROM */
8440         case 0x20000000 ... 0x3fffffff: /* SRAM */
8441         case 0x60000000 ... 0x7fffffff: /* RAM */
8442         case 0x80000000 ... 0x9fffffff: /* RAM */
8443             *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
8444             break;
8445         case 0x40000000 ... 0x5fffffff: /* Peripheral */
8446         case 0xa0000000 ... 0xbfffffff: /* Device */
8447         case 0xc0000000 ... 0xdfffffff: /* Device */
8448         case 0xe0000000 ... 0xffffffff: /* System */
8449             *prot = PAGE_READ | PAGE_WRITE;
8450             break;
8451         default:
8452             g_assert_not_reached();
8453         }
8454     }
8455 }
8456 
8457 static bool pmsav7_use_background_region(ARMCPU *cpu,
8458                                          ARMMMUIdx mmu_idx, bool is_user)
8459 {
8460     /* Return true if we should use the default memory map as a
8461      * "background" region if there are no hits against any MPU regions.
8462      */
8463     CPUARMState *env = &cpu->env;
8464 
8465     if (is_user) {
8466         return false;
8467     }
8468 
8469     if (arm_feature(env, ARM_FEATURE_M)) {
8470         return env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)]
8471             & R_V7M_MPU_CTRL_PRIVDEFENA_MASK;
8472     } else {
8473         return regime_sctlr(env, mmu_idx) & SCTLR_BR;
8474     }
8475 }
8476 
8477 static inline bool m_is_ppb_region(CPUARMState *env, uint32_t address)
8478 {
8479     /* True if address is in the M profile PPB region 0xe0000000 - 0xe00fffff */
8480     return arm_feature(env, ARM_FEATURE_M) &&
8481         extract32(address, 20, 12) == 0xe00;
8482 }
8483 
8484 static inline bool m_is_system_region(CPUARMState *env, uint32_t address)
8485 {
8486     /* True if address is in the M profile system region
8487      * 0xe0000000 - 0xffffffff
8488      */
8489     return arm_feature(env, ARM_FEATURE_M) && extract32(address, 29, 3) == 0x7;
8490 }
8491 
8492 static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
8493                                  MMUAccessType access_type, ARMMMUIdx mmu_idx,
8494                                  hwaddr *phys_ptr, int *prot, uint32_t *fsr)
8495 {
8496     ARMCPU *cpu = arm_env_get_cpu(env);
8497     int n;
8498     bool is_user = regime_is_user(env, mmu_idx);
8499 
8500     *phys_ptr = address;
8501     *prot = 0;
8502 
8503     if (regime_translation_disabled(env, mmu_idx) ||
8504         m_is_ppb_region(env, address)) {
8505         /* MPU disabled or M profile PPB access: use default memory map.
8506          * The other case which uses the default memory map in the
8507          * v7M ARM ARM pseudocode is exception vector reads from the vector
8508          * table. In QEMU those accesses are done in arm_v7m_load_vector(),
8509          * which always does a direct read using address_space_ldl(), rather
8510          * than going via this function, so we don't need to check that here.
8511          */
8512         get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
8513     } else { /* MPU enabled */
8514         for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) {
8515             /* region search */
8516             uint32_t base = env->pmsav7.drbar[n];
8517             uint32_t rsize = extract32(env->pmsav7.drsr[n], 1, 5);
8518             uint32_t rmask;
8519             bool srdis = false;
8520 
8521             if (!(env->pmsav7.drsr[n] & 0x1)) {
8522                 continue;
8523             }
8524 
8525             if (!rsize) {
8526                 qemu_log_mask(LOG_GUEST_ERROR,
8527                               "DRSR[%d]: Rsize field cannot be 0\n", n);
8528                 continue;
8529             }
8530             rsize++;
8531             rmask = (1ull << rsize) - 1;
8532 
8533             if (base & rmask) {
8534                 qemu_log_mask(LOG_GUEST_ERROR,
8535                               "DRBAR[%d]: 0x%" PRIx32 " misaligned "
8536                               "to DRSR region size, mask = 0x%" PRIx32 "\n",
8537                               n, base, rmask);
8538                 continue;
8539             }
8540 
8541             if (address < base || address > base + rmask) {
8542                 continue;
8543             }
8544 
8545             /* Region matched */
8546 
8547             if (rsize >= 8) { /* no subregions for regions < 256 bytes */
8548                 int i, snd;
8549                 uint32_t srdis_mask;
8550 
8551                 rsize -= 3; /* sub region size (power of 2) */
8552                 snd = ((address - base) >> rsize) & 0x7;
8553                 srdis = extract32(env->pmsav7.drsr[n], snd + 8, 1);
8554 
8555                 srdis_mask = srdis ? 0x3 : 0x0;
8556                 for (i = 2; i <= 8 && rsize < TARGET_PAGE_BITS; i *= 2) {
8557                     /* This will check in groups of 2, 4 and then 8, whether
8558                      * the subregion bits are consistent. rsize is incremented
8559                      * back up to give the region size, considering consistent
8560                      * adjacent subregions as one region. Stop testing if rsize
8561                      * is already big enough for an entire QEMU page.
8562                      */
8563                     int snd_rounded = snd & ~(i - 1);
8564                     uint32_t srdis_multi = extract32(env->pmsav7.drsr[n],
8565                                                      snd_rounded + 8, i);
8566                     if (srdis_mask ^ srdis_multi) {
8567                         break;
8568                     }
8569                     srdis_mask = (srdis_mask << i) | srdis_mask;
8570                     rsize++;
8571                 }
8572             }
8573             if (rsize < TARGET_PAGE_BITS) {
8574                 qemu_log_mask(LOG_UNIMP,
8575                               "DRSR[%d]: No support for MPU (sub)region "
8576                               "alignment of %" PRIu32 " bits. Minimum is %d\n",
8577                               n, rsize, TARGET_PAGE_BITS);
8578                 continue;
8579             }
8580             if (srdis) {
8581                 continue;
8582             }
8583             break;
8584         }
8585 
8586         if (n == -1) { /* no hits */
8587             if (!pmsav7_use_background_region(cpu, mmu_idx, is_user)) {
8588                 /* background fault */
8589                 *fsr = 0;
8590                 return true;
8591             }
8592             get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
8593         } else { /* a MPU hit! */
8594             uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3);
8595             uint32_t xn = extract32(env->pmsav7.dracr[n], 12, 1);
8596 
8597             if (m_is_system_region(env, address)) {
8598                 /* System space is always execute never */
8599                 xn = 1;
8600             }
8601 
8602             if (is_user) { /* User mode AP bit decoding */
8603                 switch (ap) {
8604                 case 0:
8605                 case 1:
8606                 case 5:
8607                     break; /* no access */
8608                 case 3:
8609                     *prot |= PAGE_WRITE;
8610                     /* fall through */
8611                 case 2:
8612                 case 6:
8613                     *prot |= PAGE_READ | PAGE_EXEC;
8614                     break;
8615                 default:
8616                     qemu_log_mask(LOG_GUEST_ERROR,
8617                                   "DRACR[%d]: Bad value for AP bits: 0x%"
8618                                   PRIx32 "\n", n, ap);
8619                 }
8620             } else { /* Priv. mode AP bits decoding */
8621                 switch (ap) {
8622                 case 0:
8623                     break; /* no access */
8624                 case 1:
8625                 case 2:
8626                 case 3:
8627                     *prot |= PAGE_WRITE;
8628                     /* fall through */
8629                 case 5:
8630                 case 6:
8631                     *prot |= PAGE_READ | PAGE_EXEC;
8632                     break;
8633                 default:
8634                     qemu_log_mask(LOG_GUEST_ERROR,
8635                                   "DRACR[%d]: Bad value for AP bits: 0x%"
8636                                   PRIx32 "\n", n, ap);
8637                 }
8638             }
8639 
8640             /* execute never */
8641             if (xn) {
8642                 *prot &= ~PAGE_EXEC;
8643             }
8644         }
8645     }
8646 
8647     *fsr = 0x00d; /* Permission fault */
8648     return !(*prot & (1 << access_type));
8649 }
8650 
8651 static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
8652                                  MMUAccessType access_type, ARMMMUIdx mmu_idx,
8653                                  hwaddr *phys_ptr, int *prot, uint32_t *fsr)
8654 {
8655     ARMCPU *cpu = arm_env_get_cpu(env);
8656     bool is_user = regime_is_user(env, mmu_idx);
8657     uint32_t secure = regime_is_secure(env, mmu_idx);
8658     int n;
8659     int matchregion = -1;
8660     bool hit = false;
8661 
8662     *phys_ptr = address;
8663     *prot = 0;
8664 
8665     /* Unlike the ARM ARM pseudocode, we don't need to check whether this
8666      * was an exception vector read from the vector table (which is always
8667      * done using the default system address map), because those accesses
8668      * are done in arm_v7m_load_vector(), which always does a direct
8669      * read using address_space_ldl(), rather than going via this function.
8670      */
8671     if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */
8672         hit = true;
8673     } else if (m_is_ppb_region(env, address)) {
8674         hit = true;
8675     } else if (pmsav7_use_background_region(cpu, mmu_idx, is_user)) {
8676         hit = true;
8677     } else {
8678         for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) {
8679             /* region search */
8680             /* Note that the base address is bits [31:5] from the register
8681              * with bits [4:0] all zeroes, but the limit address is bits
8682              * [31:5] from the register with bits [4:0] all ones.
8683              */
8684             uint32_t base = env->pmsav8.rbar[secure][n] & ~0x1f;
8685             uint32_t limit = env->pmsav8.rlar[secure][n] | 0x1f;
8686 
8687             if (!(env->pmsav8.rlar[secure][n] & 0x1)) {
8688                 /* Region disabled */
8689                 continue;
8690             }
8691 
8692             if (address < base || address > limit) {
8693                 continue;
8694             }
8695 
8696             if (hit) {
8697                 /* Multiple regions match -- always a failure (unlike
8698                  * PMSAv7 where highest-numbered-region wins)
8699                  */
8700                 *fsr = 0x00d; /* permission fault */
8701                 return true;
8702             }
8703 
8704             matchregion = n;
8705             hit = true;
8706 
8707             if (base & ~TARGET_PAGE_MASK) {
8708                 qemu_log_mask(LOG_UNIMP,
8709                               "MPU_RBAR[%d]: No support for MPU region base"
8710                               "address of 0x%" PRIx32 ". Minimum alignment is "
8711                               "%d\n",
8712                               n, base, TARGET_PAGE_BITS);
8713                 continue;
8714             }
8715             if ((limit + 1) & ~TARGET_PAGE_MASK) {
8716                 qemu_log_mask(LOG_UNIMP,
8717                               "MPU_RBAR[%d]: No support for MPU region limit"
8718                               "address of 0x%" PRIx32 ". Minimum alignment is "
8719                               "%d\n",
8720                               n, limit, TARGET_PAGE_BITS);
8721                 continue;
8722             }
8723         }
8724     }
8725 
8726     if (!hit) {
8727         /* background fault */
8728         *fsr = 0;
8729         return true;
8730     }
8731 
8732     if (matchregion == -1) {
8733         /* hit using the background region */
8734         get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
8735     } else {
8736         uint32_t ap = extract32(env->pmsav8.rbar[secure][matchregion], 1, 2);
8737         uint32_t xn = extract32(env->pmsav8.rbar[secure][matchregion], 0, 1);
8738 
8739         if (m_is_system_region(env, address)) {
8740             /* System space is always execute never */
8741             xn = 1;
8742         }
8743 
8744         *prot = simple_ap_to_rw_prot(env, mmu_idx, ap);
8745         if (*prot && !xn) {
8746             *prot |= PAGE_EXEC;
8747         }
8748         /* We don't need to look the attribute up in the MAIR0/MAIR1
8749          * registers because that only tells us about cacheability.
8750          */
8751     }
8752 
8753     *fsr = 0x00d; /* Permission fault */
8754     return !(*prot & (1 << access_type));
8755 }
8756 
8757 static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
8758                                  MMUAccessType access_type, ARMMMUIdx mmu_idx,
8759                                  hwaddr *phys_ptr, int *prot, uint32_t *fsr)
8760 {
8761     int n;
8762     uint32_t mask;
8763     uint32_t base;
8764     bool is_user = regime_is_user(env, mmu_idx);
8765 
8766     if (regime_translation_disabled(env, mmu_idx)) {
8767         /* MPU disabled.  */
8768         *phys_ptr = address;
8769         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
8770         return false;
8771     }
8772 
8773     *phys_ptr = address;
8774     for (n = 7; n >= 0; n--) {
8775         base = env->cp15.c6_region[n];
8776         if ((base & 1) == 0) {
8777             continue;
8778         }
8779         mask = 1 << ((base >> 1) & 0x1f);
8780         /* Keep this shift separate from the above to avoid an
8781            (undefined) << 32.  */
8782         mask = (mask << 1) - 1;
8783         if (((base ^ address) & ~mask) == 0) {
8784             break;
8785         }
8786     }
8787     if (n < 0) {
8788         *fsr = 2;
8789         return true;
8790     }
8791 
8792     if (access_type == MMU_INST_FETCH) {
8793         mask = env->cp15.pmsav5_insn_ap;
8794     } else {
8795         mask = env->cp15.pmsav5_data_ap;
8796     }
8797     mask = (mask >> (n * 4)) & 0xf;
8798     switch (mask) {
8799     case 0:
8800         *fsr = 1;
8801         return true;
8802     case 1:
8803         if (is_user) {
8804             *fsr = 1;
8805             return true;
8806         }
8807         *prot = PAGE_READ | PAGE_WRITE;
8808         break;
8809     case 2:
8810         *prot = PAGE_READ;
8811         if (!is_user) {
8812             *prot |= PAGE_WRITE;
8813         }
8814         break;
8815     case 3:
8816         *prot = PAGE_READ | PAGE_WRITE;
8817         break;
8818     case 5:
8819         if (is_user) {
8820             *fsr = 1;
8821             return true;
8822         }
8823         *prot = PAGE_READ;
8824         break;
8825     case 6:
8826         *prot = PAGE_READ;
8827         break;
8828     default:
8829         /* Bad permission.  */
8830         *fsr = 1;
8831         return true;
8832     }
8833     *prot |= PAGE_EXEC;
8834     return false;
8835 }
8836 
8837 /* get_phys_addr - get the physical address for this virtual address
8838  *
8839  * Find the physical address corresponding to the given virtual address,
8840  * by doing a translation table walk on MMU based systems or using the
8841  * MPU state on MPU based systems.
8842  *
8843  * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
8844  * prot and page_size may not be filled in, and the populated fsr value provides
8845  * information on why the translation aborted, in the format of a
8846  * DFSR/IFSR fault register, with the following caveats:
8847  *  * we honour the short vs long DFSR format differences.
8848  *  * the WnR bit is never set (the caller must do this).
8849  *  * for PSMAv5 based systems we don't bother to return a full FSR format
8850  *    value.
8851  *
8852  * @env: CPUARMState
8853  * @address: virtual address to get physical address for
8854  * @access_type: 0 for read, 1 for write, 2 for execute
8855  * @mmu_idx: MMU index indicating required translation regime
8856  * @phys_ptr: set to the physical address corresponding to the virtual address
8857  * @attrs: set to the memory transaction attributes to use
8858  * @prot: set to the permissions for the page containing phys_ptr
8859  * @page_size: set to the size of the page containing phys_ptr
8860  * @fsr: set to the DFSR/IFSR value on failure
8861  */
8862 static bool get_phys_addr(CPUARMState *env, target_ulong address,
8863                           MMUAccessType access_type, ARMMMUIdx mmu_idx,
8864                           hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
8865                           target_ulong *page_size, uint32_t *fsr,
8866                           ARMMMUFaultInfo *fi)
8867 {
8868     if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
8869         /* Call ourselves recursively to do the stage 1 and then stage 2
8870          * translations.
8871          */
8872         if (arm_feature(env, ARM_FEATURE_EL2)) {
8873             hwaddr ipa;
8874             int s2_prot;
8875             int ret;
8876 
8877             ret = get_phys_addr(env, address, access_type,
8878                                 stage_1_mmu_idx(mmu_idx), &ipa, attrs,
8879                                 prot, page_size, fsr, fi);
8880 
8881             /* If S1 fails or S2 is disabled, return early.  */
8882             if (ret || regime_translation_disabled(env, ARMMMUIdx_S2NS)) {
8883                 *phys_ptr = ipa;
8884                 return ret;
8885             }
8886 
8887             /* S1 is done. Now do S2 translation.  */
8888             ret = get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_S2NS,
8889                                      phys_ptr, attrs, &s2_prot,
8890                                      page_size, fsr, fi);
8891             fi->s2addr = ipa;
8892             /* Combine the S1 and S2 perms.  */
8893             *prot &= s2_prot;
8894             return ret;
8895         } else {
8896             /*
8897              * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
8898              */
8899             mmu_idx = stage_1_mmu_idx(mmu_idx);
8900         }
8901     }
8902 
8903     /* The page table entries may downgrade secure to non-secure, but
8904      * cannot upgrade an non-secure translation regime's attributes
8905      * to secure.
8906      */
8907     attrs->secure = regime_is_secure(env, mmu_idx);
8908     attrs->user = regime_is_user(env, mmu_idx);
8909 
8910     /* Fast Context Switch Extension. This doesn't exist at all in v8.
8911      * In v7 and earlier it affects all stage 1 translations.
8912      */
8913     if (address < 0x02000000 && mmu_idx != ARMMMUIdx_S2NS
8914         && !arm_feature(env, ARM_FEATURE_V8)) {
8915         if (regime_el(env, mmu_idx) == 3) {
8916             address += env->cp15.fcseidr_s;
8917         } else {
8918             address += env->cp15.fcseidr_ns;
8919         }
8920     }
8921 
8922     if (arm_feature(env, ARM_FEATURE_PMSA)) {
8923         bool ret;
8924         *page_size = TARGET_PAGE_SIZE;
8925 
8926         if (arm_feature(env, ARM_FEATURE_V8)) {
8927             /* PMSAv8 */
8928             ret = get_phys_addr_pmsav8(env, address, access_type, mmu_idx,
8929                                        phys_ptr, prot, fsr);
8930         } else if (arm_feature(env, ARM_FEATURE_V7)) {
8931             /* PMSAv7 */
8932             ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
8933                                        phys_ptr, prot, fsr);
8934         } else {
8935             /* Pre-v7 MPU */
8936             ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
8937                                        phys_ptr, prot, fsr);
8938         }
8939         qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32
8940                       " mmu_idx %u -> %s (prot %c%c%c)\n",
8941                       access_type == MMU_DATA_LOAD ? "reading" :
8942                       (access_type == MMU_DATA_STORE ? "writing" : "execute"),
8943                       (uint32_t)address, mmu_idx,
8944                       ret ? "Miss" : "Hit",
8945                       *prot & PAGE_READ ? 'r' : '-',
8946                       *prot & PAGE_WRITE ? 'w' : '-',
8947                       *prot & PAGE_EXEC ? 'x' : '-');
8948 
8949         return ret;
8950     }
8951 
8952     /* Definitely a real MMU, not an MPU */
8953 
8954     if (regime_translation_disabled(env, mmu_idx)) {
8955         /* MMU disabled. */
8956         *phys_ptr = address;
8957         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
8958         *page_size = TARGET_PAGE_SIZE;
8959         return 0;
8960     }
8961 
8962     if (regime_using_lpae_format(env, mmu_idx)) {
8963         return get_phys_addr_lpae(env, address, access_type, mmu_idx, phys_ptr,
8964                                   attrs, prot, page_size, fsr, fi);
8965     } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
8966         return get_phys_addr_v6(env, address, access_type, mmu_idx, phys_ptr,
8967                                 attrs, prot, page_size, fsr, fi);
8968     } else {
8969         return get_phys_addr_v5(env, address, access_type, mmu_idx, phys_ptr,
8970                                 prot, page_size, fsr, fi);
8971     }
8972 }
8973 
8974 /* Walk the page table and (if the mapping exists) add the page
8975  * to the TLB. Return false on success, or true on failure. Populate
8976  * fsr with ARM DFSR/IFSR fault register format value on failure.
8977  */
8978 bool arm_tlb_fill(CPUState *cs, vaddr address,
8979                   MMUAccessType access_type, int mmu_idx, uint32_t *fsr,
8980                   ARMMMUFaultInfo *fi)
8981 {
8982     ARMCPU *cpu = ARM_CPU(cs);
8983     CPUARMState *env = &cpu->env;
8984     hwaddr phys_addr;
8985     target_ulong page_size;
8986     int prot;
8987     int ret;
8988     MemTxAttrs attrs = {};
8989 
8990     ret = get_phys_addr(env, address, access_type,
8991                         core_to_arm_mmu_idx(env, mmu_idx), &phys_addr,
8992                         &attrs, &prot, &page_size, fsr, fi);
8993     if (!ret) {
8994         /* Map a single [sub]page.  */
8995         phys_addr &= TARGET_PAGE_MASK;
8996         address &= TARGET_PAGE_MASK;
8997         tlb_set_page_with_attrs(cs, address, phys_addr, attrs,
8998                                 prot, mmu_idx, page_size);
8999         return 0;
9000     }
9001 
9002     return ret;
9003 }
9004 
9005 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
9006                                          MemTxAttrs *attrs)
9007 {
9008     ARMCPU *cpu = ARM_CPU(cs);
9009     CPUARMState *env = &cpu->env;
9010     hwaddr phys_addr;
9011     target_ulong page_size;
9012     int prot;
9013     bool ret;
9014     uint32_t fsr;
9015     ARMMMUFaultInfo fi = {};
9016     ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false));
9017 
9018     *attrs = (MemTxAttrs) {};
9019 
9020     ret = get_phys_addr(env, addr, 0, mmu_idx, &phys_addr,
9021                         attrs, &prot, &page_size, &fsr, &fi);
9022 
9023     if (ret) {
9024         return -1;
9025     }
9026     return phys_addr;
9027 }
9028 
9029 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
9030 {
9031     uint32_t mask;
9032     unsigned el = arm_current_el(env);
9033 
9034     /* First handle registers which unprivileged can read */
9035 
9036     switch (reg) {
9037     case 0 ... 7: /* xPSR sub-fields */
9038         mask = 0;
9039         if ((reg & 1) && el) {
9040             mask |= XPSR_EXCP; /* IPSR (unpriv. reads as zero) */
9041         }
9042         if (!(reg & 4)) {
9043             mask |= XPSR_NZCV | XPSR_Q; /* APSR */
9044         }
9045         /* EPSR reads as zero */
9046         return xpsr_read(env) & mask;
9047         break;
9048     case 20: /* CONTROL */
9049         return env->v7m.control[env->v7m.secure];
9050     case 0x94: /* CONTROL_NS */
9051         /* We have to handle this here because unprivileged Secure code
9052          * can read the NS CONTROL register.
9053          */
9054         if (!env->v7m.secure) {
9055             return 0;
9056         }
9057         return env->v7m.control[M_REG_NS];
9058     }
9059 
9060     if (el == 0) {
9061         return 0; /* unprivileged reads others as zero */
9062     }
9063 
9064     if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
9065         switch (reg) {
9066         case 0x88: /* MSP_NS */
9067             if (!env->v7m.secure) {
9068                 return 0;
9069             }
9070             return env->v7m.other_ss_msp;
9071         case 0x89: /* PSP_NS */
9072             if (!env->v7m.secure) {
9073                 return 0;
9074             }
9075             return env->v7m.other_ss_psp;
9076         case 0x90: /* PRIMASK_NS */
9077             if (!env->v7m.secure) {
9078                 return 0;
9079             }
9080             return env->v7m.primask[M_REG_NS];
9081         case 0x91: /* BASEPRI_NS */
9082             if (!env->v7m.secure) {
9083                 return 0;
9084             }
9085             return env->v7m.basepri[M_REG_NS];
9086         case 0x93: /* FAULTMASK_NS */
9087             if (!env->v7m.secure) {
9088                 return 0;
9089             }
9090             return env->v7m.faultmask[M_REG_NS];
9091         case 0x98: /* SP_NS */
9092         {
9093             /* This gives the non-secure SP selected based on whether we're
9094              * currently in handler mode or not, using the NS CONTROL.SPSEL.
9095              */
9096             bool spsel = env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK;
9097 
9098             if (!env->v7m.secure) {
9099                 return 0;
9100             }
9101             if (!arm_v7m_is_handler_mode(env) && spsel) {
9102                 return env->v7m.other_ss_psp;
9103             } else {
9104                 return env->v7m.other_ss_msp;
9105             }
9106         }
9107         default:
9108             break;
9109         }
9110     }
9111 
9112     switch (reg) {
9113     case 8: /* MSP */
9114         return (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) ?
9115             env->v7m.other_sp : env->regs[13];
9116     case 9: /* PSP */
9117         return (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) ?
9118             env->regs[13] : env->v7m.other_sp;
9119     case 16: /* PRIMASK */
9120         return env->v7m.primask[env->v7m.secure];
9121     case 17: /* BASEPRI */
9122     case 18: /* BASEPRI_MAX */
9123         return env->v7m.basepri[env->v7m.secure];
9124     case 19: /* FAULTMASK */
9125         return env->v7m.faultmask[env->v7m.secure];
9126     default:
9127         qemu_log_mask(LOG_GUEST_ERROR, "Attempt to read unknown special"
9128                                        " register %d\n", reg);
9129         return 0;
9130     }
9131 }
9132 
9133 void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
9134 {
9135     /* We're passed bits [11..0] of the instruction; extract
9136      * SYSm and the mask bits.
9137      * Invalid combinations of SYSm and mask are UNPREDICTABLE;
9138      * we choose to treat them as if the mask bits were valid.
9139      * NB that the pseudocode 'mask' variable is bits [11..10],
9140      * whereas ours is [11..8].
9141      */
9142     uint32_t mask = extract32(maskreg, 8, 4);
9143     uint32_t reg = extract32(maskreg, 0, 8);
9144 
9145     if (arm_current_el(env) == 0 && reg > 7) {
9146         /* only xPSR sub-fields may be written by unprivileged */
9147         return;
9148     }
9149 
9150     if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
9151         switch (reg) {
9152         case 0x88: /* MSP_NS */
9153             if (!env->v7m.secure) {
9154                 return;
9155             }
9156             env->v7m.other_ss_msp = val;
9157             return;
9158         case 0x89: /* PSP_NS */
9159             if (!env->v7m.secure) {
9160                 return;
9161             }
9162             env->v7m.other_ss_psp = val;
9163             return;
9164         case 0x90: /* PRIMASK_NS */
9165             if (!env->v7m.secure) {
9166                 return;
9167             }
9168             env->v7m.primask[M_REG_NS] = val & 1;
9169             return;
9170         case 0x91: /* BASEPRI_NS */
9171             if (!env->v7m.secure) {
9172                 return;
9173             }
9174             env->v7m.basepri[M_REG_NS] = val & 0xff;
9175             return;
9176         case 0x93: /* FAULTMASK_NS */
9177             if (!env->v7m.secure) {
9178                 return;
9179             }
9180             env->v7m.faultmask[M_REG_NS] = val & 1;
9181             return;
9182         case 0x98: /* SP_NS */
9183         {
9184             /* This gives the non-secure SP selected based on whether we're
9185              * currently in handler mode or not, using the NS CONTROL.SPSEL.
9186              */
9187             bool spsel = env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK;
9188 
9189             if (!env->v7m.secure) {
9190                 return;
9191             }
9192             if (!arm_v7m_is_handler_mode(env) && spsel) {
9193                 env->v7m.other_ss_psp = val;
9194             } else {
9195                 env->v7m.other_ss_msp = val;
9196             }
9197             return;
9198         }
9199         default:
9200             break;
9201         }
9202     }
9203 
9204     switch (reg) {
9205     case 0 ... 7: /* xPSR sub-fields */
9206         /* only APSR is actually writable */
9207         if (!(reg & 4)) {
9208             uint32_t apsrmask = 0;
9209 
9210             if (mask & 8) {
9211                 apsrmask |= XPSR_NZCV | XPSR_Q;
9212             }
9213             if ((mask & 4) && arm_feature(env, ARM_FEATURE_THUMB_DSP)) {
9214                 apsrmask |= XPSR_GE;
9215             }
9216             xpsr_write(env, val, apsrmask);
9217         }
9218         break;
9219     case 8: /* MSP */
9220         if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) {
9221             env->v7m.other_sp = val;
9222         } else {
9223             env->regs[13] = val;
9224         }
9225         break;
9226     case 9: /* PSP */
9227         if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) {
9228             env->regs[13] = val;
9229         } else {
9230             env->v7m.other_sp = val;
9231         }
9232         break;
9233     case 16: /* PRIMASK */
9234         env->v7m.primask[env->v7m.secure] = val & 1;
9235         break;
9236     case 17: /* BASEPRI */
9237         env->v7m.basepri[env->v7m.secure] = val & 0xff;
9238         break;
9239     case 18: /* BASEPRI_MAX */
9240         val &= 0xff;
9241         if (val != 0 && (val < env->v7m.basepri[env->v7m.secure]
9242                          || env->v7m.basepri[env->v7m.secure] == 0)) {
9243             env->v7m.basepri[env->v7m.secure] = val;
9244         }
9245         break;
9246     case 19: /* FAULTMASK */
9247         env->v7m.faultmask[env->v7m.secure] = val & 1;
9248         break;
9249     case 20: /* CONTROL */
9250         /* Writing to the SPSEL bit only has an effect if we are in
9251          * thread mode; other bits can be updated by any privileged code.
9252          * write_v7m_control_spsel() deals with updating the SPSEL bit in
9253          * env->v7m.control, so we only need update the others.
9254          */
9255         if (!arm_v7m_is_handler_mode(env)) {
9256             write_v7m_control_spsel(env, (val & R_V7M_CONTROL_SPSEL_MASK) != 0);
9257         }
9258         env->v7m.control[env->v7m.secure] &= ~R_V7M_CONTROL_NPRIV_MASK;
9259         env->v7m.control[env->v7m.secure] |= val & R_V7M_CONTROL_NPRIV_MASK;
9260         break;
9261     default:
9262         qemu_log_mask(LOG_GUEST_ERROR, "Attempt to write unknown special"
9263                                        " register %d\n", reg);
9264         return;
9265     }
9266 }
9267 
9268 #endif
9269 
9270 void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
9271 {
9272     /* Implement DC ZVA, which zeroes a fixed-length block of memory.
9273      * Note that we do not implement the (architecturally mandated)
9274      * alignment fault for attempts to use this on Device memory
9275      * (which matches the usual QEMU behaviour of not implementing either
9276      * alignment faults or any memory attribute handling).
9277      */
9278 
9279     ARMCPU *cpu = arm_env_get_cpu(env);
9280     uint64_t blocklen = 4 << cpu->dcz_blocksize;
9281     uint64_t vaddr = vaddr_in & ~(blocklen - 1);
9282 
9283 #ifndef CONFIG_USER_ONLY
9284     {
9285         /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
9286          * the block size so we might have to do more than one TLB lookup.
9287          * We know that in fact for any v8 CPU the page size is at least 4K
9288          * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
9289          * 1K as an artefact of legacy v5 subpage support being present in the
9290          * same QEMU executable.
9291          */
9292         int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE);
9293         void *hostaddr[maxidx];
9294         int try, i;
9295         unsigned mmu_idx = cpu_mmu_index(env, false);
9296         TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
9297 
9298         for (try = 0; try < 2; try++) {
9299 
9300             for (i = 0; i < maxidx; i++) {
9301                 hostaddr[i] = tlb_vaddr_to_host(env,
9302                                                 vaddr + TARGET_PAGE_SIZE * i,
9303                                                 1, mmu_idx);
9304                 if (!hostaddr[i]) {
9305                     break;
9306                 }
9307             }
9308             if (i == maxidx) {
9309                 /* If it's all in the TLB it's fair game for just writing to;
9310                  * we know we don't need to update dirty status, etc.
9311                  */
9312                 for (i = 0; i < maxidx - 1; i++) {
9313                     memset(hostaddr[i], 0, TARGET_PAGE_SIZE);
9314                 }
9315                 memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE));
9316                 return;
9317             }
9318             /* OK, try a store and see if we can populate the tlb. This
9319              * might cause an exception if the memory isn't writable,
9320              * in which case we will longjmp out of here. We must for
9321              * this purpose use the actual register value passed to us
9322              * so that we get the fault address right.
9323              */
9324             helper_ret_stb_mmu(env, vaddr_in, 0, oi, GETPC());
9325             /* Now we can populate the other TLB entries, if any */
9326             for (i = 0; i < maxidx; i++) {
9327                 uint64_t va = vaddr + TARGET_PAGE_SIZE * i;
9328                 if (va != (vaddr_in & TARGET_PAGE_MASK)) {
9329                     helper_ret_stb_mmu(env, va, 0, oi, GETPC());
9330                 }
9331             }
9332         }
9333 
9334         /* Slow path (probably attempt to do this to an I/O device or
9335          * similar, or clearing of a block of code we have translations
9336          * cached for). Just do a series of byte writes as the architecture
9337          * demands. It's not worth trying to use a cpu_physical_memory_map(),
9338          * memset(), unmap() sequence here because:
9339          *  + we'd need to account for the blocksize being larger than a page
9340          *  + the direct-RAM access case is almost always going to be dealt
9341          *    with in the fastpath code above, so there's no speed benefit
9342          *  + we would have to deal with the map returning NULL because the
9343          *    bounce buffer was in use
9344          */
9345         for (i = 0; i < blocklen; i++) {
9346             helper_ret_stb_mmu(env, vaddr + i, 0, oi, GETPC());
9347         }
9348     }
9349 #else
9350     memset(g2h(vaddr), 0, blocklen);
9351 #endif
9352 }
9353 
9354 /* Note that signed overflow is undefined in C.  The following routines are
9355    careful to use unsigned types where modulo arithmetic is required.
9356    Failure to do so _will_ break on newer gcc.  */
9357 
9358 /* Signed saturating arithmetic.  */
9359 
9360 /* Perform 16-bit signed saturating addition.  */
9361 static inline uint16_t add16_sat(uint16_t a, uint16_t b)
9362 {
9363     uint16_t res;
9364 
9365     res = a + b;
9366     if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
9367         if (a & 0x8000)
9368             res = 0x8000;
9369         else
9370             res = 0x7fff;
9371     }
9372     return res;
9373 }
9374 
9375 /* Perform 8-bit signed saturating addition.  */
9376 static inline uint8_t add8_sat(uint8_t a, uint8_t b)
9377 {
9378     uint8_t res;
9379 
9380     res = a + b;
9381     if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
9382         if (a & 0x80)
9383             res = 0x80;
9384         else
9385             res = 0x7f;
9386     }
9387     return res;
9388 }
9389 
9390 /* Perform 16-bit signed saturating subtraction.  */
9391 static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
9392 {
9393     uint16_t res;
9394 
9395     res = a - b;
9396     if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
9397         if (a & 0x8000)
9398             res = 0x8000;
9399         else
9400             res = 0x7fff;
9401     }
9402     return res;
9403 }
9404 
9405 /* Perform 8-bit signed saturating subtraction.  */
9406 static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
9407 {
9408     uint8_t res;
9409 
9410     res = a - b;
9411     if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
9412         if (a & 0x80)
9413             res = 0x80;
9414         else
9415             res = 0x7f;
9416     }
9417     return res;
9418 }
9419 
9420 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
9421 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
9422 #define ADD8(a, b, n)  RESULT(add8_sat(a, b), n, 8);
9423 #define SUB8(a, b, n)  RESULT(sub8_sat(a, b), n, 8);
9424 #define PFX q
9425 
9426 #include "op_addsub.h"
9427 
9428 /* Unsigned saturating arithmetic.  */
9429 static inline uint16_t add16_usat(uint16_t a, uint16_t b)
9430 {
9431     uint16_t res;
9432     res = a + b;
9433     if (res < a)
9434         res = 0xffff;
9435     return res;
9436 }
9437 
9438 static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
9439 {
9440     if (a > b)
9441         return a - b;
9442     else
9443         return 0;
9444 }
9445 
9446 static inline uint8_t add8_usat(uint8_t a, uint8_t b)
9447 {
9448     uint8_t res;
9449     res = a + b;
9450     if (res < a)
9451         res = 0xff;
9452     return res;
9453 }
9454 
9455 static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
9456 {
9457     if (a > b)
9458         return a - b;
9459     else
9460         return 0;
9461 }
9462 
9463 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
9464 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
9465 #define ADD8(a, b, n)  RESULT(add8_usat(a, b), n, 8);
9466 #define SUB8(a, b, n)  RESULT(sub8_usat(a, b), n, 8);
9467 #define PFX uq
9468 
9469 #include "op_addsub.h"
9470 
9471 /* Signed modulo arithmetic.  */
9472 #define SARITH16(a, b, n, op) do { \
9473     int32_t sum; \
9474     sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
9475     RESULT(sum, n, 16); \
9476     if (sum >= 0) \
9477         ge |= 3 << (n * 2); \
9478     } while(0)
9479 
9480 #define SARITH8(a, b, n, op) do { \
9481     int32_t sum; \
9482     sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
9483     RESULT(sum, n, 8); \
9484     if (sum >= 0) \
9485         ge |= 1 << n; \
9486     } while(0)
9487 
9488 
9489 #define ADD16(a, b, n) SARITH16(a, b, n, +)
9490 #define SUB16(a, b, n) SARITH16(a, b, n, -)
9491 #define ADD8(a, b, n)  SARITH8(a, b, n, +)
9492 #define SUB8(a, b, n)  SARITH8(a, b, n, -)
9493 #define PFX s
9494 #define ARITH_GE
9495 
9496 #include "op_addsub.h"
9497 
9498 /* Unsigned modulo arithmetic.  */
9499 #define ADD16(a, b, n) do { \
9500     uint32_t sum; \
9501     sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
9502     RESULT(sum, n, 16); \
9503     if ((sum >> 16) == 1) \
9504         ge |= 3 << (n * 2); \
9505     } while(0)
9506 
9507 #define ADD8(a, b, n) do { \
9508     uint32_t sum; \
9509     sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
9510     RESULT(sum, n, 8); \
9511     if ((sum >> 8) == 1) \
9512         ge |= 1 << n; \
9513     } while(0)
9514 
9515 #define SUB16(a, b, n) do { \
9516     uint32_t sum; \
9517     sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
9518     RESULT(sum, n, 16); \
9519     if ((sum >> 16) == 0) \
9520         ge |= 3 << (n * 2); \
9521     } while(0)
9522 
9523 #define SUB8(a, b, n) do { \
9524     uint32_t sum; \
9525     sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
9526     RESULT(sum, n, 8); \
9527     if ((sum >> 8) == 0) \
9528         ge |= 1 << n; \
9529     } while(0)
9530 
9531 #define PFX u
9532 #define ARITH_GE
9533 
9534 #include "op_addsub.h"
9535 
9536 /* Halved signed arithmetic.  */
9537 #define ADD16(a, b, n) \
9538   RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
9539 #define SUB16(a, b, n) \
9540   RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
9541 #define ADD8(a, b, n) \
9542   RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
9543 #define SUB8(a, b, n) \
9544   RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
9545 #define PFX sh
9546 
9547 #include "op_addsub.h"
9548 
9549 /* Halved unsigned arithmetic.  */
9550 #define ADD16(a, b, n) \
9551   RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
9552 #define SUB16(a, b, n) \
9553   RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
9554 #define ADD8(a, b, n) \
9555   RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
9556 #define SUB8(a, b, n) \
9557   RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
9558 #define PFX uh
9559 
9560 #include "op_addsub.h"
9561 
9562 static inline uint8_t do_usad(uint8_t a, uint8_t b)
9563 {
9564     if (a > b)
9565         return a - b;
9566     else
9567         return b - a;
9568 }
9569 
9570 /* Unsigned sum of absolute byte differences.  */
9571 uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
9572 {
9573     uint32_t sum;
9574     sum = do_usad(a, b);
9575     sum += do_usad(a >> 8, b >> 8);
9576     sum += do_usad(a >> 16, b >>16);
9577     sum += do_usad(a >> 24, b >> 24);
9578     return sum;
9579 }
9580 
9581 /* For ARMv6 SEL instruction.  */
9582 uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
9583 {
9584     uint32_t mask;
9585 
9586     mask = 0;
9587     if (flags & 1)
9588         mask |= 0xff;
9589     if (flags & 2)
9590         mask |= 0xff00;
9591     if (flags & 4)
9592         mask |= 0xff0000;
9593     if (flags & 8)
9594         mask |= 0xff000000;
9595     return (a & mask) | (b & ~mask);
9596 }
9597 
9598 /* VFP support.  We follow the convention used for VFP instructions:
9599    Single precision routines have a "s" suffix, double precision a
9600    "d" suffix.  */
9601 
9602 /* Convert host exception flags to vfp form.  */
9603 static inline int vfp_exceptbits_from_host(int host_bits)
9604 {
9605     int target_bits = 0;
9606 
9607     if (host_bits & float_flag_invalid)
9608         target_bits |= 1;
9609     if (host_bits & float_flag_divbyzero)
9610         target_bits |= 2;
9611     if (host_bits & float_flag_overflow)
9612         target_bits |= 4;
9613     if (host_bits & (float_flag_underflow | float_flag_output_denormal))
9614         target_bits |= 8;
9615     if (host_bits & float_flag_inexact)
9616         target_bits |= 0x10;
9617     if (host_bits & float_flag_input_denormal)
9618         target_bits |= 0x80;
9619     return target_bits;
9620 }
9621 
9622 uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
9623 {
9624     int i;
9625     uint32_t fpscr;
9626 
9627     fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
9628             | (env->vfp.vec_len << 16)
9629             | (env->vfp.vec_stride << 20);
9630     i = get_float_exception_flags(&env->vfp.fp_status);
9631     i |= get_float_exception_flags(&env->vfp.standard_fp_status);
9632     fpscr |= vfp_exceptbits_from_host(i);
9633     return fpscr;
9634 }
9635 
9636 uint32_t vfp_get_fpscr(CPUARMState *env)
9637 {
9638     return HELPER(vfp_get_fpscr)(env);
9639 }
9640 
9641 /* Convert vfp exception flags to target form.  */
9642 static inline int vfp_exceptbits_to_host(int target_bits)
9643 {
9644     int host_bits = 0;
9645 
9646     if (target_bits & 1)
9647         host_bits |= float_flag_invalid;
9648     if (target_bits & 2)
9649         host_bits |= float_flag_divbyzero;
9650     if (target_bits & 4)
9651         host_bits |= float_flag_overflow;
9652     if (target_bits & 8)
9653         host_bits |= float_flag_underflow;
9654     if (target_bits & 0x10)
9655         host_bits |= float_flag_inexact;
9656     if (target_bits & 0x80)
9657         host_bits |= float_flag_input_denormal;
9658     return host_bits;
9659 }
9660 
9661 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
9662 {
9663     int i;
9664     uint32_t changed;
9665 
9666     changed = env->vfp.xregs[ARM_VFP_FPSCR];
9667     env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
9668     env->vfp.vec_len = (val >> 16) & 7;
9669     env->vfp.vec_stride = (val >> 20) & 3;
9670 
9671     changed ^= val;
9672     if (changed & (3 << 22)) {
9673         i = (val >> 22) & 3;
9674         switch (i) {
9675         case FPROUNDING_TIEEVEN:
9676             i = float_round_nearest_even;
9677             break;
9678         case FPROUNDING_POSINF:
9679             i = float_round_up;
9680             break;
9681         case FPROUNDING_NEGINF:
9682             i = float_round_down;
9683             break;
9684         case FPROUNDING_ZERO:
9685             i = float_round_to_zero;
9686             break;
9687         }
9688         set_float_rounding_mode(i, &env->vfp.fp_status);
9689     }
9690     if (changed & (1 << 24)) {
9691         set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
9692         set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
9693     }
9694     if (changed & (1 << 25))
9695         set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
9696 
9697     i = vfp_exceptbits_to_host(val);
9698     set_float_exception_flags(i, &env->vfp.fp_status);
9699     set_float_exception_flags(0, &env->vfp.standard_fp_status);
9700 }
9701 
9702 void vfp_set_fpscr(CPUARMState *env, uint32_t val)
9703 {
9704     HELPER(vfp_set_fpscr)(env, val);
9705 }
9706 
9707 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
9708 
9709 #define VFP_BINOP(name) \
9710 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
9711 { \
9712     float_status *fpst = fpstp; \
9713     return float32_ ## name(a, b, fpst); \
9714 } \
9715 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
9716 { \
9717     float_status *fpst = fpstp; \
9718     return float64_ ## name(a, b, fpst); \
9719 }
9720 VFP_BINOP(add)
9721 VFP_BINOP(sub)
9722 VFP_BINOP(mul)
9723 VFP_BINOP(div)
9724 VFP_BINOP(min)
9725 VFP_BINOP(max)
9726 VFP_BINOP(minnum)
9727 VFP_BINOP(maxnum)
9728 #undef VFP_BINOP
9729 
9730 float32 VFP_HELPER(neg, s)(float32 a)
9731 {
9732     return float32_chs(a);
9733 }
9734 
9735 float64 VFP_HELPER(neg, d)(float64 a)
9736 {
9737     return float64_chs(a);
9738 }
9739 
9740 float32 VFP_HELPER(abs, s)(float32 a)
9741 {
9742     return float32_abs(a);
9743 }
9744 
9745 float64 VFP_HELPER(abs, d)(float64 a)
9746 {
9747     return float64_abs(a);
9748 }
9749 
9750 float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
9751 {
9752     return float32_sqrt(a, &env->vfp.fp_status);
9753 }
9754 
9755 float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
9756 {
9757     return float64_sqrt(a, &env->vfp.fp_status);
9758 }
9759 
9760 /* XXX: check quiet/signaling case */
9761 #define DO_VFP_cmp(p, type) \
9762 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env)  \
9763 { \
9764     uint32_t flags; \
9765     switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
9766     case 0: flags = 0x6; break; \
9767     case -1: flags = 0x8; break; \
9768     case 1: flags = 0x2; break; \
9769     default: case 2: flags = 0x3; break; \
9770     } \
9771     env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
9772         | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
9773 } \
9774 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
9775 { \
9776     uint32_t flags; \
9777     switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
9778     case 0: flags = 0x6; break; \
9779     case -1: flags = 0x8; break; \
9780     case 1: flags = 0x2; break; \
9781     default: case 2: flags = 0x3; break; \
9782     } \
9783     env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
9784         | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
9785 }
9786 DO_VFP_cmp(s, float32)
9787 DO_VFP_cmp(d, float64)
9788 #undef DO_VFP_cmp
9789 
9790 /* Integer to float and float to integer conversions */
9791 
9792 #define CONV_ITOF(name, fsz, sign) \
9793     float##fsz HELPER(name)(uint32_t x, void *fpstp) \
9794 { \
9795     float_status *fpst = fpstp; \
9796     return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
9797 }
9798 
9799 #define CONV_FTOI(name, fsz, sign, round) \
9800 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
9801 { \
9802     float_status *fpst = fpstp; \
9803     if (float##fsz##_is_any_nan(x)) { \
9804         float_raise(float_flag_invalid, fpst); \
9805         return 0; \
9806     } \
9807     return float##fsz##_to_##sign##int32##round(x, fpst); \
9808 }
9809 
9810 #define FLOAT_CONVS(name, p, fsz, sign) \
9811 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
9812 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
9813 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
9814 
9815 FLOAT_CONVS(si, s, 32, )
9816 FLOAT_CONVS(si, d, 64, )
9817 FLOAT_CONVS(ui, s, 32, u)
9818 FLOAT_CONVS(ui, d, 64, u)
9819 
9820 #undef CONV_ITOF
9821 #undef CONV_FTOI
9822 #undef FLOAT_CONVS
9823 
9824 /* floating point conversion */
9825 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
9826 {
9827     float64 r = float32_to_float64(x, &env->vfp.fp_status);
9828     /* ARM requires that S<->D conversion of any kind of NaN generates
9829      * a quiet NaN by forcing the most significant frac bit to 1.
9830      */
9831     return float64_maybe_silence_nan(r, &env->vfp.fp_status);
9832 }
9833 
9834 float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
9835 {
9836     float32 r =  float64_to_float32(x, &env->vfp.fp_status);
9837     /* ARM requires that S<->D conversion of any kind of NaN generates
9838      * a quiet NaN by forcing the most significant frac bit to 1.
9839      */
9840     return float32_maybe_silence_nan(r, &env->vfp.fp_status);
9841 }
9842 
9843 /* VFP3 fixed point conversion.  */
9844 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
9845 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t  x, uint32_t shift, \
9846                                      void *fpstp) \
9847 { \
9848     float_status *fpst = fpstp; \
9849     float##fsz tmp; \
9850     tmp = itype##_to_##float##fsz(x, fpst); \
9851     return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
9852 }
9853 
9854 /* Notice that we want only input-denormal exception flags from the
9855  * scalbn operation: the other possible flags (overflow+inexact if
9856  * we overflow to infinity, output-denormal) aren't correct for the
9857  * complete scale-and-convert operation.
9858  */
9859 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \
9860 uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \
9861                                              uint32_t shift, \
9862                                              void *fpstp) \
9863 { \
9864     float_status *fpst = fpstp; \
9865     int old_exc_flags = get_float_exception_flags(fpst); \
9866     float##fsz tmp; \
9867     if (float##fsz##_is_any_nan(x)) { \
9868         float_raise(float_flag_invalid, fpst); \
9869         return 0; \
9870     } \
9871     tmp = float##fsz##_scalbn(x, shift, fpst); \
9872     old_exc_flags |= get_float_exception_flags(fpst) \
9873         & float_flag_input_denormal; \
9874     set_float_exception_flags(old_exc_flags, fpst); \
9875     return float##fsz##_to_##itype##round(tmp, fpst); \
9876 }
9877 
9878 #define VFP_CONV_FIX(name, p, fsz, isz, itype)                   \
9879 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype)                     \
9880 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \
9881 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
9882 
9883 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype)               \
9884 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype)                     \
9885 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
9886 
9887 VFP_CONV_FIX(sh, d, 64, 64, int16)
9888 VFP_CONV_FIX(sl, d, 64, 64, int32)
9889 VFP_CONV_FIX_A64(sq, d, 64, 64, int64)
9890 VFP_CONV_FIX(uh, d, 64, 64, uint16)
9891 VFP_CONV_FIX(ul, d, 64, 64, uint32)
9892 VFP_CONV_FIX_A64(uq, d, 64, 64, uint64)
9893 VFP_CONV_FIX(sh, s, 32, 32, int16)
9894 VFP_CONV_FIX(sl, s, 32, 32, int32)
9895 VFP_CONV_FIX_A64(sq, s, 32, 64, int64)
9896 VFP_CONV_FIX(uh, s, 32, 32, uint16)
9897 VFP_CONV_FIX(ul, s, 32, 32, uint32)
9898 VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
9899 #undef VFP_CONV_FIX
9900 #undef VFP_CONV_FIX_FLOAT
9901 #undef VFP_CONV_FLOAT_FIX_ROUND
9902 
9903 /* Set the current fp rounding mode and return the old one.
9904  * The argument is a softfloat float_round_ value.
9905  */
9906 uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env)
9907 {
9908     float_status *fp_status = &env->vfp.fp_status;
9909 
9910     uint32_t prev_rmode = get_float_rounding_mode(fp_status);
9911     set_float_rounding_mode(rmode, fp_status);
9912 
9913     return prev_rmode;
9914 }
9915 
9916 /* Set the current fp rounding mode in the standard fp status and return
9917  * the old one. This is for NEON instructions that need to change the
9918  * rounding mode but wish to use the standard FPSCR values for everything
9919  * else. Always set the rounding mode back to the correct value after
9920  * modifying it.
9921  * The argument is a softfloat float_round_ value.
9922  */
9923 uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
9924 {
9925     float_status *fp_status = &env->vfp.standard_fp_status;
9926 
9927     uint32_t prev_rmode = get_float_rounding_mode(fp_status);
9928     set_float_rounding_mode(rmode, fp_status);
9929 
9930     return prev_rmode;
9931 }
9932 
9933 /* Half precision conversions.  */
9934 static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
9935 {
9936     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
9937     float32 r = float16_to_float32(make_float16(a), ieee, s);
9938     if (ieee) {
9939         return float32_maybe_silence_nan(r, s);
9940     }
9941     return r;
9942 }
9943 
9944 static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
9945 {
9946     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
9947     float16 r = float32_to_float16(a, ieee, s);
9948     if (ieee) {
9949         r = float16_maybe_silence_nan(r, s);
9950     }
9951     return float16_val(r);
9952 }
9953 
9954 float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
9955 {
9956     return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
9957 }
9958 
9959 uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
9960 {
9961     return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
9962 }
9963 
9964 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
9965 {
9966     return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
9967 }
9968 
9969 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
9970 {
9971     return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
9972 }
9973 
9974 float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env)
9975 {
9976     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
9977     float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status);
9978     if (ieee) {
9979         return float64_maybe_silence_nan(r, &env->vfp.fp_status);
9980     }
9981     return r;
9982 }
9983 
9984 uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env)
9985 {
9986     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
9987     float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status);
9988     if (ieee) {
9989         r = float16_maybe_silence_nan(r, &env->vfp.fp_status);
9990     }
9991     return float16_val(r);
9992 }
9993 
9994 #define float32_two make_float32(0x40000000)
9995 #define float32_three make_float32(0x40400000)
9996 #define float32_one_point_five make_float32(0x3fc00000)
9997 
9998 float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
9999 {
10000     float_status *s = &env->vfp.standard_fp_status;
10001     if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
10002         (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
10003         if (!(float32_is_zero(a) || float32_is_zero(b))) {
10004             float_raise(float_flag_input_denormal, s);
10005         }
10006         return float32_two;
10007     }
10008     return float32_sub(float32_two, float32_mul(a, b, s), s);
10009 }
10010 
10011 float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
10012 {
10013     float_status *s = &env->vfp.standard_fp_status;
10014     float32 product;
10015     if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
10016         (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
10017         if (!(float32_is_zero(a) || float32_is_zero(b))) {
10018             float_raise(float_flag_input_denormal, s);
10019         }
10020         return float32_one_point_five;
10021     }
10022     product = float32_mul(a, b, s);
10023     return float32_div(float32_sub(float32_three, product, s), float32_two, s);
10024 }
10025 
10026 /* NEON helpers.  */
10027 
10028 /* Constants 256 and 512 are used in some helpers; we avoid relying on
10029  * int->float conversions at run-time.  */
10030 #define float64_256 make_float64(0x4070000000000000LL)
10031 #define float64_512 make_float64(0x4080000000000000LL)
10032 #define float32_maxnorm make_float32(0x7f7fffff)
10033 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
10034 
10035 /* Reciprocal functions
10036  *
10037  * The algorithm that must be used to calculate the estimate
10038  * is specified by the ARM ARM, see FPRecipEstimate()
10039  */
10040 
10041 static float64 recip_estimate(float64 a, float_status *real_fp_status)
10042 {
10043     /* These calculations mustn't set any fp exception flags,
10044      * so we use a local copy of the fp_status.
10045      */
10046     float_status dummy_status = *real_fp_status;
10047     float_status *s = &dummy_status;
10048     /* q = (int)(a * 512.0) */
10049     float64 q = float64_mul(float64_512, a, s);
10050     int64_t q_int = float64_to_int64_round_to_zero(q, s);
10051 
10052     /* r = 1.0 / (((double)q + 0.5) / 512.0) */
10053     q = int64_to_float64(q_int, s);
10054     q = float64_add(q, float64_half, s);
10055     q = float64_div(q, float64_512, s);
10056     q = float64_div(float64_one, q, s);
10057 
10058     /* s = (int)(256.0 * r + 0.5) */
10059     q = float64_mul(q, float64_256, s);
10060     q = float64_add(q, float64_half, s);
10061     q_int = float64_to_int64_round_to_zero(q, s);
10062 
10063     /* return (double)s / 256.0 */
10064     return float64_div(int64_to_float64(q_int, s), float64_256, s);
10065 }
10066 
10067 /* Common wrapper to call recip_estimate */
10068 static float64 call_recip_estimate(float64 num, int off, float_status *fpst)
10069 {
10070     uint64_t val64 = float64_val(num);
10071     uint64_t frac = extract64(val64, 0, 52);
10072     int64_t exp = extract64(val64, 52, 11);
10073     uint64_t sbit;
10074     float64 scaled, estimate;
10075 
10076     /* Generate the scaled number for the estimate function */
10077     if (exp == 0) {
10078         if (extract64(frac, 51, 1) == 0) {
10079             exp = -1;
10080             frac = extract64(frac, 0, 50) << 2;
10081         } else {
10082             frac = extract64(frac, 0, 51) << 1;
10083         }
10084     }
10085 
10086     /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */
10087     scaled = make_float64((0x3feULL << 52)
10088                           | extract64(frac, 44, 8) << 44);
10089 
10090     estimate = recip_estimate(scaled, fpst);
10091 
10092     /* Build new result */
10093     val64 = float64_val(estimate);
10094     sbit = 0x8000000000000000ULL & val64;
10095     exp = off - exp;
10096     frac = extract64(val64, 0, 52);
10097 
10098     if (exp == 0) {
10099         frac = 1ULL << 51 | extract64(frac, 1, 51);
10100     } else if (exp == -1) {
10101         frac = 1ULL << 50 | extract64(frac, 2, 50);
10102         exp = 0;
10103     }
10104 
10105     return make_float64(sbit | (exp << 52) | frac);
10106 }
10107 
10108 static bool round_to_inf(float_status *fpst, bool sign_bit)
10109 {
10110     switch (fpst->float_rounding_mode) {
10111     case float_round_nearest_even: /* Round to Nearest */
10112         return true;
10113     case float_round_up: /* Round to +Inf */
10114         return !sign_bit;
10115     case float_round_down: /* Round to -Inf */
10116         return sign_bit;
10117     case float_round_to_zero: /* Round to Zero */
10118         return false;
10119     }
10120 
10121     g_assert_not_reached();
10122 }
10123 
10124 float32 HELPER(recpe_f32)(float32 input, void *fpstp)
10125 {
10126     float_status *fpst = fpstp;
10127     float32 f32 = float32_squash_input_denormal(input, fpst);
10128     uint32_t f32_val = float32_val(f32);
10129     uint32_t f32_sbit = 0x80000000ULL & f32_val;
10130     int32_t f32_exp = extract32(f32_val, 23, 8);
10131     uint32_t f32_frac = extract32(f32_val, 0, 23);
10132     float64 f64, r64;
10133     uint64_t r64_val;
10134     int64_t r64_exp;
10135     uint64_t r64_frac;
10136 
10137     if (float32_is_any_nan(f32)) {
10138         float32 nan = f32;
10139         if (float32_is_signaling_nan(f32, fpst)) {
10140             float_raise(float_flag_invalid, fpst);
10141             nan = float32_maybe_silence_nan(f32, fpst);
10142         }
10143         if (fpst->default_nan_mode) {
10144             nan =  float32_default_nan(fpst);
10145         }
10146         return nan;
10147     } else if (float32_is_infinity(f32)) {
10148         return float32_set_sign(float32_zero, float32_is_neg(f32));
10149     } else if (float32_is_zero(f32)) {
10150         float_raise(float_flag_divbyzero, fpst);
10151         return float32_set_sign(float32_infinity, float32_is_neg(f32));
10152     } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) {
10153         /* Abs(value) < 2.0^-128 */
10154         float_raise(float_flag_overflow | float_flag_inexact, fpst);
10155         if (round_to_inf(fpst, f32_sbit)) {
10156             return float32_set_sign(float32_infinity, float32_is_neg(f32));
10157         } else {
10158             return float32_set_sign(float32_maxnorm, float32_is_neg(f32));
10159         }
10160     } else if (f32_exp >= 253 && fpst->flush_to_zero) {
10161         float_raise(float_flag_underflow, fpst);
10162         return float32_set_sign(float32_zero, float32_is_neg(f32));
10163     }
10164 
10165 
10166     f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29);
10167     r64 = call_recip_estimate(f64, 253, fpst);
10168     r64_val = float64_val(r64);
10169     r64_exp = extract64(r64_val, 52, 11);
10170     r64_frac = extract64(r64_val, 0, 52);
10171 
10172     /* result = sign : result_exp<7:0> : fraction<51:29>; */
10173     return make_float32(f32_sbit |
10174                         (r64_exp & 0xff) << 23 |
10175                         extract64(r64_frac, 29, 24));
10176 }
10177 
10178 float64 HELPER(recpe_f64)(float64 input, void *fpstp)
10179 {
10180     float_status *fpst = fpstp;
10181     float64 f64 = float64_squash_input_denormal(input, fpst);
10182     uint64_t f64_val = float64_val(f64);
10183     uint64_t f64_sbit = 0x8000000000000000ULL & f64_val;
10184     int64_t f64_exp = extract64(f64_val, 52, 11);
10185     float64 r64;
10186     uint64_t r64_val;
10187     int64_t r64_exp;
10188     uint64_t r64_frac;
10189 
10190     /* Deal with any special cases */
10191     if (float64_is_any_nan(f64)) {
10192         float64 nan = f64;
10193         if (float64_is_signaling_nan(f64, fpst)) {
10194             float_raise(float_flag_invalid, fpst);
10195             nan = float64_maybe_silence_nan(f64, fpst);
10196         }
10197         if (fpst->default_nan_mode) {
10198             nan =  float64_default_nan(fpst);
10199         }
10200         return nan;
10201     } else if (float64_is_infinity(f64)) {
10202         return float64_set_sign(float64_zero, float64_is_neg(f64));
10203     } else if (float64_is_zero(f64)) {
10204         float_raise(float_flag_divbyzero, fpst);
10205         return float64_set_sign(float64_infinity, float64_is_neg(f64));
10206     } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) {
10207         /* Abs(value) < 2.0^-1024 */
10208         float_raise(float_flag_overflow | float_flag_inexact, fpst);
10209         if (round_to_inf(fpst, f64_sbit)) {
10210             return float64_set_sign(float64_infinity, float64_is_neg(f64));
10211         } else {
10212             return float64_set_sign(float64_maxnorm, float64_is_neg(f64));
10213         }
10214     } else if (f64_exp >= 2045 && fpst->flush_to_zero) {
10215         float_raise(float_flag_underflow, fpst);
10216         return float64_set_sign(float64_zero, float64_is_neg(f64));
10217     }
10218 
10219     r64 = call_recip_estimate(f64, 2045, fpst);
10220     r64_val = float64_val(r64);
10221     r64_exp = extract64(r64_val, 52, 11);
10222     r64_frac = extract64(r64_val, 0, 52);
10223 
10224     /* result = sign : result_exp<10:0> : fraction<51:0> */
10225     return make_float64(f64_sbit |
10226                         ((r64_exp & 0x7ff) << 52) |
10227                         r64_frac);
10228 }
10229 
10230 /* The algorithm that must be used to calculate the estimate
10231  * is specified by the ARM ARM.
10232  */
10233 static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status)
10234 {
10235     /* These calculations mustn't set any fp exception flags,
10236      * so we use a local copy of the fp_status.
10237      */
10238     float_status dummy_status = *real_fp_status;
10239     float_status *s = &dummy_status;
10240     float64 q;
10241     int64_t q_int;
10242 
10243     if (float64_lt(a, float64_half, s)) {
10244         /* range 0.25 <= a < 0.5 */
10245 
10246         /* a in units of 1/512 rounded down */
10247         /* q0 = (int)(a * 512.0);  */
10248         q = float64_mul(float64_512, a, s);
10249         q_int = float64_to_int64_round_to_zero(q, s);
10250 
10251         /* reciprocal root r */
10252         /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0);  */
10253         q = int64_to_float64(q_int, s);
10254         q = float64_add(q, float64_half, s);
10255         q = float64_div(q, float64_512, s);
10256         q = float64_sqrt(q, s);
10257         q = float64_div(float64_one, q, s);
10258     } else {
10259         /* range 0.5 <= a < 1.0 */
10260 
10261         /* a in units of 1/256 rounded down */
10262         /* q1 = (int)(a * 256.0); */
10263         q = float64_mul(float64_256, a, s);
10264         int64_t q_int = float64_to_int64_round_to_zero(q, s);
10265 
10266         /* reciprocal root r */
10267         /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
10268         q = int64_to_float64(q_int, s);
10269         q = float64_add(q, float64_half, s);
10270         q = float64_div(q, float64_256, s);
10271         q = float64_sqrt(q, s);
10272         q = float64_div(float64_one, q, s);
10273     }
10274     /* r in units of 1/256 rounded to nearest */
10275     /* s = (int)(256.0 * r + 0.5); */
10276 
10277     q = float64_mul(q, float64_256,s );
10278     q = float64_add(q, float64_half, s);
10279     q_int = float64_to_int64_round_to_zero(q, s);
10280 
10281     /* return (double)s / 256.0;*/
10282     return float64_div(int64_to_float64(q_int, s), float64_256, s);
10283 }
10284 
10285 float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
10286 {
10287     float_status *s = fpstp;
10288     float32 f32 = float32_squash_input_denormal(input, s);
10289     uint32_t val = float32_val(f32);
10290     uint32_t f32_sbit = 0x80000000 & val;
10291     int32_t f32_exp = extract32(val, 23, 8);
10292     uint32_t f32_frac = extract32(val, 0, 23);
10293     uint64_t f64_frac;
10294     uint64_t val64;
10295     int result_exp;
10296     float64 f64;
10297 
10298     if (float32_is_any_nan(f32)) {
10299         float32 nan = f32;
10300         if (float32_is_signaling_nan(f32, s)) {
10301             float_raise(float_flag_invalid, s);
10302             nan = float32_maybe_silence_nan(f32, s);
10303         }
10304         if (s->default_nan_mode) {
10305             nan =  float32_default_nan(s);
10306         }
10307         return nan;
10308     } else if (float32_is_zero(f32)) {
10309         float_raise(float_flag_divbyzero, s);
10310         return float32_set_sign(float32_infinity, float32_is_neg(f32));
10311     } else if (float32_is_neg(f32)) {
10312         float_raise(float_flag_invalid, s);
10313         return float32_default_nan(s);
10314     } else if (float32_is_infinity(f32)) {
10315         return float32_zero;
10316     }
10317 
10318     /* Scale and normalize to a double-precision value between 0.25 and 1.0,
10319      * preserving the parity of the exponent.  */
10320 
10321     f64_frac = ((uint64_t) f32_frac) << 29;
10322     if (f32_exp == 0) {
10323         while (extract64(f64_frac, 51, 1) == 0) {
10324             f64_frac = f64_frac << 1;
10325             f32_exp = f32_exp-1;
10326         }
10327         f64_frac = extract64(f64_frac, 0, 51) << 1;
10328     }
10329 
10330     if (extract64(f32_exp, 0, 1) == 0) {
10331         f64 = make_float64(((uint64_t) f32_sbit) << 32
10332                            | (0x3feULL << 52)
10333                            | f64_frac);
10334     } else {
10335         f64 = make_float64(((uint64_t) f32_sbit) << 32
10336                            | (0x3fdULL << 52)
10337                            | f64_frac);
10338     }
10339 
10340     result_exp = (380 - f32_exp) / 2;
10341 
10342     f64 = recip_sqrt_estimate(f64, s);
10343 
10344     val64 = float64_val(f64);
10345 
10346     val = ((result_exp & 0xff) << 23)
10347         | ((val64 >> 29)  & 0x7fffff);
10348     return make_float32(val);
10349 }
10350 
10351 float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
10352 {
10353     float_status *s = fpstp;
10354     float64 f64 = float64_squash_input_denormal(input, s);
10355     uint64_t val = float64_val(f64);
10356     uint64_t f64_sbit = 0x8000000000000000ULL & val;
10357     int64_t f64_exp = extract64(val, 52, 11);
10358     uint64_t f64_frac = extract64(val, 0, 52);
10359     int64_t result_exp;
10360     uint64_t result_frac;
10361 
10362     if (float64_is_any_nan(f64)) {
10363         float64 nan = f64;
10364         if (float64_is_signaling_nan(f64, s)) {
10365             float_raise(float_flag_invalid, s);
10366             nan = float64_maybe_silence_nan(f64, s);
10367         }
10368         if (s->default_nan_mode) {
10369             nan =  float64_default_nan(s);
10370         }
10371         return nan;
10372     } else if (float64_is_zero(f64)) {
10373         float_raise(float_flag_divbyzero, s);
10374         return float64_set_sign(float64_infinity, float64_is_neg(f64));
10375     } else if (float64_is_neg(f64)) {
10376         float_raise(float_flag_invalid, s);
10377         return float64_default_nan(s);
10378     } else if (float64_is_infinity(f64)) {
10379         return float64_zero;
10380     }
10381 
10382     /* Scale and normalize to a double-precision value between 0.25 and 1.0,
10383      * preserving the parity of the exponent.  */
10384 
10385     if (f64_exp == 0) {
10386         while (extract64(f64_frac, 51, 1) == 0) {
10387             f64_frac = f64_frac << 1;
10388             f64_exp = f64_exp - 1;
10389         }
10390         f64_frac = extract64(f64_frac, 0, 51) << 1;
10391     }
10392 
10393     if (extract64(f64_exp, 0, 1) == 0) {
10394         f64 = make_float64(f64_sbit
10395                            | (0x3feULL << 52)
10396                            | f64_frac);
10397     } else {
10398         f64 = make_float64(f64_sbit
10399                            | (0x3fdULL << 52)
10400                            | f64_frac);
10401     }
10402 
10403     result_exp = (3068 - f64_exp) / 2;
10404 
10405     f64 = recip_sqrt_estimate(f64, s);
10406 
10407     result_frac = extract64(float64_val(f64), 0, 52);
10408 
10409     return make_float64(f64_sbit |
10410                         ((result_exp & 0x7ff) << 52) |
10411                         result_frac);
10412 }
10413 
10414 uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
10415 {
10416     float_status *s = fpstp;
10417     float64 f64;
10418 
10419     if ((a & 0x80000000) == 0) {
10420         return 0xffffffff;
10421     }
10422 
10423     f64 = make_float64((0x3feULL << 52)
10424                        | ((int64_t)(a & 0x7fffffff) << 21));
10425 
10426     f64 = recip_estimate(f64, s);
10427 
10428     return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
10429 }
10430 
10431 uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp)
10432 {
10433     float_status *fpst = fpstp;
10434     float64 f64;
10435 
10436     if ((a & 0xc0000000) == 0) {
10437         return 0xffffffff;
10438     }
10439 
10440     if (a & 0x80000000) {
10441         f64 = make_float64((0x3feULL << 52)
10442                            | ((uint64_t)(a & 0x7fffffff) << 21));
10443     } else { /* bits 31-30 == '01' */
10444         f64 = make_float64((0x3fdULL << 52)
10445                            | ((uint64_t)(a & 0x3fffffff) << 22));
10446     }
10447 
10448     f64 = recip_sqrt_estimate(f64, fpst);
10449 
10450     return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
10451 }
10452 
10453 /* VFPv4 fused multiply-accumulate */
10454 float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
10455 {
10456     float_status *fpst = fpstp;
10457     return float32_muladd(a, b, c, 0, fpst);
10458 }
10459 
10460 float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
10461 {
10462     float_status *fpst = fpstp;
10463     return float64_muladd(a, b, c, 0, fpst);
10464 }
10465 
10466 /* ARMv8 round to integral */
10467 float32 HELPER(rints_exact)(float32 x, void *fp_status)
10468 {
10469     return float32_round_to_int(x, fp_status);
10470 }
10471 
10472 float64 HELPER(rintd_exact)(float64 x, void *fp_status)
10473 {
10474     return float64_round_to_int(x, fp_status);
10475 }
10476 
10477 float32 HELPER(rints)(float32 x, void *fp_status)
10478 {
10479     int old_flags = get_float_exception_flags(fp_status), new_flags;
10480     float32 ret;
10481 
10482     ret = float32_round_to_int(x, fp_status);
10483 
10484     /* Suppress any inexact exceptions the conversion produced */
10485     if (!(old_flags & float_flag_inexact)) {
10486         new_flags = get_float_exception_flags(fp_status);
10487         set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
10488     }
10489 
10490     return ret;
10491 }
10492 
10493 float64 HELPER(rintd)(float64 x, void *fp_status)
10494 {
10495     int old_flags = get_float_exception_flags(fp_status), new_flags;
10496     float64 ret;
10497 
10498     ret = float64_round_to_int(x, fp_status);
10499 
10500     new_flags = get_float_exception_flags(fp_status);
10501 
10502     /* Suppress any inexact exceptions the conversion produced */
10503     if (!(old_flags & float_flag_inexact)) {
10504         new_flags = get_float_exception_flags(fp_status);
10505         set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
10506     }
10507 
10508     return ret;
10509 }
10510 
10511 /* Convert ARM rounding mode to softfloat */
10512 int arm_rmode_to_sf(int rmode)
10513 {
10514     switch (rmode) {
10515     case FPROUNDING_TIEAWAY:
10516         rmode = float_round_ties_away;
10517         break;
10518     case FPROUNDING_ODD:
10519         /* FIXME: add support for TIEAWAY and ODD */
10520         qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n",
10521                       rmode);
10522     case FPROUNDING_TIEEVEN:
10523     default:
10524         rmode = float_round_nearest_even;
10525         break;
10526     case FPROUNDING_POSINF:
10527         rmode = float_round_up;
10528         break;
10529     case FPROUNDING_NEGINF:
10530         rmode = float_round_down;
10531         break;
10532     case FPROUNDING_ZERO:
10533         rmode = float_round_to_zero;
10534         break;
10535     }
10536     return rmode;
10537 }
10538 
10539 /* CRC helpers.
10540  * The upper bytes of val (above the number specified by 'bytes') must have
10541  * been zeroed out by the caller.
10542  */
10543 uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes)
10544 {
10545     uint8_t buf[4];
10546 
10547     stl_le_p(buf, val);
10548 
10549     /* zlib crc32 converts the accumulator and output to one's complement.  */
10550     return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff;
10551 }
10552 
10553 uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes)
10554 {
10555     uint8_t buf[4];
10556 
10557     stl_le_p(buf, val);
10558 
10559     /* Linux crc32c converts the output to one's complement.  */
10560     return crc32c(acc, buf, bytes) ^ 0xffffffff;
10561 }
10562