1 /* 2 * ARM generic helpers. 3 * 4 * This code is licensed under the GNU GPL v2 or later. 5 * 6 * SPDX-License-Identifier: GPL-2.0-or-later 7 */ 8 9 #include "qemu/osdep.h" 10 #include "qemu/units.h" 11 #include "qemu/log.h" 12 #include "trace.h" 13 #include "cpu.h" 14 #include "internals.h" 15 #include "exec/helper-proto.h" 16 #include "qemu/host-utils.h" 17 #include "qemu/main-loop.h" 18 #include "qemu/timer.h" 19 #include "qemu/bitops.h" 20 #include "qemu/crc32c.h" 21 #include "qemu/qemu-print.h" 22 #include "exec/exec-all.h" 23 #include <zlib.h> /* For crc32 */ 24 #include "hw/irq.h" 25 #include "semihosting/semihost.h" 26 #include "sysemu/cpus.h" 27 #include "sysemu/cpu-timers.h" 28 #include "sysemu/kvm.h" 29 #include "qemu/range.h" 30 #include "qapi/qapi-commands-machine-target.h" 31 #include "qapi/error.h" 32 #include "qemu/guest-random.h" 33 #ifdef CONFIG_TCG 34 #include "arm_ldst.h" 35 #include "exec/cpu_ldst.h" 36 #include "semihosting/common-semi.h" 37 #endif 38 #include "cpregs.h" 39 40 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ 41 42 static void switch_mode(CPUARMState *env, int mode); 43 44 static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri) 45 { 46 assert(ri->fieldoffset); 47 if (cpreg_field_is_64bit(ri)) { 48 return CPREG_FIELD64(env, ri); 49 } else { 50 return CPREG_FIELD32(env, ri); 51 } 52 } 53 54 void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) 55 { 56 assert(ri->fieldoffset); 57 if (cpreg_field_is_64bit(ri)) { 58 CPREG_FIELD64(env, ri) = value; 59 } else { 60 CPREG_FIELD32(env, ri) = value; 61 } 62 } 63 64 static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri) 65 { 66 return (char *)env + ri->fieldoffset; 67 } 68 69 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri) 70 { 71 /* Raw read of a coprocessor register (as needed for migration, etc). */ 72 if (ri->type & ARM_CP_CONST) { 73 return ri->resetvalue; 74 } else if (ri->raw_readfn) { 75 return ri->raw_readfn(env, ri); 76 } else if (ri->readfn) { 77 return ri->readfn(env, ri); 78 } else { 79 return raw_read(env, ri); 80 } 81 } 82 83 static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri, 84 uint64_t v) 85 { 86 /* Raw write of a coprocessor register (as needed for migration, etc). 87 * Note that constant registers are treated as write-ignored; the 88 * caller should check for success by whether a readback gives the 89 * value written. 90 */ 91 if (ri->type & ARM_CP_CONST) { 92 return; 93 } else if (ri->raw_writefn) { 94 ri->raw_writefn(env, ri, v); 95 } else if (ri->writefn) { 96 ri->writefn(env, ri, v); 97 } else { 98 raw_write(env, ri, v); 99 } 100 } 101 102 static bool raw_accessors_invalid(const ARMCPRegInfo *ri) 103 { 104 /* Return true if the regdef would cause an assertion if you called 105 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a 106 * program bug for it not to have the NO_RAW flag). 107 * NB that returning false here doesn't necessarily mean that calling 108 * read/write_raw_cp_reg() is safe, because we can't distinguish "has 109 * read/write access functions which are safe for raw use" from "has 110 * read/write access functions which have side effects but has forgotten 111 * to provide raw access functions". 112 * The tests here line up with the conditions in read/write_raw_cp_reg() 113 * and assertions in raw_read()/raw_write(). 114 */ 115 if ((ri->type & ARM_CP_CONST) || 116 ri->fieldoffset || 117 ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) { 118 return false; 119 } 120 return true; 121 } 122 123 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync) 124 { 125 /* Write the coprocessor state from cpu->env to the (index,value) list. */ 126 int i; 127 bool ok = true; 128 129 for (i = 0; i < cpu->cpreg_array_len; i++) { 130 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); 131 const ARMCPRegInfo *ri; 132 uint64_t newval; 133 134 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); 135 if (!ri) { 136 ok = false; 137 continue; 138 } 139 if (ri->type & ARM_CP_NO_RAW) { 140 continue; 141 } 142 143 newval = read_raw_cp_reg(&cpu->env, ri); 144 if (kvm_sync) { 145 /* 146 * Only sync if the previous list->cpustate sync succeeded. 147 * Rather than tracking the success/failure state for every 148 * item in the list, we just recheck "does the raw write we must 149 * have made in write_list_to_cpustate() read back OK" here. 150 */ 151 uint64_t oldval = cpu->cpreg_values[i]; 152 153 if (oldval == newval) { 154 continue; 155 } 156 157 write_raw_cp_reg(&cpu->env, ri, oldval); 158 if (read_raw_cp_reg(&cpu->env, ri) != oldval) { 159 continue; 160 } 161 162 write_raw_cp_reg(&cpu->env, ri, newval); 163 } 164 cpu->cpreg_values[i] = newval; 165 } 166 return ok; 167 } 168 169 bool write_list_to_cpustate(ARMCPU *cpu) 170 { 171 int i; 172 bool ok = true; 173 174 for (i = 0; i < cpu->cpreg_array_len; i++) { 175 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); 176 uint64_t v = cpu->cpreg_values[i]; 177 const ARMCPRegInfo *ri; 178 179 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); 180 if (!ri) { 181 ok = false; 182 continue; 183 } 184 if (ri->type & ARM_CP_NO_RAW) { 185 continue; 186 } 187 /* Write value and confirm it reads back as written 188 * (to catch read-only registers and partially read-only 189 * registers where the incoming migration value doesn't match) 190 */ 191 write_raw_cp_reg(&cpu->env, ri, v); 192 if (read_raw_cp_reg(&cpu->env, ri) != v) { 193 ok = false; 194 } 195 } 196 return ok; 197 } 198 199 static void add_cpreg_to_list(gpointer key, gpointer opaque) 200 { 201 ARMCPU *cpu = opaque; 202 uint32_t regidx = (uintptr_t)key; 203 const ARMCPRegInfo *ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); 204 205 if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { 206 cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx); 207 /* The value array need not be initialized at this point */ 208 cpu->cpreg_array_len++; 209 } 210 } 211 212 static void count_cpreg(gpointer key, gpointer opaque) 213 { 214 ARMCPU *cpu = opaque; 215 const ARMCPRegInfo *ri; 216 217 ri = g_hash_table_lookup(cpu->cp_regs, key); 218 219 if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { 220 cpu->cpreg_array_len++; 221 } 222 } 223 224 static gint cpreg_key_compare(gconstpointer a, gconstpointer b) 225 { 226 uint64_t aidx = cpreg_to_kvm_id((uintptr_t)a); 227 uint64_t bidx = cpreg_to_kvm_id((uintptr_t)b); 228 229 if (aidx > bidx) { 230 return 1; 231 } 232 if (aidx < bidx) { 233 return -1; 234 } 235 return 0; 236 } 237 238 void init_cpreg_list(ARMCPU *cpu) 239 { 240 /* Initialise the cpreg_tuples[] array based on the cp_regs hash. 241 * Note that we require cpreg_tuples[] to be sorted by key ID. 242 */ 243 GList *keys; 244 int arraylen; 245 246 keys = g_hash_table_get_keys(cpu->cp_regs); 247 keys = g_list_sort(keys, cpreg_key_compare); 248 249 cpu->cpreg_array_len = 0; 250 251 g_list_foreach(keys, count_cpreg, cpu); 252 253 arraylen = cpu->cpreg_array_len; 254 cpu->cpreg_indexes = g_new(uint64_t, arraylen); 255 cpu->cpreg_values = g_new(uint64_t, arraylen); 256 cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen); 257 cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen); 258 cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len; 259 cpu->cpreg_array_len = 0; 260 261 g_list_foreach(keys, add_cpreg_to_list, cpu); 262 263 assert(cpu->cpreg_array_len == arraylen); 264 265 g_list_free(keys); 266 } 267 268 /* 269 * Some registers are not accessible from AArch32 EL3 if SCR.NS == 0. 270 */ 271 static CPAccessResult access_el3_aa32ns(CPUARMState *env, 272 const ARMCPRegInfo *ri, 273 bool isread) 274 { 275 if (!is_a64(env) && arm_current_el(env) == 3 && 276 arm_is_secure_below_el3(env)) { 277 return CP_ACCESS_TRAP_UNCATEGORIZED; 278 } 279 return CP_ACCESS_OK; 280 } 281 282 /* Some secure-only AArch32 registers trap to EL3 if used from 283 * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts). 284 * Note that an access from Secure EL1 can only happen if EL3 is AArch64. 285 * We assume that the .access field is set to PL1_RW. 286 */ 287 static CPAccessResult access_trap_aa32s_el1(CPUARMState *env, 288 const ARMCPRegInfo *ri, 289 bool isread) 290 { 291 if (arm_current_el(env) == 3) { 292 return CP_ACCESS_OK; 293 } 294 if (arm_is_secure_below_el3(env)) { 295 if (env->cp15.scr_el3 & SCR_EEL2) { 296 return CP_ACCESS_TRAP_EL2; 297 } 298 return CP_ACCESS_TRAP_EL3; 299 } 300 /* This will be EL1 NS and EL2 NS, which just UNDEF */ 301 return CP_ACCESS_TRAP_UNCATEGORIZED; 302 } 303 304 /* Check for traps to performance monitor registers, which are controlled 305 * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3. 306 */ 307 static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri, 308 bool isread) 309 { 310 int el = arm_current_el(env); 311 uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); 312 313 if (el < 2 && (mdcr_el2 & MDCR_TPM)) { 314 return CP_ACCESS_TRAP_EL2; 315 } 316 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { 317 return CP_ACCESS_TRAP_EL3; 318 } 319 return CP_ACCESS_OK; 320 } 321 322 /* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM. */ 323 static CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri, 324 bool isread) 325 { 326 if (arm_current_el(env) == 1) { 327 uint64_t trap = isread ? HCR_TRVM : HCR_TVM; 328 if (arm_hcr_el2_eff(env) & trap) { 329 return CP_ACCESS_TRAP_EL2; 330 } 331 } 332 return CP_ACCESS_OK; 333 } 334 335 /* Check for traps from EL1 due to HCR_EL2.TSW. */ 336 static CPAccessResult access_tsw(CPUARMState *env, const ARMCPRegInfo *ri, 337 bool isread) 338 { 339 if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TSW)) { 340 return CP_ACCESS_TRAP_EL2; 341 } 342 return CP_ACCESS_OK; 343 } 344 345 /* Check for traps from EL1 due to HCR_EL2.TACR. */ 346 static CPAccessResult access_tacr(CPUARMState *env, const ARMCPRegInfo *ri, 347 bool isread) 348 { 349 if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TACR)) { 350 return CP_ACCESS_TRAP_EL2; 351 } 352 return CP_ACCESS_OK; 353 } 354 355 /* Check for traps from EL1 due to HCR_EL2.TTLB. */ 356 static CPAccessResult access_ttlb(CPUARMState *env, const ARMCPRegInfo *ri, 357 bool isread) 358 { 359 if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TTLB)) { 360 return CP_ACCESS_TRAP_EL2; 361 } 362 return CP_ACCESS_OK; 363 } 364 365 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) 366 { 367 ARMCPU *cpu = env_archcpu(env); 368 369 raw_write(env, ri, value); 370 tlb_flush(CPU(cpu)); /* Flush TLB as domain not tracked in TLB */ 371 } 372 373 static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) 374 { 375 ARMCPU *cpu = env_archcpu(env); 376 377 if (raw_read(env, ri) != value) { 378 /* Unlike real hardware the qemu TLB uses virtual addresses, 379 * not modified virtual addresses, so this causes a TLB flush. 380 */ 381 tlb_flush(CPU(cpu)); 382 raw_write(env, ri, value); 383 } 384 } 385 386 static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, 387 uint64_t value) 388 { 389 ARMCPU *cpu = env_archcpu(env); 390 391 if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_PMSA) 392 && !extended_addresses_enabled(env)) { 393 /* For VMSA (when not using the LPAE long descriptor page table 394 * format) this register includes the ASID, so do a TLB flush. 395 * For PMSA it is purely a process ID and no action is needed. 396 */ 397 tlb_flush(CPU(cpu)); 398 } 399 raw_write(env, ri, value); 400 } 401 402 /* IS variants of TLB operations must affect all cores */ 403 static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri, 404 uint64_t value) 405 { 406 CPUState *cs = env_cpu(env); 407 408 tlb_flush_all_cpus_synced(cs); 409 } 410 411 static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri, 412 uint64_t value) 413 { 414 CPUState *cs = env_cpu(env); 415 416 tlb_flush_all_cpus_synced(cs); 417 } 418 419 static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri, 420 uint64_t value) 421 { 422 CPUState *cs = env_cpu(env); 423 424 tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK); 425 } 426 427 static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri, 428 uint64_t value) 429 { 430 CPUState *cs = env_cpu(env); 431 432 tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK); 433 } 434 435 /* 436 * Non-IS variants of TLB operations are upgraded to 437 * IS versions if we are at EL1 and HCR_EL2.FB is effectively set to 438 * force broadcast of these operations. 439 */ 440 static bool tlb_force_broadcast(CPUARMState *env) 441 { 442 return arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_FB); 443 } 444 445 static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri, 446 uint64_t value) 447 { 448 /* Invalidate all (TLBIALL) */ 449 CPUState *cs = env_cpu(env); 450 451 if (tlb_force_broadcast(env)) { 452 tlb_flush_all_cpus_synced(cs); 453 } else { 454 tlb_flush(cs); 455 } 456 } 457 458 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, 459 uint64_t value) 460 { 461 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ 462 CPUState *cs = env_cpu(env); 463 464 value &= TARGET_PAGE_MASK; 465 if (tlb_force_broadcast(env)) { 466 tlb_flush_page_all_cpus_synced(cs, value); 467 } else { 468 tlb_flush_page(cs, value); 469 } 470 } 471 472 static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, 473 uint64_t value) 474 { 475 /* Invalidate by ASID (TLBIASID) */ 476 CPUState *cs = env_cpu(env); 477 478 if (tlb_force_broadcast(env)) { 479 tlb_flush_all_cpus_synced(cs); 480 } else { 481 tlb_flush(cs); 482 } 483 } 484 485 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, 486 uint64_t value) 487 { 488 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ 489 CPUState *cs = env_cpu(env); 490 491 value &= TARGET_PAGE_MASK; 492 if (tlb_force_broadcast(env)) { 493 tlb_flush_page_all_cpus_synced(cs, value); 494 } else { 495 tlb_flush_page(cs, value); 496 } 497 } 498 499 static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri, 500 uint64_t value) 501 { 502 CPUState *cs = env_cpu(env); 503 504 tlb_flush_by_mmuidx(cs, 505 ARMMMUIdxBit_E10_1 | 506 ARMMMUIdxBit_E10_1_PAN | 507 ARMMMUIdxBit_E10_0); 508 } 509 510 static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri, 511 uint64_t value) 512 { 513 CPUState *cs = env_cpu(env); 514 515 tlb_flush_by_mmuidx_all_cpus_synced(cs, 516 ARMMMUIdxBit_E10_1 | 517 ARMMMUIdxBit_E10_1_PAN | 518 ARMMMUIdxBit_E10_0); 519 } 520 521 522 static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, 523 uint64_t value) 524 { 525 CPUState *cs = env_cpu(env); 526 527 tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2); 528 } 529 530 static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, 531 uint64_t value) 532 { 533 CPUState *cs = env_cpu(env); 534 535 tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2); 536 } 537 538 static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, 539 uint64_t value) 540 { 541 CPUState *cs = env_cpu(env); 542 uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12); 543 544 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2); 545 } 546 547 static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, 548 uint64_t value) 549 { 550 CPUState *cs = env_cpu(env); 551 uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12); 552 553 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, 554 ARMMMUIdxBit_E2); 555 } 556 557 static const ARMCPRegInfo cp_reginfo[] = { 558 /* Define the secure and non-secure FCSE identifier CP registers 559 * separately because there is no secure bank in V8 (no _EL3). This allows 560 * the secure register to be properly reset and migrated. There is also no 561 * v8 EL1 version of the register so the non-secure instance stands alone. 562 */ 563 { .name = "FCSEIDR", 564 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0, 565 .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS, 566 .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_ns), 567 .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, }, 568 { .name = "FCSEIDR_S", 569 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0, 570 .access = PL1_RW, .secure = ARM_CP_SECSTATE_S, 571 .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s), 572 .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, }, 573 /* Define the secure and non-secure context identifier CP registers 574 * separately because there is no secure bank in V8 (no _EL3). This allows 575 * the secure register to be properly reset and migrated. In the 576 * non-secure case, the 32-bit register will have reset and migration 577 * disabled during registration as it is handled by the 64-bit instance. 578 */ 579 { .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH, 580 .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, 581 .access = PL1_RW, .accessfn = access_tvm_trvm, 582 .secure = ARM_CP_SECSTATE_NS, 583 .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]), 584 .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, 585 { .name = "CONTEXTIDR_S", .state = ARM_CP_STATE_AA32, 586 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, 587 .access = PL1_RW, .accessfn = access_tvm_trvm, 588 .secure = ARM_CP_SECSTATE_S, 589 .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s), 590 .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, 591 }; 592 593 static const ARMCPRegInfo not_v8_cp_reginfo[] = { 594 /* NB: Some of these registers exist in v8 but with more precise 595 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]). 596 */ 597 /* MMU Domain access control / MPU write buffer control */ 598 { .name = "DACR", 599 .cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY, 600 .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0, 601 .writefn = dacr_write, .raw_writefn = raw_write, 602 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s), 603 offsetoflow32(CPUARMState, cp15.dacr_ns) } }, 604 /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs. 605 * For v6 and v5, these mappings are overly broad. 606 */ 607 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 0, 608 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, 609 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 1, 610 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, 611 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 4, 612 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, 613 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 8, 614 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, 615 /* Cache maintenance ops; some of this space may be overridden later. */ 616 { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, 617 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, 618 .type = ARM_CP_NOP | ARM_CP_OVERRIDE }, 619 }; 620 621 static const ARMCPRegInfo not_v6_cp_reginfo[] = { 622 /* Not all pre-v6 cores implemented this WFI, so this is slightly 623 * over-broad. 624 */ 625 { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2, 626 .access = PL1_W, .type = ARM_CP_WFI }, 627 }; 628 629 static const ARMCPRegInfo not_v7_cp_reginfo[] = { 630 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which 631 * is UNPREDICTABLE; we choose to NOP as most implementations do). 632 */ 633 { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, 634 .access = PL1_W, .type = ARM_CP_WFI }, 635 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice 636 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and 637 * OMAPCP will override this space. 638 */ 639 { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0, 640 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data), 641 .resetvalue = 0 }, 642 { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1, 643 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn), 644 .resetvalue = 0 }, 645 /* v6 doesn't have the cache ID registers but Linux reads them anyway */ 646 { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY, 647 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, 648 .resetvalue = 0 }, 649 /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR; 650 * implementing it as RAZ means the "debug architecture version" bits 651 * will read as a reserved value, which should cause Linux to not try 652 * to use the debug hardware. 653 */ 654 { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, 655 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 656 /* MMU TLB control. Note that the wildcarding means we cover not just 657 * the unified TLB ops but also the dside/iside/inner-shareable variants. 658 */ 659 { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY, 660 .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write, 661 .type = ARM_CP_NO_RAW }, 662 { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY, 663 .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write, 664 .type = ARM_CP_NO_RAW }, 665 { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY, 666 .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write, 667 .type = ARM_CP_NO_RAW }, 668 { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY, 669 .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write, 670 .type = ARM_CP_NO_RAW }, 671 { .name = "PRRR", .cp = 15, .crn = 10, .crm = 2, 672 .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP }, 673 { .name = "NMRR", .cp = 15, .crn = 10, .crm = 2, 674 .opc1 = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_NOP }, 675 }; 676 677 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, 678 uint64_t value) 679 { 680 uint32_t mask = 0; 681 682 /* In ARMv8 most bits of CPACR_EL1 are RES0. */ 683 if (!arm_feature(env, ARM_FEATURE_V8)) { 684 /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI. 685 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP. 686 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell. 687 */ 688 if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) { 689 /* VFP coprocessor: cp10 & cp11 [23:20] */ 690 mask |= R_CPACR_ASEDIS_MASK | 691 R_CPACR_D32DIS_MASK | 692 R_CPACR_CP11_MASK | 693 R_CPACR_CP10_MASK; 694 695 if (!arm_feature(env, ARM_FEATURE_NEON)) { 696 /* ASEDIS [31] bit is RAO/WI */ 697 value |= R_CPACR_ASEDIS_MASK; 698 } 699 700 /* VFPv3 and upwards with NEON implement 32 double precision 701 * registers (D0-D31). 702 */ 703 if (!cpu_isar_feature(aa32_simd_r32, env_archcpu(env))) { 704 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */ 705 value |= R_CPACR_D32DIS_MASK; 706 } 707 } 708 value &= mask; 709 } 710 711 /* 712 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10 713 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00. 714 */ 715 if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && 716 !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { 717 mask = R_CPACR_CP11_MASK | R_CPACR_CP10_MASK; 718 value = (value & ~mask) | (env->cp15.cpacr_el1 & mask); 719 } 720 721 env->cp15.cpacr_el1 = value; 722 } 723 724 static uint64_t cpacr_read(CPUARMState *env, const ARMCPRegInfo *ri) 725 { 726 /* 727 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10 728 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00. 729 */ 730 uint64_t value = env->cp15.cpacr_el1; 731 732 if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && 733 !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { 734 value = ~(R_CPACR_CP11_MASK | R_CPACR_CP10_MASK); 735 } 736 return value; 737 } 738 739 740 static void cpacr_reset(CPUARMState *env, const ARMCPRegInfo *ri) 741 { 742 /* Call cpacr_write() so that we reset with the correct RAO bits set 743 * for our CPU features. 744 */ 745 cpacr_write(env, ri, 0); 746 } 747 748 static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri, 749 bool isread) 750 { 751 if (arm_feature(env, ARM_FEATURE_V8)) { 752 /* Check if CPACR accesses are to be trapped to EL2 */ 753 if (arm_current_el(env) == 1 && arm_is_el2_enabled(env) && 754 FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TCPAC)) { 755 return CP_ACCESS_TRAP_EL2; 756 /* Check if CPACR accesses are to be trapped to EL3 */ 757 } else if (arm_current_el(env) < 3 && 758 FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, TCPAC)) { 759 return CP_ACCESS_TRAP_EL3; 760 } 761 } 762 763 return CP_ACCESS_OK; 764 } 765 766 static CPAccessResult cptr_access(CPUARMState *env, const ARMCPRegInfo *ri, 767 bool isread) 768 { 769 /* Check if CPTR accesses are set to trap to EL3 */ 770 if (arm_current_el(env) == 2 && 771 FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, TCPAC)) { 772 return CP_ACCESS_TRAP_EL3; 773 } 774 775 return CP_ACCESS_OK; 776 } 777 778 static const ARMCPRegInfo v6_cp_reginfo[] = { 779 /* prefetch by MVA in v6, NOP in v7 */ 780 { .name = "MVA_prefetch", 781 .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1, 782 .access = PL1_W, .type = ARM_CP_NOP }, 783 /* We need to break the TB after ISB to execute self-modifying code 784 * correctly and also to take any pending interrupts immediately. 785 * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag. 786 */ 787 { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4, 788 .access = PL0_W, .type = ARM_CP_NO_RAW, .writefn = arm_cp_write_ignore }, 789 { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4, 790 .access = PL0_W, .type = ARM_CP_NOP }, 791 { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5, 792 .access = PL0_W, .type = ARM_CP_NOP }, 793 { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2, 794 .access = PL1_RW, .accessfn = access_tvm_trvm, 795 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s), 796 offsetof(CPUARMState, cp15.ifar_ns) }, 797 .resetvalue = 0, }, 798 /* Watchpoint Fault Address Register : should actually only be present 799 * for 1136, 1176, 11MPCore. 800 */ 801 { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, 802 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, }, 803 { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, 804 .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access, 805 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1), 806 .resetfn = cpacr_reset, .writefn = cpacr_write, .readfn = cpacr_read }, 807 }; 808 809 typedef struct pm_event { 810 uint16_t number; /* PMEVTYPER.evtCount is 16 bits wide */ 811 /* If the event is supported on this CPU (used to generate PMCEID[01]) */ 812 bool (*supported)(CPUARMState *); 813 /* 814 * Retrieve the current count of the underlying event. The programmed 815 * counters hold a difference from the return value from this function 816 */ 817 uint64_t (*get_count)(CPUARMState *); 818 /* 819 * Return how many nanoseconds it will take (at a minimum) for count events 820 * to occur. A negative value indicates the counter will never overflow, or 821 * that the counter has otherwise arranged for the overflow bit to be set 822 * and the PMU interrupt to be raised on overflow. 823 */ 824 int64_t (*ns_per_count)(uint64_t); 825 } pm_event; 826 827 static bool event_always_supported(CPUARMState *env) 828 { 829 return true; 830 } 831 832 static uint64_t swinc_get_count(CPUARMState *env) 833 { 834 /* 835 * SW_INCR events are written directly to the pmevcntr's by writes to 836 * PMSWINC, so there is no underlying count maintained by the PMU itself 837 */ 838 return 0; 839 } 840 841 static int64_t swinc_ns_per(uint64_t ignored) 842 { 843 return -1; 844 } 845 846 /* 847 * Return the underlying cycle count for the PMU cycle counters. If we're in 848 * usermode, simply return 0. 849 */ 850 static uint64_t cycles_get_count(CPUARMState *env) 851 { 852 #ifndef CONFIG_USER_ONLY 853 return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 854 ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); 855 #else 856 return cpu_get_host_ticks(); 857 #endif 858 } 859 860 #ifndef CONFIG_USER_ONLY 861 static int64_t cycles_ns_per(uint64_t cycles) 862 { 863 return (ARM_CPU_FREQ / NANOSECONDS_PER_SECOND) * cycles; 864 } 865 866 static bool instructions_supported(CPUARMState *env) 867 { 868 return icount_enabled() == 1; /* Precise instruction counting */ 869 } 870 871 static uint64_t instructions_get_count(CPUARMState *env) 872 { 873 return (uint64_t)icount_get_raw(); 874 } 875 876 static int64_t instructions_ns_per(uint64_t icount) 877 { 878 return icount_to_ns((int64_t)icount); 879 } 880 #endif 881 882 static bool pmu_8_1_events_supported(CPUARMState *env) 883 { 884 /* For events which are supported in any v8.1 PMU */ 885 return cpu_isar_feature(any_pmu_8_1, env_archcpu(env)); 886 } 887 888 static bool pmu_8_4_events_supported(CPUARMState *env) 889 { 890 /* For events which are supported in any v8.1 PMU */ 891 return cpu_isar_feature(any_pmu_8_4, env_archcpu(env)); 892 } 893 894 static uint64_t zero_event_get_count(CPUARMState *env) 895 { 896 /* For events which on QEMU never fire, so their count is always zero */ 897 return 0; 898 } 899 900 static int64_t zero_event_ns_per(uint64_t cycles) 901 { 902 /* An event which never fires can never overflow */ 903 return -1; 904 } 905 906 static const pm_event pm_events[] = { 907 { .number = 0x000, /* SW_INCR */ 908 .supported = event_always_supported, 909 .get_count = swinc_get_count, 910 .ns_per_count = swinc_ns_per, 911 }, 912 #ifndef CONFIG_USER_ONLY 913 { .number = 0x008, /* INST_RETIRED, Instruction architecturally executed */ 914 .supported = instructions_supported, 915 .get_count = instructions_get_count, 916 .ns_per_count = instructions_ns_per, 917 }, 918 { .number = 0x011, /* CPU_CYCLES, Cycle */ 919 .supported = event_always_supported, 920 .get_count = cycles_get_count, 921 .ns_per_count = cycles_ns_per, 922 }, 923 #endif 924 { .number = 0x023, /* STALL_FRONTEND */ 925 .supported = pmu_8_1_events_supported, 926 .get_count = zero_event_get_count, 927 .ns_per_count = zero_event_ns_per, 928 }, 929 { .number = 0x024, /* STALL_BACKEND */ 930 .supported = pmu_8_1_events_supported, 931 .get_count = zero_event_get_count, 932 .ns_per_count = zero_event_ns_per, 933 }, 934 { .number = 0x03c, /* STALL */ 935 .supported = pmu_8_4_events_supported, 936 .get_count = zero_event_get_count, 937 .ns_per_count = zero_event_ns_per, 938 }, 939 }; 940 941 /* 942 * Note: Before increasing MAX_EVENT_ID beyond 0x3f into the 0x40xx range of 943 * events (i.e. the statistical profiling extension), this implementation 944 * should first be updated to something sparse instead of the current 945 * supported_event_map[] array. 946 */ 947 #define MAX_EVENT_ID 0x3c 948 #define UNSUPPORTED_EVENT UINT16_MAX 949 static uint16_t supported_event_map[MAX_EVENT_ID + 1]; 950 951 /* 952 * Called upon CPU initialization to initialize PMCEID[01]_EL0 and build a map 953 * of ARM event numbers to indices in our pm_events array. 954 * 955 * Note: Events in the 0x40XX range are not currently supported. 956 */ 957 void pmu_init(ARMCPU *cpu) 958 { 959 unsigned int i; 960 961 /* 962 * Empty supported_event_map and cpu->pmceid[01] before adding supported 963 * events to them 964 */ 965 for (i = 0; i < ARRAY_SIZE(supported_event_map); i++) { 966 supported_event_map[i] = UNSUPPORTED_EVENT; 967 } 968 cpu->pmceid0 = 0; 969 cpu->pmceid1 = 0; 970 971 for (i = 0; i < ARRAY_SIZE(pm_events); i++) { 972 const pm_event *cnt = &pm_events[i]; 973 assert(cnt->number <= MAX_EVENT_ID); 974 /* We do not currently support events in the 0x40xx range */ 975 assert(cnt->number <= 0x3f); 976 977 if (cnt->supported(&cpu->env)) { 978 supported_event_map[cnt->number] = i; 979 uint64_t event_mask = 1ULL << (cnt->number & 0x1f); 980 if (cnt->number & 0x20) { 981 cpu->pmceid1 |= event_mask; 982 } else { 983 cpu->pmceid0 |= event_mask; 984 } 985 } 986 } 987 } 988 989 /* 990 * Check at runtime whether a PMU event is supported for the current machine 991 */ 992 static bool event_supported(uint16_t number) 993 { 994 if (number > MAX_EVENT_ID) { 995 return false; 996 } 997 return supported_event_map[number] != UNSUPPORTED_EVENT; 998 } 999 1000 static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri, 1001 bool isread) 1002 { 1003 /* Performance monitor registers user accessibility is controlled 1004 * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable 1005 * trapping to EL2 or EL3 for other accesses. 1006 */ 1007 int el = arm_current_el(env); 1008 uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); 1009 1010 if (el == 0 && !(env->cp15.c9_pmuserenr & 1)) { 1011 return CP_ACCESS_TRAP; 1012 } 1013 if (el < 2 && (mdcr_el2 & MDCR_TPM)) { 1014 return CP_ACCESS_TRAP_EL2; 1015 } 1016 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { 1017 return CP_ACCESS_TRAP_EL3; 1018 } 1019 1020 return CP_ACCESS_OK; 1021 } 1022 1023 static CPAccessResult pmreg_access_xevcntr(CPUARMState *env, 1024 const ARMCPRegInfo *ri, 1025 bool isread) 1026 { 1027 /* ER: event counter read trap control */ 1028 if (arm_feature(env, ARM_FEATURE_V8) 1029 && arm_current_el(env) == 0 1030 && (env->cp15.c9_pmuserenr & (1 << 3)) != 0 1031 && isread) { 1032 return CP_ACCESS_OK; 1033 } 1034 1035 return pmreg_access(env, ri, isread); 1036 } 1037 1038 static CPAccessResult pmreg_access_swinc(CPUARMState *env, 1039 const ARMCPRegInfo *ri, 1040 bool isread) 1041 { 1042 /* SW: software increment write trap control */ 1043 if (arm_feature(env, ARM_FEATURE_V8) 1044 && arm_current_el(env) == 0 1045 && (env->cp15.c9_pmuserenr & (1 << 1)) != 0 1046 && !isread) { 1047 return CP_ACCESS_OK; 1048 } 1049 1050 return pmreg_access(env, ri, isread); 1051 } 1052 1053 static CPAccessResult pmreg_access_selr(CPUARMState *env, 1054 const ARMCPRegInfo *ri, 1055 bool isread) 1056 { 1057 /* ER: event counter read trap control */ 1058 if (arm_feature(env, ARM_FEATURE_V8) 1059 && arm_current_el(env) == 0 1060 && (env->cp15.c9_pmuserenr & (1 << 3)) != 0) { 1061 return CP_ACCESS_OK; 1062 } 1063 1064 return pmreg_access(env, ri, isread); 1065 } 1066 1067 static CPAccessResult pmreg_access_ccntr(CPUARMState *env, 1068 const ARMCPRegInfo *ri, 1069 bool isread) 1070 { 1071 /* CR: cycle counter read trap control */ 1072 if (arm_feature(env, ARM_FEATURE_V8) 1073 && arm_current_el(env) == 0 1074 && (env->cp15.c9_pmuserenr & (1 << 2)) != 0 1075 && isread) { 1076 return CP_ACCESS_OK; 1077 } 1078 1079 return pmreg_access(env, ri, isread); 1080 } 1081 1082 /* Returns true if the counter (pass 31 for PMCCNTR) should count events using 1083 * the current EL, security state, and register configuration. 1084 */ 1085 static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter) 1086 { 1087 uint64_t filter; 1088 bool e, p, u, nsk, nsu, nsh, m; 1089 bool enabled, prohibited, filtered; 1090 bool secure = arm_is_secure(env); 1091 int el = arm_current_el(env); 1092 uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); 1093 uint8_t hpmn = mdcr_el2 & MDCR_HPMN; 1094 1095 if (!arm_feature(env, ARM_FEATURE_PMU)) { 1096 return false; 1097 } 1098 1099 if (!arm_feature(env, ARM_FEATURE_EL2) || 1100 (counter < hpmn || counter == 31)) { 1101 e = env->cp15.c9_pmcr & PMCRE; 1102 } else { 1103 e = mdcr_el2 & MDCR_HPME; 1104 } 1105 enabled = e && (env->cp15.c9_pmcnten & (1 << counter)); 1106 1107 if (!secure) { 1108 if (el == 2 && (counter < hpmn || counter == 31)) { 1109 prohibited = mdcr_el2 & MDCR_HPMD; 1110 } else { 1111 prohibited = false; 1112 } 1113 } else { 1114 prohibited = arm_feature(env, ARM_FEATURE_EL3) && 1115 !(env->cp15.mdcr_el3 & MDCR_SPME); 1116 } 1117 1118 if (prohibited && counter == 31) { 1119 prohibited = env->cp15.c9_pmcr & PMCRDP; 1120 } 1121 1122 if (counter == 31) { 1123 filter = env->cp15.pmccfiltr_el0; 1124 } else { 1125 filter = env->cp15.c14_pmevtyper[counter]; 1126 } 1127 1128 p = filter & PMXEVTYPER_P; 1129 u = filter & PMXEVTYPER_U; 1130 nsk = arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSK); 1131 nsu = arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSU); 1132 nsh = arm_feature(env, ARM_FEATURE_EL2) && (filter & PMXEVTYPER_NSH); 1133 m = arm_el_is_aa64(env, 1) && 1134 arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_M); 1135 1136 if (el == 0) { 1137 filtered = secure ? u : u != nsu; 1138 } else if (el == 1) { 1139 filtered = secure ? p : p != nsk; 1140 } else if (el == 2) { 1141 filtered = !nsh; 1142 } else { /* EL3 */ 1143 filtered = m != p; 1144 } 1145 1146 if (counter != 31) { 1147 /* 1148 * If not checking PMCCNTR, ensure the counter is setup to an event we 1149 * support 1150 */ 1151 uint16_t event = filter & PMXEVTYPER_EVTCOUNT; 1152 if (!event_supported(event)) { 1153 return false; 1154 } 1155 } 1156 1157 return enabled && !prohibited && !filtered; 1158 } 1159 1160 static void pmu_update_irq(CPUARMState *env) 1161 { 1162 ARMCPU *cpu = env_archcpu(env); 1163 qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) && 1164 (env->cp15.c9_pminten & env->cp15.c9_pmovsr)); 1165 } 1166 1167 /* 1168 * Ensure c15_ccnt is the guest-visible count so that operations such as 1169 * enabling/disabling the counter or filtering, modifying the count itself, 1170 * etc. can be done logically. This is essentially a no-op if the counter is 1171 * not enabled at the time of the call. 1172 */ 1173 static void pmccntr_op_start(CPUARMState *env) 1174 { 1175 uint64_t cycles = cycles_get_count(env); 1176 1177 if (pmu_counter_enabled(env, 31)) { 1178 uint64_t eff_cycles = cycles; 1179 if (env->cp15.c9_pmcr & PMCRD) { 1180 /* Increment once every 64 processor clock cycles */ 1181 eff_cycles /= 64; 1182 } 1183 1184 uint64_t new_pmccntr = eff_cycles - env->cp15.c15_ccnt_delta; 1185 1186 uint64_t overflow_mask = env->cp15.c9_pmcr & PMCRLC ? \ 1187 1ull << 63 : 1ull << 31; 1188 if (env->cp15.c15_ccnt & ~new_pmccntr & overflow_mask) { 1189 env->cp15.c9_pmovsr |= (1 << 31); 1190 pmu_update_irq(env); 1191 } 1192 1193 env->cp15.c15_ccnt = new_pmccntr; 1194 } 1195 env->cp15.c15_ccnt_delta = cycles; 1196 } 1197 1198 /* 1199 * If PMCCNTR is enabled, recalculate the delta between the clock and the 1200 * guest-visible count. A call to pmccntr_op_finish should follow every call to 1201 * pmccntr_op_start. 1202 */ 1203 static void pmccntr_op_finish(CPUARMState *env) 1204 { 1205 if (pmu_counter_enabled(env, 31)) { 1206 #ifndef CONFIG_USER_ONLY 1207 /* Calculate when the counter will next overflow */ 1208 uint64_t remaining_cycles = -env->cp15.c15_ccnt; 1209 if (!(env->cp15.c9_pmcr & PMCRLC)) { 1210 remaining_cycles = (uint32_t)remaining_cycles; 1211 } 1212 int64_t overflow_in = cycles_ns_per(remaining_cycles); 1213 1214 if (overflow_in > 0) { 1215 int64_t overflow_at = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 1216 overflow_in; 1217 ARMCPU *cpu = env_archcpu(env); 1218 timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); 1219 } 1220 #endif 1221 1222 uint64_t prev_cycles = env->cp15.c15_ccnt_delta; 1223 if (env->cp15.c9_pmcr & PMCRD) { 1224 /* Increment once every 64 processor clock cycles */ 1225 prev_cycles /= 64; 1226 } 1227 env->cp15.c15_ccnt_delta = prev_cycles - env->cp15.c15_ccnt; 1228 } 1229 } 1230 1231 static void pmevcntr_op_start(CPUARMState *env, uint8_t counter) 1232 { 1233 1234 uint16_t event = env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_EVTCOUNT; 1235 uint64_t count = 0; 1236 if (event_supported(event)) { 1237 uint16_t event_idx = supported_event_map[event]; 1238 count = pm_events[event_idx].get_count(env); 1239 } 1240 1241 if (pmu_counter_enabled(env, counter)) { 1242 uint32_t new_pmevcntr = count - env->cp15.c14_pmevcntr_delta[counter]; 1243 1244 if (env->cp15.c14_pmevcntr[counter] & ~new_pmevcntr & INT32_MIN) { 1245 env->cp15.c9_pmovsr |= (1 << counter); 1246 pmu_update_irq(env); 1247 } 1248 env->cp15.c14_pmevcntr[counter] = new_pmevcntr; 1249 } 1250 env->cp15.c14_pmevcntr_delta[counter] = count; 1251 } 1252 1253 static void pmevcntr_op_finish(CPUARMState *env, uint8_t counter) 1254 { 1255 if (pmu_counter_enabled(env, counter)) { 1256 #ifndef CONFIG_USER_ONLY 1257 uint16_t event = env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_EVTCOUNT; 1258 uint16_t event_idx = supported_event_map[event]; 1259 uint64_t delta = UINT32_MAX - 1260 (uint32_t)env->cp15.c14_pmevcntr[counter] + 1; 1261 int64_t overflow_in = pm_events[event_idx].ns_per_count(delta); 1262 1263 if (overflow_in > 0) { 1264 int64_t overflow_at = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 1265 overflow_in; 1266 ARMCPU *cpu = env_archcpu(env); 1267 timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); 1268 } 1269 #endif 1270 1271 env->cp15.c14_pmevcntr_delta[counter] -= 1272 env->cp15.c14_pmevcntr[counter]; 1273 } 1274 } 1275 1276 void pmu_op_start(CPUARMState *env) 1277 { 1278 unsigned int i; 1279 pmccntr_op_start(env); 1280 for (i = 0; i < pmu_num_counters(env); i++) { 1281 pmevcntr_op_start(env, i); 1282 } 1283 } 1284 1285 void pmu_op_finish(CPUARMState *env) 1286 { 1287 unsigned int i; 1288 pmccntr_op_finish(env); 1289 for (i = 0; i < pmu_num_counters(env); i++) { 1290 pmevcntr_op_finish(env, i); 1291 } 1292 } 1293 1294 void pmu_pre_el_change(ARMCPU *cpu, void *ignored) 1295 { 1296 pmu_op_start(&cpu->env); 1297 } 1298 1299 void pmu_post_el_change(ARMCPU *cpu, void *ignored) 1300 { 1301 pmu_op_finish(&cpu->env); 1302 } 1303 1304 void arm_pmu_timer_cb(void *opaque) 1305 { 1306 ARMCPU *cpu = opaque; 1307 1308 /* 1309 * Update all the counter values based on the current underlying counts, 1310 * triggering interrupts to be raised, if necessary. pmu_op_finish() also 1311 * has the effect of setting the cpu->pmu_timer to the next earliest time a 1312 * counter may expire. 1313 */ 1314 pmu_op_start(&cpu->env); 1315 pmu_op_finish(&cpu->env); 1316 } 1317 1318 static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1319 uint64_t value) 1320 { 1321 pmu_op_start(env); 1322 1323 if (value & PMCRC) { 1324 /* The counter has been reset */ 1325 env->cp15.c15_ccnt = 0; 1326 } 1327 1328 if (value & PMCRP) { 1329 unsigned int i; 1330 for (i = 0; i < pmu_num_counters(env); i++) { 1331 env->cp15.c14_pmevcntr[i] = 0; 1332 } 1333 } 1334 1335 env->cp15.c9_pmcr &= ~PMCR_WRITABLE_MASK; 1336 env->cp15.c9_pmcr |= (value & PMCR_WRITABLE_MASK); 1337 1338 pmu_op_finish(env); 1339 } 1340 1341 static void pmswinc_write(CPUARMState *env, const ARMCPRegInfo *ri, 1342 uint64_t value) 1343 { 1344 unsigned int i; 1345 for (i = 0; i < pmu_num_counters(env); i++) { 1346 /* Increment a counter's count iff: */ 1347 if ((value & (1 << i)) && /* counter's bit is set */ 1348 /* counter is enabled and not filtered */ 1349 pmu_counter_enabled(env, i) && 1350 /* counter is SW_INCR */ 1351 (env->cp15.c14_pmevtyper[i] & PMXEVTYPER_EVTCOUNT) == 0x0) { 1352 pmevcntr_op_start(env, i); 1353 1354 /* 1355 * Detect if this write causes an overflow since we can't predict 1356 * PMSWINC overflows like we can for other events 1357 */ 1358 uint32_t new_pmswinc = env->cp15.c14_pmevcntr[i] + 1; 1359 1360 if (env->cp15.c14_pmevcntr[i] & ~new_pmswinc & INT32_MIN) { 1361 env->cp15.c9_pmovsr |= (1 << i); 1362 pmu_update_irq(env); 1363 } 1364 1365 env->cp15.c14_pmevcntr[i] = new_pmswinc; 1366 1367 pmevcntr_op_finish(env, i); 1368 } 1369 } 1370 } 1371 1372 static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) 1373 { 1374 uint64_t ret; 1375 pmccntr_op_start(env); 1376 ret = env->cp15.c15_ccnt; 1377 pmccntr_op_finish(env); 1378 return ret; 1379 } 1380 1381 static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1382 uint64_t value) 1383 { 1384 /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and 1385 * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the 1386 * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are 1387 * accessed. 1388 */ 1389 env->cp15.c9_pmselr = value & 0x1f; 1390 } 1391 1392 static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1393 uint64_t value) 1394 { 1395 pmccntr_op_start(env); 1396 env->cp15.c15_ccnt = value; 1397 pmccntr_op_finish(env); 1398 } 1399 1400 static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri, 1401 uint64_t value) 1402 { 1403 uint64_t cur_val = pmccntr_read(env, NULL); 1404 1405 pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value)); 1406 } 1407 1408 static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1409 uint64_t value) 1410 { 1411 pmccntr_op_start(env); 1412 env->cp15.pmccfiltr_el0 = value & PMCCFILTR_EL0; 1413 pmccntr_op_finish(env); 1414 } 1415 1416 static void pmccfiltr_write_a32(CPUARMState *env, const ARMCPRegInfo *ri, 1417 uint64_t value) 1418 { 1419 pmccntr_op_start(env); 1420 /* M is not accessible from AArch32 */ 1421 env->cp15.pmccfiltr_el0 = (env->cp15.pmccfiltr_el0 & PMCCFILTR_M) | 1422 (value & PMCCFILTR); 1423 pmccntr_op_finish(env); 1424 } 1425 1426 static uint64_t pmccfiltr_read_a32(CPUARMState *env, const ARMCPRegInfo *ri) 1427 { 1428 /* M is not visible in AArch32 */ 1429 return env->cp15.pmccfiltr_el0 & PMCCFILTR; 1430 } 1431 1432 static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, 1433 uint64_t value) 1434 { 1435 value &= pmu_counter_mask(env); 1436 env->cp15.c9_pmcnten |= value; 1437 } 1438 1439 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1440 uint64_t value) 1441 { 1442 value &= pmu_counter_mask(env); 1443 env->cp15.c9_pmcnten &= ~value; 1444 } 1445 1446 static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1447 uint64_t value) 1448 { 1449 value &= pmu_counter_mask(env); 1450 env->cp15.c9_pmovsr &= ~value; 1451 pmu_update_irq(env); 1452 } 1453 1454 static void pmovsset_write(CPUARMState *env, const ARMCPRegInfo *ri, 1455 uint64_t value) 1456 { 1457 value &= pmu_counter_mask(env); 1458 env->cp15.c9_pmovsr |= value; 1459 pmu_update_irq(env); 1460 } 1461 1462 static void pmevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, 1463 uint64_t value, const uint8_t counter) 1464 { 1465 if (counter == 31) { 1466 pmccfiltr_write(env, ri, value); 1467 } else if (counter < pmu_num_counters(env)) { 1468 pmevcntr_op_start(env, counter); 1469 1470 /* 1471 * If this counter's event type is changing, store the current 1472 * underlying count for the new type in c14_pmevcntr_delta[counter] so 1473 * pmevcntr_op_finish has the correct baseline when it converts back to 1474 * a delta. 1475 */ 1476 uint16_t old_event = env->cp15.c14_pmevtyper[counter] & 1477 PMXEVTYPER_EVTCOUNT; 1478 uint16_t new_event = value & PMXEVTYPER_EVTCOUNT; 1479 if (old_event != new_event) { 1480 uint64_t count = 0; 1481 if (event_supported(new_event)) { 1482 uint16_t event_idx = supported_event_map[new_event]; 1483 count = pm_events[event_idx].get_count(env); 1484 } 1485 env->cp15.c14_pmevcntr_delta[counter] = count; 1486 } 1487 1488 env->cp15.c14_pmevtyper[counter] = value & PMXEVTYPER_MASK; 1489 pmevcntr_op_finish(env, counter); 1490 } 1491 /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when 1492 * PMSELR value is equal to or greater than the number of implemented 1493 * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI. 1494 */ 1495 } 1496 1497 static uint64_t pmevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri, 1498 const uint8_t counter) 1499 { 1500 if (counter == 31) { 1501 return env->cp15.pmccfiltr_el0; 1502 } else if (counter < pmu_num_counters(env)) { 1503 return env->cp15.c14_pmevtyper[counter]; 1504 } else { 1505 /* 1506 * We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER 1507 * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write(). 1508 */ 1509 return 0; 1510 } 1511 } 1512 1513 static void pmevtyper_writefn(CPUARMState *env, const ARMCPRegInfo *ri, 1514 uint64_t value) 1515 { 1516 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); 1517 pmevtyper_write(env, ri, value, counter); 1518 } 1519 1520 static void pmevtyper_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri, 1521 uint64_t value) 1522 { 1523 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); 1524 env->cp15.c14_pmevtyper[counter] = value; 1525 1526 /* 1527 * pmevtyper_rawwrite is called between a pair of pmu_op_start and 1528 * pmu_op_finish calls when loading saved state for a migration. Because 1529 * we're potentially updating the type of event here, the value written to 1530 * c14_pmevcntr_delta by the preceeding pmu_op_start call may be for a 1531 * different counter type. Therefore, we need to set this value to the 1532 * current count for the counter type we're writing so that pmu_op_finish 1533 * has the correct count for its calculation. 1534 */ 1535 uint16_t event = value & PMXEVTYPER_EVTCOUNT; 1536 if (event_supported(event)) { 1537 uint16_t event_idx = supported_event_map[event]; 1538 env->cp15.c14_pmevcntr_delta[counter] = 1539 pm_events[event_idx].get_count(env); 1540 } 1541 } 1542 1543 static uint64_t pmevtyper_readfn(CPUARMState *env, const ARMCPRegInfo *ri) 1544 { 1545 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); 1546 return pmevtyper_read(env, ri, counter); 1547 } 1548 1549 static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, 1550 uint64_t value) 1551 { 1552 pmevtyper_write(env, ri, value, env->cp15.c9_pmselr & 31); 1553 } 1554 1555 static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri) 1556 { 1557 return pmevtyper_read(env, ri, env->cp15.c9_pmselr & 31); 1558 } 1559 1560 static void pmevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1561 uint64_t value, uint8_t counter) 1562 { 1563 if (counter < pmu_num_counters(env)) { 1564 pmevcntr_op_start(env, counter); 1565 env->cp15.c14_pmevcntr[counter] = value; 1566 pmevcntr_op_finish(env, counter); 1567 } 1568 /* 1569 * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR 1570 * are CONSTRAINED UNPREDICTABLE. 1571 */ 1572 } 1573 1574 static uint64_t pmevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri, 1575 uint8_t counter) 1576 { 1577 if (counter < pmu_num_counters(env)) { 1578 uint64_t ret; 1579 pmevcntr_op_start(env, counter); 1580 ret = env->cp15.c14_pmevcntr[counter]; 1581 pmevcntr_op_finish(env, counter); 1582 return ret; 1583 } else { 1584 /* We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR 1585 * are CONSTRAINED UNPREDICTABLE. */ 1586 return 0; 1587 } 1588 } 1589 1590 static void pmevcntr_writefn(CPUARMState *env, const ARMCPRegInfo *ri, 1591 uint64_t value) 1592 { 1593 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); 1594 pmevcntr_write(env, ri, value, counter); 1595 } 1596 1597 static uint64_t pmevcntr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) 1598 { 1599 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); 1600 return pmevcntr_read(env, ri, counter); 1601 } 1602 1603 static void pmevcntr_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri, 1604 uint64_t value) 1605 { 1606 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); 1607 assert(counter < pmu_num_counters(env)); 1608 env->cp15.c14_pmevcntr[counter] = value; 1609 pmevcntr_write(env, ri, value, counter); 1610 } 1611 1612 static uint64_t pmevcntr_rawread(CPUARMState *env, const ARMCPRegInfo *ri) 1613 { 1614 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); 1615 assert(counter < pmu_num_counters(env)); 1616 return env->cp15.c14_pmevcntr[counter]; 1617 } 1618 1619 static void pmxevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1620 uint64_t value) 1621 { 1622 pmevcntr_write(env, ri, value, env->cp15.c9_pmselr & 31); 1623 } 1624 1625 static uint64_t pmxevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri) 1626 { 1627 return pmevcntr_read(env, ri, env->cp15.c9_pmselr & 31); 1628 } 1629 1630 static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1631 uint64_t value) 1632 { 1633 if (arm_feature(env, ARM_FEATURE_V8)) { 1634 env->cp15.c9_pmuserenr = value & 0xf; 1635 } else { 1636 env->cp15.c9_pmuserenr = value & 1; 1637 } 1638 } 1639 1640 static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri, 1641 uint64_t value) 1642 { 1643 /* We have no event counters so only the C bit can be changed */ 1644 value &= pmu_counter_mask(env); 1645 env->cp15.c9_pminten |= value; 1646 pmu_update_irq(env); 1647 } 1648 1649 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1650 uint64_t value) 1651 { 1652 value &= pmu_counter_mask(env); 1653 env->cp15.c9_pminten &= ~value; 1654 pmu_update_irq(env); 1655 } 1656 1657 static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, 1658 uint64_t value) 1659 { 1660 /* Note that even though the AArch64 view of this register has bits 1661 * [10:0] all RES0 we can only mask the bottom 5, to comply with the 1662 * architectural requirements for bits which are RES0 only in some 1663 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7 1664 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.) 1665 */ 1666 raw_write(env, ri, value & ~0x1FULL); 1667 } 1668 1669 static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) 1670 { 1671 /* Begin with base v8.0 state. */ 1672 uint32_t valid_mask = 0x3fff; 1673 ARMCPU *cpu = env_archcpu(env); 1674 1675 /* 1676 * Because SCR_EL3 is the "real" cpreg and SCR is the alias, reset always 1677 * passes the reginfo for SCR_EL3, which has type ARM_CP_STATE_AA64. 1678 * Instead, choose the format based on the mode of EL3. 1679 */ 1680 if (arm_el_is_aa64(env, 3)) { 1681 value |= SCR_FW | SCR_AW; /* RES1 */ 1682 valid_mask &= ~SCR_NET; /* RES0 */ 1683 1684 if (!cpu_isar_feature(aa64_aa32_el1, cpu) && 1685 !cpu_isar_feature(aa64_aa32_el2, cpu)) { 1686 value |= SCR_RW; /* RAO/WI */ 1687 } 1688 if (cpu_isar_feature(aa64_ras, cpu)) { 1689 valid_mask |= SCR_TERR; 1690 } 1691 if (cpu_isar_feature(aa64_lor, cpu)) { 1692 valid_mask |= SCR_TLOR; 1693 } 1694 if (cpu_isar_feature(aa64_pauth, cpu)) { 1695 valid_mask |= SCR_API | SCR_APK; 1696 } 1697 if (cpu_isar_feature(aa64_sel2, cpu)) { 1698 valid_mask |= SCR_EEL2; 1699 } 1700 if (cpu_isar_feature(aa64_mte, cpu)) { 1701 valid_mask |= SCR_ATA; 1702 } 1703 if (cpu_isar_feature(aa64_scxtnum, cpu)) { 1704 valid_mask |= SCR_ENSCXT; 1705 } 1706 if (cpu_isar_feature(aa64_doublefault, cpu)) { 1707 valid_mask |= SCR_EASE | SCR_NMEA; 1708 } 1709 } else { 1710 valid_mask &= ~(SCR_RW | SCR_ST); 1711 if (cpu_isar_feature(aa32_ras, cpu)) { 1712 valid_mask |= SCR_TERR; 1713 } 1714 } 1715 1716 if (!arm_feature(env, ARM_FEATURE_EL2)) { 1717 valid_mask &= ~SCR_HCE; 1718 1719 /* On ARMv7, SMD (or SCD as it is called in v7) is only 1720 * supported if EL2 exists. The bit is UNK/SBZP when 1721 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero 1722 * when EL2 is unavailable. 1723 * On ARMv8, this bit is always available. 1724 */ 1725 if (arm_feature(env, ARM_FEATURE_V7) && 1726 !arm_feature(env, ARM_FEATURE_V8)) { 1727 valid_mask &= ~SCR_SMD; 1728 } 1729 } 1730 1731 /* Clear all-context RES0 bits. */ 1732 value &= valid_mask; 1733 raw_write(env, ri, value); 1734 } 1735 1736 static void scr_reset(CPUARMState *env, const ARMCPRegInfo *ri) 1737 { 1738 /* 1739 * scr_write will set the RES1 bits on an AArch64-only CPU. 1740 * The reset value will be 0x30 on an AArch64-only CPU and 0 otherwise. 1741 */ 1742 scr_write(env, ri, 0); 1743 } 1744 1745 static CPAccessResult access_aa64_tid2(CPUARMState *env, 1746 const ARMCPRegInfo *ri, 1747 bool isread) 1748 { 1749 if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID2)) { 1750 return CP_ACCESS_TRAP_EL2; 1751 } 1752 1753 return CP_ACCESS_OK; 1754 } 1755 1756 static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) 1757 { 1758 ARMCPU *cpu = env_archcpu(env); 1759 1760 /* Acquire the CSSELR index from the bank corresponding to the CCSIDR 1761 * bank 1762 */ 1763 uint32_t index = A32_BANKED_REG_GET(env, csselr, 1764 ri->secure & ARM_CP_SECSTATE_S); 1765 1766 return cpu->ccsidr[index]; 1767 } 1768 1769 static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1770 uint64_t value) 1771 { 1772 raw_write(env, ri, value & 0xf); 1773 } 1774 1775 static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) 1776 { 1777 CPUState *cs = env_cpu(env); 1778 bool el1 = arm_current_el(env) == 1; 1779 uint64_t hcr_el2 = el1 ? arm_hcr_el2_eff(env) : 0; 1780 uint64_t ret = 0; 1781 1782 if (hcr_el2 & HCR_IMO) { 1783 if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) { 1784 ret |= CPSR_I; 1785 } 1786 } else { 1787 if (cs->interrupt_request & CPU_INTERRUPT_HARD) { 1788 ret |= CPSR_I; 1789 } 1790 } 1791 1792 if (hcr_el2 & HCR_FMO) { 1793 if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) { 1794 ret |= CPSR_F; 1795 } 1796 } else { 1797 if (cs->interrupt_request & CPU_INTERRUPT_FIQ) { 1798 ret |= CPSR_F; 1799 } 1800 } 1801 1802 if (hcr_el2 & HCR_AMO) { 1803 if (cs->interrupt_request & CPU_INTERRUPT_VSERR) { 1804 ret |= CPSR_A; 1805 } 1806 } 1807 1808 return ret; 1809 } 1810 1811 static CPAccessResult access_aa64_tid1(CPUARMState *env, const ARMCPRegInfo *ri, 1812 bool isread) 1813 { 1814 if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID1)) { 1815 return CP_ACCESS_TRAP_EL2; 1816 } 1817 1818 return CP_ACCESS_OK; 1819 } 1820 1821 static CPAccessResult access_aa32_tid1(CPUARMState *env, const ARMCPRegInfo *ri, 1822 bool isread) 1823 { 1824 if (arm_feature(env, ARM_FEATURE_V8)) { 1825 return access_aa64_tid1(env, ri, isread); 1826 } 1827 1828 return CP_ACCESS_OK; 1829 } 1830 1831 static const ARMCPRegInfo v7_cp_reginfo[] = { 1832 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */ 1833 { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, 1834 .access = PL1_W, .type = ARM_CP_NOP }, 1835 /* Performance monitors are implementation defined in v7, 1836 * but with an ARM recommended set of registers, which we 1837 * follow. 1838 * 1839 * Performance registers fall into three categories: 1840 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR) 1841 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR) 1842 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others) 1843 * For the cases controlled by PMUSERENR we must set .access to PL0_RW 1844 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn. 1845 */ 1846 { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1, 1847 .access = PL0_RW, .type = ARM_CP_ALIAS, 1848 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten), 1849 .writefn = pmcntenset_write, 1850 .accessfn = pmreg_access, 1851 .raw_writefn = raw_write }, 1852 { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64, 1853 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1, 1854 .access = PL0_RW, .accessfn = pmreg_access, 1855 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0, 1856 .writefn = pmcntenset_write, .raw_writefn = raw_write }, 1857 { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2, 1858 .access = PL0_RW, 1859 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten), 1860 .accessfn = pmreg_access, 1861 .writefn = pmcntenclr_write, 1862 .type = ARM_CP_ALIAS }, 1863 { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64, 1864 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2, 1865 .access = PL0_RW, .accessfn = pmreg_access, 1866 .type = ARM_CP_ALIAS, 1867 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), 1868 .writefn = pmcntenclr_write }, 1869 { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3, 1870 .access = PL0_RW, .type = ARM_CP_IO, 1871 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr), 1872 .accessfn = pmreg_access, 1873 .writefn = pmovsr_write, 1874 .raw_writefn = raw_write }, 1875 { .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64, 1876 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 3, 1877 .access = PL0_RW, .accessfn = pmreg_access, 1878 .type = ARM_CP_ALIAS | ARM_CP_IO, 1879 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), 1880 .writefn = pmovsr_write, 1881 .raw_writefn = raw_write }, 1882 { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4, 1883 .access = PL0_W, .accessfn = pmreg_access_swinc, 1884 .type = ARM_CP_NO_RAW | ARM_CP_IO, 1885 .writefn = pmswinc_write }, 1886 { .name = "PMSWINC_EL0", .state = ARM_CP_STATE_AA64, 1887 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 4, 1888 .access = PL0_W, .accessfn = pmreg_access_swinc, 1889 .type = ARM_CP_NO_RAW | ARM_CP_IO, 1890 .writefn = pmswinc_write }, 1891 { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5, 1892 .access = PL0_RW, .type = ARM_CP_ALIAS, 1893 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr), 1894 .accessfn = pmreg_access_selr, .writefn = pmselr_write, 1895 .raw_writefn = raw_write}, 1896 { .name = "PMSELR_EL0", .state = ARM_CP_STATE_AA64, 1897 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 5, 1898 .access = PL0_RW, .accessfn = pmreg_access_selr, 1899 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmselr), 1900 .writefn = pmselr_write, .raw_writefn = raw_write, }, 1901 { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0, 1902 .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_ALIAS | ARM_CP_IO, 1903 .readfn = pmccntr_read, .writefn = pmccntr_write32, 1904 .accessfn = pmreg_access_ccntr }, 1905 { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64, 1906 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0, 1907 .access = PL0_RW, .accessfn = pmreg_access_ccntr, 1908 .type = ARM_CP_IO, 1909 .fieldoffset = offsetof(CPUARMState, cp15.c15_ccnt), 1910 .readfn = pmccntr_read, .writefn = pmccntr_write, 1911 .raw_readfn = raw_read, .raw_writefn = raw_write, }, 1912 { .name = "PMCCFILTR", .cp = 15, .opc1 = 0, .crn = 14, .crm = 15, .opc2 = 7, 1913 .writefn = pmccfiltr_write_a32, .readfn = pmccfiltr_read_a32, 1914 .access = PL0_RW, .accessfn = pmreg_access, 1915 .type = ARM_CP_ALIAS | ARM_CP_IO, 1916 .resetvalue = 0, }, 1917 { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64, 1918 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7, 1919 .writefn = pmccfiltr_write, .raw_writefn = raw_write, 1920 .access = PL0_RW, .accessfn = pmreg_access, 1921 .type = ARM_CP_IO, 1922 .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0), 1923 .resetvalue = 0, }, 1924 { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1, 1925 .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, 1926 .accessfn = pmreg_access, 1927 .writefn = pmxevtyper_write, .readfn = pmxevtyper_read }, 1928 { .name = "PMXEVTYPER_EL0", .state = ARM_CP_STATE_AA64, 1929 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 1, 1930 .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, 1931 .accessfn = pmreg_access, 1932 .writefn = pmxevtyper_write, .readfn = pmxevtyper_read }, 1933 { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2, 1934 .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, 1935 .accessfn = pmreg_access_xevcntr, 1936 .writefn = pmxevcntr_write, .readfn = pmxevcntr_read }, 1937 { .name = "PMXEVCNTR_EL0", .state = ARM_CP_STATE_AA64, 1938 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 2, 1939 .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, 1940 .accessfn = pmreg_access_xevcntr, 1941 .writefn = pmxevcntr_write, .readfn = pmxevcntr_read }, 1942 { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0, 1943 .access = PL0_R | PL1_RW, .accessfn = access_tpm, 1944 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmuserenr), 1945 .resetvalue = 0, 1946 .writefn = pmuserenr_write, .raw_writefn = raw_write }, 1947 { .name = "PMUSERENR_EL0", .state = ARM_CP_STATE_AA64, 1948 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 0, 1949 .access = PL0_R | PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS, 1950 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr), 1951 .resetvalue = 0, 1952 .writefn = pmuserenr_write, .raw_writefn = raw_write }, 1953 { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1, 1954 .access = PL1_RW, .accessfn = access_tpm, 1955 .type = ARM_CP_ALIAS | ARM_CP_IO, 1956 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pminten), 1957 .resetvalue = 0, 1958 .writefn = pmintenset_write, .raw_writefn = raw_write }, 1959 { .name = "PMINTENSET_EL1", .state = ARM_CP_STATE_AA64, 1960 .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 1, 1961 .access = PL1_RW, .accessfn = access_tpm, 1962 .type = ARM_CP_IO, 1963 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), 1964 .writefn = pmintenset_write, .raw_writefn = raw_write, 1965 .resetvalue = 0x0 }, 1966 { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2, 1967 .access = PL1_RW, .accessfn = access_tpm, 1968 .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, 1969 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), 1970 .writefn = pmintenclr_write, }, 1971 { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64, 1972 .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2, 1973 .access = PL1_RW, .accessfn = access_tpm, 1974 .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, 1975 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), 1976 .writefn = pmintenclr_write }, 1977 { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, 1978 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, 1979 .access = PL1_R, 1980 .accessfn = access_aa64_tid2, 1981 .readfn = ccsidr_read, .type = ARM_CP_NO_RAW }, 1982 { .name = "CSSELR", .state = ARM_CP_STATE_BOTH, 1983 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0, 1984 .access = PL1_RW, 1985 .accessfn = access_aa64_tid2, 1986 .writefn = csselr_write, .resetvalue = 0, 1987 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s), 1988 offsetof(CPUARMState, cp15.csselr_ns) } }, 1989 /* Auxiliary ID register: this actually has an IMPDEF value but for now 1990 * just RAZ for all cores: 1991 */ 1992 { .name = "AIDR", .state = ARM_CP_STATE_BOTH, 1993 .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7, 1994 .access = PL1_R, .type = ARM_CP_CONST, 1995 .accessfn = access_aa64_tid1, 1996 .resetvalue = 0 }, 1997 /* Auxiliary fault status registers: these also are IMPDEF, and we 1998 * choose to RAZ/WI for all cores. 1999 */ 2000 { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH, 2001 .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0, 2002 .access = PL1_RW, .accessfn = access_tvm_trvm, 2003 .type = ARM_CP_CONST, .resetvalue = 0 }, 2004 { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH, 2005 .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1, 2006 .access = PL1_RW, .accessfn = access_tvm_trvm, 2007 .type = ARM_CP_CONST, .resetvalue = 0 }, 2008 /* MAIR can just read-as-written because we don't implement caches 2009 * and so don't need to care about memory attributes. 2010 */ 2011 { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64, 2012 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, 2013 .access = PL1_RW, .accessfn = access_tvm_trvm, 2014 .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]), 2015 .resetvalue = 0 }, 2016 { .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64, 2017 .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0, 2018 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]), 2019 .resetvalue = 0 }, 2020 /* For non-long-descriptor page tables these are PRRR and NMRR; 2021 * regardless they still act as reads-as-written for QEMU. 2022 */ 2023 /* MAIR0/1 are defined separately from their 64-bit counterpart which 2024 * allows them to assign the correct fieldoffset based on the endianness 2025 * handled in the field definitions. 2026 */ 2027 { .name = "MAIR0", .state = ARM_CP_STATE_AA32, 2028 .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, 2029 .access = PL1_RW, .accessfn = access_tvm_trvm, 2030 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair0_s), 2031 offsetof(CPUARMState, cp15.mair0_ns) }, 2032 .resetfn = arm_cp_reset_ignore }, 2033 { .name = "MAIR1", .state = ARM_CP_STATE_AA32, 2034 .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, 2035 .access = PL1_RW, .accessfn = access_tvm_trvm, 2036 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair1_s), 2037 offsetof(CPUARMState, cp15.mair1_ns) }, 2038 .resetfn = arm_cp_reset_ignore }, 2039 { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH, 2040 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0, 2041 .type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read }, 2042 /* 32 bit ITLB invalidates */ 2043 { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0, 2044 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, 2045 .writefn = tlbiall_write }, 2046 { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1, 2047 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, 2048 .writefn = tlbimva_write }, 2049 { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2, 2050 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, 2051 .writefn = tlbiasid_write }, 2052 /* 32 bit DTLB invalidates */ 2053 { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0, 2054 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, 2055 .writefn = tlbiall_write }, 2056 { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1, 2057 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, 2058 .writefn = tlbimva_write }, 2059 { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2, 2060 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, 2061 .writefn = tlbiasid_write }, 2062 /* 32 bit TLB invalidates */ 2063 { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, 2064 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, 2065 .writefn = tlbiall_write }, 2066 { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, 2067 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, 2068 .writefn = tlbimva_write }, 2069 { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, 2070 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, 2071 .writefn = tlbiasid_write }, 2072 { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, 2073 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, 2074 .writefn = tlbimvaa_write }, 2075 }; 2076 2077 static const ARMCPRegInfo v7mp_cp_reginfo[] = { 2078 /* 32 bit TLB invalidates, Inner Shareable */ 2079 { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, 2080 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, 2081 .writefn = tlbiall_is_write }, 2082 { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, 2083 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, 2084 .writefn = tlbimva_is_write }, 2085 { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, 2086 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, 2087 .writefn = tlbiasid_is_write }, 2088 { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, 2089 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, 2090 .writefn = tlbimvaa_is_write }, 2091 }; 2092 2093 static const ARMCPRegInfo pmovsset_cp_reginfo[] = { 2094 /* PMOVSSET is not implemented in v7 before v7ve */ 2095 { .name = "PMOVSSET", .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 3, 2096 .access = PL0_RW, .accessfn = pmreg_access, 2097 .type = ARM_CP_ALIAS | ARM_CP_IO, 2098 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr), 2099 .writefn = pmovsset_write, 2100 .raw_writefn = raw_write }, 2101 { .name = "PMOVSSET_EL0", .state = ARM_CP_STATE_AA64, 2102 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 3, 2103 .access = PL0_RW, .accessfn = pmreg_access, 2104 .type = ARM_CP_ALIAS | ARM_CP_IO, 2105 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), 2106 .writefn = pmovsset_write, 2107 .raw_writefn = raw_write }, 2108 }; 2109 2110 static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, 2111 uint64_t value) 2112 { 2113 value &= 1; 2114 env->teecr = value; 2115 } 2116 2117 static CPAccessResult teecr_access(CPUARMState *env, const ARMCPRegInfo *ri, 2118 bool isread) 2119 { 2120 /* 2121 * HSTR.TTEE only exists in v7A, not v8A, but v8A doesn't have T2EE 2122 * at all, so we don't need to check whether we're v8A. 2123 */ 2124 if (arm_current_el(env) < 2 && !arm_is_secure_below_el3(env) && 2125 (env->cp15.hstr_el2 & HSTR_TTEE)) { 2126 return CP_ACCESS_TRAP_EL2; 2127 } 2128 return CP_ACCESS_OK; 2129 } 2130 2131 static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri, 2132 bool isread) 2133 { 2134 if (arm_current_el(env) == 0 && (env->teecr & 1)) { 2135 return CP_ACCESS_TRAP; 2136 } 2137 return teecr_access(env, ri, isread); 2138 } 2139 2140 static const ARMCPRegInfo t2ee_cp_reginfo[] = { 2141 { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0, 2142 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr), 2143 .resetvalue = 0, 2144 .writefn = teecr_write, .accessfn = teecr_access }, 2145 { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0, 2146 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr), 2147 .accessfn = teehbr_access, .resetvalue = 0 }, 2148 }; 2149 2150 static const ARMCPRegInfo v6k_cp_reginfo[] = { 2151 { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64, 2152 .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0, 2153 .access = PL0_RW, 2154 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 }, 2155 { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2, 2156 .access = PL0_RW, 2157 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s), 2158 offsetoflow32(CPUARMState, cp15.tpidrurw_ns) }, 2159 .resetfn = arm_cp_reset_ignore }, 2160 { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64, 2161 .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0, 2162 .access = PL0_R|PL1_W, 2163 .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]), 2164 .resetvalue = 0}, 2165 { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3, 2166 .access = PL0_R|PL1_W, 2167 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s), 2168 offsetoflow32(CPUARMState, cp15.tpidruro_ns) }, 2169 .resetfn = arm_cp_reset_ignore }, 2170 { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64, 2171 .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0, 2172 .access = PL1_RW, 2173 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 }, 2174 { .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4, 2175 .access = PL1_RW, 2176 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s), 2177 offsetoflow32(CPUARMState, cp15.tpidrprw_ns) }, 2178 .resetvalue = 0 }, 2179 }; 2180 2181 #ifndef CONFIG_USER_ONLY 2182 2183 static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri, 2184 bool isread) 2185 { 2186 /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero. 2187 * Writable only at the highest implemented exception level. 2188 */ 2189 int el = arm_current_el(env); 2190 uint64_t hcr; 2191 uint32_t cntkctl; 2192 2193 switch (el) { 2194 case 0: 2195 hcr = arm_hcr_el2_eff(env); 2196 if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { 2197 cntkctl = env->cp15.cnthctl_el2; 2198 } else { 2199 cntkctl = env->cp15.c14_cntkctl; 2200 } 2201 if (!extract32(cntkctl, 0, 2)) { 2202 return CP_ACCESS_TRAP; 2203 } 2204 break; 2205 case 1: 2206 if (!isread && ri->state == ARM_CP_STATE_AA32 && 2207 arm_is_secure_below_el3(env)) { 2208 /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */ 2209 return CP_ACCESS_TRAP_UNCATEGORIZED; 2210 } 2211 break; 2212 case 2: 2213 case 3: 2214 break; 2215 } 2216 2217 if (!isread && el < arm_highest_el(env)) { 2218 return CP_ACCESS_TRAP_UNCATEGORIZED; 2219 } 2220 2221 return CP_ACCESS_OK; 2222 } 2223 2224 static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx, 2225 bool isread) 2226 { 2227 unsigned int cur_el = arm_current_el(env); 2228 bool has_el2 = arm_is_el2_enabled(env); 2229 uint64_t hcr = arm_hcr_el2_eff(env); 2230 2231 switch (cur_el) { 2232 case 0: 2233 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]CTEN. */ 2234 if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { 2235 return (extract32(env->cp15.cnthctl_el2, timeridx, 1) 2236 ? CP_ACCESS_OK : CP_ACCESS_TRAP_EL2); 2237 } 2238 2239 /* CNT[PV]CT: not visible from PL0 if EL0[PV]CTEN is zero */ 2240 if (!extract32(env->cp15.c14_cntkctl, timeridx, 1)) { 2241 return CP_ACCESS_TRAP; 2242 } 2243 2244 /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PCTEN. */ 2245 if (hcr & HCR_E2H) { 2246 if (timeridx == GTIMER_PHYS && 2247 !extract32(env->cp15.cnthctl_el2, 10, 1)) { 2248 return CP_ACCESS_TRAP_EL2; 2249 } 2250 } else { 2251 /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */ 2252 if (has_el2 && timeridx == GTIMER_PHYS && 2253 !extract32(env->cp15.cnthctl_el2, 1, 1)) { 2254 return CP_ACCESS_TRAP_EL2; 2255 } 2256 } 2257 break; 2258 2259 case 1: 2260 /* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H. */ 2261 if (has_el2 && timeridx == GTIMER_PHYS && 2262 (hcr & HCR_E2H 2263 ? !extract32(env->cp15.cnthctl_el2, 10, 1) 2264 : !extract32(env->cp15.cnthctl_el2, 0, 1))) { 2265 return CP_ACCESS_TRAP_EL2; 2266 } 2267 break; 2268 } 2269 return CP_ACCESS_OK; 2270 } 2271 2272 static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx, 2273 bool isread) 2274 { 2275 unsigned int cur_el = arm_current_el(env); 2276 bool has_el2 = arm_is_el2_enabled(env); 2277 uint64_t hcr = arm_hcr_el2_eff(env); 2278 2279 switch (cur_el) { 2280 case 0: 2281 if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { 2282 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]TEN. */ 2283 return (extract32(env->cp15.cnthctl_el2, 9 - timeridx, 1) 2284 ? CP_ACCESS_OK : CP_ACCESS_TRAP_EL2); 2285 } 2286 2287 /* 2288 * CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from 2289 * EL0 if EL0[PV]TEN is zero. 2290 */ 2291 if (!extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) { 2292 return CP_ACCESS_TRAP; 2293 } 2294 /* fall through */ 2295 2296 case 1: 2297 if (has_el2 && timeridx == GTIMER_PHYS) { 2298 if (hcr & HCR_E2H) { 2299 /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PTEN. */ 2300 if (!extract32(env->cp15.cnthctl_el2, 11, 1)) { 2301 return CP_ACCESS_TRAP_EL2; 2302 } 2303 } else { 2304 /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */ 2305 if (!extract32(env->cp15.cnthctl_el2, 1, 1)) { 2306 return CP_ACCESS_TRAP_EL2; 2307 } 2308 } 2309 } 2310 break; 2311 } 2312 return CP_ACCESS_OK; 2313 } 2314 2315 static CPAccessResult gt_pct_access(CPUARMState *env, 2316 const ARMCPRegInfo *ri, 2317 bool isread) 2318 { 2319 return gt_counter_access(env, GTIMER_PHYS, isread); 2320 } 2321 2322 static CPAccessResult gt_vct_access(CPUARMState *env, 2323 const ARMCPRegInfo *ri, 2324 bool isread) 2325 { 2326 return gt_counter_access(env, GTIMER_VIRT, isread); 2327 } 2328 2329 static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri, 2330 bool isread) 2331 { 2332 return gt_timer_access(env, GTIMER_PHYS, isread); 2333 } 2334 2335 static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri, 2336 bool isread) 2337 { 2338 return gt_timer_access(env, GTIMER_VIRT, isread); 2339 } 2340 2341 static CPAccessResult gt_stimer_access(CPUARMState *env, 2342 const ARMCPRegInfo *ri, 2343 bool isread) 2344 { 2345 /* The AArch64 register view of the secure physical timer is 2346 * always accessible from EL3, and configurably accessible from 2347 * Secure EL1. 2348 */ 2349 switch (arm_current_el(env)) { 2350 case 1: 2351 if (!arm_is_secure(env)) { 2352 return CP_ACCESS_TRAP; 2353 } 2354 if (!(env->cp15.scr_el3 & SCR_ST)) { 2355 return CP_ACCESS_TRAP_EL3; 2356 } 2357 return CP_ACCESS_OK; 2358 case 0: 2359 case 2: 2360 return CP_ACCESS_TRAP; 2361 case 3: 2362 return CP_ACCESS_OK; 2363 default: 2364 g_assert_not_reached(); 2365 } 2366 } 2367 2368 static uint64_t gt_get_countervalue(CPUARMState *env) 2369 { 2370 ARMCPU *cpu = env_archcpu(env); 2371 2372 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / gt_cntfrq_period_ns(cpu); 2373 } 2374 2375 static void gt_recalc_timer(ARMCPU *cpu, int timeridx) 2376 { 2377 ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx]; 2378 2379 if (gt->ctl & 1) { 2380 /* Timer enabled: calculate and set current ISTATUS, irq, and 2381 * reset timer to when ISTATUS next has to change 2382 */ 2383 uint64_t offset = timeridx == GTIMER_VIRT ? 2384 cpu->env.cp15.cntvoff_el2 : 0; 2385 uint64_t count = gt_get_countervalue(&cpu->env); 2386 /* Note that this must be unsigned 64 bit arithmetic: */ 2387 int istatus = count - offset >= gt->cval; 2388 uint64_t nexttick; 2389 int irqstate; 2390 2391 gt->ctl = deposit32(gt->ctl, 2, 1, istatus); 2392 2393 irqstate = (istatus && !(gt->ctl & 2)); 2394 qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate); 2395 2396 if (istatus) { 2397 /* Next transition is when count rolls back over to zero */ 2398 nexttick = UINT64_MAX; 2399 } else { 2400 /* Next transition is when we hit cval */ 2401 nexttick = gt->cval + offset; 2402 } 2403 /* Note that the desired next expiry time might be beyond the 2404 * signed-64-bit range of a QEMUTimer -- in this case we just 2405 * set the timer for as far in the future as possible. When the 2406 * timer expires we will reset the timer for any remaining period. 2407 */ 2408 if (nexttick > INT64_MAX / gt_cntfrq_period_ns(cpu)) { 2409 timer_mod_ns(cpu->gt_timer[timeridx], INT64_MAX); 2410 } else { 2411 timer_mod(cpu->gt_timer[timeridx], nexttick); 2412 } 2413 trace_arm_gt_recalc(timeridx, irqstate, nexttick); 2414 } else { 2415 /* Timer disabled: ISTATUS and timer output always clear */ 2416 gt->ctl &= ~4; 2417 qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0); 2418 timer_del(cpu->gt_timer[timeridx]); 2419 trace_arm_gt_recalc_disabled(timeridx); 2420 } 2421 } 2422 2423 static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri, 2424 int timeridx) 2425 { 2426 ARMCPU *cpu = env_archcpu(env); 2427 2428 timer_del(cpu->gt_timer[timeridx]); 2429 } 2430 2431 static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) 2432 { 2433 return gt_get_countervalue(env); 2434 } 2435 2436 static uint64_t gt_virt_cnt_offset(CPUARMState *env) 2437 { 2438 uint64_t hcr; 2439 2440 switch (arm_current_el(env)) { 2441 case 2: 2442 hcr = arm_hcr_el2_eff(env); 2443 if (hcr & HCR_E2H) { 2444 return 0; 2445 } 2446 break; 2447 case 0: 2448 hcr = arm_hcr_el2_eff(env); 2449 if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { 2450 return 0; 2451 } 2452 break; 2453 } 2454 2455 return env->cp15.cntvoff_el2; 2456 } 2457 2458 static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) 2459 { 2460 return gt_get_countervalue(env) - gt_virt_cnt_offset(env); 2461 } 2462 2463 static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, 2464 int timeridx, 2465 uint64_t value) 2466 { 2467 trace_arm_gt_cval_write(timeridx, value); 2468 env->cp15.c14_timer[timeridx].cval = value; 2469 gt_recalc_timer(env_archcpu(env), timeridx); 2470 } 2471 2472 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri, 2473 int timeridx) 2474 { 2475 uint64_t offset = 0; 2476 2477 switch (timeridx) { 2478 case GTIMER_VIRT: 2479 case GTIMER_HYPVIRT: 2480 offset = gt_virt_cnt_offset(env); 2481 break; 2482 } 2483 2484 return (uint32_t)(env->cp15.c14_timer[timeridx].cval - 2485 (gt_get_countervalue(env) - offset)); 2486 } 2487 2488 static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, 2489 int timeridx, 2490 uint64_t value) 2491 { 2492 uint64_t offset = 0; 2493 2494 switch (timeridx) { 2495 case GTIMER_VIRT: 2496 case GTIMER_HYPVIRT: 2497 offset = gt_virt_cnt_offset(env); 2498 break; 2499 } 2500 2501 trace_arm_gt_tval_write(timeridx, value); 2502 env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset + 2503 sextract64(value, 0, 32); 2504 gt_recalc_timer(env_archcpu(env), timeridx); 2505 } 2506 2507 static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, 2508 int timeridx, 2509 uint64_t value) 2510 { 2511 ARMCPU *cpu = env_archcpu(env); 2512 uint32_t oldval = env->cp15.c14_timer[timeridx].ctl; 2513 2514 trace_arm_gt_ctl_write(timeridx, value); 2515 env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value); 2516 if ((oldval ^ value) & 1) { 2517 /* Enable toggled */ 2518 gt_recalc_timer(cpu, timeridx); 2519 } else if ((oldval ^ value) & 2) { 2520 /* IMASK toggled: don't need to recalculate, 2521 * just set the interrupt line based on ISTATUS 2522 */ 2523 int irqstate = (oldval & 4) && !(value & 2); 2524 2525 trace_arm_gt_imask_toggle(timeridx, irqstate); 2526 qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate); 2527 } 2528 } 2529 2530 static void gt_phys_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) 2531 { 2532 gt_timer_reset(env, ri, GTIMER_PHYS); 2533 } 2534 2535 static void gt_phys_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, 2536 uint64_t value) 2537 { 2538 gt_cval_write(env, ri, GTIMER_PHYS, value); 2539 } 2540 2541 static uint64_t gt_phys_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) 2542 { 2543 return gt_tval_read(env, ri, GTIMER_PHYS); 2544 } 2545 2546 static void gt_phys_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, 2547 uint64_t value) 2548 { 2549 gt_tval_write(env, ri, GTIMER_PHYS, value); 2550 } 2551 2552 static void gt_phys_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, 2553 uint64_t value) 2554 { 2555 gt_ctl_write(env, ri, GTIMER_PHYS, value); 2556 } 2557 2558 static int gt_phys_redir_timeridx(CPUARMState *env) 2559 { 2560 switch (arm_mmu_idx(env)) { 2561 case ARMMMUIdx_E20_0: 2562 case ARMMMUIdx_E20_2: 2563 case ARMMMUIdx_E20_2_PAN: 2564 case ARMMMUIdx_SE20_0: 2565 case ARMMMUIdx_SE20_2: 2566 case ARMMMUIdx_SE20_2_PAN: 2567 return GTIMER_HYP; 2568 default: 2569 return GTIMER_PHYS; 2570 } 2571 } 2572 2573 static int gt_virt_redir_timeridx(CPUARMState *env) 2574 { 2575 switch (arm_mmu_idx(env)) { 2576 case ARMMMUIdx_E20_0: 2577 case ARMMMUIdx_E20_2: 2578 case ARMMMUIdx_E20_2_PAN: 2579 case ARMMMUIdx_SE20_0: 2580 case ARMMMUIdx_SE20_2: 2581 case ARMMMUIdx_SE20_2_PAN: 2582 return GTIMER_HYPVIRT; 2583 default: 2584 return GTIMER_VIRT; 2585 } 2586 } 2587 2588 static uint64_t gt_phys_redir_cval_read(CPUARMState *env, 2589 const ARMCPRegInfo *ri) 2590 { 2591 int timeridx = gt_phys_redir_timeridx(env); 2592 return env->cp15.c14_timer[timeridx].cval; 2593 } 2594 2595 static void gt_phys_redir_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, 2596 uint64_t value) 2597 { 2598 int timeridx = gt_phys_redir_timeridx(env); 2599 gt_cval_write(env, ri, timeridx, value); 2600 } 2601 2602 static uint64_t gt_phys_redir_tval_read(CPUARMState *env, 2603 const ARMCPRegInfo *ri) 2604 { 2605 int timeridx = gt_phys_redir_timeridx(env); 2606 return gt_tval_read(env, ri, timeridx); 2607 } 2608 2609 static void gt_phys_redir_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, 2610 uint64_t value) 2611 { 2612 int timeridx = gt_phys_redir_timeridx(env); 2613 gt_tval_write(env, ri, timeridx, value); 2614 } 2615 2616 static uint64_t gt_phys_redir_ctl_read(CPUARMState *env, 2617 const ARMCPRegInfo *ri) 2618 { 2619 int timeridx = gt_phys_redir_timeridx(env); 2620 return env->cp15.c14_timer[timeridx].ctl; 2621 } 2622 2623 static void gt_phys_redir_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, 2624 uint64_t value) 2625 { 2626 int timeridx = gt_phys_redir_timeridx(env); 2627 gt_ctl_write(env, ri, timeridx, value); 2628 } 2629 2630 static void gt_virt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) 2631 { 2632 gt_timer_reset(env, ri, GTIMER_VIRT); 2633 } 2634 2635 static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, 2636 uint64_t value) 2637 { 2638 gt_cval_write(env, ri, GTIMER_VIRT, value); 2639 } 2640 2641 static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) 2642 { 2643 return gt_tval_read(env, ri, GTIMER_VIRT); 2644 } 2645 2646 static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, 2647 uint64_t value) 2648 { 2649 gt_tval_write(env, ri, GTIMER_VIRT, value); 2650 } 2651 2652 static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, 2653 uint64_t value) 2654 { 2655 gt_ctl_write(env, ri, GTIMER_VIRT, value); 2656 } 2657 2658 static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri, 2659 uint64_t value) 2660 { 2661 ARMCPU *cpu = env_archcpu(env); 2662 2663 trace_arm_gt_cntvoff_write(value); 2664 raw_write(env, ri, value); 2665 gt_recalc_timer(cpu, GTIMER_VIRT); 2666 } 2667 2668 static uint64_t gt_virt_redir_cval_read(CPUARMState *env, 2669 const ARMCPRegInfo *ri) 2670 { 2671 int timeridx = gt_virt_redir_timeridx(env); 2672 return env->cp15.c14_timer[timeridx].cval; 2673 } 2674 2675 static void gt_virt_redir_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, 2676 uint64_t value) 2677 { 2678 int timeridx = gt_virt_redir_timeridx(env); 2679 gt_cval_write(env, ri, timeridx, value); 2680 } 2681 2682 static uint64_t gt_virt_redir_tval_read(CPUARMState *env, 2683 const ARMCPRegInfo *ri) 2684 { 2685 int timeridx = gt_virt_redir_timeridx(env); 2686 return gt_tval_read(env, ri, timeridx); 2687 } 2688 2689 static void gt_virt_redir_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, 2690 uint64_t value) 2691 { 2692 int timeridx = gt_virt_redir_timeridx(env); 2693 gt_tval_write(env, ri, timeridx, value); 2694 } 2695 2696 static uint64_t gt_virt_redir_ctl_read(CPUARMState *env, 2697 const ARMCPRegInfo *ri) 2698 { 2699 int timeridx = gt_virt_redir_timeridx(env); 2700 return env->cp15.c14_timer[timeridx].ctl; 2701 } 2702 2703 static void gt_virt_redir_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, 2704 uint64_t value) 2705 { 2706 int timeridx = gt_virt_redir_timeridx(env); 2707 gt_ctl_write(env, ri, timeridx, value); 2708 } 2709 2710 static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) 2711 { 2712 gt_timer_reset(env, ri, GTIMER_HYP); 2713 } 2714 2715 static void gt_hyp_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, 2716 uint64_t value) 2717 { 2718 gt_cval_write(env, ri, GTIMER_HYP, value); 2719 } 2720 2721 static uint64_t gt_hyp_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) 2722 { 2723 return gt_tval_read(env, ri, GTIMER_HYP); 2724 } 2725 2726 static void gt_hyp_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, 2727 uint64_t value) 2728 { 2729 gt_tval_write(env, ri, GTIMER_HYP, value); 2730 } 2731 2732 static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, 2733 uint64_t value) 2734 { 2735 gt_ctl_write(env, ri, GTIMER_HYP, value); 2736 } 2737 2738 static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) 2739 { 2740 gt_timer_reset(env, ri, GTIMER_SEC); 2741 } 2742 2743 static void gt_sec_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, 2744 uint64_t value) 2745 { 2746 gt_cval_write(env, ri, GTIMER_SEC, value); 2747 } 2748 2749 static uint64_t gt_sec_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) 2750 { 2751 return gt_tval_read(env, ri, GTIMER_SEC); 2752 } 2753 2754 static void gt_sec_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, 2755 uint64_t value) 2756 { 2757 gt_tval_write(env, ri, GTIMER_SEC, value); 2758 } 2759 2760 static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, 2761 uint64_t value) 2762 { 2763 gt_ctl_write(env, ri, GTIMER_SEC, value); 2764 } 2765 2766 static void gt_hv_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) 2767 { 2768 gt_timer_reset(env, ri, GTIMER_HYPVIRT); 2769 } 2770 2771 static void gt_hv_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, 2772 uint64_t value) 2773 { 2774 gt_cval_write(env, ri, GTIMER_HYPVIRT, value); 2775 } 2776 2777 static uint64_t gt_hv_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) 2778 { 2779 return gt_tval_read(env, ri, GTIMER_HYPVIRT); 2780 } 2781 2782 static void gt_hv_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, 2783 uint64_t value) 2784 { 2785 gt_tval_write(env, ri, GTIMER_HYPVIRT, value); 2786 } 2787 2788 static void gt_hv_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, 2789 uint64_t value) 2790 { 2791 gt_ctl_write(env, ri, GTIMER_HYPVIRT, value); 2792 } 2793 2794 void arm_gt_ptimer_cb(void *opaque) 2795 { 2796 ARMCPU *cpu = opaque; 2797 2798 gt_recalc_timer(cpu, GTIMER_PHYS); 2799 } 2800 2801 void arm_gt_vtimer_cb(void *opaque) 2802 { 2803 ARMCPU *cpu = opaque; 2804 2805 gt_recalc_timer(cpu, GTIMER_VIRT); 2806 } 2807 2808 void arm_gt_htimer_cb(void *opaque) 2809 { 2810 ARMCPU *cpu = opaque; 2811 2812 gt_recalc_timer(cpu, GTIMER_HYP); 2813 } 2814 2815 void arm_gt_stimer_cb(void *opaque) 2816 { 2817 ARMCPU *cpu = opaque; 2818 2819 gt_recalc_timer(cpu, GTIMER_SEC); 2820 } 2821 2822 void arm_gt_hvtimer_cb(void *opaque) 2823 { 2824 ARMCPU *cpu = opaque; 2825 2826 gt_recalc_timer(cpu, GTIMER_HYPVIRT); 2827 } 2828 2829 static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *opaque) 2830 { 2831 ARMCPU *cpu = env_archcpu(env); 2832 2833 cpu->env.cp15.c14_cntfrq = cpu->gt_cntfrq_hz; 2834 } 2835 2836 static const ARMCPRegInfo generic_timer_cp_reginfo[] = { 2837 /* Note that CNTFRQ is purely reads-as-written for the benefit 2838 * of software; writing it doesn't actually change the timer frequency. 2839 * Our reset value matches the fixed frequency we implement the timer at. 2840 */ 2841 { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0, 2842 .type = ARM_CP_ALIAS, 2843 .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, 2844 .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq), 2845 }, 2846 { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64, 2847 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0, 2848 .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, 2849 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq), 2850 .resetfn = arm_gt_cntfrq_reset, 2851 }, 2852 /* overall control: mostly access permissions */ 2853 { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH, 2854 .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0, 2855 .access = PL1_RW, 2856 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl), 2857 .resetvalue = 0, 2858 }, 2859 /* per-timer control */ 2860 { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1, 2861 .secure = ARM_CP_SECSTATE_NS, 2862 .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL0_RW, 2863 .accessfn = gt_ptimer_access, 2864 .fieldoffset = offsetoflow32(CPUARMState, 2865 cp15.c14_timer[GTIMER_PHYS].ctl), 2866 .readfn = gt_phys_redir_ctl_read, .raw_readfn = raw_read, 2867 .writefn = gt_phys_redir_ctl_write, .raw_writefn = raw_write, 2868 }, 2869 { .name = "CNTP_CTL_S", 2870 .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1, 2871 .secure = ARM_CP_SECSTATE_S, 2872 .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL0_RW, 2873 .accessfn = gt_ptimer_access, 2874 .fieldoffset = offsetoflow32(CPUARMState, 2875 cp15.c14_timer[GTIMER_SEC].ctl), 2876 .writefn = gt_sec_ctl_write, .raw_writefn = raw_write, 2877 }, 2878 { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64, 2879 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1, 2880 .type = ARM_CP_IO, .access = PL0_RW, 2881 .accessfn = gt_ptimer_access, 2882 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl), 2883 .resetvalue = 0, 2884 .readfn = gt_phys_redir_ctl_read, .raw_readfn = raw_read, 2885 .writefn = gt_phys_redir_ctl_write, .raw_writefn = raw_write, 2886 }, 2887 { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1, 2888 .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL0_RW, 2889 .accessfn = gt_vtimer_access, 2890 .fieldoffset = offsetoflow32(CPUARMState, 2891 cp15.c14_timer[GTIMER_VIRT].ctl), 2892 .readfn = gt_virt_redir_ctl_read, .raw_readfn = raw_read, 2893 .writefn = gt_virt_redir_ctl_write, .raw_writefn = raw_write, 2894 }, 2895 { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64, 2896 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1, 2897 .type = ARM_CP_IO, .access = PL0_RW, 2898 .accessfn = gt_vtimer_access, 2899 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl), 2900 .resetvalue = 0, 2901 .readfn = gt_virt_redir_ctl_read, .raw_readfn = raw_read, 2902 .writefn = gt_virt_redir_ctl_write, .raw_writefn = raw_write, 2903 }, 2904 /* TimerValue views: a 32 bit downcounting view of the underlying state */ 2905 { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0, 2906 .secure = ARM_CP_SECSTATE_NS, 2907 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, 2908 .accessfn = gt_ptimer_access, 2909 .readfn = gt_phys_redir_tval_read, .writefn = gt_phys_redir_tval_write, 2910 }, 2911 { .name = "CNTP_TVAL_S", 2912 .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0, 2913 .secure = ARM_CP_SECSTATE_S, 2914 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, 2915 .accessfn = gt_ptimer_access, 2916 .readfn = gt_sec_tval_read, .writefn = gt_sec_tval_write, 2917 }, 2918 { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64, 2919 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0, 2920 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, 2921 .accessfn = gt_ptimer_access, .resetfn = gt_phys_timer_reset, 2922 .readfn = gt_phys_redir_tval_read, .writefn = gt_phys_redir_tval_write, 2923 }, 2924 { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0, 2925 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, 2926 .accessfn = gt_vtimer_access, 2927 .readfn = gt_virt_redir_tval_read, .writefn = gt_virt_redir_tval_write, 2928 }, 2929 { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64, 2930 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0, 2931 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, 2932 .accessfn = gt_vtimer_access, .resetfn = gt_virt_timer_reset, 2933 .readfn = gt_virt_redir_tval_read, .writefn = gt_virt_redir_tval_write, 2934 }, 2935 /* The counter itself */ 2936 { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0, 2937 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, 2938 .accessfn = gt_pct_access, 2939 .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore, 2940 }, 2941 { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64, 2942 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1, 2943 .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, 2944 .accessfn = gt_pct_access, .readfn = gt_cnt_read, 2945 }, 2946 { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1, 2947 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, 2948 .accessfn = gt_vct_access, 2949 .readfn = gt_virt_cnt_read, .resetfn = arm_cp_reset_ignore, 2950 }, 2951 { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64, 2952 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2, 2953 .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, 2954 .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read, 2955 }, 2956 /* Comparison value, indicating when the timer goes off */ 2957 { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2, 2958 .secure = ARM_CP_SECSTATE_NS, 2959 .access = PL0_RW, 2960 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, 2961 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), 2962 .accessfn = gt_ptimer_access, 2963 .readfn = gt_phys_redir_cval_read, .raw_readfn = raw_read, 2964 .writefn = gt_phys_redir_cval_write, .raw_writefn = raw_write, 2965 }, 2966 { .name = "CNTP_CVAL_S", .cp = 15, .crm = 14, .opc1 = 2, 2967 .secure = ARM_CP_SECSTATE_S, 2968 .access = PL0_RW, 2969 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, 2970 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval), 2971 .accessfn = gt_ptimer_access, 2972 .writefn = gt_sec_cval_write, .raw_writefn = raw_write, 2973 }, 2974 { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64, 2975 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2, 2976 .access = PL0_RW, 2977 .type = ARM_CP_IO, 2978 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), 2979 .resetvalue = 0, .accessfn = gt_ptimer_access, 2980 .readfn = gt_phys_redir_cval_read, .raw_readfn = raw_read, 2981 .writefn = gt_phys_redir_cval_write, .raw_writefn = raw_write, 2982 }, 2983 { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3, 2984 .access = PL0_RW, 2985 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, 2986 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), 2987 .accessfn = gt_vtimer_access, 2988 .readfn = gt_virt_redir_cval_read, .raw_readfn = raw_read, 2989 .writefn = gt_virt_redir_cval_write, .raw_writefn = raw_write, 2990 }, 2991 { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64, 2992 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2, 2993 .access = PL0_RW, 2994 .type = ARM_CP_IO, 2995 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), 2996 .resetvalue = 0, .accessfn = gt_vtimer_access, 2997 .readfn = gt_virt_redir_cval_read, .raw_readfn = raw_read, 2998 .writefn = gt_virt_redir_cval_write, .raw_writefn = raw_write, 2999 }, 3000 /* Secure timer -- this is actually restricted to only EL3 3001 * and configurably Secure-EL1 via the accessfn. 3002 */ 3003 { .name = "CNTPS_TVAL_EL1", .state = ARM_CP_STATE_AA64, 3004 .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 0, 3005 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW, 3006 .accessfn = gt_stimer_access, 3007 .readfn = gt_sec_tval_read, 3008 .writefn = gt_sec_tval_write, 3009 .resetfn = gt_sec_timer_reset, 3010 }, 3011 { .name = "CNTPS_CTL_EL1", .state = ARM_CP_STATE_AA64, 3012 .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 1, 3013 .type = ARM_CP_IO, .access = PL1_RW, 3014 .accessfn = gt_stimer_access, 3015 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].ctl), 3016 .resetvalue = 0, 3017 .writefn = gt_sec_ctl_write, .raw_writefn = raw_write, 3018 }, 3019 { .name = "CNTPS_CVAL_EL1", .state = ARM_CP_STATE_AA64, 3020 .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 2, 3021 .type = ARM_CP_IO, .access = PL1_RW, 3022 .accessfn = gt_stimer_access, 3023 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval), 3024 .writefn = gt_sec_cval_write, .raw_writefn = raw_write, 3025 }, 3026 }; 3027 3028 static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri, 3029 bool isread) 3030 { 3031 if (!(arm_hcr_el2_eff(env) & HCR_E2H)) { 3032 return CP_ACCESS_TRAP; 3033 } 3034 return CP_ACCESS_OK; 3035 } 3036 3037 #else 3038 3039 /* In user-mode most of the generic timer registers are inaccessible 3040 * however modern kernels (4.12+) allow access to cntvct_el0 3041 */ 3042 3043 static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) 3044 { 3045 ARMCPU *cpu = env_archcpu(env); 3046 3047 /* Currently we have no support for QEMUTimer in linux-user so we 3048 * can't call gt_get_countervalue(env), instead we directly 3049 * call the lower level functions. 3050 */ 3051 return cpu_get_clock() / gt_cntfrq_period_ns(cpu); 3052 } 3053 3054 static const ARMCPRegInfo generic_timer_cp_reginfo[] = { 3055 { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64, 3056 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0, 3057 .type = ARM_CP_CONST, .access = PL0_R /* no PL1_RW in linux-user */, 3058 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq), 3059 .resetvalue = NANOSECONDS_PER_SECOND / GTIMER_SCALE, 3060 }, 3061 { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64, 3062 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2, 3063 .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, 3064 .readfn = gt_virt_cnt_read, 3065 }, 3066 }; 3067 3068 #endif 3069 3070 static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) 3071 { 3072 if (arm_feature(env, ARM_FEATURE_LPAE)) { 3073 raw_write(env, ri, value); 3074 } else if (arm_feature(env, ARM_FEATURE_V7)) { 3075 raw_write(env, ri, value & 0xfffff6ff); 3076 } else { 3077 raw_write(env, ri, value & 0xfffff1ff); 3078 } 3079 } 3080 3081 #ifndef CONFIG_USER_ONLY 3082 /* get_phys_addr() isn't present for user-mode-only targets */ 3083 3084 static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri, 3085 bool isread) 3086 { 3087 if (ri->opc2 & 4) { 3088 /* The ATS12NSO* operations must trap to EL3 or EL2 if executed in 3089 * Secure EL1 (which can only happen if EL3 is AArch64). 3090 * They are simply UNDEF if executed from NS EL1. 3091 * They function normally from EL2 or EL3. 3092 */ 3093 if (arm_current_el(env) == 1) { 3094 if (arm_is_secure_below_el3(env)) { 3095 if (env->cp15.scr_el3 & SCR_EEL2) { 3096 return CP_ACCESS_TRAP_UNCATEGORIZED_EL2; 3097 } 3098 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3; 3099 } 3100 return CP_ACCESS_TRAP_UNCATEGORIZED; 3101 } 3102 } 3103 return CP_ACCESS_OK; 3104 } 3105 3106 #ifdef CONFIG_TCG 3107 static uint64_t do_ats_write(CPUARMState *env, uint64_t value, 3108 MMUAccessType access_type, ARMMMUIdx mmu_idx) 3109 { 3110 hwaddr phys_addr; 3111 target_ulong page_size; 3112 int prot; 3113 bool ret; 3114 uint64_t par64; 3115 bool format64 = false; 3116 MemTxAttrs attrs = {}; 3117 ARMMMUFaultInfo fi = {}; 3118 ARMCacheAttrs cacheattrs = {}; 3119 3120 ret = get_phys_addr(env, value, access_type, mmu_idx, &phys_addr, &attrs, 3121 &prot, &page_size, &fi, &cacheattrs); 3122 3123 /* 3124 * ATS operations only do S1 or S1+S2 translations, so we never 3125 * have to deal with the ARMCacheAttrs format for S2 only. 3126 */ 3127 assert(!cacheattrs.is_s2_format); 3128 3129 if (ret) { 3130 /* 3131 * Some kinds of translation fault must cause exceptions rather 3132 * than being reported in the PAR. 3133 */ 3134 int current_el = arm_current_el(env); 3135 int target_el; 3136 uint32_t syn, fsr, fsc; 3137 bool take_exc = false; 3138 3139 if (fi.s1ptw && current_el == 1 3140 && arm_mmu_idx_is_stage1_of_2(mmu_idx)) { 3141 /* 3142 * Synchronous stage 2 fault on an access made as part of the 3143 * translation table walk for AT S1E0* or AT S1E1* insn 3144 * executed from NS EL1. If this is a synchronous external abort 3145 * and SCR_EL3.EA == 1, then we take a synchronous external abort 3146 * to EL3. Otherwise the fault is taken as an exception to EL2, 3147 * and HPFAR_EL2 holds the faulting IPA. 3148 */ 3149 if (fi.type == ARMFault_SyncExternalOnWalk && 3150 (env->cp15.scr_el3 & SCR_EA)) { 3151 target_el = 3; 3152 } else { 3153 env->cp15.hpfar_el2 = extract64(fi.s2addr, 12, 47) << 4; 3154 if (arm_is_secure_below_el3(env) && fi.s1ns) { 3155 env->cp15.hpfar_el2 |= HPFAR_NS; 3156 } 3157 target_el = 2; 3158 } 3159 take_exc = true; 3160 } else if (fi.type == ARMFault_SyncExternalOnWalk) { 3161 /* 3162 * Synchronous external aborts during a translation table walk 3163 * are taken as Data Abort exceptions. 3164 */ 3165 if (fi.stage2) { 3166 if (current_el == 3) { 3167 target_el = 3; 3168 } else { 3169 target_el = 2; 3170 } 3171 } else { 3172 target_el = exception_target_el(env); 3173 } 3174 take_exc = true; 3175 } 3176 3177 if (take_exc) { 3178 /* Construct FSR and FSC using same logic as arm_deliver_fault() */ 3179 if (target_el == 2 || arm_el_is_aa64(env, target_el) || 3180 arm_s1_regime_using_lpae_format(env, mmu_idx)) { 3181 fsr = arm_fi_to_lfsc(&fi); 3182 fsc = extract32(fsr, 0, 6); 3183 } else { 3184 fsr = arm_fi_to_sfsc(&fi); 3185 fsc = 0x3f; 3186 } 3187 /* 3188 * Report exception with ESR indicating a fault due to a 3189 * translation table walk for a cache maintenance instruction. 3190 */ 3191 syn = syn_data_abort_no_iss(current_el == target_el, 0, 3192 fi.ea, 1, fi.s1ptw, 1, fsc); 3193 env->exception.vaddress = value; 3194 env->exception.fsr = fsr; 3195 raise_exception(env, EXCP_DATA_ABORT, syn, target_el); 3196 } 3197 } 3198 3199 if (is_a64(env)) { 3200 format64 = true; 3201 } else if (arm_feature(env, ARM_FEATURE_LPAE)) { 3202 /* 3203 * ATS1Cxx: 3204 * * TTBCR.EAE determines whether the result is returned using the 3205 * 32-bit or the 64-bit PAR format 3206 * * Instructions executed in Hyp mode always use the 64bit format 3207 * 3208 * ATS1S2NSOxx uses the 64bit format if any of the following is true: 3209 * * The Non-secure TTBCR.EAE bit is set to 1 3210 * * The implementation includes EL2, and the value of HCR.VM is 1 3211 * 3212 * (Note that HCR.DC makes HCR.VM behave as if it is 1.) 3213 * 3214 * ATS1Hx always uses the 64bit format. 3215 */ 3216 format64 = arm_s1_regime_using_lpae_format(env, mmu_idx); 3217 3218 if (arm_feature(env, ARM_FEATURE_EL2)) { 3219 if (mmu_idx == ARMMMUIdx_E10_0 || 3220 mmu_idx == ARMMMUIdx_E10_1 || 3221 mmu_idx == ARMMMUIdx_E10_1_PAN) { 3222 format64 |= env->cp15.hcr_el2 & (HCR_VM | HCR_DC); 3223 } else { 3224 format64 |= arm_current_el(env) == 2; 3225 } 3226 } 3227 } 3228 3229 if (format64) { 3230 /* Create a 64-bit PAR */ 3231 par64 = (1 << 11); /* LPAE bit always set */ 3232 if (!ret) { 3233 par64 |= phys_addr & ~0xfffULL; 3234 if (!attrs.secure) { 3235 par64 |= (1 << 9); /* NS */ 3236 } 3237 par64 |= (uint64_t)cacheattrs.attrs << 56; /* ATTR */ 3238 par64 |= cacheattrs.shareability << 7; /* SH */ 3239 } else { 3240 uint32_t fsr = arm_fi_to_lfsc(&fi); 3241 3242 par64 |= 1; /* F */ 3243 par64 |= (fsr & 0x3f) << 1; /* FS */ 3244 if (fi.stage2) { 3245 par64 |= (1 << 9); /* S */ 3246 } 3247 if (fi.s1ptw) { 3248 par64 |= (1 << 8); /* PTW */ 3249 } 3250 } 3251 } else { 3252 /* fsr is a DFSR/IFSR value for the short descriptor 3253 * translation table format (with WnR always clear). 3254 * Convert it to a 32-bit PAR. 3255 */ 3256 if (!ret) { 3257 /* We do not set any attribute bits in the PAR */ 3258 if (page_size == (1 << 24) 3259 && arm_feature(env, ARM_FEATURE_V7)) { 3260 par64 = (phys_addr & 0xff000000) | (1 << 1); 3261 } else { 3262 par64 = phys_addr & 0xfffff000; 3263 } 3264 if (!attrs.secure) { 3265 par64 |= (1 << 9); /* NS */ 3266 } 3267 } else { 3268 uint32_t fsr = arm_fi_to_sfsc(&fi); 3269 3270 par64 = ((fsr & (1 << 10)) >> 5) | ((fsr & (1 << 12)) >> 6) | 3271 ((fsr & 0xf) << 1) | 1; 3272 } 3273 } 3274 return par64; 3275 } 3276 #endif /* CONFIG_TCG */ 3277 3278 static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) 3279 { 3280 #ifdef CONFIG_TCG 3281 MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; 3282 uint64_t par64; 3283 ARMMMUIdx mmu_idx; 3284 int el = arm_current_el(env); 3285 bool secure = arm_is_secure_below_el3(env); 3286 3287 switch (ri->opc2 & 6) { 3288 case 0: 3289 /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP */ 3290 switch (el) { 3291 case 3: 3292 mmu_idx = ARMMMUIdx_SE3; 3293 break; 3294 case 2: 3295 g_assert(!secure); /* ARMv8.4-SecEL2 is 64-bit only */ 3296 /* fall through */ 3297 case 1: 3298 if (ri->crm == 9 && (env->uncached_cpsr & CPSR_PAN)) { 3299 mmu_idx = (secure ? ARMMMUIdx_Stage1_SE1_PAN 3300 : ARMMMUIdx_Stage1_E1_PAN); 3301 } else { 3302 mmu_idx = secure ? ARMMMUIdx_Stage1_SE1 : ARMMMUIdx_Stage1_E1; 3303 } 3304 break; 3305 default: 3306 g_assert_not_reached(); 3307 } 3308 break; 3309 case 2: 3310 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */ 3311 switch (el) { 3312 case 3: 3313 mmu_idx = ARMMMUIdx_SE10_0; 3314 break; 3315 case 2: 3316 g_assert(!secure); /* ARMv8.4-SecEL2 is 64-bit only */ 3317 mmu_idx = ARMMMUIdx_Stage1_E0; 3318 break; 3319 case 1: 3320 mmu_idx = secure ? ARMMMUIdx_Stage1_SE0 : ARMMMUIdx_Stage1_E0; 3321 break; 3322 default: 3323 g_assert_not_reached(); 3324 } 3325 break; 3326 case 4: 3327 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */ 3328 mmu_idx = ARMMMUIdx_E10_1; 3329 break; 3330 case 6: 3331 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */ 3332 mmu_idx = ARMMMUIdx_E10_0; 3333 break; 3334 default: 3335 g_assert_not_reached(); 3336 } 3337 3338 par64 = do_ats_write(env, value, access_type, mmu_idx); 3339 3340 A32_BANKED_CURRENT_REG_SET(env, par, par64); 3341 #else 3342 /* Handled by hardware accelerator. */ 3343 g_assert_not_reached(); 3344 #endif /* CONFIG_TCG */ 3345 } 3346 3347 static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri, 3348 uint64_t value) 3349 { 3350 #ifdef CONFIG_TCG 3351 MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; 3352 uint64_t par64; 3353 3354 par64 = do_ats_write(env, value, access_type, ARMMMUIdx_E2); 3355 3356 A32_BANKED_CURRENT_REG_SET(env, par, par64); 3357 #else 3358 /* Handled by hardware accelerator. */ 3359 g_assert_not_reached(); 3360 #endif /* CONFIG_TCG */ 3361 } 3362 3363 static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri, 3364 bool isread) 3365 { 3366 if (arm_current_el(env) == 3 && 3367 !(env->cp15.scr_el3 & (SCR_NS | SCR_EEL2))) { 3368 return CP_ACCESS_TRAP; 3369 } 3370 return CP_ACCESS_OK; 3371 } 3372 3373 static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, 3374 uint64_t value) 3375 { 3376 #ifdef CONFIG_TCG 3377 MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; 3378 ARMMMUIdx mmu_idx; 3379 int secure = arm_is_secure_below_el3(env); 3380 3381 switch (ri->opc2 & 6) { 3382 case 0: 3383 switch (ri->opc1) { 3384 case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */ 3385 if (ri->crm == 9 && (env->pstate & PSTATE_PAN)) { 3386 mmu_idx = (secure ? ARMMMUIdx_Stage1_SE1_PAN 3387 : ARMMMUIdx_Stage1_E1_PAN); 3388 } else { 3389 mmu_idx = secure ? ARMMMUIdx_Stage1_SE1 : ARMMMUIdx_Stage1_E1; 3390 } 3391 break; 3392 case 4: /* AT S1E2R, AT S1E2W */ 3393 mmu_idx = secure ? ARMMMUIdx_SE2 : ARMMMUIdx_E2; 3394 break; 3395 case 6: /* AT S1E3R, AT S1E3W */ 3396 mmu_idx = ARMMMUIdx_SE3; 3397 break; 3398 default: 3399 g_assert_not_reached(); 3400 } 3401 break; 3402 case 2: /* AT S1E0R, AT S1E0W */ 3403 mmu_idx = secure ? ARMMMUIdx_Stage1_SE0 : ARMMMUIdx_Stage1_E0; 3404 break; 3405 case 4: /* AT S12E1R, AT S12E1W */ 3406 mmu_idx = secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_E10_1; 3407 break; 3408 case 6: /* AT S12E0R, AT S12E0W */ 3409 mmu_idx = secure ? ARMMMUIdx_SE10_0 : ARMMMUIdx_E10_0; 3410 break; 3411 default: 3412 g_assert_not_reached(); 3413 } 3414 3415 env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx); 3416 #else 3417 /* Handled by hardware accelerator. */ 3418 g_assert_not_reached(); 3419 #endif /* CONFIG_TCG */ 3420 } 3421 #endif 3422 3423 static const ARMCPRegInfo vapa_cp_reginfo[] = { 3424 { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0, 3425 .access = PL1_RW, .resetvalue = 0, 3426 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s), 3427 offsetoflow32(CPUARMState, cp15.par_ns) }, 3428 .writefn = par_write }, 3429 #ifndef CONFIG_USER_ONLY 3430 /* This underdecoding is safe because the reginfo is NO_RAW. */ 3431 { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY, 3432 .access = PL1_W, .accessfn = ats_access, 3433 .writefn = ats_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC }, 3434 #endif 3435 }; 3436 3437 /* Return basic MPU access permission bits. */ 3438 static uint32_t simple_mpu_ap_bits(uint32_t val) 3439 { 3440 uint32_t ret; 3441 uint32_t mask; 3442 int i; 3443 ret = 0; 3444 mask = 3; 3445 for (i = 0; i < 16; i += 2) { 3446 ret |= (val >> i) & mask; 3447 mask <<= 2; 3448 } 3449 return ret; 3450 } 3451 3452 /* Pad basic MPU access permission bits to extended format. */ 3453 static uint32_t extended_mpu_ap_bits(uint32_t val) 3454 { 3455 uint32_t ret; 3456 uint32_t mask; 3457 int i; 3458 ret = 0; 3459 mask = 3; 3460 for (i = 0; i < 16; i += 2) { 3461 ret |= (val & mask) << i; 3462 mask <<= 2; 3463 } 3464 return ret; 3465 } 3466 3467 static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, 3468 uint64_t value) 3469 { 3470 env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value); 3471 } 3472 3473 static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) 3474 { 3475 return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap); 3476 } 3477 3478 static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, 3479 uint64_t value) 3480 { 3481 env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value); 3482 } 3483 3484 static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) 3485 { 3486 return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap); 3487 } 3488 3489 static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri) 3490 { 3491 uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri); 3492 3493 if (!u32p) { 3494 return 0; 3495 } 3496 3497 u32p += env->pmsav7.rnr[M_REG_NS]; 3498 return *u32p; 3499 } 3500 3501 static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri, 3502 uint64_t value) 3503 { 3504 ARMCPU *cpu = env_archcpu(env); 3505 uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri); 3506 3507 if (!u32p) { 3508 return; 3509 } 3510 3511 u32p += env->pmsav7.rnr[M_REG_NS]; 3512 tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ 3513 *u32p = value; 3514 } 3515 3516 static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri, 3517 uint64_t value) 3518 { 3519 ARMCPU *cpu = env_archcpu(env); 3520 uint32_t nrgs = cpu->pmsav7_dregion; 3521 3522 if (value >= nrgs) { 3523 qemu_log_mask(LOG_GUEST_ERROR, 3524 "PMSAv7 RGNR write >= # supported regions, %" PRIu32 3525 " > %" PRIu32 "\n", (uint32_t)value, nrgs); 3526 return; 3527 } 3528 3529 raw_write(env, ri, value); 3530 } 3531 3532 static const ARMCPRegInfo pmsav7_cp_reginfo[] = { 3533 /* Reset for all these registers is handled in arm_cpu_reset(), 3534 * because the PMSAv7 is also used by M-profile CPUs, which do 3535 * not register cpregs but still need the state to be reset. 3536 */ 3537 { .name = "DRBAR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 0, 3538 .access = PL1_RW, .type = ARM_CP_NO_RAW, 3539 .fieldoffset = offsetof(CPUARMState, pmsav7.drbar), 3540 .readfn = pmsav7_read, .writefn = pmsav7_write, 3541 .resetfn = arm_cp_reset_ignore }, 3542 { .name = "DRSR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 2, 3543 .access = PL1_RW, .type = ARM_CP_NO_RAW, 3544 .fieldoffset = offsetof(CPUARMState, pmsav7.drsr), 3545 .readfn = pmsav7_read, .writefn = pmsav7_write, 3546 .resetfn = arm_cp_reset_ignore }, 3547 { .name = "DRACR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 4, 3548 .access = PL1_RW, .type = ARM_CP_NO_RAW, 3549 .fieldoffset = offsetof(CPUARMState, pmsav7.dracr), 3550 .readfn = pmsav7_read, .writefn = pmsav7_write, 3551 .resetfn = arm_cp_reset_ignore }, 3552 { .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0, 3553 .access = PL1_RW, 3554 .fieldoffset = offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]), 3555 .writefn = pmsav7_rgnr_write, 3556 .resetfn = arm_cp_reset_ignore }, 3557 }; 3558 3559 static const ARMCPRegInfo pmsav5_cp_reginfo[] = { 3560 { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, 3561 .access = PL1_RW, .type = ARM_CP_ALIAS, 3562 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap), 3563 .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, }, 3564 { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, 3565 .access = PL1_RW, .type = ARM_CP_ALIAS, 3566 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap), 3567 .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, }, 3568 { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2, 3569 .access = PL1_RW, 3570 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap), 3571 .resetvalue = 0, }, 3572 { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3, 3573 .access = PL1_RW, 3574 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap), 3575 .resetvalue = 0, }, 3576 { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, 3577 .access = PL1_RW, 3578 .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, }, 3579 { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1, 3580 .access = PL1_RW, 3581 .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, }, 3582 /* Protection region base and size registers */ 3583 { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, 3584 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, 3585 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) }, 3586 { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0, 3587 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, 3588 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) }, 3589 { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0, 3590 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, 3591 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) }, 3592 { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0, 3593 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, 3594 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) }, 3595 { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0, 3596 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, 3597 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) }, 3598 { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0, 3599 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, 3600 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) }, 3601 { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0, 3602 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, 3603 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) }, 3604 { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0, 3605 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, 3606 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) }, 3607 }; 3608 3609 static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, 3610 uint64_t value) 3611 { 3612 ARMCPU *cpu = env_archcpu(env); 3613 3614 if (!arm_feature(env, ARM_FEATURE_V8)) { 3615 if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) { 3616 /* 3617 * Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when 3618 * using Long-descriptor translation table format 3619 */ 3620 value &= ~((7 << 19) | (3 << 14) | (0xf << 3)); 3621 } else if (arm_feature(env, ARM_FEATURE_EL3)) { 3622 /* 3623 * In an implementation that includes the Security Extensions 3624 * TTBCR has additional fields PD0 [4] and PD1 [5] for 3625 * Short-descriptor translation table format. 3626 */ 3627 value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N; 3628 } else { 3629 value &= TTBCR_N; 3630 } 3631 } 3632 3633 if (arm_feature(env, ARM_FEATURE_LPAE)) { 3634 /* With LPAE the TTBCR could result in a change of ASID 3635 * via the TTBCR.A1 bit, so do a TLB flush. 3636 */ 3637 tlb_flush(CPU(cpu)); 3638 } 3639 raw_write(env, ri, value); 3640 } 3641 3642 static void vmsa_tcr_el12_write(CPUARMState *env, const ARMCPRegInfo *ri, 3643 uint64_t value) 3644 { 3645 ARMCPU *cpu = env_archcpu(env); 3646 3647 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */ 3648 tlb_flush(CPU(cpu)); 3649 raw_write(env, ri, value); 3650 } 3651 3652 static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, 3653 uint64_t value) 3654 { 3655 /* If the ASID changes (with a 64-bit write), we must flush the TLB. */ 3656 if (cpreg_field_is_64bit(ri) && 3657 extract64(raw_read(env, ri) ^ value, 48, 16) != 0) { 3658 ARMCPU *cpu = env_archcpu(env); 3659 tlb_flush(CPU(cpu)); 3660 } 3661 raw_write(env, ri, value); 3662 } 3663 3664 static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, 3665 uint64_t value) 3666 { 3667 /* 3668 * If we are running with E2&0 regime, then an ASID is active. 3669 * Flush if that might be changing. Note we're not checking 3670 * TCR_EL2.A1 to know if this is really the TTBRx_EL2 that 3671 * holds the active ASID, only checking the field that might. 3672 */ 3673 if (extract64(raw_read(env, ri) ^ value, 48, 16) && 3674 (arm_hcr_el2_eff(env) & HCR_E2H)) { 3675 uint16_t mask = ARMMMUIdxBit_E20_2 | 3676 ARMMMUIdxBit_E20_2_PAN | 3677 ARMMMUIdxBit_E20_0; 3678 3679 if (arm_is_secure_below_el3(env)) { 3680 mask >>= ARM_MMU_IDX_A_NS; 3681 } 3682 3683 tlb_flush_by_mmuidx(env_cpu(env), mask); 3684 } 3685 raw_write(env, ri, value); 3686 } 3687 3688 static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, 3689 uint64_t value) 3690 { 3691 ARMCPU *cpu = env_archcpu(env); 3692 CPUState *cs = CPU(cpu); 3693 3694 /* 3695 * A change in VMID to the stage2 page table (Stage2) invalidates 3696 * the combined stage 1&2 tlbs (EL10_1 and EL10_0). 3697 */ 3698 if (raw_read(env, ri) != value) { 3699 uint16_t mask = ARMMMUIdxBit_E10_1 | 3700 ARMMMUIdxBit_E10_1_PAN | 3701 ARMMMUIdxBit_E10_0; 3702 3703 if (arm_is_secure_below_el3(env)) { 3704 mask >>= ARM_MMU_IDX_A_NS; 3705 } 3706 3707 tlb_flush_by_mmuidx(cs, mask); 3708 raw_write(env, ri, value); 3709 } 3710 } 3711 3712 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = { 3713 { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, 3714 .access = PL1_RW, .accessfn = access_tvm_trvm, .type = ARM_CP_ALIAS, 3715 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s), 3716 offsetoflow32(CPUARMState, cp15.dfsr_ns) }, }, 3717 { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, 3718 .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0, 3719 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s), 3720 offsetoflow32(CPUARMState, cp15.ifsr_ns) } }, 3721 { .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0, 3722 .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0, 3723 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s), 3724 offsetof(CPUARMState, cp15.dfar_ns) } }, 3725 { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64, 3726 .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, 3727 .access = PL1_RW, .accessfn = access_tvm_trvm, 3728 .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]), 3729 .resetvalue = 0, }, 3730 }; 3731 3732 static const ARMCPRegInfo vmsa_cp_reginfo[] = { 3733 { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64, 3734 .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0, 3735 .access = PL1_RW, .accessfn = access_tvm_trvm, 3736 .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, }, 3737 { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH, 3738 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0, 3739 .access = PL1_RW, .accessfn = access_tvm_trvm, 3740 .writefn = vmsa_ttbr_write, .resetvalue = 0, 3741 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), 3742 offsetof(CPUARMState, cp15.ttbr0_ns) } }, 3743 { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH, 3744 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1, 3745 .access = PL1_RW, .accessfn = access_tvm_trvm, 3746 .writefn = vmsa_ttbr_write, .resetvalue = 0, 3747 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), 3748 offsetof(CPUARMState, cp15.ttbr1_ns) } }, 3749 { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64, 3750 .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, 3751 .access = PL1_RW, .accessfn = access_tvm_trvm, 3752 .writefn = vmsa_tcr_el12_write, 3753 .raw_writefn = raw_write, 3754 .resetvalue = 0, 3755 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) }, 3756 { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, 3757 .access = PL1_RW, .accessfn = access_tvm_trvm, 3758 .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write, 3759 .raw_writefn = raw_write, 3760 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]), 3761 offsetoflow32(CPUARMState, cp15.tcr_el[1])} }, 3762 }; 3763 3764 /* Note that unlike TTBCR, writing to TTBCR2 does not require flushing 3765 * qemu tlbs nor adjusting cached masks. 3766 */ 3767 static const ARMCPRegInfo ttbcr2_reginfo = { 3768 .name = "TTBCR2", .cp = 15, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 3, 3769 .access = PL1_RW, .accessfn = access_tvm_trvm, 3770 .type = ARM_CP_ALIAS, 3771 .bank_fieldoffsets = { 3772 offsetofhigh32(CPUARMState, cp15.tcr_el[3]), 3773 offsetofhigh32(CPUARMState, cp15.tcr_el[1]), 3774 }, 3775 }; 3776 3777 static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri, 3778 uint64_t value) 3779 { 3780 env->cp15.c15_ticonfig = value & 0xe7; 3781 /* The OS_TYPE bit in this register changes the reported CPUID! */ 3782 env->cp15.c0_cpuid = (value & (1 << 5)) ? 3783 ARM_CPUID_TI915T : ARM_CPUID_TI925T; 3784 } 3785 3786 static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri, 3787 uint64_t value) 3788 { 3789 env->cp15.c15_threadid = value & 0xffff; 3790 } 3791 3792 static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri, 3793 uint64_t value) 3794 { 3795 /* Wait-for-interrupt (deprecated) */ 3796 cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HALT); 3797 } 3798 3799 static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri, 3800 uint64_t value) 3801 { 3802 /* On OMAP there are registers indicating the max/min index of dcache lines 3803 * containing a dirty line; cache flush operations have to reset these. 3804 */ 3805 env->cp15.c15_i_max = 0x000; 3806 env->cp15.c15_i_min = 0xff0; 3807 } 3808 3809 static const ARMCPRegInfo omap_cp_reginfo[] = { 3810 { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY, 3811 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE, 3812 .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]), 3813 .resetvalue = 0, }, 3814 { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, 3815 .access = PL1_RW, .type = ARM_CP_NOP }, 3816 { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, 3817 .access = PL1_RW, 3818 .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0, 3819 .writefn = omap_ticonfig_write }, 3820 { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0, 3821 .access = PL1_RW, 3822 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, }, 3823 { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0, 3824 .access = PL1_RW, .resetvalue = 0xff0, 3825 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) }, 3826 { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0, 3827 .access = PL1_RW, 3828 .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0, 3829 .writefn = omap_threadid_write }, 3830 { .name = "TI925T_STATUS", .cp = 15, .crn = 15, 3831 .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW, 3832 .type = ARM_CP_NO_RAW, 3833 .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, }, 3834 /* TODO: Peripheral port remap register: 3835 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller 3836 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff), 3837 * when MMU is off. 3838 */ 3839 { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, 3840 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, 3841 .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW, 3842 .writefn = omap_cachemaint_write }, 3843 { .name = "C9", .cp = 15, .crn = 9, 3844 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, 3845 .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 }, 3846 }; 3847 3848 static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri, 3849 uint64_t value) 3850 { 3851 env->cp15.c15_cpar = value & 0x3fff; 3852 } 3853 3854 static const ARMCPRegInfo xscale_cp_reginfo[] = { 3855 { .name = "XSCALE_CPAR", 3856 .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW, 3857 .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0, 3858 .writefn = xscale_cpar_write, }, 3859 { .name = "XSCALE_AUXCR", 3860 .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW, 3861 .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr), 3862 .resetvalue = 0, }, 3863 /* XScale specific cache-lockdown: since we have no cache we NOP these 3864 * and hope the guest does not really rely on cache behaviour. 3865 */ 3866 { .name = "XSCALE_LOCK_ICACHE_LINE", 3867 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, 3868 .access = PL1_W, .type = ARM_CP_NOP }, 3869 { .name = "XSCALE_UNLOCK_ICACHE", 3870 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, 3871 .access = PL1_W, .type = ARM_CP_NOP }, 3872 { .name = "XSCALE_DCACHE_LOCK", 3873 .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0, 3874 .access = PL1_RW, .type = ARM_CP_NOP }, 3875 { .name = "XSCALE_UNLOCK_DCACHE", 3876 .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1, 3877 .access = PL1_W, .type = ARM_CP_NOP }, 3878 }; 3879 3880 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = { 3881 /* RAZ/WI the whole crn=15 space, when we don't have a more specific 3882 * implementation of this implementation-defined space. 3883 * Ideally this should eventually disappear in favour of actually 3884 * implementing the correct behaviour for all cores. 3885 */ 3886 { .name = "C15_IMPDEF", .cp = 15, .crn = 15, 3887 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, 3888 .access = PL1_RW, 3889 .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE, 3890 .resetvalue = 0 }, 3891 }; 3892 3893 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = { 3894 /* Cache status: RAZ because we have no cache so it's always clean */ 3895 { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6, 3896 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, 3897 .resetvalue = 0 }, 3898 }; 3899 3900 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = { 3901 /* We never have a block transfer operation in progress */ 3902 { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4, 3903 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, 3904 .resetvalue = 0 }, 3905 /* The cache ops themselves: these all NOP for QEMU */ 3906 { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0, 3907 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, 3908 { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0, 3909 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, 3910 { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0, 3911 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, 3912 { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1, 3913 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, 3914 { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2, 3915 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, 3916 { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0, 3917 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, 3918 }; 3919 3920 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = { 3921 /* The cache test-and-clean instructions always return (1 << 30) 3922 * to indicate that there are no dirty cache lines. 3923 */ 3924 { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3, 3925 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, 3926 .resetvalue = (1 << 30) }, 3927 { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3, 3928 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, 3929 .resetvalue = (1 << 30) }, 3930 }; 3931 3932 static const ARMCPRegInfo strongarm_cp_reginfo[] = { 3933 /* Ignore ReadBuffer accesses */ 3934 { .name = "C9_READBUFFER", .cp = 15, .crn = 9, 3935 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, 3936 .access = PL1_RW, .resetvalue = 0, 3937 .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW }, 3938 }; 3939 3940 static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri) 3941 { 3942 unsigned int cur_el = arm_current_el(env); 3943 3944 if (arm_is_el2_enabled(env) && cur_el == 1) { 3945 return env->cp15.vpidr_el2; 3946 } 3947 return raw_read(env, ri); 3948 } 3949 3950 static uint64_t mpidr_read_val(CPUARMState *env) 3951 { 3952 ARMCPU *cpu = env_archcpu(env); 3953 uint64_t mpidr = cpu->mp_affinity; 3954 3955 if (arm_feature(env, ARM_FEATURE_V7MP)) { 3956 mpidr |= (1U << 31); 3957 /* Cores which are uniprocessor (non-coherent) 3958 * but still implement the MP extensions set 3959 * bit 30. (For instance, Cortex-R5). 3960 */ 3961 if (cpu->mp_is_up) { 3962 mpidr |= (1u << 30); 3963 } 3964 } 3965 return mpidr; 3966 } 3967 3968 static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri) 3969 { 3970 unsigned int cur_el = arm_current_el(env); 3971 3972 if (arm_is_el2_enabled(env) && cur_el == 1) { 3973 return env->cp15.vmpidr_el2; 3974 } 3975 return mpidr_read_val(env); 3976 } 3977 3978 static const ARMCPRegInfo lpae_cp_reginfo[] = { 3979 /* NOP AMAIR0/1 */ 3980 { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH, 3981 .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0, 3982 .access = PL1_RW, .accessfn = access_tvm_trvm, 3983 .type = ARM_CP_CONST, .resetvalue = 0 }, 3984 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */ 3985 { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1, 3986 .access = PL1_RW, .accessfn = access_tvm_trvm, 3987 .type = ARM_CP_CONST, .resetvalue = 0 }, 3988 { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0, 3989 .access = PL1_RW, .type = ARM_CP_64BIT, .resetvalue = 0, 3990 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.par_s), 3991 offsetof(CPUARMState, cp15.par_ns)} }, 3992 { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0, 3993 .access = PL1_RW, .accessfn = access_tvm_trvm, 3994 .type = ARM_CP_64BIT | ARM_CP_ALIAS, 3995 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), 3996 offsetof(CPUARMState, cp15.ttbr0_ns) }, 3997 .writefn = vmsa_ttbr_write, }, 3998 { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1, 3999 .access = PL1_RW, .accessfn = access_tvm_trvm, 4000 .type = ARM_CP_64BIT | ARM_CP_ALIAS, 4001 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), 4002 offsetof(CPUARMState, cp15.ttbr1_ns) }, 4003 .writefn = vmsa_ttbr_write, }, 4004 }; 4005 4006 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri) 4007 { 4008 return vfp_get_fpcr(env); 4009 } 4010 4011 static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri, 4012 uint64_t value) 4013 { 4014 vfp_set_fpcr(env, value); 4015 } 4016 4017 static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri) 4018 { 4019 return vfp_get_fpsr(env); 4020 } 4021 4022 static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri, 4023 uint64_t value) 4024 { 4025 vfp_set_fpsr(env, value); 4026 } 4027 4028 static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri, 4029 bool isread) 4030 { 4031 if (arm_current_el(env) == 0 && !(arm_sctlr(env, 0) & SCTLR_UMA)) { 4032 return CP_ACCESS_TRAP; 4033 } 4034 return CP_ACCESS_OK; 4035 } 4036 4037 static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri, 4038 uint64_t value) 4039 { 4040 env->daif = value & PSTATE_DAIF; 4041 } 4042 4043 static uint64_t aa64_pan_read(CPUARMState *env, const ARMCPRegInfo *ri) 4044 { 4045 return env->pstate & PSTATE_PAN; 4046 } 4047 4048 static void aa64_pan_write(CPUARMState *env, const ARMCPRegInfo *ri, 4049 uint64_t value) 4050 { 4051 env->pstate = (env->pstate & ~PSTATE_PAN) | (value & PSTATE_PAN); 4052 } 4053 4054 static const ARMCPRegInfo pan_reginfo = { 4055 .name = "PAN", .state = ARM_CP_STATE_AA64, 4056 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 3, 4057 .type = ARM_CP_NO_RAW, .access = PL1_RW, 4058 .readfn = aa64_pan_read, .writefn = aa64_pan_write 4059 }; 4060 4061 static uint64_t aa64_uao_read(CPUARMState *env, const ARMCPRegInfo *ri) 4062 { 4063 return env->pstate & PSTATE_UAO; 4064 } 4065 4066 static void aa64_uao_write(CPUARMState *env, const ARMCPRegInfo *ri, 4067 uint64_t value) 4068 { 4069 env->pstate = (env->pstate & ~PSTATE_UAO) | (value & PSTATE_UAO); 4070 } 4071 4072 static const ARMCPRegInfo uao_reginfo = { 4073 .name = "UAO", .state = ARM_CP_STATE_AA64, 4074 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 4, 4075 .type = ARM_CP_NO_RAW, .access = PL1_RW, 4076 .readfn = aa64_uao_read, .writefn = aa64_uao_write 4077 }; 4078 4079 static uint64_t aa64_dit_read(CPUARMState *env, const ARMCPRegInfo *ri) 4080 { 4081 return env->pstate & PSTATE_DIT; 4082 } 4083 4084 static void aa64_dit_write(CPUARMState *env, const ARMCPRegInfo *ri, 4085 uint64_t value) 4086 { 4087 env->pstate = (env->pstate & ~PSTATE_DIT) | (value & PSTATE_DIT); 4088 } 4089 4090 static const ARMCPRegInfo dit_reginfo = { 4091 .name = "DIT", .state = ARM_CP_STATE_AA64, 4092 .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 5, 4093 .type = ARM_CP_NO_RAW, .access = PL0_RW, 4094 .readfn = aa64_dit_read, .writefn = aa64_dit_write 4095 }; 4096 4097 static uint64_t aa64_ssbs_read(CPUARMState *env, const ARMCPRegInfo *ri) 4098 { 4099 return env->pstate & PSTATE_SSBS; 4100 } 4101 4102 static void aa64_ssbs_write(CPUARMState *env, const ARMCPRegInfo *ri, 4103 uint64_t value) 4104 { 4105 env->pstate = (env->pstate & ~PSTATE_SSBS) | (value & PSTATE_SSBS); 4106 } 4107 4108 static const ARMCPRegInfo ssbs_reginfo = { 4109 .name = "SSBS", .state = ARM_CP_STATE_AA64, 4110 .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 6, 4111 .type = ARM_CP_NO_RAW, .access = PL0_RW, 4112 .readfn = aa64_ssbs_read, .writefn = aa64_ssbs_write 4113 }; 4114 4115 static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env, 4116 const ARMCPRegInfo *ri, 4117 bool isread) 4118 { 4119 /* Cache invalidate/clean to Point of Coherency or Persistence... */ 4120 switch (arm_current_el(env)) { 4121 case 0: 4122 /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */ 4123 if (!(arm_sctlr(env, 0) & SCTLR_UCI)) { 4124 return CP_ACCESS_TRAP; 4125 } 4126 /* fall through */ 4127 case 1: 4128 /* ... EL1 must trap to EL2 if HCR_EL2.TPCP is set. */ 4129 if (arm_hcr_el2_eff(env) & HCR_TPCP) { 4130 return CP_ACCESS_TRAP_EL2; 4131 } 4132 break; 4133 } 4134 return CP_ACCESS_OK; 4135 } 4136 4137 static CPAccessResult aa64_cacheop_pou_access(CPUARMState *env, 4138 const ARMCPRegInfo *ri, 4139 bool isread) 4140 { 4141 /* Cache invalidate/clean to Point of Unification... */ 4142 switch (arm_current_el(env)) { 4143 case 0: 4144 /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */ 4145 if (!(arm_sctlr(env, 0) & SCTLR_UCI)) { 4146 return CP_ACCESS_TRAP; 4147 } 4148 /* fall through */ 4149 case 1: 4150 /* ... EL1 must trap to EL2 if HCR_EL2.TPU is set. */ 4151 if (arm_hcr_el2_eff(env) & HCR_TPU) { 4152 return CP_ACCESS_TRAP_EL2; 4153 } 4154 break; 4155 } 4156 return CP_ACCESS_OK; 4157 } 4158 4159 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions 4160 * Page D4-1736 (DDI0487A.b) 4161 */ 4162 4163 static int vae1_tlbmask(CPUARMState *env) 4164 { 4165 uint64_t hcr = arm_hcr_el2_eff(env); 4166 uint16_t mask; 4167 4168 if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { 4169 mask = ARMMMUIdxBit_E20_2 | 4170 ARMMMUIdxBit_E20_2_PAN | 4171 ARMMMUIdxBit_E20_0; 4172 } else { 4173 mask = ARMMMUIdxBit_E10_1 | 4174 ARMMMUIdxBit_E10_1_PAN | 4175 ARMMMUIdxBit_E10_0; 4176 } 4177 4178 if (arm_is_secure_below_el3(env)) { 4179 mask >>= ARM_MMU_IDX_A_NS; 4180 } 4181 4182 return mask; 4183 } 4184 4185 /* Return 56 if TBI is enabled, 64 otherwise. */ 4186 static int tlbbits_for_regime(CPUARMState *env, ARMMMUIdx mmu_idx, 4187 uint64_t addr) 4188 { 4189 uint64_t tcr = regime_tcr(env, mmu_idx); 4190 int tbi = aa64_va_parameter_tbi(tcr, mmu_idx); 4191 int select = extract64(addr, 55, 1); 4192 4193 return (tbi >> select) & 1 ? 56 : 64; 4194 } 4195 4196 static int vae1_tlbbits(CPUARMState *env, uint64_t addr) 4197 { 4198 uint64_t hcr = arm_hcr_el2_eff(env); 4199 ARMMMUIdx mmu_idx; 4200 4201 /* Only the regime of the mmu_idx below is significant. */ 4202 if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { 4203 mmu_idx = ARMMMUIdx_E20_0; 4204 } else { 4205 mmu_idx = ARMMMUIdx_E10_0; 4206 } 4207 4208 if (arm_is_secure_below_el3(env)) { 4209 mmu_idx &= ~ARM_MMU_IDX_A_NS; 4210 } 4211 4212 return tlbbits_for_regime(env, mmu_idx, addr); 4213 } 4214 4215 static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, 4216 uint64_t value) 4217 { 4218 CPUState *cs = env_cpu(env); 4219 int mask = vae1_tlbmask(env); 4220 4221 tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); 4222 } 4223 4224 static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri, 4225 uint64_t value) 4226 { 4227 CPUState *cs = env_cpu(env); 4228 int mask = vae1_tlbmask(env); 4229 4230 if (tlb_force_broadcast(env)) { 4231 tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); 4232 } else { 4233 tlb_flush_by_mmuidx(cs, mask); 4234 } 4235 } 4236 4237 static int alle1_tlbmask(CPUARMState *env) 4238 { 4239 /* 4240 * Note that the 'ALL' scope must invalidate both stage 1 and 4241 * stage 2 translations, whereas most other scopes only invalidate 4242 * stage 1 translations. 4243 */ 4244 if (arm_is_secure_below_el3(env)) { 4245 return ARMMMUIdxBit_SE10_1 | 4246 ARMMMUIdxBit_SE10_1_PAN | 4247 ARMMMUIdxBit_SE10_0; 4248 } else { 4249 return ARMMMUIdxBit_E10_1 | 4250 ARMMMUIdxBit_E10_1_PAN | 4251 ARMMMUIdxBit_E10_0; 4252 } 4253 } 4254 4255 static int e2_tlbmask(CPUARMState *env) 4256 { 4257 if (arm_is_secure_below_el3(env)) { 4258 return ARMMMUIdxBit_SE20_0 | 4259 ARMMMUIdxBit_SE20_2 | 4260 ARMMMUIdxBit_SE20_2_PAN | 4261 ARMMMUIdxBit_SE2; 4262 } else { 4263 return ARMMMUIdxBit_E20_0 | 4264 ARMMMUIdxBit_E20_2 | 4265 ARMMMUIdxBit_E20_2_PAN | 4266 ARMMMUIdxBit_E2; 4267 } 4268 } 4269 4270 static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, 4271 uint64_t value) 4272 { 4273 CPUState *cs = env_cpu(env); 4274 int mask = alle1_tlbmask(env); 4275 4276 tlb_flush_by_mmuidx(cs, mask); 4277 } 4278 4279 static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri, 4280 uint64_t value) 4281 { 4282 CPUState *cs = env_cpu(env); 4283 int mask = e2_tlbmask(env); 4284 4285 tlb_flush_by_mmuidx(cs, mask); 4286 } 4287 4288 static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri, 4289 uint64_t value) 4290 { 4291 ARMCPU *cpu = env_archcpu(env); 4292 CPUState *cs = CPU(cpu); 4293 4294 tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_SE3); 4295 } 4296 4297 static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, 4298 uint64_t value) 4299 { 4300 CPUState *cs = env_cpu(env); 4301 int mask = alle1_tlbmask(env); 4302 4303 tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); 4304 } 4305 4306 static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri, 4307 uint64_t value) 4308 { 4309 CPUState *cs = env_cpu(env); 4310 int mask = e2_tlbmask(env); 4311 4312 tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); 4313 } 4314 4315 static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri, 4316 uint64_t value) 4317 { 4318 CPUState *cs = env_cpu(env); 4319 4320 tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_SE3); 4321 } 4322 4323 static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri, 4324 uint64_t value) 4325 { 4326 /* Invalidate by VA, EL2 4327 * Currently handles both VAE2 and VALE2, since we don't support 4328 * flush-last-level-only. 4329 */ 4330 CPUState *cs = env_cpu(env); 4331 int mask = e2_tlbmask(env); 4332 uint64_t pageaddr = sextract64(value << 12, 0, 56); 4333 4334 tlb_flush_page_by_mmuidx(cs, pageaddr, mask); 4335 } 4336 4337 static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri, 4338 uint64_t value) 4339 { 4340 /* Invalidate by VA, EL3 4341 * Currently handles both VAE3 and VALE3, since we don't support 4342 * flush-last-level-only. 4343 */ 4344 ARMCPU *cpu = env_archcpu(env); 4345 CPUState *cs = CPU(cpu); 4346 uint64_t pageaddr = sextract64(value << 12, 0, 56); 4347 4348 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_SE3); 4349 } 4350 4351 static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri, 4352 uint64_t value) 4353 { 4354 CPUState *cs = env_cpu(env); 4355 int mask = vae1_tlbmask(env); 4356 uint64_t pageaddr = sextract64(value << 12, 0, 56); 4357 int bits = vae1_tlbbits(env, pageaddr); 4358 4359 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits); 4360 } 4361 4362 static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri, 4363 uint64_t value) 4364 { 4365 /* Invalidate by VA, EL1&0 (AArch64 version). 4366 * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1, 4367 * since we don't support flush-for-specific-ASID-only or 4368 * flush-last-level-only. 4369 */ 4370 CPUState *cs = env_cpu(env); 4371 int mask = vae1_tlbmask(env); 4372 uint64_t pageaddr = sextract64(value << 12, 0, 56); 4373 int bits = vae1_tlbbits(env, pageaddr); 4374 4375 if (tlb_force_broadcast(env)) { 4376 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits); 4377 } else { 4378 tlb_flush_page_bits_by_mmuidx(cs, pageaddr, mask, bits); 4379 } 4380 } 4381 4382 static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri, 4383 uint64_t value) 4384 { 4385 CPUState *cs = env_cpu(env); 4386 uint64_t pageaddr = sextract64(value << 12, 0, 56); 4387 bool secure = arm_is_secure_below_el3(env); 4388 int mask = secure ? ARMMMUIdxBit_SE2 : ARMMMUIdxBit_E2; 4389 int bits = tlbbits_for_regime(env, secure ? ARMMMUIdx_SE2 : ARMMMUIdx_E2, 4390 pageaddr); 4391 4392 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits); 4393 } 4394 4395 static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri, 4396 uint64_t value) 4397 { 4398 CPUState *cs = env_cpu(env); 4399 uint64_t pageaddr = sextract64(value << 12, 0, 56); 4400 int bits = tlbbits_for_regime(env, ARMMMUIdx_SE3, pageaddr); 4401 4402 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, 4403 ARMMMUIdxBit_SE3, bits); 4404 } 4405 4406 #ifdef TARGET_AARCH64 4407 typedef struct { 4408 uint64_t base; 4409 uint64_t length; 4410 } TLBIRange; 4411 4412 static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx, 4413 uint64_t value) 4414 { 4415 unsigned int page_size_granule, page_shift, num, scale, exponent; 4416 /* Extract one bit to represent the va selector in use. */ 4417 uint64_t select = sextract64(value, 36, 1); 4418 ARMVAParameters param = aa64_va_parameters(env, select, mmuidx, true); 4419 TLBIRange ret = { }; 4420 4421 page_size_granule = extract64(value, 46, 2); 4422 4423 /* The granule encoded in value must match the granule in use. */ 4424 if (page_size_granule != (param.using64k ? 3 : param.using16k ? 2 : 1)) { 4425 qemu_log_mask(LOG_GUEST_ERROR, "Invalid tlbi page size granule %d\n", 4426 page_size_granule); 4427 return ret; 4428 } 4429 4430 page_shift = (page_size_granule - 1) * 2 + 12; 4431 num = extract64(value, 39, 5); 4432 scale = extract64(value, 44, 2); 4433 exponent = (5 * scale) + 1; 4434 4435 ret.length = (num + 1) << (exponent + page_shift); 4436 4437 if (param.select) { 4438 ret.base = sextract64(value, 0, 37); 4439 } else { 4440 ret.base = extract64(value, 0, 37); 4441 } 4442 if (param.ds) { 4443 /* 4444 * With DS=1, BaseADDR is always shifted 16 so that it is able 4445 * to address all 52 va bits. The input address is perforce 4446 * aligned on a 64k boundary regardless of translation granule. 4447 */ 4448 page_shift = 16; 4449 } 4450 ret.base <<= page_shift; 4451 4452 return ret; 4453 } 4454 4455 static void do_rvae_write(CPUARMState *env, uint64_t value, 4456 int idxmap, bool synced) 4457 { 4458 ARMMMUIdx one_idx = ARM_MMU_IDX_A | ctz32(idxmap); 4459 TLBIRange range; 4460 int bits; 4461 4462 range = tlbi_aa64_get_range(env, one_idx, value); 4463 bits = tlbbits_for_regime(env, one_idx, range.base); 4464 4465 if (synced) { 4466 tlb_flush_range_by_mmuidx_all_cpus_synced(env_cpu(env), 4467 range.base, 4468 range.length, 4469 idxmap, 4470 bits); 4471 } else { 4472 tlb_flush_range_by_mmuidx(env_cpu(env), range.base, 4473 range.length, idxmap, bits); 4474 } 4475 } 4476 4477 static void tlbi_aa64_rvae1_write(CPUARMState *env, 4478 const ARMCPRegInfo *ri, 4479 uint64_t value) 4480 { 4481 /* 4482 * Invalidate by VA range, EL1&0. 4483 * Currently handles all of RVAE1, RVAAE1, RVAALE1 and RVALE1, 4484 * since we don't support flush-for-specific-ASID-only or 4485 * flush-last-level-only. 4486 */ 4487 4488 do_rvae_write(env, value, vae1_tlbmask(env), 4489 tlb_force_broadcast(env)); 4490 } 4491 4492 static void tlbi_aa64_rvae1is_write(CPUARMState *env, 4493 const ARMCPRegInfo *ri, 4494 uint64_t value) 4495 { 4496 /* 4497 * Invalidate by VA range, Inner/Outer Shareable EL1&0. 4498 * Currently handles all of RVAE1IS, RVAE1OS, RVAAE1IS, RVAAE1OS, 4499 * RVAALE1IS, RVAALE1OS, RVALE1IS and RVALE1OS, since we don't support 4500 * flush-for-specific-ASID-only, flush-last-level-only or inner/outer 4501 * shareable specific flushes. 4502 */ 4503 4504 do_rvae_write(env, value, vae1_tlbmask(env), true); 4505 } 4506 4507 static int vae2_tlbmask(CPUARMState *env) 4508 { 4509 return (arm_is_secure_below_el3(env) 4510 ? ARMMMUIdxBit_SE2 : ARMMMUIdxBit_E2); 4511 } 4512 4513 static void tlbi_aa64_rvae2_write(CPUARMState *env, 4514 const ARMCPRegInfo *ri, 4515 uint64_t value) 4516 { 4517 /* 4518 * Invalidate by VA range, EL2. 4519 * Currently handles all of RVAE2 and RVALE2, 4520 * since we don't support flush-for-specific-ASID-only or 4521 * flush-last-level-only. 4522 */ 4523 4524 do_rvae_write(env, value, vae2_tlbmask(env), 4525 tlb_force_broadcast(env)); 4526 4527 4528 } 4529 4530 static void tlbi_aa64_rvae2is_write(CPUARMState *env, 4531 const ARMCPRegInfo *ri, 4532 uint64_t value) 4533 { 4534 /* 4535 * Invalidate by VA range, Inner/Outer Shareable, EL2. 4536 * Currently handles all of RVAE2IS, RVAE2OS, RVALE2IS and RVALE2OS, 4537 * since we don't support flush-for-specific-ASID-only, 4538 * flush-last-level-only or inner/outer shareable specific flushes. 4539 */ 4540 4541 do_rvae_write(env, value, vae2_tlbmask(env), true); 4542 4543 } 4544 4545 static void tlbi_aa64_rvae3_write(CPUARMState *env, 4546 const ARMCPRegInfo *ri, 4547 uint64_t value) 4548 { 4549 /* 4550 * Invalidate by VA range, EL3. 4551 * Currently handles all of RVAE3 and RVALE3, 4552 * since we don't support flush-for-specific-ASID-only or 4553 * flush-last-level-only. 4554 */ 4555 4556 do_rvae_write(env, value, ARMMMUIdxBit_SE3, 4557 tlb_force_broadcast(env)); 4558 } 4559 4560 static void tlbi_aa64_rvae3is_write(CPUARMState *env, 4561 const ARMCPRegInfo *ri, 4562 uint64_t value) 4563 { 4564 /* 4565 * Invalidate by VA range, EL3, Inner/Outer Shareable. 4566 * Currently handles all of RVAE3IS, RVAE3OS, RVALE3IS and RVALE3OS, 4567 * since we don't support flush-for-specific-ASID-only, 4568 * flush-last-level-only or inner/outer specific flushes. 4569 */ 4570 4571 do_rvae_write(env, value, ARMMMUIdxBit_SE3, true); 4572 } 4573 #endif 4574 4575 static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri, 4576 bool isread) 4577 { 4578 int cur_el = arm_current_el(env); 4579 4580 if (cur_el < 2) { 4581 uint64_t hcr = arm_hcr_el2_eff(env); 4582 4583 if (cur_el == 0) { 4584 if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { 4585 if (!(env->cp15.sctlr_el[2] & SCTLR_DZE)) { 4586 return CP_ACCESS_TRAP_EL2; 4587 } 4588 } else { 4589 if (!(env->cp15.sctlr_el[1] & SCTLR_DZE)) { 4590 return CP_ACCESS_TRAP; 4591 } 4592 if (hcr & HCR_TDZ) { 4593 return CP_ACCESS_TRAP_EL2; 4594 } 4595 } 4596 } else if (hcr & HCR_TDZ) { 4597 return CP_ACCESS_TRAP_EL2; 4598 } 4599 } 4600 return CP_ACCESS_OK; 4601 } 4602 4603 static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri) 4604 { 4605 ARMCPU *cpu = env_archcpu(env); 4606 int dzp_bit = 1 << 4; 4607 4608 /* DZP indicates whether DC ZVA access is allowed */ 4609 if (aa64_zva_access(env, NULL, false) == CP_ACCESS_OK) { 4610 dzp_bit = 0; 4611 } 4612 return cpu->dcz_blocksize | dzp_bit; 4613 } 4614 4615 static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri, 4616 bool isread) 4617 { 4618 if (!(env->pstate & PSTATE_SP)) { 4619 /* Access to SP_EL0 is undefined if it's being used as 4620 * the stack pointer. 4621 */ 4622 return CP_ACCESS_TRAP_UNCATEGORIZED; 4623 } 4624 return CP_ACCESS_OK; 4625 } 4626 4627 static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri) 4628 { 4629 return env->pstate & PSTATE_SP; 4630 } 4631 4632 static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) 4633 { 4634 update_spsel(env, val); 4635 } 4636 4637 static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, 4638 uint64_t value) 4639 { 4640 ARMCPU *cpu = env_archcpu(env); 4641 4642 if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) { 4643 /* M bit is RAZ/WI for PMSA with no MPU implemented */ 4644 value &= ~SCTLR_M; 4645 } 4646 4647 /* ??? Lots of these bits are not implemented. */ 4648 4649 if (ri->state == ARM_CP_STATE_AA64 && !cpu_isar_feature(aa64_mte, cpu)) { 4650 if (ri->opc1 == 6) { /* SCTLR_EL3 */ 4651 value &= ~(SCTLR_ITFSB | SCTLR_TCF | SCTLR_ATA); 4652 } else { 4653 value &= ~(SCTLR_ITFSB | SCTLR_TCF0 | SCTLR_TCF | 4654 SCTLR_ATA0 | SCTLR_ATA); 4655 } 4656 } 4657 4658 if (raw_read(env, ri) == value) { 4659 /* Skip the TLB flush if nothing actually changed; Linux likes 4660 * to do a lot of pointless SCTLR writes. 4661 */ 4662 return; 4663 } 4664 4665 raw_write(env, ri, value); 4666 4667 /* This may enable/disable the MMU, so do a TLB flush. */ 4668 tlb_flush(CPU(cpu)); 4669 4670 if (ri->type & ARM_CP_SUPPRESS_TB_END) { 4671 /* 4672 * Normally we would always end the TB on an SCTLR write; see the 4673 * comment in ARMCPRegInfo sctlr initialization below for why Xscale 4674 * is special. Setting ARM_CP_SUPPRESS_TB_END also stops the rebuild 4675 * of hflags from the translator, so do it here. 4676 */ 4677 arm_rebuild_hflags(env); 4678 } 4679 } 4680 4681 static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri, 4682 uint64_t value) 4683 { 4684 env->cp15.mdcr_el3 = value & SDCR_VALID_MASK; 4685 } 4686 4687 static const ARMCPRegInfo v8_cp_reginfo[] = { 4688 /* Minimal set of EL0-visible registers. This will need to be expanded 4689 * significantly for system emulation of AArch64 CPUs. 4690 */ 4691 { .name = "NZCV", .state = ARM_CP_STATE_AA64, 4692 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2, 4693 .access = PL0_RW, .type = ARM_CP_NZCV }, 4694 { .name = "DAIF", .state = ARM_CP_STATE_AA64, 4695 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2, 4696 .type = ARM_CP_NO_RAW, 4697 .access = PL0_RW, .accessfn = aa64_daif_access, 4698 .fieldoffset = offsetof(CPUARMState, daif), 4699 .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore }, 4700 { .name = "FPCR", .state = ARM_CP_STATE_AA64, 4701 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4, 4702 .access = PL0_RW, .type = ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END, 4703 .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write }, 4704 { .name = "FPSR", .state = ARM_CP_STATE_AA64, 4705 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4, 4706 .access = PL0_RW, .type = ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END, 4707 .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write }, 4708 { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64, 4709 .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0, 4710 .access = PL0_R, .type = ARM_CP_NO_RAW, 4711 .readfn = aa64_dczid_read }, 4712 { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64, 4713 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1, 4714 .access = PL0_W, .type = ARM_CP_DC_ZVA, 4715 #ifndef CONFIG_USER_ONLY 4716 /* Avoid overhead of an access check that always passes in user-mode */ 4717 .accessfn = aa64_zva_access, 4718 #endif 4719 }, 4720 { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64, 4721 .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2, 4722 .access = PL1_R, .type = ARM_CP_CURRENTEL }, 4723 /* Cache ops: all NOPs since we don't emulate caches */ 4724 { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64, 4725 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, 4726 .access = PL1_W, .type = ARM_CP_NOP, 4727 .accessfn = aa64_cacheop_pou_access }, 4728 { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64, 4729 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, 4730 .access = PL1_W, .type = ARM_CP_NOP, 4731 .accessfn = aa64_cacheop_pou_access }, 4732 { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64, 4733 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1, 4734 .access = PL0_W, .type = ARM_CP_NOP, 4735 .accessfn = aa64_cacheop_pou_access }, 4736 { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64, 4737 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, 4738 .access = PL1_W, .accessfn = aa64_cacheop_poc_access, 4739 .type = ARM_CP_NOP }, 4740 { .name = "DC_ISW", .state = ARM_CP_STATE_AA64, 4741 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, 4742 .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP }, 4743 { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64, 4744 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1, 4745 .access = PL0_W, .type = ARM_CP_NOP, 4746 .accessfn = aa64_cacheop_poc_access }, 4747 { .name = "DC_CSW", .state = ARM_CP_STATE_AA64, 4748 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, 4749 .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP }, 4750 { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64, 4751 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1, 4752 .access = PL0_W, .type = ARM_CP_NOP, 4753 .accessfn = aa64_cacheop_pou_access }, 4754 { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64, 4755 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1, 4756 .access = PL0_W, .type = ARM_CP_NOP, 4757 .accessfn = aa64_cacheop_poc_access }, 4758 { .name = "DC_CISW", .state = ARM_CP_STATE_AA64, 4759 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, 4760 .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP }, 4761 /* TLBI operations */ 4762 { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64, 4763 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, 4764 .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, 4765 .writefn = tlbi_aa64_vmalle1is_write }, 4766 { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64, 4767 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, 4768 .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, 4769 .writefn = tlbi_aa64_vae1is_write }, 4770 { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64, 4771 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, 4772 .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, 4773 .writefn = tlbi_aa64_vmalle1is_write }, 4774 { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64, 4775 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, 4776 .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, 4777 .writefn = tlbi_aa64_vae1is_write }, 4778 { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64, 4779 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, 4780 .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, 4781 .writefn = tlbi_aa64_vae1is_write }, 4782 { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64, 4783 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, 4784 .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, 4785 .writefn = tlbi_aa64_vae1is_write }, 4786 { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64, 4787 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, 4788 .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, 4789 .writefn = tlbi_aa64_vmalle1_write }, 4790 { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64, 4791 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, 4792 .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, 4793 .writefn = tlbi_aa64_vae1_write }, 4794 { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64, 4795 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, 4796 .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, 4797 .writefn = tlbi_aa64_vmalle1_write }, 4798 { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64, 4799 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, 4800 .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, 4801 .writefn = tlbi_aa64_vae1_write }, 4802 { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64, 4803 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, 4804 .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, 4805 .writefn = tlbi_aa64_vae1_write }, 4806 { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64, 4807 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, 4808 .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, 4809 .writefn = tlbi_aa64_vae1_write }, 4810 { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64, 4811 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1, 4812 .access = PL2_W, .type = ARM_CP_NOP }, 4813 { .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64, 4814 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5, 4815 .access = PL2_W, .type = ARM_CP_NOP }, 4816 { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64, 4817 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4, 4818 .access = PL2_W, .type = ARM_CP_NO_RAW, 4819 .writefn = tlbi_aa64_alle1is_write }, 4820 { .name = "TLBI_VMALLS12E1IS", .state = ARM_CP_STATE_AA64, 4821 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 6, 4822 .access = PL2_W, .type = ARM_CP_NO_RAW, 4823 .writefn = tlbi_aa64_alle1is_write }, 4824 { .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64, 4825 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1, 4826 .access = PL2_W, .type = ARM_CP_NOP }, 4827 { .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64, 4828 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5, 4829 .access = PL2_W, .type = ARM_CP_NOP }, 4830 { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64, 4831 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4, 4832 .access = PL2_W, .type = ARM_CP_NO_RAW, 4833 .writefn = tlbi_aa64_alle1_write }, 4834 { .name = "TLBI_VMALLS12E1", .state = ARM_CP_STATE_AA64, 4835 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6, 4836 .access = PL2_W, .type = ARM_CP_NO_RAW, 4837 .writefn = tlbi_aa64_alle1is_write }, 4838 #ifndef CONFIG_USER_ONLY 4839 /* 64 bit address translation operations */ 4840 { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64, 4841 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0, 4842 .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, 4843 .writefn = ats_write64 }, 4844 { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64, 4845 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1, 4846 .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, 4847 .writefn = ats_write64 }, 4848 { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64, 4849 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2, 4850 .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, 4851 .writefn = ats_write64 }, 4852 { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64, 4853 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3, 4854 .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, 4855 .writefn = ats_write64 }, 4856 { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64, 4857 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4, 4858 .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, 4859 .writefn = ats_write64 }, 4860 { .name = "AT_S12E1W", .state = ARM_CP_STATE_AA64, 4861 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 5, 4862 .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, 4863 .writefn = ats_write64 }, 4864 { .name = "AT_S12E0R", .state = ARM_CP_STATE_AA64, 4865 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 6, 4866 .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, 4867 .writefn = ats_write64 }, 4868 { .name = "AT_S12E0W", .state = ARM_CP_STATE_AA64, 4869 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 7, 4870 .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, 4871 .writefn = ats_write64 }, 4872 /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */ 4873 { .name = "AT_S1E3R", .state = ARM_CP_STATE_AA64, 4874 .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 0, 4875 .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, 4876 .writefn = ats_write64 }, 4877 { .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64, 4878 .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1, 4879 .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, 4880 .writefn = ats_write64 }, 4881 { .name = "PAR_EL1", .state = ARM_CP_STATE_AA64, 4882 .type = ARM_CP_ALIAS, 4883 .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0, 4884 .access = PL1_RW, .resetvalue = 0, 4885 .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]), 4886 .writefn = par_write }, 4887 #endif 4888 /* TLB invalidate last level of translation table walk */ 4889 { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, 4890 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, 4891 .writefn = tlbimva_is_write }, 4892 { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, 4893 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, 4894 .writefn = tlbimvaa_is_write }, 4895 { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, 4896 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, 4897 .writefn = tlbimva_write }, 4898 { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, 4899 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, 4900 .writefn = tlbimvaa_write }, 4901 { .name = "TLBIMVALH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5, 4902 .type = ARM_CP_NO_RAW, .access = PL2_W, 4903 .writefn = tlbimva_hyp_write }, 4904 { .name = "TLBIMVALHIS", 4905 .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5, 4906 .type = ARM_CP_NO_RAW, .access = PL2_W, 4907 .writefn = tlbimva_hyp_is_write }, 4908 { .name = "TLBIIPAS2", 4909 .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1, 4910 .type = ARM_CP_NOP, .access = PL2_W }, 4911 { .name = "TLBIIPAS2IS", 4912 .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1, 4913 .type = ARM_CP_NOP, .access = PL2_W }, 4914 { .name = "TLBIIPAS2L", 4915 .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5, 4916 .type = ARM_CP_NOP, .access = PL2_W }, 4917 { .name = "TLBIIPAS2LIS", 4918 .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5, 4919 .type = ARM_CP_NOP, .access = PL2_W }, 4920 /* 32 bit cache operations */ 4921 { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, 4922 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access }, 4923 { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6, 4924 .type = ARM_CP_NOP, .access = PL1_W }, 4925 { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, 4926 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access }, 4927 { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1, 4928 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access }, 4929 { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6, 4930 .type = ARM_CP_NOP, .access = PL1_W }, 4931 { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7, 4932 .type = ARM_CP_NOP, .access = PL1_W }, 4933 { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, 4934 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_poc_access }, 4935 { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, 4936 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, 4937 { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1, 4938 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_poc_access }, 4939 { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, 4940 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, 4941 { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1, 4942 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access }, 4943 { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1, 4944 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_poc_access }, 4945 { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, 4946 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, 4947 /* MMU Domain access control / MPU write buffer control */ 4948 { .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0, 4949 .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0, 4950 .writefn = dacr_write, .raw_writefn = raw_write, 4951 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s), 4952 offsetoflow32(CPUARMState, cp15.dacr_ns) } }, 4953 { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64, 4954 .type = ARM_CP_ALIAS, 4955 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1, 4956 .access = PL1_RW, 4957 .fieldoffset = offsetof(CPUARMState, elr_el[1]) }, 4958 { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64, 4959 .type = ARM_CP_ALIAS, 4960 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0, 4961 .access = PL1_RW, 4962 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_SVC]) }, 4963 /* We rely on the access checks not allowing the guest to write to the 4964 * state field when SPSel indicates that it's being used as the stack 4965 * pointer. 4966 */ 4967 { .name = "SP_EL0", .state = ARM_CP_STATE_AA64, 4968 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0, 4969 .access = PL1_RW, .accessfn = sp_el0_access, 4970 .type = ARM_CP_ALIAS, 4971 .fieldoffset = offsetof(CPUARMState, sp_el[0]) }, 4972 { .name = "SP_EL1", .state = ARM_CP_STATE_AA64, 4973 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0, 4974 .access = PL2_RW, .type = ARM_CP_ALIAS, 4975 .fieldoffset = offsetof(CPUARMState, sp_el[1]) }, 4976 { .name = "SPSel", .state = ARM_CP_STATE_AA64, 4977 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0, 4978 .type = ARM_CP_NO_RAW, 4979 .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write }, 4980 { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64, 4981 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0, 4982 .access = PL2_RW, 4983 .type = ARM_CP_ALIAS | ARM_CP_FPU | ARM_CP_EL3_NO_EL2_KEEP, 4984 .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]) }, 4985 { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64, 4986 .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0, 4987 .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP, 4988 .writefn = dacr_write, .raw_writefn = raw_write, 4989 .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) }, 4990 { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64, 4991 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1, 4992 .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP, 4993 .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) }, 4994 { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64, 4995 .type = ARM_CP_ALIAS, 4996 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 0, 4997 .access = PL2_RW, 4998 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_IRQ]) }, 4999 { .name = "SPSR_ABT", .state = ARM_CP_STATE_AA64, 5000 .type = ARM_CP_ALIAS, 5001 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 1, 5002 .access = PL2_RW, 5003 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_ABT]) }, 5004 { .name = "SPSR_UND", .state = ARM_CP_STATE_AA64, 5005 .type = ARM_CP_ALIAS, 5006 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 2, 5007 .access = PL2_RW, 5008 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_UND]) }, 5009 { .name = "SPSR_FIQ", .state = ARM_CP_STATE_AA64, 5010 .type = ARM_CP_ALIAS, 5011 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 3, 5012 .access = PL2_RW, 5013 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) }, 5014 { .name = "MDCR_EL3", .state = ARM_CP_STATE_AA64, 5015 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1, 5016 .resetvalue = 0, 5017 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) }, 5018 { .name = "SDCR", .type = ARM_CP_ALIAS, 5019 .cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1, 5020 .access = PL1_RW, .accessfn = access_trap_aa32s_el1, 5021 .writefn = sdcr_write, 5022 .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) }, 5023 }; 5024 5025 static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) 5026 { 5027 ARMCPU *cpu = env_archcpu(env); 5028 5029 if (arm_feature(env, ARM_FEATURE_V8)) { 5030 valid_mask |= MAKE_64BIT_MASK(0, 34); /* ARMv8.0 */ 5031 } else { 5032 valid_mask |= MAKE_64BIT_MASK(0, 28); /* ARMv7VE */ 5033 } 5034 5035 if (arm_feature(env, ARM_FEATURE_EL3)) { 5036 valid_mask &= ~HCR_HCD; 5037 } else if (cpu->psci_conduit != QEMU_PSCI_CONDUIT_SMC) { 5038 /* Architecturally HCR.TSC is RES0 if EL3 is not implemented. 5039 * However, if we're using the SMC PSCI conduit then QEMU is 5040 * effectively acting like EL3 firmware and so the guest at 5041 * EL2 should retain the ability to prevent EL1 from being 5042 * able to make SMC calls into the ersatz firmware, so in 5043 * that case HCR.TSC should be read/write. 5044 */ 5045 valid_mask &= ~HCR_TSC; 5046 } 5047 5048 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 5049 if (cpu_isar_feature(aa64_vh, cpu)) { 5050 valid_mask |= HCR_E2H; 5051 } 5052 if (cpu_isar_feature(aa64_ras, cpu)) { 5053 valid_mask |= HCR_TERR | HCR_TEA; 5054 } 5055 if (cpu_isar_feature(aa64_lor, cpu)) { 5056 valid_mask |= HCR_TLOR; 5057 } 5058 if (cpu_isar_feature(aa64_pauth, cpu)) { 5059 valid_mask |= HCR_API | HCR_APK; 5060 } 5061 if (cpu_isar_feature(aa64_mte, cpu)) { 5062 valid_mask |= HCR_ATA | HCR_DCT | HCR_TID5; 5063 } 5064 if (cpu_isar_feature(aa64_scxtnum, cpu)) { 5065 valid_mask |= HCR_ENSCXT; 5066 } 5067 if (cpu_isar_feature(aa64_fwb, cpu)) { 5068 valid_mask |= HCR_FWB; 5069 } 5070 } 5071 5072 /* Clear RES0 bits. */ 5073 value &= valid_mask; 5074 5075 /* 5076 * These bits change the MMU setup: 5077 * HCR_VM enables stage 2 translation 5078 * HCR_PTW forbids certain page-table setups 5079 * HCR_DC disables stage1 and enables stage2 translation 5080 * HCR_DCT enables tagging on (disabled) stage1 translation 5081 * HCR_FWB changes the interpretation of stage2 descriptor bits 5082 */ 5083 if ((env->cp15.hcr_el2 ^ value) & 5084 (HCR_VM | HCR_PTW | HCR_DC | HCR_DCT | HCR_FWB)) { 5085 tlb_flush(CPU(cpu)); 5086 } 5087 env->cp15.hcr_el2 = value; 5088 5089 /* 5090 * Updates to VI and VF require us to update the status of 5091 * virtual interrupts, which are the logical OR of these bits 5092 * and the state of the input lines from the GIC. (This requires 5093 * that we have the iothread lock, which is done by marking the 5094 * reginfo structs as ARM_CP_IO.) 5095 * Note that if a write to HCR pends a VIRQ or VFIQ it is never 5096 * possible for it to be taken immediately, because VIRQ and 5097 * VFIQ are masked unless running at EL0 or EL1, and HCR 5098 * can only be written at EL2. 5099 */ 5100 g_assert(qemu_mutex_iothread_locked()); 5101 arm_cpu_update_virq(cpu); 5102 arm_cpu_update_vfiq(cpu); 5103 arm_cpu_update_vserr(cpu); 5104 } 5105 5106 static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) 5107 { 5108 do_hcr_write(env, value, 0); 5109 } 5110 5111 static void hcr_writehigh(CPUARMState *env, const ARMCPRegInfo *ri, 5112 uint64_t value) 5113 { 5114 /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */ 5115 value = deposit64(env->cp15.hcr_el2, 32, 32, value); 5116 do_hcr_write(env, value, MAKE_64BIT_MASK(0, 32)); 5117 } 5118 5119 static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri, 5120 uint64_t value) 5121 { 5122 /* Handle HCR write, i.e. write to low half of HCR_EL2 */ 5123 value = deposit64(env->cp15.hcr_el2, 0, 32, value); 5124 do_hcr_write(env, value, MAKE_64BIT_MASK(32, 32)); 5125 } 5126 5127 /* 5128 * Return the effective value of HCR_EL2. 5129 * Bits that are not included here: 5130 * RW (read from SCR_EL3.RW as needed) 5131 */ 5132 uint64_t arm_hcr_el2_eff(CPUARMState *env) 5133 { 5134 uint64_t ret = env->cp15.hcr_el2; 5135 5136 if (!arm_is_el2_enabled(env)) { 5137 /* 5138 * "This register has no effect if EL2 is not enabled in the 5139 * current Security state". This is ARMv8.4-SecEL2 speak for 5140 * !(SCR_EL3.NS==1 || SCR_EL3.EEL2==1). 5141 * 5142 * Prior to that, the language was "In an implementation that 5143 * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves 5144 * as if this field is 0 for all purposes other than a direct 5145 * read or write access of HCR_EL2". With lots of enumeration 5146 * on a per-field basis. In current QEMU, this is condition 5147 * is arm_is_secure_below_el3. 5148 * 5149 * Since the v8.4 language applies to the entire register, and 5150 * appears to be backward compatible, use that. 5151 */ 5152 return 0; 5153 } 5154 5155 /* 5156 * For a cpu that supports both aarch64 and aarch32, we can set bits 5157 * in HCR_EL2 (e.g. via EL3) that are RES0 when we enter EL2 as aa32. 5158 * Ignore all of the bits in HCR+HCR2 that are not valid for aarch32. 5159 */ 5160 if (!arm_el_is_aa64(env, 2)) { 5161 uint64_t aa32_valid; 5162 5163 /* 5164 * These bits are up-to-date as of ARMv8.6. 5165 * For HCR, it's easiest to list just the 2 bits that are invalid. 5166 * For HCR2, list those that are valid. 5167 */ 5168 aa32_valid = MAKE_64BIT_MASK(0, 32) & ~(HCR_RW | HCR_TDZ); 5169 aa32_valid |= (HCR_CD | HCR_ID | HCR_TERR | HCR_TEA | HCR_MIOCNCE | 5170 HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_TTLBIS); 5171 ret &= aa32_valid; 5172 } 5173 5174 if (ret & HCR_TGE) { 5175 /* These bits are up-to-date as of ARMv8.6. */ 5176 if (ret & HCR_E2H) { 5177 ret &= ~(HCR_VM | HCR_FMO | HCR_IMO | HCR_AMO | 5178 HCR_BSU_MASK | HCR_DC | HCR_TWI | HCR_TWE | 5179 HCR_TID0 | HCR_TID2 | HCR_TPCP | HCR_TPU | 5180 HCR_TDZ | HCR_CD | HCR_ID | HCR_MIOCNCE | 5181 HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_ENSCXT | 5182 HCR_TTLBIS | HCR_TTLBOS | HCR_TID5); 5183 } else { 5184 ret |= HCR_FMO | HCR_IMO | HCR_AMO; 5185 } 5186 ret &= ~(HCR_SWIO | HCR_PTW | HCR_VF | HCR_VI | HCR_VSE | 5187 HCR_FB | HCR_TID1 | HCR_TID3 | HCR_TSC | HCR_TACR | 5188 HCR_TSW | HCR_TTLB | HCR_TVM | HCR_HCD | HCR_TRVM | 5189 HCR_TLOR); 5190 } 5191 5192 return ret; 5193 } 5194 5195 /* 5196 * Corresponds to ARM pseudocode function ELIsInHost(). 5197 */ 5198 bool el_is_in_host(CPUARMState *env, int el) 5199 { 5200 uint64_t mask; 5201 5202 /* 5203 * Since we only care about E2H and TGE, we can skip arm_hcr_el2_eff(). 5204 * Perform the simplest bit tests first, and validate EL2 afterward. 5205 */ 5206 if (el & 1) { 5207 return false; /* EL1 or EL3 */ 5208 } 5209 5210 /* 5211 * Note that hcr_write() checks isar_feature_aa64_vh(), 5212 * aka HaveVirtHostExt(), in allowing HCR_E2H to be set. 5213 */ 5214 mask = el ? HCR_E2H : HCR_E2H | HCR_TGE; 5215 if ((env->cp15.hcr_el2 & mask) != mask) { 5216 return false; 5217 } 5218 5219 /* TGE and/or E2H set: double check those bits are currently legal. */ 5220 return arm_is_el2_enabled(env) && arm_el_is_aa64(env, 2); 5221 } 5222 5223 static void hcrx_write(CPUARMState *env, const ARMCPRegInfo *ri, 5224 uint64_t value) 5225 { 5226 uint64_t valid_mask = 0; 5227 5228 /* No features adding bits to HCRX are implemented. */ 5229 5230 /* Clear RES0 bits. */ 5231 env->cp15.hcrx_el2 = value & valid_mask; 5232 } 5233 5234 static CPAccessResult access_hxen(CPUARMState *env, const ARMCPRegInfo *ri, 5235 bool isread) 5236 { 5237 if (arm_current_el(env) < 3 5238 && arm_feature(env, ARM_FEATURE_EL3) 5239 && !(env->cp15.scr_el3 & SCR_HXEN)) { 5240 return CP_ACCESS_TRAP_EL3; 5241 } 5242 return CP_ACCESS_OK; 5243 } 5244 5245 static const ARMCPRegInfo hcrx_el2_reginfo = { 5246 .name = "HCRX_EL2", .state = ARM_CP_STATE_AA64, 5247 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 2, 5248 .access = PL2_RW, .writefn = hcrx_write, .accessfn = access_hxen, 5249 .fieldoffset = offsetof(CPUARMState, cp15.hcrx_el2), 5250 }; 5251 5252 /* Return the effective value of HCRX_EL2. */ 5253 uint64_t arm_hcrx_el2_eff(CPUARMState *env) 5254 { 5255 /* 5256 * The bits in this register behave as 0 for all purposes other than 5257 * direct reads of the register if: 5258 * - EL2 is not enabled in the current security state, 5259 * - SCR_EL3.HXEn is 0. 5260 */ 5261 if (!arm_is_el2_enabled(env) 5262 || (arm_feature(env, ARM_FEATURE_EL3) 5263 && !(env->cp15.scr_el3 & SCR_HXEN))) { 5264 return 0; 5265 } 5266 return env->cp15.hcrx_el2; 5267 } 5268 5269 static void cptr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, 5270 uint64_t value) 5271 { 5272 /* 5273 * For A-profile AArch32 EL3, if NSACR.CP10 5274 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1. 5275 */ 5276 if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && 5277 !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { 5278 uint64_t mask = R_HCPTR_TCP11_MASK | R_HCPTR_TCP10_MASK; 5279 value = (value & ~mask) | (env->cp15.cptr_el[2] & mask); 5280 } 5281 env->cp15.cptr_el[2] = value; 5282 } 5283 5284 static uint64_t cptr_el2_read(CPUARMState *env, const ARMCPRegInfo *ri) 5285 { 5286 /* 5287 * For A-profile AArch32 EL3, if NSACR.CP10 5288 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1. 5289 */ 5290 uint64_t value = env->cp15.cptr_el[2]; 5291 5292 if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && 5293 !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { 5294 value |= R_HCPTR_TCP11_MASK | R_HCPTR_TCP10_MASK; 5295 } 5296 return value; 5297 } 5298 5299 static const ARMCPRegInfo el2_cp_reginfo[] = { 5300 { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64, 5301 .type = ARM_CP_IO, 5302 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, 5303 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), 5304 .writefn = hcr_write }, 5305 { .name = "HCR", .state = ARM_CP_STATE_AA32, 5306 .type = ARM_CP_ALIAS | ARM_CP_IO, 5307 .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, 5308 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), 5309 .writefn = hcr_writelow }, 5310 { .name = "HACR_EL2", .state = ARM_CP_STATE_BOTH, 5311 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 7, 5312 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 5313 { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64, 5314 .type = ARM_CP_ALIAS, 5315 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1, 5316 .access = PL2_RW, 5317 .fieldoffset = offsetof(CPUARMState, elr_el[2]) }, 5318 { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH, 5319 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, 5320 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) }, 5321 { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH, 5322 .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, 5323 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) }, 5324 { .name = "HIFAR", .state = ARM_CP_STATE_AA32, 5325 .type = ARM_CP_ALIAS, 5326 .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2, 5327 .access = PL2_RW, 5328 .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[2]) }, 5329 { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64, 5330 .type = ARM_CP_ALIAS, 5331 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0, 5332 .access = PL2_RW, 5333 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_HYP]) }, 5334 { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH, 5335 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, 5336 .access = PL2_RW, .writefn = vbar_write, 5337 .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]), 5338 .resetvalue = 0 }, 5339 { .name = "SP_EL2", .state = ARM_CP_STATE_AA64, 5340 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0, 5341 .access = PL3_RW, .type = ARM_CP_ALIAS, 5342 .fieldoffset = offsetof(CPUARMState, sp_el[2]) }, 5343 { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH, 5344 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, 5345 .access = PL2_RW, .accessfn = cptr_access, .resetvalue = 0, 5346 .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[2]), 5347 .readfn = cptr_el2_read, .writefn = cptr_el2_write }, 5348 { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH, 5349 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0, 5350 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[2]), 5351 .resetvalue = 0 }, 5352 { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, 5353 .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, 5354 .access = PL2_RW, .type = ARM_CP_ALIAS, 5355 .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el[2]) }, 5356 { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH, 5357 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0, 5358 .access = PL2_RW, .type = ARM_CP_CONST, 5359 .resetvalue = 0 }, 5360 /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */ 5361 { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32, 5362 .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, 5363 .access = PL2_RW, .type = ARM_CP_CONST, 5364 .resetvalue = 0 }, 5365 { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH, 5366 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0, 5367 .access = PL2_RW, .type = ARM_CP_CONST, 5368 .resetvalue = 0 }, 5369 { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH, 5370 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1, 5371 .access = PL2_RW, .type = ARM_CP_CONST, 5372 .resetvalue = 0 }, 5373 { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, 5374 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, 5375 .access = PL2_RW, .writefn = vmsa_tcr_el12_write, 5376 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) }, 5377 { .name = "VTCR", .state = ARM_CP_STATE_AA32, 5378 .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, 5379 .type = ARM_CP_ALIAS, 5380 .access = PL2_RW, .accessfn = access_el3_aa32ns, 5381 .fieldoffset = offsetoflow32(CPUARMState, cp15.vtcr_el2) }, 5382 { .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64, 5383 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, 5384 .access = PL2_RW, 5385 /* no .writefn needed as this can't cause an ASID change */ 5386 .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) }, 5387 { .name = "VTTBR", .state = ARM_CP_STATE_AA32, 5388 .cp = 15, .opc1 = 6, .crm = 2, 5389 .type = ARM_CP_64BIT | ARM_CP_ALIAS, 5390 .access = PL2_RW, .accessfn = access_el3_aa32ns, 5391 .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2), 5392 .writefn = vttbr_write }, 5393 { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64, 5394 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0, 5395 .access = PL2_RW, .writefn = vttbr_write, 5396 .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2) }, 5397 { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH, 5398 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, 5399 .access = PL2_RW, .raw_writefn = raw_write, .writefn = sctlr_write, 5400 .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[2]) }, 5401 { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH, 5402 .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2, 5403 .access = PL2_RW, .resetvalue = 0, 5404 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) }, 5405 { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64, 5406 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, 5407 .access = PL2_RW, .resetvalue = 0, .writefn = vmsa_tcr_ttbr_el2_write, 5408 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) }, 5409 { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2, 5410 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, 5411 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) }, 5412 { .name = "TLBIALLNSNH", 5413 .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4, 5414 .type = ARM_CP_NO_RAW, .access = PL2_W, 5415 .writefn = tlbiall_nsnh_write }, 5416 { .name = "TLBIALLNSNHIS", 5417 .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4, 5418 .type = ARM_CP_NO_RAW, .access = PL2_W, 5419 .writefn = tlbiall_nsnh_is_write }, 5420 { .name = "TLBIALLH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0, 5421 .type = ARM_CP_NO_RAW, .access = PL2_W, 5422 .writefn = tlbiall_hyp_write }, 5423 { .name = "TLBIALLHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0, 5424 .type = ARM_CP_NO_RAW, .access = PL2_W, 5425 .writefn = tlbiall_hyp_is_write }, 5426 { .name = "TLBIMVAH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1, 5427 .type = ARM_CP_NO_RAW, .access = PL2_W, 5428 .writefn = tlbimva_hyp_write }, 5429 { .name = "TLBIMVAHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1, 5430 .type = ARM_CP_NO_RAW, .access = PL2_W, 5431 .writefn = tlbimva_hyp_is_write }, 5432 { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64, 5433 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0, 5434 .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, 5435 .writefn = tlbi_aa64_alle2_write }, 5436 { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64, 5437 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1, 5438 .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, 5439 .writefn = tlbi_aa64_vae2_write }, 5440 { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64, 5441 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5, 5442 .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, 5443 .writefn = tlbi_aa64_vae2_write }, 5444 { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64, 5445 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0, 5446 .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, 5447 .writefn = tlbi_aa64_alle2is_write }, 5448 { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64, 5449 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1, 5450 .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, 5451 .writefn = tlbi_aa64_vae2is_write }, 5452 { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64, 5453 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5, 5454 .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, 5455 .writefn = tlbi_aa64_vae2is_write }, 5456 #ifndef CONFIG_USER_ONLY 5457 /* Unlike the other EL2-related AT operations, these must 5458 * UNDEF from EL3 if EL2 is not implemented, which is why we 5459 * define them here rather than with the rest of the AT ops. 5460 */ 5461 { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64, 5462 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, 5463 .access = PL2_W, .accessfn = at_s1e2_access, 5464 .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF, 5465 .writefn = ats_write64 }, 5466 { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64, 5467 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, 5468 .access = PL2_W, .accessfn = at_s1e2_access, 5469 .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF, 5470 .writefn = ats_write64 }, 5471 /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE 5472 * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3 5473 * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose 5474 * to behave as if SCR.NS was 1. 5475 */ 5476 { .name = "ATS1HR", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, 5477 .access = PL2_W, 5478 .writefn = ats1h_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC }, 5479 { .name = "ATS1HW", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, 5480 .access = PL2_W, 5481 .writefn = ats1h_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC }, 5482 { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH, 5483 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0, 5484 /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the 5485 * reset values as IMPDEF. We choose to reset to 3 to comply with 5486 * both ARMv7 and ARMv8. 5487 */ 5488 .access = PL2_RW, .resetvalue = 3, 5489 .fieldoffset = offsetof(CPUARMState, cp15.cnthctl_el2) }, 5490 { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64, 5491 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3, 5492 .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0, 5493 .writefn = gt_cntvoff_write, 5494 .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) }, 5495 { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14, 5496 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS | ARM_CP_IO, 5497 .writefn = gt_cntvoff_write, 5498 .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) }, 5499 { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64, 5500 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2, 5501 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval), 5502 .type = ARM_CP_IO, .access = PL2_RW, 5503 .writefn = gt_hyp_cval_write, .raw_writefn = raw_write }, 5504 { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14, 5505 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval), 5506 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_IO, 5507 .writefn = gt_hyp_cval_write, .raw_writefn = raw_write }, 5508 { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH, 5509 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0, 5510 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW, 5511 .resetfn = gt_hyp_timer_reset, 5512 .readfn = gt_hyp_tval_read, .writefn = gt_hyp_tval_write }, 5513 { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, 5514 .type = ARM_CP_IO, 5515 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, 5516 .access = PL2_RW, 5517 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].ctl), 5518 .resetvalue = 0, 5519 .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write }, 5520 #endif 5521 { .name = "HPFAR", .state = ARM_CP_STATE_AA32, 5522 .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, 5523 .access = PL2_RW, .accessfn = access_el3_aa32ns, 5524 .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, 5525 { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64, 5526 .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, 5527 .access = PL2_RW, 5528 .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, 5529 { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH, 5530 .cp = 15, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3, 5531 .access = PL2_RW, 5532 .fieldoffset = offsetof(CPUARMState, cp15.hstr_el2) }, 5533 }; 5534 5535 static const ARMCPRegInfo el2_v8_cp_reginfo[] = { 5536 { .name = "HCR2", .state = ARM_CP_STATE_AA32, 5537 .type = ARM_CP_ALIAS | ARM_CP_IO, 5538 .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4, 5539 .access = PL2_RW, 5540 .fieldoffset = offsetofhigh32(CPUARMState, cp15.hcr_el2), 5541 .writefn = hcr_writehigh }, 5542 }; 5543 5544 static CPAccessResult sel2_access(CPUARMState *env, const ARMCPRegInfo *ri, 5545 bool isread) 5546 { 5547 if (arm_current_el(env) == 3 || arm_is_secure_below_el3(env)) { 5548 return CP_ACCESS_OK; 5549 } 5550 return CP_ACCESS_TRAP_UNCATEGORIZED; 5551 } 5552 5553 static const ARMCPRegInfo el2_sec_cp_reginfo[] = { 5554 { .name = "VSTTBR_EL2", .state = ARM_CP_STATE_AA64, 5555 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 6, .opc2 = 0, 5556 .access = PL2_RW, .accessfn = sel2_access, 5557 .fieldoffset = offsetof(CPUARMState, cp15.vsttbr_el2) }, 5558 { .name = "VSTCR_EL2", .state = ARM_CP_STATE_AA64, 5559 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 6, .opc2 = 2, 5560 .access = PL2_RW, .accessfn = sel2_access, 5561 .fieldoffset = offsetof(CPUARMState, cp15.vstcr_el2) }, 5562 }; 5563 5564 static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri, 5565 bool isread) 5566 { 5567 /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2. 5568 * At Secure EL1 it traps to EL3 or EL2. 5569 */ 5570 if (arm_current_el(env) == 3) { 5571 return CP_ACCESS_OK; 5572 } 5573 if (arm_is_secure_below_el3(env)) { 5574 if (env->cp15.scr_el3 & SCR_EEL2) { 5575 return CP_ACCESS_TRAP_EL2; 5576 } 5577 return CP_ACCESS_TRAP_EL3; 5578 } 5579 /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */ 5580 if (isread) { 5581 return CP_ACCESS_OK; 5582 } 5583 return CP_ACCESS_TRAP_UNCATEGORIZED; 5584 } 5585 5586 static const ARMCPRegInfo el3_cp_reginfo[] = { 5587 { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64, 5588 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0, 5589 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), 5590 .resetfn = scr_reset, .writefn = scr_write }, 5591 { .name = "SCR", .type = ARM_CP_ALIAS | ARM_CP_NEWEL, 5592 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0, 5593 .access = PL1_RW, .accessfn = access_trap_aa32s_el1, 5594 .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3), 5595 .writefn = scr_write }, 5596 { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64, 5597 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1, 5598 .access = PL3_RW, .resetvalue = 0, 5599 .fieldoffset = offsetof(CPUARMState, cp15.sder) }, 5600 { .name = "SDER", 5601 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1, 5602 .access = PL3_RW, .resetvalue = 0, 5603 .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) }, 5604 { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, 5605 .access = PL1_RW, .accessfn = access_trap_aa32s_el1, 5606 .writefn = vbar_write, .resetvalue = 0, 5607 .fieldoffset = offsetof(CPUARMState, cp15.mvbar) }, 5608 { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64, 5609 .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0, 5610 .access = PL3_RW, .resetvalue = 0, 5611 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) }, 5612 { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64, 5613 .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2, 5614 .access = PL3_RW, 5615 /* no .writefn needed as this can't cause an ASID change */ 5616 .resetvalue = 0, 5617 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) }, 5618 { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64, 5619 .type = ARM_CP_ALIAS, 5620 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1, 5621 .access = PL3_RW, 5622 .fieldoffset = offsetof(CPUARMState, elr_el[3]) }, 5623 { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64, 5624 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0, 5625 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) }, 5626 { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64, 5627 .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0, 5628 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) }, 5629 { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64, 5630 .type = ARM_CP_ALIAS, 5631 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0, 5632 .access = PL3_RW, 5633 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_MON]) }, 5634 { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64, 5635 .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0, 5636 .access = PL3_RW, .writefn = vbar_write, 5637 .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]), 5638 .resetvalue = 0 }, 5639 { .name = "CPTR_EL3", .state = ARM_CP_STATE_AA64, 5640 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 2, 5641 .access = PL3_RW, .accessfn = cptr_access, .resetvalue = 0, 5642 .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[3]) }, 5643 { .name = "TPIDR_EL3", .state = ARM_CP_STATE_AA64, 5644 .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 2, 5645 .access = PL3_RW, .resetvalue = 0, 5646 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[3]) }, 5647 { .name = "AMAIR_EL3", .state = ARM_CP_STATE_AA64, 5648 .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0, 5649 .access = PL3_RW, .type = ARM_CP_CONST, 5650 .resetvalue = 0 }, 5651 { .name = "AFSR0_EL3", .state = ARM_CP_STATE_BOTH, 5652 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 0, 5653 .access = PL3_RW, .type = ARM_CP_CONST, 5654 .resetvalue = 0 }, 5655 { .name = "AFSR1_EL3", .state = ARM_CP_STATE_BOTH, 5656 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 1, 5657 .access = PL3_RW, .type = ARM_CP_CONST, 5658 .resetvalue = 0 }, 5659 { .name = "TLBI_ALLE3IS", .state = ARM_CP_STATE_AA64, 5660 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 0, 5661 .access = PL3_W, .type = ARM_CP_NO_RAW, 5662 .writefn = tlbi_aa64_alle3is_write }, 5663 { .name = "TLBI_VAE3IS", .state = ARM_CP_STATE_AA64, 5664 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 1, 5665 .access = PL3_W, .type = ARM_CP_NO_RAW, 5666 .writefn = tlbi_aa64_vae3is_write }, 5667 { .name = "TLBI_VALE3IS", .state = ARM_CP_STATE_AA64, 5668 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 5, 5669 .access = PL3_W, .type = ARM_CP_NO_RAW, 5670 .writefn = tlbi_aa64_vae3is_write }, 5671 { .name = "TLBI_ALLE3", .state = ARM_CP_STATE_AA64, 5672 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 0, 5673 .access = PL3_W, .type = ARM_CP_NO_RAW, 5674 .writefn = tlbi_aa64_alle3_write }, 5675 { .name = "TLBI_VAE3", .state = ARM_CP_STATE_AA64, 5676 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 1, 5677 .access = PL3_W, .type = ARM_CP_NO_RAW, 5678 .writefn = tlbi_aa64_vae3_write }, 5679 { .name = "TLBI_VALE3", .state = ARM_CP_STATE_AA64, 5680 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5, 5681 .access = PL3_W, .type = ARM_CP_NO_RAW, 5682 .writefn = tlbi_aa64_vae3_write }, 5683 }; 5684 5685 #ifndef CONFIG_USER_ONLY 5686 /* Test if system register redirection is to occur in the current state. */ 5687 static bool redirect_for_e2h(CPUARMState *env) 5688 { 5689 return arm_current_el(env) == 2 && (arm_hcr_el2_eff(env) & HCR_E2H); 5690 } 5691 5692 static uint64_t el2_e2h_read(CPUARMState *env, const ARMCPRegInfo *ri) 5693 { 5694 CPReadFn *readfn; 5695 5696 if (redirect_for_e2h(env)) { 5697 /* Switch to the saved EL2 version of the register. */ 5698 ri = ri->opaque; 5699 readfn = ri->readfn; 5700 } else { 5701 readfn = ri->orig_readfn; 5702 } 5703 if (readfn == NULL) { 5704 readfn = raw_read; 5705 } 5706 return readfn(env, ri); 5707 } 5708 5709 static void el2_e2h_write(CPUARMState *env, const ARMCPRegInfo *ri, 5710 uint64_t value) 5711 { 5712 CPWriteFn *writefn; 5713 5714 if (redirect_for_e2h(env)) { 5715 /* Switch to the saved EL2 version of the register. */ 5716 ri = ri->opaque; 5717 writefn = ri->writefn; 5718 } else { 5719 writefn = ri->orig_writefn; 5720 } 5721 if (writefn == NULL) { 5722 writefn = raw_write; 5723 } 5724 writefn(env, ri, value); 5725 } 5726 5727 static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu) 5728 { 5729 struct E2HAlias { 5730 uint32_t src_key, dst_key, new_key; 5731 const char *src_name, *dst_name, *new_name; 5732 bool (*feature)(const ARMISARegisters *id); 5733 }; 5734 5735 #define K(op0, op1, crn, crm, op2) \ 5736 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2) 5737 5738 static const struct E2HAlias aliases[] = { 5739 { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0), 5740 "SCTLR", "SCTLR_EL2", "SCTLR_EL12" }, 5741 { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2), 5742 "CPACR", "CPTR_EL2", "CPACR_EL12" }, 5743 { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0), 5744 "TTBR0_EL1", "TTBR0_EL2", "TTBR0_EL12" }, 5745 { K(3, 0, 2, 0, 1), K(3, 4, 2, 0, 1), K(3, 5, 2, 0, 1), 5746 "TTBR1_EL1", "TTBR1_EL2", "TTBR1_EL12" }, 5747 { K(3, 0, 2, 0, 2), K(3, 4, 2, 0, 2), K(3, 5, 2, 0, 2), 5748 "TCR_EL1", "TCR_EL2", "TCR_EL12" }, 5749 { K(3, 0, 4, 0, 0), K(3, 4, 4, 0, 0), K(3, 5, 4, 0, 0), 5750 "SPSR_EL1", "SPSR_EL2", "SPSR_EL12" }, 5751 { K(3, 0, 4, 0, 1), K(3, 4, 4, 0, 1), K(3, 5, 4, 0, 1), 5752 "ELR_EL1", "ELR_EL2", "ELR_EL12" }, 5753 { K(3, 0, 5, 1, 0), K(3, 4, 5, 1, 0), K(3, 5, 5, 1, 0), 5754 "AFSR0_EL1", "AFSR0_EL2", "AFSR0_EL12" }, 5755 { K(3, 0, 5, 1, 1), K(3, 4, 5, 1, 1), K(3, 5, 5, 1, 1), 5756 "AFSR1_EL1", "AFSR1_EL2", "AFSR1_EL12" }, 5757 { K(3, 0, 5, 2, 0), K(3, 4, 5, 2, 0), K(3, 5, 5, 2, 0), 5758 "ESR_EL1", "ESR_EL2", "ESR_EL12" }, 5759 { K(3, 0, 6, 0, 0), K(3, 4, 6, 0, 0), K(3, 5, 6, 0, 0), 5760 "FAR_EL1", "FAR_EL2", "FAR_EL12" }, 5761 { K(3, 0, 10, 2, 0), K(3, 4, 10, 2, 0), K(3, 5, 10, 2, 0), 5762 "MAIR_EL1", "MAIR_EL2", "MAIR_EL12" }, 5763 { K(3, 0, 10, 3, 0), K(3, 4, 10, 3, 0), K(3, 5, 10, 3, 0), 5764 "AMAIR0", "AMAIR_EL2", "AMAIR_EL12" }, 5765 { K(3, 0, 12, 0, 0), K(3, 4, 12, 0, 0), K(3, 5, 12, 0, 0), 5766 "VBAR", "VBAR_EL2", "VBAR_EL12" }, 5767 { K(3, 0, 13, 0, 1), K(3, 4, 13, 0, 1), K(3, 5, 13, 0, 1), 5768 "CONTEXTIDR_EL1", "CONTEXTIDR_EL2", "CONTEXTIDR_EL12" }, 5769 { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0), 5770 "CNTKCTL", "CNTHCTL_EL2", "CNTKCTL_EL12" }, 5771 5772 /* 5773 * Note that redirection of ZCR is mentioned in the description 5774 * of ZCR_EL2, and aliasing in the description of ZCR_EL1, but 5775 * not in the summary table. 5776 */ 5777 { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0), 5778 "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve }, 5779 { K(3, 0, 1, 2, 6), K(3, 4, 1, 2, 6), K(3, 5, 1, 2, 6), 5780 "SMCR_EL1", "SMCR_EL2", "SMCR_EL12", isar_feature_aa64_sme }, 5781 5782 { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0), 5783 "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte }, 5784 5785 { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7), 5786 "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12", 5787 isar_feature_aa64_scxtnum }, 5788 5789 /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */ 5790 /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */ 5791 }; 5792 #undef K 5793 5794 size_t i; 5795 5796 for (i = 0; i < ARRAY_SIZE(aliases); i++) { 5797 const struct E2HAlias *a = &aliases[i]; 5798 ARMCPRegInfo *src_reg, *dst_reg, *new_reg; 5799 bool ok; 5800 5801 if (a->feature && !a->feature(&cpu->isar)) { 5802 continue; 5803 } 5804 5805 src_reg = g_hash_table_lookup(cpu->cp_regs, 5806 (gpointer)(uintptr_t)a->src_key); 5807 dst_reg = g_hash_table_lookup(cpu->cp_regs, 5808 (gpointer)(uintptr_t)a->dst_key); 5809 g_assert(src_reg != NULL); 5810 g_assert(dst_reg != NULL); 5811 5812 /* Cross-compare names to detect typos in the keys. */ 5813 g_assert(strcmp(src_reg->name, a->src_name) == 0); 5814 g_assert(strcmp(dst_reg->name, a->dst_name) == 0); 5815 5816 /* None of the core system registers use opaque; we will. */ 5817 g_assert(src_reg->opaque == NULL); 5818 5819 /* Create alias before redirection so we dup the right data. */ 5820 new_reg = g_memdup(src_reg, sizeof(ARMCPRegInfo)); 5821 5822 new_reg->name = a->new_name; 5823 new_reg->type |= ARM_CP_ALIAS; 5824 /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */ 5825 new_reg->access &= PL2_RW | PL3_RW; 5826 5827 ok = g_hash_table_insert(cpu->cp_regs, 5828 (gpointer)(uintptr_t)a->new_key, new_reg); 5829 g_assert(ok); 5830 5831 src_reg->opaque = dst_reg; 5832 src_reg->orig_readfn = src_reg->readfn ?: raw_read; 5833 src_reg->orig_writefn = src_reg->writefn ?: raw_write; 5834 if (!src_reg->raw_readfn) { 5835 src_reg->raw_readfn = raw_read; 5836 } 5837 if (!src_reg->raw_writefn) { 5838 src_reg->raw_writefn = raw_write; 5839 } 5840 src_reg->readfn = el2_e2h_read; 5841 src_reg->writefn = el2_e2h_write; 5842 } 5843 } 5844 #endif 5845 5846 static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri, 5847 bool isread) 5848 { 5849 int cur_el = arm_current_el(env); 5850 5851 if (cur_el < 2) { 5852 uint64_t hcr = arm_hcr_el2_eff(env); 5853 5854 if (cur_el == 0) { 5855 if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { 5856 if (!(env->cp15.sctlr_el[2] & SCTLR_UCT)) { 5857 return CP_ACCESS_TRAP_EL2; 5858 } 5859 } else { 5860 if (!(env->cp15.sctlr_el[1] & SCTLR_UCT)) { 5861 return CP_ACCESS_TRAP; 5862 } 5863 if (hcr & HCR_TID2) { 5864 return CP_ACCESS_TRAP_EL2; 5865 } 5866 } 5867 } else if (hcr & HCR_TID2) { 5868 return CP_ACCESS_TRAP_EL2; 5869 } 5870 } 5871 5872 if (arm_current_el(env) < 2 && arm_hcr_el2_eff(env) & HCR_TID2) { 5873 return CP_ACCESS_TRAP_EL2; 5874 } 5875 5876 return CP_ACCESS_OK; 5877 } 5878 5879 /* 5880 * Check for traps to RAS registers, which are controlled 5881 * by HCR_EL2.TERR and SCR_EL3.TERR. 5882 */ 5883 static CPAccessResult access_terr(CPUARMState *env, const ARMCPRegInfo *ri, 5884 bool isread) 5885 { 5886 int el = arm_current_el(env); 5887 5888 if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TERR)) { 5889 return CP_ACCESS_TRAP_EL2; 5890 } 5891 if (el < 3 && (env->cp15.scr_el3 & SCR_TERR)) { 5892 return CP_ACCESS_TRAP_EL3; 5893 } 5894 return CP_ACCESS_OK; 5895 } 5896 5897 static uint64_t disr_read(CPUARMState *env, const ARMCPRegInfo *ri) 5898 { 5899 int el = arm_current_el(env); 5900 5901 if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) { 5902 return env->cp15.vdisr_el2; 5903 } 5904 if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) { 5905 return 0; /* RAZ/WI */ 5906 } 5907 return env->cp15.disr_el1; 5908 } 5909 5910 static void disr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) 5911 { 5912 int el = arm_current_el(env); 5913 5914 if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) { 5915 env->cp15.vdisr_el2 = val; 5916 return; 5917 } 5918 if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) { 5919 return; /* RAZ/WI */ 5920 } 5921 env->cp15.disr_el1 = val; 5922 } 5923 5924 /* 5925 * Minimal RAS implementation with no Error Records. 5926 * Which means that all of the Error Record registers: 5927 * ERXADDR_EL1 5928 * ERXCTLR_EL1 5929 * ERXFR_EL1 5930 * ERXMISC0_EL1 5931 * ERXMISC1_EL1 5932 * ERXMISC2_EL1 5933 * ERXMISC3_EL1 5934 * ERXPFGCDN_EL1 (RASv1p1) 5935 * ERXPFGCTL_EL1 (RASv1p1) 5936 * ERXPFGF_EL1 (RASv1p1) 5937 * ERXSTATUS_EL1 5938 * and 5939 * ERRSELR_EL1 5940 * may generate UNDEFINED, which is the effect we get by not 5941 * listing them at all. 5942 */ 5943 static const ARMCPRegInfo minimal_ras_reginfo[] = { 5944 { .name = "DISR_EL1", .state = ARM_CP_STATE_BOTH, 5945 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 1, 5946 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.disr_el1), 5947 .readfn = disr_read, .writefn = disr_write, .raw_writefn = raw_write }, 5948 { .name = "ERRIDR_EL1", .state = ARM_CP_STATE_BOTH, 5949 .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 3, .opc2 = 0, 5950 .access = PL1_R, .accessfn = access_terr, 5951 .type = ARM_CP_CONST, .resetvalue = 0 }, 5952 { .name = "VDISR_EL2", .state = ARM_CP_STATE_BOTH, 5953 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 1, .opc2 = 1, 5954 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vdisr_el2) }, 5955 { .name = "VSESR_EL2", .state = ARM_CP_STATE_BOTH, 5956 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 3, 5957 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vsesr_el2) }, 5958 }; 5959 5960 /* 5961 * Return the exception level to which exceptions should be taken 5962 * via SVEAccessTrap. This excludes the check for whether the exception 5963 * should be routed through AArch64.AdvSIMDFPAccessTrap. That can easily 5964 * be found by testing 0 < fp_exception_el < sve_exception_el. 5965 * 5966 * C.f. the ARM pseudocode function CheckSVEEnabled. Note that the 5967 * pseudocode does *not* separate out the FP trap checks, but has them 5968 * all in one function. 5969 */ 5970 int sve_exception_el(CPUARMState *env, int el) 5971 { 5972 #ifndef CONFIG_USER_ONLY 5973 if (el <= 1 && !el_is_in_host(env, el)) { 5974 switch (FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, ZEN)) { 5975 case 1: 5976 if (el != 0) { 5977 break; 5978 } 5979 /* fall through */ 5980 case 0: 5981 case 2: 5982 return 1; 5983 } 5984 } 5985 5986 if (el <= 2 && arm_is_el2_enabled(env)) { 5987 /* CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). */ 5988 if (env->cp15.hcr_el2 & HCR_E2H) { 5989 switch (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, ZEN)) { 5990 case 1: 5991 if (el != 0 || !(env->cp15.hcr_el2 & HCR_TGE)) { 5992 break; 5993 } 5994 /* fall through */ 5995 case 0: 5996 case 2: 5997 return 2; 5998 } 5999 } else { 6000 if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TZ)) { 6001 return 2; 6002 } 6003 } 6004 } 6005 6006 /* CPTR_EL3. Since EZ is negative we must check for EL3. */ 6007 if (arm_feature(env, ARM_FEATURE_EL3) 6008 && !FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, EZ)) { 6009 return 3; 6010 } 6011 #endif 6012 return 0; 6013 } 6014 6015 /* 6016 * Return the exception level to which exceptions should be taken for SME. 6017 * C.f. the ARM pseudocode function CheckSMEAccess. 6018 */ 6019 int sme_exception_el(CPUARMState *env, int el) 6020 { 6021 #ifndef CONFIG_USER_ONLY 6022 if (el <= 1 && !el_is_in_host(env, el)) { 6023 switch (FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, SMEN)) { 6024 case 1: 6025 if (el != 0) { 6026 break; 6027 } 6028 /* fall through */ 6029 case 0: 6030 case 2: 6031 return 1; 6032 } 6033 } 6034 6035 if (el <= 2 && arm_is_el2_enabled(env)) { 6036 /* CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). */ 6037 if (env->cp15.hcr_el2 & HCR_E2H) { 6038 switch (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, SMEN)) { 6039 case 1: 6040 if (el != 0 || !(env->cp15.hcr_el2 & HCR_TGE)) { 6041 break; 6042 } 6043 /* fall through */ 6044 case 0: 6045 case 2: 6046 return 2; 6047 } 6048 } else { 6049 if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TSM)) { 6050 return 2; 6051 } 6052 } 6053 } 6054 6055 /* CPTR_EL3. Since ESM is negative we must check for EL3. */ 6056 if (arm_feature(env, ARM_FEATURE_EL3) 6057 && !FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, ESM)) { 6058 return 3; 6059 } 6060 #endif 6061 return 0; 6062 } 6063 6064 /* This corresponds to the ARM pseudocode function IsFullA64Enabled(). */ 6065 static bool sme_fa64(CPUARMState *env, int el) 6066 { 6067 if (!cpu_isar_feature(aa64_sme_fa64, env_archcpu(env))) { 6068 return false; 6069 } 6070 6071 if (el <= 1 && !el_is_in_host(env, el)) { 6072 if (!FIELD_EX64(env->vfp.smcr_el[1], SMCR, FA64)) { 6073 return false; 6074 } 6075 } 6076 if (el <= 2 && arm_is_el2_enabled(env)) { 6077 if (!FIELD_EX64(env->vfp.smcr_el[2], SMCR, FA64)) { 6078 return false; 6079 } 6080 } 6081 if (arm_feature(env, ARM_FEATURE_EL3)) { 6082 if (!FIELD_EX64(env->vfp.smcr_el[3], SMCR, FA64)) { 6083 return false; 6084 } 6085 } 6086 6087 return true; 6088 } 6089 6090 /* 6091 * Given that SVE is enabled, return the vector length for EL. 6092 */ 6093 uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm) 6094 { 6095 ARMCPU *cpu = env_archcpu(env); 6096 uint64_t *cr = env->vfp.zcr_el; 6097 uint32_t map = cpu->sve_vq.map; 6098 uint32_t len = ARM_MAX_VQ - 1; 6099 6100 if (sm) { 6101 cr = env->vfp.smcr_el; 6102 map = cpu->sme_vq.map; 6103 } 6104 6105 if (el <= 1 && !el_is_in_host(env, el)) { 6106 len = MIN(len, 0xf & (uint32_t)cr[1]); 6107 } 6108 if (el <= 2 && arm_feature(env, ARM_FEATURE_EL2)) { 6109 len = MIN(len, 0xf & (uint32_t)cr[2]); 6110 } 6111 if (arm_feature(env, ARM_FEATURE_EL3)) { 6112 len = MIN(len, 0xf & (uint32_t)cr[3]); 6113 } 6114 6115 map &= MAKE_64BIT_MASK(0, len + 1); 6116 if (map != 0) { 6117 return 31 - clz32(map); 6118 } 6119 6120 /* Bit 0 is always set for Normal SVE -- not so for Streaming SVE. */ 6121 assert(sm); 6122 return ctz32(cpu->sme_vq.map); 6123 } 6124 6125 uint32_t sve_vqm1_for_el(CPUARMState *env, int el) 6126 { 6127 return sve_vqm1_for_el_sm(env, el, FIELD_EX64(env->svcr, SVCR, SM)); 6128 } 6129 6130 static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, 6131 uint64_t value) 6132 { 6133 int cur_el = arm_current_el(env); 6134 int old_len = sve_vqm1_for_el(env, cur_el); 6135 int new_len; 6136 6137 /* Bits other than [3:0] are RAZ/WI. */ 6138 QEMU_BUILD_BUG_ON(ARM_MAX_VQ > 16); 6139 raw_write(env, ri, value & 0xf); 6140 6141 /* 6142 * Because we arrived here, we know both FP and SVE are enabled; 6143 * otherwise we would have trapped access to the ZCR_ELn register. 6144 */ 6145 new_len = sve_vqm1_for_el(env, cur_el); 6146 if (new_len < old_len) { 6147 aarch64_sve_narrow_vq(env, new_len + 1); 6148 } 6149 } 6150 6151 static const ARMCPRegInfo zcr_reginfo[] = { 6152 { .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64, 6153 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0, 6154 .access = PL1_RW, .type = ARM_CP_SVE, 6155 .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]), 6156 .writefn = zcr_write, .raw_writefn = raw_write }, 6157 { .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64, 6158 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0, 6159 .access = PL2_RW, .type = ARM_CP_SVE, 6160 .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]), 6161 .writefn = zcr_write, .raw_writefn = raw_write }, 6162 { .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64, 6163 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0, 6164 .access = PL3_RW, .type = ARM_CP_SVE, 6165 .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]), 6166 .writefn = zcr_write, .raw_writefn = raw_write }, 6167 }; 6168 6169 #ifdef TARGET_AARCH64 6170 static CPAccessResult access_tpidr2(CPUARMState *env, const ARMCPRegInfo *ri, 6171 bool isread) 6172 { 6173 int el = arm_current_el(env); 6174 6175 if (el == 0) { 6176 uint64_t sctlr = arm_sctlr(env, el); 6177 if (!(sctlr & SCTLR_EnTP2)) { 6178 return CP_ACCESS_TRAP; 6179 } 6180 } 6181 /* TODO: FEAT_FGT */ 6182 if (el < 3 6183 && arm_feature(env, ARM_FEATURE_EL3) 6184 && !(env->cp15.scr_el3 & SCR_ENTP2)) { 6185 return CP_ACCESS_TRAP_EL3; 6186 } 6187 return CP_ACCESS_OK; 6188 } 6189 6190 static CPAccessResult access_esm(CPUARMState *env, const ARMCPRegInfo *ri, 6191 bool isread) 6192 { 6193 /* TODO: FEAT_FGT for SMPRI_EL1 but not SMPRIMAP_EL2 */ 6194 if (arm_current_el(env) < 3 6195 && arm_feature(env, ARM_FEATURE_EL3) 6196 && !FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, ESM)) { 6197 return CP_ACCESS_TRAP_EL3; 6198 } 6199 return CP_ACCESS_OK; 6200 } 6201 6202 static void svcr_write(CPUARMState *env, const ARMCPRegInfo *ri, 6203 uint64_t value) 6204 { 6205 helper_set_pstate_sm(env, FIELD_EX64(value, SVCR, SM)); 6206 helper_set_pstate_za(env, FIELD_EX64(value, SVCR, ZA)); 6207 arm_rebuild_hflags(env); 6208 } 6209 6210 static void smcr_write(CPUARMState *env, const ARMCPRegInfo *ri, 6211 uint64_t value) 6212 { 6213 int cur_el = arm_current_el(env); 6214 int old_len = sve_vqm1_for_el(env, cur_el); 6215 int new_len; 6216 6217 QEMU_BUILD_BUG_ON(ARM_MAX_VQ > R_SMCR_LEN_MASK + 1); 6218 value &= R_SMCR_LEN_MASK | R_SMCR_FA64_MASK; 6219 raw_write(env, ri, value); 6220 6221 /* 6222 * Note that it is CONSTRAINED UNPREDICTABLE what happens to ZA storage 6223 * when SVL is widened (old values kept, or zeros). Choose to keep the 6224 * current values for simplicity. But for QEMU internals, we must still 6225 * apply the narrower SVL to the Zregs and Pregs -- see the comment 6226 * above aarch64_sve_narrow_vq. 6227 */ 6228 new_len = sve_vqm1_for_el(env, cur_el); 6229 if (new_len < old_len) { 6230 aarch64_sve_narrow_vq(env, new_len + 1); 6231 } 6232 } 6233 6234 static const ARMCPRegInfo sme_reginfo[] = { 6235 { .name = "TPIDR2_EL0", .state = ARM_CP_STATE_AA64, 6236 .opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 5, 6237 .access = PL0_RW, .accessfn = access_tpidr2, 6238 .fieldoffset = offsetof(CPUARMState, cp15.tpidr2_el0) }, 6239 { .name = "SVCR", .state = ARM_CP_STATE_AA64, 6240 .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 2, 6241 .access = PL0_RW, .type = ARM_CP_SME, 6242 .fieldoffset = offsetof(CPUARMState, svcr), 6243 .writefn = svcr_write, .raw_writefn = raw_write }, 6244 { .name = "SMCR_EL1", .state = ARM_CP_STATE_AA64, 6245 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 6, 6246 .access = PL1_RW, .type = ARM_CP_SME, 6247 .fieldoffset = offsetof(CPUARMState, vfp.smcr_el[1]), 6248 .writefn = smcr_write, .raw_writefn = raw_write }, 6249 { .name = "SMCR_EL2", .state = ARM_CP_STATE_AA64, 6250 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 6, 6251 .access = PL2_RW, .type = ARM_CP_SME, 6252 .fieldoffset = offsetof(CPUARMState, vfp.smcr_el[2]), 6253 .writefn = smcr_write, .raw_writefn = raw_write }, 6254 { .name = "SMCR_EL3", .state = ARM_CP_STATE_AA64, 6255 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 6, 6256 .access = PL3_RW, .type = ARM_CP_SME, 6257 .fieldoffset = offsetof(CPUARMState, vfp.smcr_el[3]), 6258 .writefn = smcr_write, .raw_writefn = raw_write }, 6259 { .name = "SMIDR_EL1", .state = ARM_CP_STATE_AA64, 6260 .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 6, 6261 .access = PL1_R, .accessfn = access_aa64_tid1, 6262 /* 6263 * IMPLEMENTOR = 0 (software) 6264 * REVISION = 0 (implementation defined) 6265 * SMPS = 0 (no streaming execution priority in QEMU) 6266 * AFFINITY = 0 (streaming sve mode not shared with other PEs) 6267 */ 6268 .type = ARM_CP_CONST, .resetvalue = 0, }, 6269 /* 6270 * Because SMIDR_EL1.SMPS is 0, SMPRI_EL1 and SMPRIMAP_EL2 are RES 0. 6271 */ 6272 { .name = "SMPRI_EL1", .state = ARM_CP_STATE_AA64, 6273 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 4, 6274 .access = PL1_RW, .accessfn = access_esm, 6275 .type = ARM_CP_CONST, .resetvalue = 0 }, 6276 { .name = "SMPRIMAP_EL2", .state = ARM_CP_STATE_AA64, 6277 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 5, 6278 .access = PL2_RW, .accessfn = access_esm, 6279 .type = ARM_CP_CONST, .resetvalue = 0 }, 6280 }; 6281 #endif /* TARGET_AARCH64 */ 6282 6283 static void define_pmu_regs(ARMCPU *cpu) 6284 { 6285 /* 6286 * v7 performance monitor control register: same implementor 6287 * field as main ID register, and we implement four counters in 6288 * addition to the cycle count register. 6289 */ 6290 unsigned int i, pmcrn = pmu_num_counters(&cpu->env); 6291 ARMCPRegInfo pmcr = { 6292 .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0, 6293 .access = PL0_RW, 6294 .type = ARM_CP_IO | ARM_CP_ALIAS, 6295 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr), 6296 .accessfn = pmreg_access, .writefn = pmcr_write, 6297 .raw_writefn = raw_write, 6298 }; 6299 ARMCPRegInfo pmcr64 = { 6300 .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64, 6301 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0, 6302 .access = PL0_RW, .accessfn = pmreg_access, 6303 .type = ARM_CP_IO, 6304 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr), 6305 .resetvalue = cpu->isar.reset_pmcr_el0, 6306 .writefn = pmcr_write, .raw_writefn = raw_write, 6307 }; 6308 6309 define_one_arm_cp_reg(cpu, &pmcr); 6310 define_one_arm_cp_reg(cpu, &pmcr64); 6311 for (i = 0; i < pmcrn; i++) { 6312 char *pmevcntr_name = g_strdup_printf("PMEVCNTR%d", i); 6313 char *pmevcntr_el0_name = g_strdup_printf("PMEVCNTR%d_EL0", i); 6314 char *pmevtyper_name = g_strdup_printf("PMEVTYPER%d", i); 6315 char *pmevtyper_el0_name = g_strdup_printf("PMEVTYPER%d_EL0", i); 6316 ARMCPRegInfo pmev_regs[] = { 6317 { .name = pmevcntr_name, .cp = 15, .crn = 14, 6318 .crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7, 6319 .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS, 6320 .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn, 6321 .accessfn = pmreg_access_xevcntr }, 6322 { .name = pmevcntr_el0_name, .state = ARM_CP_STATE_AA64, 6323 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 8 | (3 & (i >> 3)), 6324 .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access_xevcntr, 6325 .type = ARM_CP_IO, 6326 .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn, 6327 .raw_readfn = pmevcntr_rawread, 6328 .raw_writefn = pmevcntr_rawwrite }, 6329 { .name = pmevtyper_name, .cp = 15, .crn = 14, 6330 .crm = 12 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7, 6331 .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS, 6332 .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn, 6333 .accessfn = pmreg_access }, 6334 { .name = pmevtyper_el0_name, .state = ARM_CP_STATE_AA64, 6335 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 12 | (3 & (i >> 3)), 6336 .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access, 6337 .type = ARM_CP_IO, 6338 .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn, 6339 .raw_writefn = pmevtyper_rawwrite }, 6340 }; 6341 define_arm_cp_regs(cpu, pmev_regs); 6342 g_free(pmevcntr_name); 6343 g_free(pmevcntr_el0_name); 6344 g_free(pmevtyper_name); 6345 g_free(pmevtyper_el0_name); 6346 } 6347 if (cpu_isar_feature(aa32_pmu_8_1, cpu)) { 6348 ARMCPRegInfo v81_pmu_regs[] = { 6349 { .name = "PMCEID2", .state = ARM_CP_STATE_AA32, 6350 .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 4, 6351 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, 6352 .resetvalue = extract64(cpu->pmceid0, 32, 32) }, 6353 { .name = "PMCEID3", .state = ARM_CP_STATE_AA32, 6354 .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 5, 6355 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, 6356 .resetvalue = extract64(cpu->pmceid1, 32, 32) }, 6357 }; 6358 define_arm_cp_regs(cpu, v81_pmu_regs); 6359 } 6360 if (cpu_isar_feature(any_pmu_8_4, cpu)) { 6361 static const ARMCPRegInfo v84_pmmir = { 6362 .name = "PMMIR_EL1", .state = ARM_CP_STATE_BOTH, 6363 .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 6, 6364 .access = PL1_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, 6365 .resetvalue = 0 6366 }; 6367 define_one_arm_cp_reg(cpu, &v84_pmmir); 6368 } 6369 } 6370 6371 /* We don't know until after realize whether there's a GICv3 6372 * attached, and that is what registers the gicv3 sysregs. 6373 * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1 6374 * at runtime. 6375 */ 6376 static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri) 6377 { 6378 ARMCPU *cpu = env_archcpu(env); 6379 uint64_t pfr1 = cpu->isar.id_pfr1; 6380 6381 if (env->gicv3state) { 6382 pfr1 |= 1 << 28; 6383 } 6384 return pfr1; 6385 } 6386 6387 #ifndef CONFIG_USER_ONLY 6388 static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) 6389 { 6390 ARMCPU *cpu = env_archcpu(env); 6391 uint64_t pfr0 = cpu->isar.id_aa64pfr0; 6392 6393 if (env->gicv3state) { 6394 pfr0 |= 1 << 24; 6395 } 6396 return pfr0; 6397 } 6398 #endif 6399 6400 /* Shared logic between LORID and the rest of the LOR* registers. 6401 * Secure state exclusion has already been dealt with. 6402 */ 6403 static CPAccessResult access_lor_ns(CPUARMState *env, 6404 const ARMCPRegInfo *ri, bool isread) 6405 { 6406 int el = arm_current_el(env); 6407 6408 if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TLOR)) { 6409 return CP_ACCESS_TRAP_EL2; 6410 } 6411 if (el < 3 && (env->cp15.scr_el3 & SCR_TLOR)) { 6412 return CP_ACCESS_TRAP_EL3; 6413 } 6414 return CP_ACCESS_OK; 6415 } 6416 6417 static CPAccessResult access_lor_other(CPUARMState *env, 6418 const ARMCPRegInfo *ri, bool isread) 6419 { 6420 if (arm_is_secure_below_el3(env)) { 6421 /* Access denied in secure mode. */ 6422 return CP_ACCESS_TRAP; 6423 } 6424 return access_lor_ns(env, ri, isread); 6425 } 6426 6427 /* 6428 * A trivial implementation of ARMv8.1-LOR leaves all of these 6429 * registers fixed at 0, which indicates that there are zero 6430 * supported Limited Ordering regions. 6431 */ 6432 static const ARMCPRegInfo lor_reginfo[] = { 6433 { .name = "LORSA_EL1", .state = ARM_CP_STATE_AA64, 6434 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 0, 6435 .access = PL1_RW, .accessfn = access_lor_other, 6436 .type = ARM_CP_CONST, .resetvalue = 0 }, 6437 { .name = "LOREA_EL1", .state = ARM_CP_STATE_AA64, 6438 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 1, 6439 .access = PL1_RW, .accessfn = access_lor_other, 6440 .type = ARM_CP_CONST, .resetvalue = 0 }, 6441 { .name = "LORN_EL1", .state = ARM_CP_STATE_AA64, 6442 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 2, 6443 .access = PL1_RW, .accessfn = access_lor_other, 6444 .type = ARM_CP_CONST, .resetvalue = 0 }, 6445 { .name = "LORC_EL1", .state = ARM_CP_STATE_AA64, 6446 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 3, 6447 .access = PL1_RW, .accessfn = access_lor_other, 6448 .type = ARM_CP_CONST, .resetvalue = 0 }, 6449 { .name = "LORID_EL1", .state = ARM_CP_STATE_AA64, 6450 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7, 6451 .access = PL1_R, .accessfn = access_lor_ns, 6452 .type = ARM_CP_CONST, .resetvalue = 0 }, 6453 }; 6454 6455 #ifdef TARGET_AARCH64 6456 static CPAccessResult access_pauth(CPUARMState *env, const ARMCPRegInfo *ri, 6457 bool isread) 6458 { 6459 int el = arm_current_el(env); 6460 6461 if (el < 2 && 6462 arm_is_el2_enabled(env) && 6463 !(arm_hcr_el2_eff(env) & HCR_APK)) { 6464 return CP_ACCESS_TRAP_EL2; 6465 } 6466 if (el < 3 && 6467 arm_feature(env, ARM_FEATURE_EL3) && 6468 !(env->cp15.scr_el3 & SCR_APK)) { 6469 return CP_ACCESS_TRAP_EL3; 6470 } 6471 return CP_ACCESS_OK; 6472 } 6473 6474 static const ARMCPRegInfo pauth_reginfo[] = { 6475 { .name = "APDAKEYLO_EL1", .state = ARM_CP_STATE_AA64, 6476 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 0, 6477 .access = PL1_RW, .accessfn = access_pauth, 6478 .fieldoffset = offsetof(CPUARMState, keys.apda.lo) }, 6479 { .name = "APDAKEYHI_EL1", .state = ARM_CP_STATE_AA64, 6480 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 1, 6481 .access = PL1_RW, .accessfn = access_pauth, 6482 .fieldoffset = offsetof(CPUARMState, keys.apda.hi) }, 6483 { .name = "APDBKEYLO_EL1", .state = ARM_CP_STATE_AA64, 6484 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 2, 6485 .access = PL1_RW, .accessfn = access_pauth, 6486 .fieldoffset = offsetof(CPUARMState, keys.apdb.lo) }, 6487 { .name = "APDBKEYHI_EL1", .state = ARM_CP_STATE_AA64, 6488 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 3, 6489 .access = PL1_RW, .accessfn = access_pauth, 6490 .fieldoffset = offsetof(CPUARMState, keys.apdb.hi) }, 6491 { .name = "APGAKEYLO_EL1", .state = ARM_CP_STATE_AA64, 6492 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 0, 6493 .access = PL1_RW, .accessfn = access_pauth, 6494 .fieldoffset = offsetof(CPUARMState, keys.apga.lo) }, 6495 { .name = "APGAKEYHI_EL1", .state = ARM_CP_STATE_AA64, 6496 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 1, 6497 .access = PL1_RW, .accessfn = access_pauth, 6498 .fieldoffset = offsetof(CPUARMState, keys.apga.hi) }, 6499 { .name = "APIAKEYLO_EL1", .state = ARM_CP_STATE_AA64, 6500 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 0, 6501 .access = PL1_RW, .accessfn = access_pauth, 6502 .fieldoffset = offsetof(CPUARMState, keys.apia.lo) }, 6503 { .name = "APIAKEYHI_EL1", .state = ARM_CP_STATE_AA64, 6504 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 1, 6505 .access = PL1_RW, .accessfn = access_pauth, 6506 .fieldoffset = offsetof(CPUARMState, keys.apia.hi) }, 6507 { .name = "APIBKEYLO_EL1", .state = ARM_CP_STATE_AA64, 6508 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 2, 6509 .access = PL1_RW, .accessfn = access_pauth, 6510 .fieldoffset = offsetof(CPUARMState, keys.apib.lo) }, 6511 { .name = "APIBKEYHI_EL1", .state = ARM_CP_STATE_AA64, 6512 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 3, 6513 .access = PL1_RW, .accessfn = access_pauth, 6514 .fieldoffset = offsetof(CPUARMState, keys.apib.hi) }, 6515 }; 6516 6517 static const ARMCPRegInfo tlbirange_reginfo[] = { 6518 { .name = "TLBI_RVAE1IS", .state = ARM_CP_STATE_AA64, 6519 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 1, 6520 .access = PL1_W, .type = ARM_CP_NO_RAW, 6521 .writefn = tlbi_aa64_rvae1is_write }, 6522 { .name = "TLBI_RVAAE1IS", .state = ARM_CP_STATE_AA64, 6523 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 3, 6524 .access = PL1_W, .type = ARM_CP_NO_RAW, 6525 .writefn = tlbi_aa64_rvae1is_write }, 6526 { .name = "TLBI_RVALE1IS", .state = ARM_CP_STATE_AA64, 6527 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 5, 6528 .access = PL1_W, .type = ARM_CP_NO_RAW, 6529 .writefn = tlbi_aa64_rvae1is_write }, 6530 { .name = "TLBI_RVAALE1IS", .state = ARM_CP_STATE_AA64, 6531 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 7, 6532 .access = PL1_W, .type = ARM_CP_NO_RAW, 6533 .writefn = tlbi_aa64_rvae1is_write }, 6534 { .name = "TLBI_RVAE1OS", .state = ARM_CP_STATE_AA64, 6535 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1, 6536 .access = PL1_W, .type = ARM_CP_NO_RAW, 6537 .writefn = tlbi_aa64_rvae1is_write }, 6538 { .name = "TLBI_RVAAE1OS", .state = ARM_CP_STATE_AA64, 6539 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 3, 6540 .access = PL1_W, .type = ARM_CP_NO_RAW, 6541 .writefn = tlbi_aa64_rvae1is_write }, 6542 { .name = "TLBI_RVALE1OS", .state = ARM_CP_STATE_AA64, 6543 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 5, 6544 .access = PL1_W, .type = ARM_CP_NO_RAW, 6545 .writefn = tlbi_aa64_rvae1is_write }, 6546 { .name = "TLBI_RVAALE1OS", .state = ARM_CP_STATE_AA64, 6547 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 7, 6548 .access = PL1_W, .type = ARM_CP_NO_RAW, 6549 .writefn = tlbi_aa64_rvae1is_write }, 6550 { .name = "TLBI_RVAE1", .state = ARM_CP_STATE_AA64, 6551 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1, 6552 .access = PL1_W, .type = ARM_CP_NO_RAW, 6553 .writefn = tlbi_aa64_rvae1_write }, 6554 { .name = "TLBI_RVAAE1", .state = ARM_CP_STATE_AA64, 6555 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 3, 6556 .access = PL1_W, .type = ARM_CP_NO_RAW, 6557 .writefn = tlbi_aa64_rvae1_write }, 6558 { .name = "TLBI_RVALE1", .state = ARM_CP_STATE_AA64, 6559 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 5, 6560 .access = PL1_W, .type = ARM_CP_NO_RAW, 6561 .writefn = tlbi_aa64_rvae1_write }, 6562 { .name = "TLBI_RVAALE1", .state = ARM_CP_STATE_AA64, 6563 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 7, 6564 .access = PL1_W, .type = ARM_CP_NO_RAW, 6565 .writefn = tlbi_aa64_rvae1_write }, 6566 { .name = "TLBI_RIPAS2E1IS", .state = ARM_CP_STATE_AA64, 6567 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 2, 6568 .access = PL2_W, .type = ARM_CP_NOP }, 6569 { .name = "TLBI_RIPAS2LE1IS", .state = ARM_CP_STATE_AA64, 6570 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 6, 6571 .access = PL2_W, .type = ARM_CP_NOP }, 6572 { .name = "TLBI_RVAE2IS", .state = ARM_CP_STATE_AA64, 6573 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 1, 6574 .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, 6575 .writefn = tlbi_aa64_rvae2is_write }, 6576 { .name = "TLBI_RVALE2IS", .state = ARM_CP_STATE_AA64, 6577 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 5, 6578 .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, 6579 .writefn = tlbi_aa64_rvae2is_write }, 6580 { .name = "TLBI_RIPAS2E1", .state = ARM_CP_STATE_AA64, 6581 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 2, 6582 .access = PL2_W, .type = ARM_CP_NOP }, 6583 { .name = "TLBI_RIPAS2LE1", .state = ARM_CP_STATE_AA64, 6584 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 6, 6585 .access = PL2_W, .type = ARM_CP_NOP }, 6586 { .name = "TLBI_RVAE2OS", .state = ARM_CP_STATE_AA64, 6587 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 1, 6588 .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, 6589 .writefn = tlbi_aa64_rvae2is_write }, 6590 { .name = "TLBI_RVALE2OS", .state = ARM_CP_STATE_AA64, 6591 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 5, 6592 .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, 6593 .writefn = tlbi_aa64_rvae2is_write }, 6594 { .name = "TLBI_RVAE2", .state = ARM_CP_STATE_AA64, 6595 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 1, 6596 .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, 6597 .writefn = tlbi_aa64_rvae2_write }, 6598 { .name = "TLBI_RVALE2", .state = ARM_CP_STATE_AA64, 6599 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 5, 6600 .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, 6601 .writefn = tlbi_aa64_rvae2_write }, 6602 { .name = "TLBI_RVAE3IS", .state = ARM_CP_STATE_AA64, 6603 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 1, 6604 .access = PL3_W, .type = ARM_CP_NO_RAW, 6605 .writefn = tlbi_aa64_rvae3is_write }, 6606 { .name = "TLBI_RVALE3IS", .state = ARM_CP_STATE_AA64, 6607 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 5, 6608 .access = PL3_W, .type = ARM_CP_NO_RAW, 6609 .writefn = tlbi_aa64_rvae3is_write }, 6610 { .name = "TLBI_RVAE3OS", .state = ARM_CP_STATE_AA64, 6611 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 5, .opc2 = 1, 6612 .access = PL3_W, .type = ARM_CP_NO_RAW, 6613 .writefn = tlbi_aa64_rvae3is_write }, 6614 { .name = "TLBI_RVALE3OS", .state = ARM_CP_STATE_AA64, 6615 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 5, .opc2 = 5, 6616 .access = PL3_W, .type = ARM_CP_NO_RAW, 6617 .writefn = tlbi_aa64_rvae3is_write }, 6618 { .name = "TLBI_RVAE3", .state = ARM_CP_STATE_AA64, 6619 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 6, .opc2 = 1, 6620 .access = PL3_W, .type = ARM_CP_NO_RAW, 6621 .writefn = tlbi_aa64_rvae3_write }, 6622 { .name = "TLBI_RVALE3", .state = ARM_CP_STATE_AA64, 6623 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 6, .opc2 = 5, 6624 .access = PL3_W, .type = ARM_CP_NO_RAW, 6625 .writefn = tlbi_aa64_rvae3_write }, 6626 }; 6627 6628 static const ARMCPRegInfo tlbios_reginfo[] = { 6629 { .name = "TLBI_VMALLE1OS", .state = ARM_CP_STATE_AA64, 6630 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 0, 6631 .access = PL1_W, .type = ARM_CP_NO_RAW, 6632 .writefn = tlbi_aa64_vmalle1is_write }, 6633 { .name = "TLBI_VAE1OS", .state = ARM_CP_STATE_AA64, 6634 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 1, 6635 .access = PL1_W, .type = ARM_CP_NO_RAW, 6636 .writefn = tlbi_aa64_vae1is_write }, 6637 { .name = "TLBI_ASIDE1OS", .state = ARM_CP_STATE_AA64, 6638 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 2, 6639 .access = PL1_W, .type = ARM_CP_NO_RAW, 6640 .writefn = tlbi_aa64_vmalle1is_write }, 6641 { .name = "TLBI_VAAE1OS", .state = ARM_CP_STATE_AA64, 6642 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 3, 6643 .access = PL1_W, .type = ARM_CP_NO_RAW, 6644 .writefn = tlbi_aa64_vae1is_write }, 6645 { .name = "TLBI_VALE1OS", .state = ARM_CP_STATE_AA64, 6646 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 5, 6647 .access = PL1_W, .type = ARM_CP_NO_RAW, 6648 .writefn = tlbi_aa64_vae1is_write }, 6649 { .name = "TLBI_VAALE1OS", .state = ARM_CP_STATE_AA64, 6650 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 7, 6651 .access = PL1_W, .type = ARM_CP_NO_RAW, 6652 .writefn = tlbi_aa64_vae1is_write }, 6653 { .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64, 6654 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0, 6655 .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, 6656 .writefn = tlbi_aa64_alle2is_write }, 6657 { .name = "TLBI_VAE2OS", .state = ARM_CP_STATE_AA64, 6658 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 1, 6659 .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, 6660 .writefn = tlbi_aa64_vae2is_write }, 6661 { .name = "TLBI_ALLE1OS", .state = ARM_CP_STATE_AA64, 6662 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 4, 6663 .access = PL2_W, .type = ARM_CP_NO_RAW, 6664 .writefn = tlbi_aa64_alle1is_write }, 6665 { .name = "TLBI_VALE2OS", .state = ARM_CP_STATE_AA64, 6666 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 5, 6667 .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, 6668 .writefn = tlbi_aa64_vae2is_write }, 6669 { .name = "TLBI_VMALLS12E1OS", .state = ARM_CP_STATE_AA64, 6670 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 6, 6671 .access = PL2_W, .type = ARM_CP_NO_RAW, 6672 .writefn = tlbi_aa64_alle1is_write }, 6673 { .name = "TLBI_IPAS2E1OS", .state = ARM_CP_STATE_AA64, 6674 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 0, 6675 .access = PL2_W, .type = ARM_CP_NOP }, 6676 { .name = "TLBI_RIPAS2E1OS", .state = ARM_CP_STATE_AA64, 6677 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 3, 6678 .access = PL2_W, .type = ARM_CP_NOP }, 6679 { .name = "TLBI_IPAS2LE1OS", .state = ARM_CP_STATE_AA64, 6680 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 4, 6681 .access = PL2_W, .type = ARM_CP_NOP }, 6682 { .name = "TLBI_RIPAS2LE1OS", .state = ARM_CP_STATE_AA64, 6683 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 7, 6684 .access = PL2_W, .type = ARM_CP_NOP }, 6685 { .name = "TLBI_ALLE3OS", .state = ARM_CP_STATE_AA64, 6686 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 0, 6687 .access = PL3_W, .type = ARM_CP_NO_RAW, 6688 .writefn = tlbi_aa64_alle3is_write }, 6689 { .name = "TLBI_VAE3OS", .state = ARM_CP_STATE_AA64, 6690 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 1, 6691 .access = PL3_W, .type = ARM_CP_NO_RAW, 6692 .writefn = tlbi_aa64_vae3is_write }, 6693 { .name = "TLBI_VALE3OS", .state = ARM_CP_STATE_AA64, 6694 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 5, 6695 .access = PL3_W, .type = ARM_CP_NO_RAW, 6696 .writefn = tlbi_aa64_vae3is_write }, 6697 }; 6698 6699 static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) 6700 { 6701 Error *err = NULL; 6702 uint64_t ret; 6703 6704 /* Success sets NZCV = 0000. */ 6705 env->NF = env->CF = env->VF = 0, env->ZF = 1; 6706 6707 if (qemu_guest_getrandom(&ret, sizeof(ret), &err) < 0) { 6708 /* 6709 * ??? Failed, for unknown reasons in the crypto subsystem. 6710 * The best we can do is log the reason and return the 6711 * timed-out indication to the guest. There is no reason 6712 * we know to expect this failure to be transitory, so the 6713 * guest may well hang retrying the operation. 6714 */ 6715 qemu_log_mask(LOG_UNIMP, "%s: Crypto failure: %s", 6716 ri->name, error_get_pretty(err)); 6717 error_free(err); 6718 6719 env->ZF = 0; /* NZCF = 0100 */ 6720 return 0; 6721 } 6722 return ret; 6723 } 6724 6725 /* We do not support re-seeding, so the two registers operate the same. */ 6726 static const ARMCPRegInfo rndr_reginfo[] = { 6727 { .name = "RNDR", .state = ARM_CP_STATE_AA64, 6728 .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO, 6729 .opc0 = 3, .opc1 = 3, .crn = 2, .crm = 4, .opc2 = 0, 6730 .access = PL0_R, .readfn = rndr_readfn }, 6731 { .name = "RNDRRS", .state = ARM_CP_STATE_AA64, 6732 .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO, 6733 .opc0 = 3, .opc1 = 3, .crn = 2, .crm = 4, .opc2 = 1, 6734 .access = PL0_R, .readfn = rndr_readfn }, 6735 }; 6736 6737 #ifndef CONFIG_USER_ONLY 6738 static void dccvap_writefn(CPUARMState *env, const ARMCPRegInfo *opaque, 6739 uint64_t value) 6740 { 6741 ARMCPU *cpu = env_archcpu(env); 6742 /* CTR_EL0 System register -> DminLine, bits [19:16] */ 6743 uint64_t dline_size = 4 << ((cpu->ctr >> 16) & 0xF); 6744 uint64_t vaddr_in = (uint64_t) value; 6745 uint64_t vaddr = vaddr_in & ~(dline_size - 1); 6746 void *haddr; 6747 int mem_idx = cpu_mmu_index(env, false); 6748 6749 /* This won't be crossing page boundaries */ 6750 haddr = probe_read(env, vaddr, dline_size, mem_idx, GETPC()); 6751 if (haddr) { 6752 6753 ram_addr_t offset; 6754 MemoryRegion *mr; 6755 6756 /* RCU lock is already being held */ 6757 mr = memory_region_from_host(haddr, &offset); 6758 6759 if (mr) { 6760 memory_region_writeback(mr, offset, dline_size); 6761 } 6762 } 6763 } 6764 6765 static const ARMCPRegInfo dcpop_reg[] = { 6766 { .name = "DC_CVAP", .state = ARM_CP_STATE_AA64, 6767 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 1, 6768 .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, 6769 .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn }, 6770 }; 6771 6772 static const ARMCPRegInfo dcpodp_reg[] = { 6773 { .name = "DC_CVADP", .state = ARM_CP_STATE_AA64, 6774 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 1, 6775 .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, 6776 .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn }, 6777 }; 6778 #endif /*CONFIG_USER_ONLY*/ 6779 6780 static CPAccessResult access_aa64_tid5(CPUARMState *env, const ARMCPRegInfo *ri, 6781 bool isread) 6782 { 6783 if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID5)) { 6784 return CP_ACCESS_TRAP_EL2; 6785 } 6786 6787 return CP_ACCESS_OK; 6788 } 6789 6790 static CPAccessResult access_mte(CPUARMState *env, const ARMCPRegInfo *ri, 6791 bool isread) 6792 { 6793 int el = arm_current_el(env); 6794 6795 if (el < 2 && arm_is_el2_enabled(env)) { 6796 uint64_t hcr = arm_hcr_el2_eff(env); 6797 if (!(hcr & HCR_ATA) && (!(hcr & HCR_E2H) || !(hcr & HCR_TGE))) { 6798 return CP_ACCESS_TRAP_EL2; 6799 } 6800 } 6801 if (el < 3 && 6802 arm_feature(env, ARM_FEATURE_EL3) && 6803 !(env->cp15.scr_el3 & SCR_ATA)) { 6804 return CP_ACCESS_TRAP_EL3; 6805 } 6806 return CP_ACCESS_OK; 6807 } 6808 6809 static uint64_t tco_read(CPUARMState *env, const ARMCPRegInfo *ri) 6810 { 6811 return env->pstate & PSTATE_TCO; 6812 } 6813 6814 static void tco_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) 6815 { 6816 env->pstate = (env->pstate & ~PSTATE_TCO) | (val & PSTATE_TCO); 6817 } 6818 6819 static const ARMCPRegInfo mte_reginfo[] = { 6820 { .name = "TFSRE0_EL1", .state = ARM_CP_STATE_AA64, 6821 .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 6, .opc2 = 1, 6822 .access = PL1_RW, .accessfn = access_mte, 6823 .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[0]) }, 6824 { .name = "TFSR_EL1", .state = ARM_CP_STATE_AA64, 6825 .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 6, .opc2 = 0, 6826 .access = PL1_RW, .accessfn = access_mte, 6827 .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[1]) }, 6828 { .name = "TFSR_EL2", .state = ARM_CP_STATE_AA64, 6829 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 6, .opc2 = 0, 6830 .access = PL2_RW, .accessfn = access_mte, 6831 .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[2]) }, 6832 { .name = "TFSR_EL3", .state = ARM_CP_STATE_AA64, 6833 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 6, .opc2 = 0, 6834 .access = PL3_RW, 6835 .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[3]) }, 6836 { .name = "RGSR_EL1", .state = ARM_CP_STATE_AA64, 6837 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 5, 6838 .access = PL1_RW, .accessfn = access_mte, 6839 .fieldoffset = offsetof(CPUARMState, cp15.rgsr_el1) }, 6840 { .name = "GCR_EL1", .state = ARM_CP_STATE_AA64, 6841 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 6, 6842 .access = PL1_RW, .accessfn = access_mte, 6843 .fieldoffset = offsetof(CPUARMState, cp15.gcr_el1) }, 6844 { .name = "GMID_EL1", .state = ARM_CP_STATE_AA64, 6845 .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4, 6846 .access = PL1_R, .accessfn = access_aa64_tid5, 6847 .type = ARM_CP_CONST, .resetvalue = GMID_EL1_BS }, 6848 { .name = "TCO", .state = ARM_CP_STATE_AA64, 6849 .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7, 6850 .type = ARM_CP_NO_RAW, 6851 .access = PL0_RW, .readfn = tco_read, .writefn = tco_write }, 6852 { .name = "DC_IGVAC", .state = ARM_CP_STATE_AA64, 6853 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 3, 6854 .type = ARM_CP_NOP, .access = PL1_W, 6855 .accessfn = aa64_cacheop_poc_access }, 6856 { .name = "DC_IGSW", .state = ARM_CP_STATE_AA64, 6857 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 4, 6858 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, 6859 { .name = "DC_IGDVAC", .state = ARM_CP_STATE_AA64, 6860 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 5, 6861 .type = ARM_CP_NOP, .access = PL1_W, 6862 .accessfn = aa64_cacheop_poc_access }, 6863 { .name = "DC_IGDSW", .state = ARM_CP_STATE_AA64, 6864 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 6, 6865 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, 6866 { .name = "DC_CGSW", .state = ARM_CP_STATE_AA64, 6867 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 4, 6868 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, 6869 { .name = "DC_CGDSW", .state = ARM_CP_STATE_AA64, 6870 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 6, 6871 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, 6872 { .name = "DC_CIGSW", .state = ARM_CP_STATE_AA64, 6873 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 4, 6874 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, 6875 { .name = "DC_CIGDSW", .state = ARM_CP_STATE_AA64, 6876 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 6, 6877 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, 6878 }; 6879 6880 static const ARMCPRegInfo mte_tco_ro_reginfo[] = { 6881 { .name = "TCO", .state = ARM_CP_STATE_AA64, 6882 .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7, 6883 .type = ARM_CP_CONST, .access = PL0_RW, }, 6884 }; 6885 6886 static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = { 6887 { .name = "DC_CGVAC", .state = ARM_CP_STATE_AA64, 6888 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 3, 6889 .type = ARM_CP_NOP, .access = PL0_W, 6890 .accessfn = aa64_cacheop_poc_access }, 6891 { .name = "DC_CGDVAC", .state = ARM_CP_STATE_AA64, 6892 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 5, 6893 .type = ARM_CP_NOP, .access = PL0_W, 6894 .accessfn = aa64_cacheop_poc_access }, 6895 { .name = "DC_CGVAP", .state = ARM_CP_STATE_AA64, 6896 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 3, 6897 .type = ARM_CP_NOP, .access = PL0_W, 6898 .accessfn = aa64_cacheop_poc_access }, 6899 { .name = "DC_CGDVAP", .state = ARM_CP_STATE_AA64, 6900 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 5, 6901 .type = ARM_CP_NOP, .access = PL0_W, 6902 .accessfn = aa64_cacheop_poc_access }, 6903 { .name = "DC_CGVADP", .state = ARM_CP_STATE_AA64, 6904 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 3, 6905 .type = ARM_CP_NOP, .access = PL0_W, 6906 .accessfn = aa64_cacheop_poc_access }, 6907 { .name = "DC_CGDVADP", .state = ARM_CP_STATE_AA64, 6908 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 5, 6909 .type = ARM_CP_NOP, .access = PL0_W, 6910 .accessfn = aa64_cacheop_poc_access }, 6911 { .name = "DC_CIGVAC", .state = ARM_CP_STATE_AA64, 6912 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 3, 6913 .type = ARM_CP_NOP, .access = PL0_W, 6914 .accessfn = aa64_cacheop_poc_access }, 6915 { .name = "DC_CIGDVAC", .state = ARM_CP_STATE_AA64, 6916 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 5, 6917 .type = ARM_CP_NOP, .access = PL0_W, 6918 .accessfn = aa64_cacheop_poc_access }, 6919 { .name = "DC_GVA", .state = ARM_CP_STATE_AA64, 6920 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 3, 6921 .access = PL0_W, .type = ARM_CP_DC_GVA, 6922 #ifndef CONFIG_USER_ONLY 6923 /* Avoid overhead of an access check that always passes in user-mode */ 6924 .accessfn = aa64_zva_access, 6925 #endif 6926 }, 6927 { .name = "DC_GZVA", .state = ARM_CP_STATE_AA64, 6928 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 4, 6929 .access = PL0_W, .type = ARM_CP_DC_GZVA, 6930 #ifndef CONFIG_USER_ONLY 6931 /* Avoid overhead of an access check that always passes in user-mode */ 6932 .accessfn = aa64_zva_access, 6933 #endif 6934 }, 6935 }; 6936 6937 static CPAccessResult access_scxtnum(CPUARMState *env, const ARMCPRegInfo *ri, 6938 bool isread) 6939 { 6940 uint64_t hcr = arm_hcr_el2_eff(env); 6941 int el = arm_current_el(env); 6942 6943 if (el == 0 && !((hcr & HCR_E2H) && (hcr & HCR_TGE))) { 6944 if (env->cp15.sctlr_el[1] & SCTLR_TSCXT) { 6945 if (hcr & HCR_TGE) { 6946 return CP_ACCESS_TRAP_EL2; 6947 } 6948 return CP_ACCESS_TRAP; 6949 } 6950 } else if (el < 2 && (env->cp15.sctlr_el[2] & SCTLR_TSCXT)) { 6951 return CP_ACCESS_TRAP_EL2; 6952 } 6953 if (el < 2 && arm_is_el2_enabled(env) && !(hcr & HCR_ENSCXT)) { 6954 return CP_ACCESS_TRAP_EL2; 6955 } 6956 if (el < 3 6957 && arm_feature(env, ARM_FEATURE_EL3) 6958 && !(env->cp15.scr_el3 & SCR_ENSCXT)) { 6959 return CP_ACCESS_TRAP_EL3; 6960 } 6961 return CP_ACCESS_OK; 6962 } 6963 6964 static const ARMCPRegInfo scxtnum_reginfo[] = { 6965 { .name = "SCXTNUM_EL0", .state = ARM_CP_STATE_AA64, 6966 .opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 7, 6967 .access = PL0_RW, .accessfn = access_scxtnum, 6968 .fieldoffset = offsetof(CPUARMState, scxtnum_el[0]) }, 6969 { .name = "SCXTNUM_EL1", .state = ARM_CP_STATE_AA64, 6970 .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 7, 6971 .access = PL1_RW, .accessfn = access_scxtnum, 6972 .fieldoffset = offsetof(CPUARMState, scxtnum_el[1]) }, 6973 { .name = "SCXTNUM_EL2", .state = ARM_CP_STATE_AA64, 6974 .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 7, 6975 .access = PL2_RW, .accessfn = access_scxtnum, 6976 .fieldoffset = offsetof(CPUARMState, scxtnum_el[2]) }, 6977 { .name = "SCXTNUM_EL3", .state = ARM_CP_STATE_AA64, 6978 .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 7, 6979 .access = PL3_RW, 6980 .fieldoffset = offsetof(CPUARMState, scxtnum_el[3]) }, 6981 }; 6982 #endif /* TARGET_AARCH64 */ 6983 6984 static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri, 6985 bool isread) 6986 { 6987 int el = arm_current_el(env); 6988 6989 if (el == 0) { 6990 uint64_t sctlr = arm_sctlr(env, el); 6991 if (!(sctlr & SCTLR_EnRCTX)) { 6992 return CP_ACCESS_TRAP; 6993 } 6994 } else if (el == 1) { 6995 uint64_t hcr = arm_hcr_el2_eff(env); 6996 if (hcr & HCR_NV) { 6997 return CP_ACCESS_TRAP_EL2; 6998 } 6999 } 7000 return CP_ACCESS_OK; 7001 } 7002 7003 static const ARMCPRegInfo predinv_reginfo[] = { 7004 { .name = "CFP_RCTX", .state = ARM_CP_STATE_AA64, 7005 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 4, 7006 .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, 7007 { .name = "DVP_RCTX", .state = ARM_CP_STATE_AA64, 7008 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 5, 7009 .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, 7010 { .name = "CPP_RCTX", .state = ARM_CP_STATE_AA64, 7011 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 7, 7012 .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, 7013 /* 7014 * Note the AArch32 opcodes have a different OPC1. 7015 */ 7016 { .name = "CFPRCTX", .state = ARM_CP_STATE_AA32, 7017 .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 4, 7018 .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, 7019 { .name = "DVPRCTX", .state = ARM_CP_STATE_AA32, 7020 .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 5, 7021 .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, 7022 { .name = "CPPRCTX", .state = ARM_CP_STATE_AA32, 7023 .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 7, 7024 .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, 7025 }; 7026 7027 static uint64_t ccsidr2_read(CPUARMState *env, const ARMCPRegInfo *ri) 7028 { 7029 /* Read the high 32 bits of the current CCSIDR */ 7030 return extract64(ccsidr_read(env, ri), 32, 32); 7031 } 7032 7033 static const ARMCPRegInfo ccsidr2_reginfo[] = { 7034 { .name = "CCSIDR2", .state = ARM_CP_STATE_BOTH, 7035 .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 2, 7036 .access = PL1_R, 7037 .accessfn = access_aa64_tid2, 7038 .readfn = ccsidr2_read, .type = ARM_CP_NO_RAW }, 7039 }; 7040 7041 static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInfo *ri, 7042 bool isread) 7043 { 7044 if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID3)) { 7045 return CP_ACCESS_TRAP_EL2; 7046 } 7047 7048 return CP_ACCESS_OK; 7049 } 7050 7051 static CPAccessResult access_aa32_tid3(CPUARMState *env, const ARMCPRegInfo *ri, 7052 bool isread) 7053 { 7054 if (arm_feature(env, ARM_FEATURE_V8)) { 7055 return access_aa64_tid3(env, ri, isread); 7056 } 7057 7058 return CP_ACCESS_OK; 7059 } 7060 7061 static CPAccessResult access_jazelle(CPUARMState *env, const ARMCPRegInfo *ri, 7062 bool isread) 7063 { 7064 if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID0)) { 7065 return CP_ACCESS_TRAP_EL2; 7066 } 7067 7068 return CP_ACCESS_OK; 7069 } 7070 7071 static CPAccessResult access_joscr_jmcr(CPUARMState *env, 7072 const ARMCPRegInfo *ri, bool isread) 7073 { 7074 /* 7075 * HSTR.TJDBX traps JOSCR and JMCR accesses, but it exists only 7076 * in v7A, not in v8A. 7077 */ 7078 if (!arm_feature(env, ARM_FEATURE_V8) && 7079 arm_current_el(env) < 2 && !arm_is_secure_below_el3(env) && 7080 (env->cp15.hstr_el2 & HSTR_TJDBX)) { 7081 return CP_ACCESS_TRAP_EL2; 7082 } 7083 return CP_ACCESS_OK; 7084 } 7085 7086 static const ARMCPRegInfo jazelle_regs[] = { 7087 { .name = "JIDR", 7088 .cp = 14, .crn = 0, .crm = 0, .opc1 = 7, .opc2 = 0, 7089 .access = PL1_R, .accessfn = access_jazelle, 7090 .type = ARM_CP_CONST, .resetvalue = 0 }, 7091 { .name = "JOSCR", 7092 .cp = 14, .crn = 1, .crm = 0, .opc1 = 7, .opc2 = 0, 7093 .accessfn = access_joscr_jmcr, 7094 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 7095 { .name = "JMCR", 7096 .cp = 14, .crn = 2, .crm = 0, .opc1 = 7, .opc2 = 0, 7097 .accessfn = access_joscr_jmcr, 7098 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 7099 }; 7100 7101 static const ARMCPRegInfo contextidr_el2 = { 7102 .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64, 7103 .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1, 7104 .access = PL2_RW, 7105 .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2]) 7106 }; 7107 7108 static const ARMCPRegInfo vhe_reginfo[] = { 7109 { .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64, 7110 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1, 7111 .access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write, 7112 .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el[2]) }, 7113 #ifndef CONFIG_USER_ONLY 7114 { .name = "CNTHV_CVAL_EL2", .state = ARM_CP_STATE_AA64, 7115 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 3, .opc2 = 2, 7116 .fieldoffset = 7117 offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYPVIRT].cval), 7118 .type = ARM_CP_IO, .access = PL2_RW, 7119 .writefn = gt_hv_cval_write, .raw_writefn = raw_write }, 7120 { .name = "CNTHV_TVAL_EL2", .state = ARM_CP_STATE_BOTH, 7121 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 3, .opc2 = 0, 7122 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW, 7123 .resetfn = gt_hv_timer_reset, 7124 .readfn = gt_hv_tval_read, .writefn = gt_hv_tval_write }, 7125 { .name = "CNTHV_CTL_EL2", .state = ARM_CP_STATE_BOTH, 7126 .type = ARM_CP_IO, 7127 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 3, .opc2 = 1, 7128 .access = PL2_RW, 7129 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYPVIRT].ctl), 7130 .writefn = gt_hv_ctl_write, .raw_writefn = raw_write }, 7131 { .name = "CNTP_CTL_EL02", .state = ARM_CP_STATE_AA64, 7132 .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 1, 7133 .type = ARM_CP_IO | ARM_CP_ALIAS, 7134 .access = PL2_RW, .accessfn = e2h_access, 7135 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl), 7136 .writefn = gt_phys_ctl_write, .raw_writefn = raw_write }, 7137 { .name = "CNTV_CTL_EL02", .state = ARM_CP_STATE_AA64, 7138 .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 1, 7139 .type = ARM_CP_IO | ARM_CP_ALIAS, 7140 .access = PL2_RW, .accessfn = e2h_access, 7141 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl), 7142 .writefn = gt_virt_ctl_write, .raw_writefn = raw_write }, 7143 { .name = "CNTP_TVAL_EL02", .state = ARM_CP_STATE_AA64, 7144 .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 0, 7145 .type = ARM_CP_NO_RAW | ARM_CP_IO | ARM_CP_ALIAS, 7146 .access = PL2_RW, .accessfn = e2h_access, 7147 .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write }, 7148 { .name = "CNTV_TVAL_EL02", .state = ARM_CP_STATE_AA64, 7149 .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 0, 7150 .type = ARM_CP_NO_RAW | ARM_CP_IO | ARM_CP_ALIAS, 7151 .access = PL2_RW, .accessfn = e2h_access, 7152 .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write }, 7153 { .name = "CNTP_CVAL_EL02", .state = ARM_CP_STATE_AA64, 7154 .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 2, 7155 .type = ARM_CP_IO | ARM_CP_ALIAS, 7156 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), 7157 .access = PL2_RW, .accessfn = e2h_access, 7158 .writefn = gt_phys_cval_write, .raw_writefn = raw_write }, 7159 { .name = "CNTV_CVAL_EL02", .state = ARM_CP_STATE_AA64, 7160 .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 2, 7161 .type = ARM_CP_IO | ARM_CP_ALIAS, 7162 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), 7163 .access = PL2_RW, .accessfn = e2h_access, 7164 .writefn = gt_virt_cval_write, .raw_writefn = raw_write }, 7165 #endif 7166 }; 7167 7168 #ifndef CONFIG_USER_ONLY 7169 static const ARMCPRegInfo ats1e1_reginfo[] = { 7170 { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64, 7171 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0, 7172 .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, 7173 .writefn = ats_write64 }, 7174 { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64, 7175 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1, 7176 .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, 7177 .writefn = ats_write64 }, 7178 }; 7179 7180 static const ARMCPRegInfo ats1cp_reginfo[] = { 7181 { .name = "ATS1CPRP", 7182 .cp = 15, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0, 7183 .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, 7184 .writefn = ats_write }, 7185 { .name = "ATS1CPWP", 7186 .cp = 15, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1, 7187 .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, 7188 .writefn = ats_write }, 7189 }; 7190 #endif 7191 7192 /* 7193 * ACTLR2 and HACTLR2 map to ACTLR_EL1[63:32] and 7194 * ACTLR_EL2[63:32]. They exist only if the ID_MMFR4.AC2 field 7195 * is non-zero, which is never for ARMv7, optionally in ARMv8 7196 * and mandatorily for ARMv8.2 and up. 7197 * ACTLR2 is banked for S and NS if EL3 is AArch32. Since QEMU's 7198 * implementation is RAZ/WI we can ignore this detail, as we 7199 * do for ACTLR. 7200 */ 7201 static const ARMCPRegInfo actlr2_hactlr2_reginfo[] = { 7202 { .name = "ACTLR2", .state = ARM_CP_STATE_AA32, 7203 .cp = 15, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 3, 7204 .access = PL1_RW, .accessfn = access_tacr, 7205 .type = ARM_CP_CONST, .resetvalue = 0 }, 7206 { .name = "HACTLR2", .state = ARM_CP_STATE_AA32, 7207 .cp = 15, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 3, 7208 .access = PL2_RW, .type = ARM_CP_CONST, 7209 .resetvalue = 0 }, 7210 }; 7211 7212 void register_cp_regs_for_features(ARMCPU *cpu) 7213 { 7214 /* Register all the coprocessor registers based on feature bits */ 7215 CPUARMState *env = &cpu->env; 7216 if (arm_feature(env, ARM_FEATURE_M)) { 7217 /* M profile has no coprocessor registers */ 7218 return; 7219 } 7220 7221 define_arm_cp_regs(cpu, cp_reginfo); 7222 if (!arm_feature(env, ARM_FEATURE_V8)) { 7223 /* Must go early as it is full of wildcards that may be 7224 * overridden by later definitions. 7225 */ 7226 define_arm_cp_regs(cpu, not_v8_cp_reginfo); 7227 } 7228 7229 if (arm_feature(env, ARM_FEATURE_V6)) { 7230 /* The ID registers all have impdef reset values */ 7231 ARMCPRegInfo v6_idregs[] = { 7232 { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH, 7233 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, 7234 .access = PL1_R, .type = ARM_CP_CONST, 7235 .accessfn = access_aa32_tid3, 7236 .resetvalue = cpu->isar.id_pfr0 }, 7237 /* ID_PFR1 is not a plain ARM_CP_CONST because we don't know 7238 * the value of the GIC field until after we define these regs. 7239 */ 7240 { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH, 7241 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1, 7242 .access = PL1_R, .type = ARM_CP_NO_RAW, 7243 .accessfn = access_aa32_tid3, 7244 .readfn = id_pfr1_read, 7245 .writefn = arm_cp_write_ignore }, 7246 { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH, 7247 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2, 7248 .access = PL1_R, .type = ARM_CP_CONST, 7249 .accessfn = access_aa32_tid3, 7250 .resetvalue = cpu->isar.id_dfr0 }, 7251 { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH, 7252 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3, 7253 .access = PL1_R, .type = ARM_CP_CONST, 7254 .accessfn = access_aa32_tid3, 7255 .resetvalue = cpu->id_afr0 }, 7256 { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH, 7257 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4, 7258 .access = PL1_R, .type = ARM_CP_CONST, 7259 .accessfn = access_aa32_tid3, 7260 .resetvalue = cpu->isar.id_mmfr0 }, 7261 { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH, 7262 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5, 7263 .access = PL1_R, .type = ARM_CP_CONST, 7264 .accessfn = access_aa32_tid3, 7265 .resetvalue = cpu->isar.id_mmfr1 }, 7266 { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH, 7267 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6, 7268 .access = PL1_R, .type = ARM_CP_CONST, 7269 .accessfn = access_aa32_tid3, 7270 .resetvalue = cpu->isar.id_mmfr2 }, 7271 { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH, 7272 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7, 7273 .access = PL1_R, .type = ARM_CP_CONST, 7274 .accessfn = access_aa32_tid3, 7275 .resetvalue = cpu->isar.id_mmfr3 }, 7276 { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH, 7277 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, 7278 .access = PL1_R, .type = ARM_CP_CONST, 7279 .accessfn = access_aa32_tid3, 7280 .resetvalue = cpu->isar.id_isar0 }, 7281 { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH, 7282 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1, 7283 .access = PL1_R, .type = ARM_CP_CONST, 7284 .accessfn = access_aa32_tid3, 7285 .resetvalue = cpu->isar.id_isar1 }, 7286 { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH, 7287 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, 7288 .access = PL1_R, .type = ARM_CP_CONST, 7289 .accessfn = access_aa32_tid3, 7290 .resetvalue = cpu->isar.id_isar2 }, 7291 { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH, 7292 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3, 7293 .access = PL1_R, .type = ARM_CP_CONST, 7294 .accessfn = access_aa32_tid3, 7295 .resetvalue = cpu->isar.id_isar3 }, 7296 { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH, 7297 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4, 7298 .access = PL1_R, .type = ARM_CP_CONST, 7299 .accessfn = access_aa32_tid3, 7300 .resetvalue = cpu->isar.id_isar4 }, 7301 { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH, 7302 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5, 7303 .access = PL1_R, .type = ARM_CP_CONST, 7304 .accessfn = access_aa32_tid3, 7305 .resetvalue = cpu->isar.id_isar5 }, 7306 { .name = "ID_MMFR4", .state = ARM_CP_STATE_BOTH, 7307 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6, 7308 .access = PL1_R, .type = ARM_CP_CONST, 7309 .accessfn = access_aa32_tid3, 7310 .resetvalue = cpu->isar.id_mmfr4 }, 7311 { .name = "ID_ISAR6", .state = ARM_CP_STATE_BOTH, 7312 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7, 7313 .access = PL1_R, .type = ARM_CP_CONST, 7314 .accessfn = access_aa32_tid3, 7315 .resetvalue = cpu->isar.id_isar6 }, 7316 }; 7317 define_arm_cp_regs(cpu, v6_idregs); 7318 define_arm_cp_regs(cpu, v6_cp_reginfo); 7319 } else { 7320 define_arm_cp_regs(cpu, not_v6_cp_reginfo); 7321 } 7322 if (arm_feature(env, ARM_FEATURE_V6K)) { 7323 define_arm_cp_regs(cpu, v6k_cp_reginfo); 7324 } 7325 if (arm_feature(env, ARM_FEATURE_V7MP) && 7326 !arm_feature(env, ARM_FEATURE_PMSA)) { 7327 define_arm_cp_regs(cpu, v7mp_cp_reginfo); 7328 } 7329 if (arm_feature(env, ARM_FEATURE_V7VE)) { 7330 define_arm_cp_regs(cpu, pmovsset_cp_reginfo); 7331 } 7332 if (arm_feature(env, ARM_FEATURE_V7)) { 7333 ARMCPRegInfo clidr = { 7334 .name = "CLIDR", .state = ARM_CP_STATE_BOTH, 7335 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1, 7336 .access = PL1_R, .type = ARM_CP_CONST, 7337 .accessfn = access_aa64_tid2, 7338 .resetvalue = cpu->clidr 7339 }; 7340 define_one_arm_cp_reg(cpu, &clidr); 7341 define_arm_cp_regs(cpu, v7_cp_reginfo); 7342 define_debug_regs(cpu); 7343 define_pmu_regs(cpu); 7344 } else { 7345 define_arm_cp_regs(cpu, not_v7_cp_reginfo); 7346 } 7347 if (arm_feature(env, ARM_FEATURE_V8)) { 7348 /* AArch64 ID registers, which all have impdef reset values. 7349 * Note that within the ID register ranges the unused slots 7350 * must all RAZ, not UNDEF; future architecture versions may 7351 * define new registers here. 7352 */ 7353 ARMCPRegInfo v8_idregs[] = { 7354 /* 7355 * ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST in system 7356 * emulation because we don't know the right value for the 7357 * GIC field until after we define these regs. 7358 */ 7359 { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64, 7360 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0, 7361 .access = PL1_R, 7362 #ifdef CONFIG_USER_ONLY 7363 .type = ARM_CP_CONST, 7364 .resetvalue = cpu->isar.id_aa64pfr0 7365 #else 7366 .type = ARM_CP_NO_RAW, 7367 .accessfn = access_aa64_tid3, 7368 .readfn = id_aa64pfr0_read, 7369 .writefn = arm_cp_write_ignore 7370 #endif 7371 }, 7372 { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64, 7373 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1, 7374 .access = PL1_R, .type = ARM_CP_CONST, 7375 .accessfn = access_aa64_tid3, 7376 .resetvalue = cpu->isar.id_aa64pfr1}, 7377 { .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 7378 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2, 7379 .access = PL1_R, .type = ARM_CP_CONST, 7380 .accessfn = access_aa64_tid3, 7381 .resetvalue = 0 }, 7382 { .name = "ID_AA64PFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 7383 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3, 7384 .access = PL1_R, .type = ARM_CP_CONST, 7385 .accessfn = access_aa64_tid3, 7386 .resetvalue = 0 }, 7387 { .name = "ID_AA64ZFR0_EL1", .state = ARM_CP_STATE_AA64, 7388 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4, 7389 .access = PL1_R, .type = ARM_CP_CONST, 7390 .accessfn = access_aa64_tid3, 7391 .resetvalue = cpu->isar.id_aa64zfr0 }, 7392 { .name = "ID_AA64SMFR0_EL1", .state = ARM_CP_STATE_AA64, 7393 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5, 7394 .access = PL1_R, .type = ARM_CP_CONST, 7395 .accessfn = access_aa64_tid3, 7396 .resetvalue = cpu->isar.id_aa64smfr0 }, 7397 { .name = "ID_AA64PFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 7398 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6, 7399 .access = PL1_R, .type = ARM_CP_CONST, 7400 .accessfn = access_aa64_tid3, 7401 .resetvalue = 0 }, 7402 { .name = "ID_AA64PFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 7403 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 7, 7404 .access = PL1_R, .type = ARM_CP_CONST, 7405 .accessfn = access_aa64_tid3, 7406 .resetvalue = 0 }, 7407 { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64, 7408 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0, 7409 .access = PL1_R, .type = ARM_CP_CONST, 7410 .accessfn = access_aa64_tid3, 7411 .resetvalue = cpu->isar.id_aa64dfr0 }, 7412 { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64, 7413 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1, 7414 .access = PL1_R, .type = ARM_CP_CONST, 7415 .accessfn = access_aa64_tid3, 7416 .resetvalue = cpu->isar.id_aa64dfr1 }, 7417 { .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 7418 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2, 7419 .access = PL1_R, .type = ARM_CP_CONST, 7420 .accessfn = access_aa64_tid3, 7421 .resetvalue = 0 }, 7422 { .name = "ID_AA64DFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 7423 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 3, 7424 .access = PL1_R, .type = ARM_CP_CONST, 7425 .accessfn = access_aa64_tid3, 7426 .resetvalue = 0 }, 7427 { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64, 7428 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4, 7429 .access = PL1_R, .type = ARM_CP_CONST, 7430 .accessfn = access_aa64_tid3, 7431 .resetvalue = cpu->id_aa64afr0 }, 7432 { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64, 7433 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5, 7434 .access = PL1_R, .type = ARM_CP_CONST, 7435 .accessfn = access_aa64_tid3, 7436 .resetvalue = cpu->id_aa64afr1 }, 7437 { .name = "ID_AA64AFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 7438 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 6, 7439 .access = PL1_R, .type = ARM_CP_CONST, 7440 .accessfn = access_aa64_tid3, 7441 .resetvalue = 0 }, 7442 { .name = "ID_AA64AFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 7443 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 7, 7444 .access = PL1_R, .type = ARM_CP_CONST, 7445 .accessfn = access_aa64_tid3, 7446 .resetvalue = 0 }, 7447 { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64, 7448 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0, 7449 .access = PL1_R, .type = ARM_CP_CONST, 7450 .accessfn = access_aa64_tid3, 7451 .resetvalue = cpu->isar.id_aa64isar0 }, 7452 { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64, 7453 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1, 7454 .access = PL1_R, .type = ARM_CP_CONST, 7455 .accessfn = access_aa64_tid3, 7456 .resetvalue = cpu->isar.id_aa64isar1 }, 7457 { .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 7458 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2, 7459 .access = PL1_R, .type = ARM_CP_CONST, 7460 .accessfn = access_aa64_tid3, 7461 .resetvalue = 0 }, 7462 { .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 7463 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3, 7464 .access = PL1_R, .type = ARM_CP_CONST, 7465 .accessfn = access_aa64_tid3, 7466 .resetvalue = 0 }, 7467 { .name = "ID_AA64ISAR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 7468 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 4, 7469 .access = PL1_R, .type = ARM_CP_CONST, 7470 .accessfn = access_aa64_tid3, 7471 .resetvalue = 0 }, 7472 { .name = "ID_AA64ISAR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 7473 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 5, 7474 .access = PL1_R, .type = ARM_CP_CONST, 7475 .accessfn = access_aa64_tid3, 7476 .resetvalue = 0 }, 7477 { .name = "ID_AA64ISAR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 7478 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 6, 7479 .access = PL1_R, .type = ARM_CP_CONST, 7480 .accessfn = access_aa64_tid3, 7481 .resetvalue = 0 }, 7482 { .name = "ID_AA64ISAR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 7483 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 7, 7484 .access = PL1_R, .type = ARM_CP_CONST, 7485 .accessfn = access_aa64_tid3, 7486 .resetvalue = 0 }, 7487 { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64, 7488 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, 7489 .access = PL1_R, .type = ARM_CP_CONST, 7490 .accessfn = access_aa64_tid3, 7491 .resetvalue = cpu->isar.id_aa64mmfr0 }, 7492 { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64, 7493 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1, 7494 .access = PL1_R, .type = ARM_CP_CONST, 7495 .accessfn = access_aa64_tid3, 7496 .resetvalue = cpu->isar.id_aa64mmfr1 }, 7497 { .name = "ID_AA64MMFR2_EL1", .state = ARM_CP_STATE_AA64, 7498 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2, 7499 .access = PL1_R, .type = ARM_CP_CONST, 7500 .accessfn = access_aa64_tid3, 7501 .resetvalue = cpu->isar.id_aa64mmfr2 }, 7502 { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 7503 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3, 7504 .access = PL1_R, .type = ARM_CP_CONST, 7505 .accessfn = access_aa64_tid3, 7506 .resetvalue = 0 }, 7507 { .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 7508 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4, 7509 .access = PL1_R, .type = ARM_CP_CONST, 7510 .accessfn = access_aa64_tid3, 7511 .resetvalue = 0 }, 7512 { .name = "ID_AA64MMFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 7513 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5, 7514 .access = PL1_R, .type = ARM_CP_CONST, 7515 .accessfn = access_aa64_tid3, 7516 .resetvalue = 0 }, 7517 { .name = "ID_AA64MMFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 7518 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 6, 7519 .access = PL1_R, .type = ARM_CP_CONST, 7520 .accessfn = access_aa64_tid3, 7521 .resetvalue = 0 }, 7522 { .name = "ID_AA64MMFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 7523 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 7, 7524 .access = PL1_R, .type = ARM_CP_CONST, 7525 .accessfn = access_aa64_tid3, 7526 .resetvalue = 0 }, 7527 { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64, 7528 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0, 7529 .access = PL1_R, .type = ARM_CP_CONST, 7530 .accessfn = access_aa64_tid3, 7531 .resetvalue = cpu->isar.mvfr0 }, 7532 { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64, 7533 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1, 7534 .access = PL1_R, .type = ARM_CP_CONST, 7535 .accessfn = access_aa64_tid3, 7536 .resetvalue = cpu->isar.mvfr1 }, 7537 { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64, 7538 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2, 7539 .access = PL1_R, .type = ARM_CP_CONST, 7540 .accessfn = access_aa64_tid3, 7541 .resetvalue = cpu->isar.mvfr2 }, 7542 { .name = "MVFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 7543 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3, 7544 .access = PL1_R, .type = ARM_CP_CONST, 7545 .accessfn = access_aa64_tid3, 7546 .resetvalue = 0 }, 7547 { .name = "ID_PFR2", .state = ARM_CP_STATE_BOTH, 7548 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4, 7549 .access = PL1_R, .type = ARM_CP_CONST, 7550 .accessfn = access_aa64_tid3, 7551 .resetvalue = cpu->isar.id_pfr2 }, 7552 { .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 7553 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5, 7554 .access = PL1_R, .type = ARM_CP_CONST, 7555 .accessfn = access_aa64_tid3, 7556 .resetvalue = 0 }, 7557 { .name = "MVFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 7558 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6, 7559 .access = PL1_R, .type = ARM_CP_CONST, 7560 .accessfn = access_aa64_tid3, 7561 .resetvalue = 0 }, 7562 { .name = "MVFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 7563 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7, 7564 .access = PL1_R, .type = ARM_CP_CONST, 7565 .accessfn = access_aa64_tid3, 7566 .resetvalue = 0 }, 7567 { .name = "PMCEID0", .state = ARM_CP_STATE_AA32, 7568 .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6, 7569 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, 7570 .resetvalue = extract64(cpu->pmceid0, 0, 32) }, 7571 { .name = "PMCEID0_EL0", .state = ARM_CP_STATE_AA64, 7572 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 6, 7573 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, 7574 .resetvalue = cpu->pmceid0 }, 7575 { .name = "PMCEID1", .state = ARM_CP_STATE_AA32, 7576 .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 7, 7577 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, 7578 .resetvalue = extract64(cpu->pmceid1, 0, 32) }, 7579 { .name = "PMCEID1_EL0", .state = ARM_CP_STATE_AA64, 7580 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7, 7581 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, 7582 .resetvalue = cpu->pmceid1 }, 7583 }; 7584 #ifdef CONFIG_USER_ONLY 7585 static const ARMCPRegUserSpaceInfo v8_user_idregs[] = { 7586 { .name = "ID_AA64PFR0_EL1", 7587 .exported_bits = 0x000f000f00ff0000, 7588 .fixed_bits = 0x0000000000000011 }, 7589 { .name = "ID_AA64PFR1_EL1", 7590 .exported_bits = 0x00000000000000f0 }, 7591 { .name = "ID_AA64PFR*_EL1_RESERVED", 7592 .is_glob = true }, 7593 { .name = "ID_AA64ZFR0_EL1" }, 7594 { .name = "ID_AA64MMFR0_EL1", 7595 .fixed_bits = 0x00000000ff000000 }, 7596 { .name = "ID_AA64MMFR1_EL1" }, 7597 { .name = "ID_AA64MMFR*_EL1_RESERVED", 7598 .is_glob = true }, 7599 { .name = "ID_AA64DFR0_EL1", 7600 .fixed_bits = 0x0000000000000006 }, 7601 { .name = "ID_AA64DFR1_EL1" }, 7602 { .name = "ID_AA64DFR*_EL1_RESERVED", 7603 .is_glob = true }, 7604 { .name = "ID_AA64AFR*", 7605 .is_glob = true }, 7606 { .name = "ID_AA64ISAR0_EL1", 7607 .exported_bits = 0x00fffffff0fffff0 }, 7608 { .name = "ID_AA64ISAR1_EL1", 7609 .exported_bits = 0x000000f0ffffffff }, 7610 { .name = "ID_AA64ISAR*_EL1_RESERVED", 7611 .is_glob = true }, 7612 }; 7613 modify_arm_cp_regs(v8_idregs, v8_user_idregs); 7614 #endif 7615 /* RVBAR_EL1 is only implemented if EL1 is the highest EL */ 7616 if (!arm_feature(env, ARM_FEATURE_EL3) && 7617 !arm_feature(env, ARM_FEATURE_EL2)) { 7618 ARMCPRegInfo rvbar = { 7619 .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64, 7620 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, 7621 .access = PL1_R, 7622 .fieldoffset = offsetof(CPUARMState, cp15.rvbar), 7623 }; 7624 define_one_arm_cp_reg(cpu, &rvbar); 7625 } 7626 define_arm_cp_regs(cpu, v8_idregs); 7627 define_arm_cp_regs(cpu, v8_cp_reginfo); 7628 } 7629 7630 /* 7631 * Register the base EL2 cpregs. 7632 * Pre v8, these registers are implemented only as part of the 7633 * Virtualization Extensions (EL2 present). Beginning with v8, 7634 * if EL2 is missing but EL3 is enabled, mostly these become 7635 * RES0 from EL3, with some specific exceptions. 7636 */ 7637 if (arm_feature(env, ARM_FEATURE_EL2) 7638 || (arm_feature(env, ARM_FEATURE_EL3) 7639 && arm_feature(env, ARM_FEATURE_V8))) { 7640 uint64_t vmpidr_def = mpidr_read_val(env); 7641 ARMCPRegInfo vpidr_regs[] = { 7642 { .name = "VPIDR", .state = ARM_CP_STATE_AA32, 7643 .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, 7644 .access = PL2_RW, .accessfn = access_el3_aa32ns, 7645 .resetvalue = cpu->midr, 7646 .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ, 7647 .fieldoffset = offsetoflow32(CPUARMState, cp15.vpidr_el2) }, 7648 { .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64, 7649 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, 7650 .access = PL2_RW, .resetvalue = cpu->midr, 7651 .type = ARM_CP_EL3_NO_EL2_C_NZ, 7652 .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, 7653 { .name = "VMPIDR", .state = ARM_CP_STATE_AA32, 7654 .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, 7655 .access = PL2_RW, .accessfn = access_el3_aa32ns, 7656 .resetvalue = vmpidr_def, 7657 .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ, 7658 .fieldoffset = offsetoflow32(CPUARMState, cp15.vmpidr_el2) }, 7659 { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64, 7660 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, 7661 .access = PL2_RW, .resetvalue = vmpidr_def, 7662 .type = ARM_CP_EL3_NO_EL2_C_NZ, 7663 .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) }, 7664 }; 7665 /* 7666 * The only field of MDCR_EL2 that has a defined architectural reset 7667 * value is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N. 7668 */ 7669 ARMCPRegInfo mdcr_el2 = { 7670 .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, 7671 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1, 7672 .access = PL2_RW, .resetvalue = pmu_num_counters(env), 7673 .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), 7674 }; 7675 define_one_arm_cp_reg(cpu, &mdcr_el2); 7676 define_arm_cp_regs(cpu, vpidr_regs); 7677 define_arm_cp_regs(cpu, el2_cp_reginfo); 7678 if (arm_feature(env, ARM_FEATURE_V8)) { 7679 define_arm_cp_regs(cpu, el2_v8_cp_reginfo); 7680 } 7681 if (cpu_isar_feature(aa64_sel2, cpu)) { 7682 define_arm_cp_regs(cpu, el2_sec_cp_reginfo); 7683 } 7684 /* RVBAR_EL2 is only implemented if EL2 is the highest EL */ 7685 if (!arm_feature(env, ARM_FEATURE_EL3)) { 7686 ARMCPRegInfo rvbar = { 7687 .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64, 7688 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1, 7689 .access = PL2_R, 7690 .fieldoffset = offsetof(CPUARMState, cp15.rvbar), 7691 }; 7692 define_one_arm_cp_reg(cpu, &rvbar); 7693 } 7694 } 7695 7696 /* Register the base EL3 cpregs. */ 7697 if (arm_feature(env, ARM_FEATURE_EL3)) { 7698 define_arm_cp_regs(cpu, el3_cp_reginfo); 7699 ARMCPRegInfo el3_regs[] = { 7700 { .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64, 7701 .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1, 7702 .access = PL3_R, 7703 .fieldoffset = offsetof(CPUARMState, cp15.rvbar), 7704 }, 7705 { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64, 7706 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0, 7707 .access = PL3_RW, 7708 .raw_writefn = raw_write, .writefn = sctlr_write, 7709 .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]), 7710 .resetvalue = cpu->reset_sctlr }, 7711 }; 7712 7713 define_arm_cp_regs(cpu, el3_regs); 7714 } 7715 /* The behaviour of NSACR is sufficiently various that we don't 7716 * try to describe it in a single reginfo: 7717 * if EL3 is 64 bit, then trap to EL3 from S EL1, 7718 * reads as constant 0xc00 from NS EL1 and NS EL2 7719 * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2 7720 * if v7 without EL3, register doesn't exist 7721 * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2 7722 */ 7723 if (arm_feature(env, ARM_FEATURE_EL3)) { 7724 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 7725 static const ARMCPRegInfo nsacr = { 7726 .name = "NSACR", .type = ARM_CP_CONST, 7727 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, 7728 .access = PL1_RW, .accessfn = nsacr_access, 7729 .resetvalue = 0xc00 7730 }; 7731 define_one_arm_cp_reg(cpu, &nsacr); 7732 } else { 7733 static const ARMCPRegInfo nsacr = { 7734 .name = "NSACR", 7735 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, 7736 .access = PL3_RW | PL1_R, 7737 .resetvalue = 0, 7738 .fieldoffset = offsetof(CPUARMState, cp15.nsacr) 7739 }; 7740 define_one_arm_cp_reg(cpu, &nsacr); 7741 } 7742 } else { 7743 if (arm_feature(env, ARM_FEATURE_V8)) { 7744 static const ARMCPRegInfo nsacr = { 7745 .name = "NSACR", .type = ARM_CP_CONST, 7746 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, 7747 .access = PL1_R, 7748 .resetvalue = 0xc00 7749 }; 7750 define_one_arm_cp_reg(cpu, &nsacr); 7751 } 7752 } 7753 7754 if (arm_feature(env, ARM_FEATURE_PMSA)) { 7755 if (arm_feature(env, ARM_FEATURE_V6)) { 7756 /* PMSAv6 not implemented */ 7757 assert(arm_feature(env, ARM_FEATURE_V7)); 7758 define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); 7759 define_arm_cp_regs(cpu, pmsav7_cp_reginfo); 7760 } else { 7761 define_arm_cp_regs(cpu, pmsav5_cp_reginfo); 7762 } 7763 } else { 7764 define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); 7765 define_arm_cp_regs(cpu, vmsa_cp_reginfo); 7766 /* TTCBR2 is introduced with ARMv8.2-AA32HPD. */ 7767 if (cpu_isar_feature(aa32_hpd, cpu)) { 7768 define_one_arm_cp_reg(cpu, &ttbcr2_reginfo); 7769 } 7770 } 7771 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { 7772 define_arm_cp_regs(cpu, t2ee_cp_reginfo); 7773 } 7774 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { 7775 define_arm_cp_regs(cpu, generic_timer_cp_reginfo); 7776 } 7777 if (arm_feature(env, ARM_FEATURE_VAPA)) { 7778 define_arm_cp_regs(cpu, vapa_cp_reginfo); 7779 } 7780 if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) { 7781 define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo); 7782 } 7783 if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) { 7784 define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo); 7785 } 7786 if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) { 7787 define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo); 7788 } 7789 if (arm_feature(env, ARM_FEATURE_OMAPCP)) { 7790 define_arm_cp_regs(cpu, omap_cp_reginfo); 7791 } 7792 if (arm_feature(env, ARM_FEATURE_STRONGARM)) { 7793 define_arm_cp_regs(cpu, strongarm_cp_reginfo); 7794 } 7795 if (arm_feature(env, ARM_FEATURE_XSCALE)) { 7796 define_arm_cp_regs(cpu, xscale_cp_reginfo); 7797 } 7798 if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) { 7799 define_arm_cp_regs(cpu, dummy_c15_cp_reginfo); 7800 } 7801 if (arm_feature(env, ARM_FEATURE_LPAE)) { 7802 define_arm_cp_regs(cpu, lpae_cp_reginfo); 7803 } 7804 if (cpu_isar_feature(aa32_jazelle, cpu)) { 7805 define_arm_cp_regs(cpu, jazelle_regs); 7806 } 7807 /* Slightly awkwardly, the OMAP and StrongARM cores need all of 7808 * cp15 crn=0 to be writes-ignored, whereas for other cores they should 7809 * be read-only (ie write causes UNDEF exception). 7810 */ 7811 { 7812 ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = { 7813 /* Pre-v8 MIDR space. 7814 * Note that the MIDR isn't a simple constant register because 7815 * of the TI925 behaviour where writes to another register can 7816 * cause the MIDR value to change. 7817 * 7818 * Unimplemented registers in the c15 0 0 0 space default to 7819 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR 7820 * and friends override accordingly. 7821 */ 7822 { .name = "MIDR", 7823 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY, 7824 .access = PL1_R, .resetvalue = cpu->midr, 7825 .writefn = arm_cp_write_ignore, .raw_writefn = raw_write, 7826 .readfn = midr_read, 7827 .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), 7828 .type = ARM_CP_OVERRIDE }, 7829 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */ 7830 { .name = "DUMMY", 7831 .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY, 7832 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 7833 { .name = "DUMMY", 7834 .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY, 7835 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 7836 { .name = "DUMMY", 7837 .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY, 7838 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 7839 { .name = "DUMMY", 7840 .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY, 7841 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 7842 { .name = "DUMMY", 7843 .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY, 7844 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 7845 }; 7846 ARMCPRegInfo id_v8_midr_cp_reginfo[] = { 7847 { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH, 7848 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0, 7849 .access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr, 7850 .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), 7851 .readfn = midr_read }, 7852 /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */ 7853 { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST, 7854 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4, 7855 .access = PL1_R, .resetvalue = cpu->midr }, 7856 { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST, 7857 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7, 7858 .access = PL1_R, .resetvalue = cpu->midr }, 7859 { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH, 7860 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6, 7861 .access = PL1_R, 7862 .accessfn = access_aa64_tid1, 7863 .type = ARM_CP_CONST, .resetvalue = cpu->revidr }, 7864 }; 7865 ARMCPRegInfo id_cp_reginfo[] = { 7866 /* These are common to v8 and pre-v8 */ 7867 { .name = "CTR", 7868 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1, 7869 .access = PL1_R, .accessfn = ctr_el0_access, 7870 .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, 7871 { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64, 7872 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0, 7873 .access = PL0_R, .accessfn = ctr_el0_access, 7874 .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, 7875 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */ 7876 { .name = "TCMTR", 7877 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2, 7878 .access = PL1_R, 7879 .accessfn = access_aa32_tid1, 7880 .type = ARM_CP_CONST, .resetvalue = 0 }, 7881 }; 7882 /* TLBTR is specific to VMSA */ 7883 ARMCPRegInfo id_tlbtr_reginfo = { 7884 .name = "TLBTR", 7885 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3, 7886 .access = PL1_R, 7887 .accessfn = access_aa32_tid1, 7888 .type = ARM_CP_CONST, .resetvalue = 0, 7889 }; 7890 /* MPUIR is specific to PMSA V6+ */ 7891 ARMCPRegInfo id_mpuir_reginfo = { 7892 .name = "MPUIR", 7893 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4, 7894 .access = PL1_R, .type = ARM_CP_CONST, 7895 .resetvalue = cpu->pmsav7_dregion << 8 7896 }; 7897 static const ARMCPRegInfo crn0_wi_reginfo = { 7898 .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY, 7899 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W, 7900 .type = ARM_CP_NOP | ARM_CP_OVERRIDE 7901 }; 7902 #ifdef CONFIG_USER_ONLY 7903 static const ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = { 7904 { .name = "MIDR_EL1", 7905 .exported_bits = 0x00000000ffffffff }, 7906 { .name = "REVIDR_EL1" }, 7907 }; 7908 modify_arm_cp_regs(id_v8_midr_cp_reginfo, id_v8_user_midr_cp_reginfo); 7909 #endif 7910 if (arm_feature(env, ARM_FEATURE_OMAPCP) || 7911 arm_feature(env, ARM_FEATURE_STRONGARM)) { 7912 size_t i; 7913 /* Register the blanket "writes ignored" value first to cover the 7914 * whole space. Then update the specific ID registers to allow write 7915 * access, so that they ignore writes rather than causing them to 7916 * UNDEF. 7917 */ 7918 define_one_arm_cp_reg(cpu, &crn0_wi_reginfo); 7919 for (i = 0; i < ARRAY_SIZE(id_pre_v8_midr_cp_reginfo); ++i) { 7920 id_pre_v8_midr_cp_reginfo[i].access = PL1_RW; 7921 } 7922 for (i = 0; i < ARRAY_SIZE(id_cp_reginfo); ++i) { 7923 id_cp_reginfo[i].access = PL1_RW; 7924 } 7925 id_mpuir_reginfo.access = PL1_RW; 7926 id_tlbtr_reginfo.access = PL1_RW; 7927 } 7928 if (arm_feature(env, ARM_FEATURE_V8)) { 7929 define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo); 7930 } else { 7931 define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo); 7932 } 7933 define_arm_cp_regs(cpu, id_cp_reginfo); 7934 if (!arm_feature(env, ARM_FEATURE_PMSA)) { 7935 define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo); 7936 } else if (arm_feature(env, ARM_FEATURE_V7)) { 7937 define_one_arm_cp_reg(cpu, &id_mpuir_reginfo); 7938 } 7939 } 7940 7941 if (arm_feature(env, ARM_FEATURE_MPIDR)) { 7942 ARMCPRegInfo mpidr_cp_reginfo[] = { 7943 { .name = "MPIDR_EL1", .state = ARM_CP_STATE_BOTH, 7944 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5, 7945 .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW }, 7946 }; 7947 #ifdef CONFIG_USER_ONLY 7948 static const ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] = { 7949 { .name = "MPIDR_EL1", 7950 .fixed_bits = 0x0000000080000000 }, 7951 }; 7952 modify_arm_cp_regs(mpidr_cp_reginfo, mpidr_user_cp_reginfo); 7953 #endif 7954 define_arm_cp_regs(cpu, mpidr_cp_reginfo); 7955 } 7956 7957 if (arm_feature(env, ARM_FEATURE_AUXCR)) { 7958 ARMCPRegInfo auxcr_reginfo[] = { 7959 { .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH, 7960 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1, 7961 .access = PL1_RW, .accessfn = access_tacr, 7962 .type = ARM_CP_CONST, .resetvalue = cpu->reset_auxcr }, 7963 { .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH, 7964 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1, 7965 .access = PL2_RW, .type = ARM_CP_CONST, 7966 .resetvalue = 0 }, 7967 { .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64, 7968 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1, 7969 .access = PL3_RW, .type = ARM_CP_CONST, 7970 .resetvalue = 0 }, 7971 }; 7972 define_arm_cp_regs(cpu, auxcr_reginfo); 7973 if (cpu_isar_feature(aa32_ac2, cpu)) { 7974 define_arm_cp_regs(cpu, actlr2_hactlr2_reginfo); 7975 } 7976 } 7977 7978 if (arm_feature(env, ARM_FEATURE_CBAR)) { 7979 /* 7980 * CBAR is IMPDEF, but common on Arm Cortex-A implementations. 7981 * There are two flavours: 7982 * (1) older 32-bit only cores have a simple 32-bit CBAR 7983 * (2) 64-bit cores have a 64-bit CBAR visible to AArch64, plus a 7984 * 32-bit register visible to AArch32 at a different encoding 7985 * to the "flavour 1" register and with the bits rearranged to 7986 * be able to squash a 64-bit address into the 32-bit view. 7987 * We distinguish the two via the ARM_FEATURE_AARCH64 flag, but 7988 * in future if we support AArch32-only configs of some of the 7989 * AArch64 cores we might need to add a specific feature flag 7990 * to indicate cores with "flavour 2" CBAR. 7991 */ 7992 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 7993 /* 32 bit view is [31:18] 0...0 [43:32]. */ 7994 uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18) 7995 | extract64(cpu->reset_cbar, 32, 12); 7996 ARMCPRegInfo cbar_reginfo[] = { 7997 { .name = "CBAR", 7998 .type = ARM_CP_CONST, 7999 .cp = 15, .crn = 15, .crm = 3, .opc1 = 1, .opc2 = 0, 8000 .access = PL1_R, .resetvalue = cbar32 }, 8001 { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64, 8002 .type = ARM_CP_CONST, 8003 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0, 8004 .access = PL1_R, .resetvalue = cpu->reset_cbar }, 8005 }; 8006 /* We don't implement a r/w 64 bit CBAR currently */ 8007 assert(arm_feature(env, ARM_FEATURE_CBAR_RO)); 8008 define_arm_cp_regs(cpu, cbar_reginfo); 8009 } else { 8010 ARMCPRegInfo cbar = { 8011 .name = "CBAR", 8012 .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0, 8013 .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar, 8014 .fieldoffset = offsetof(CPUARMState, 8015 cp15.c15_config_base_address) 8016 }; 8017 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 8018 cbar.access = PL1_R; 8019 cbar.fieldoffset = 0; 8020 cbar.type = ARM_CP_CONST; 8021 } 8022 define_one_arm_cp_reg(cpu, &cbar); 8023 } 8024 } 8025 8026 if (arm_feature(env, ARM_FEATURE_VBAR)) { 8027 static const ARMCPRegInfo vbar_cp_reginfo[] = { 8028 { .name = "VBAR", .state = ARM_CP_STATE_BOTH, 8029 .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0, 8030 .access = PL1_RW, .writefn = vbar_write, 8031 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s), 8032 offsetof(CPUARMState, cp15.vbar_ns) }, 8033 .resetvalue = 0 }, 8034 }; 8035 define_arm_cp_regs(cpu, vbar_cp_reginfo); 8036 } 8037 8038 /* Generic registers whose values depend on the implementation */ 8039 { 8040 ARMCPRegInfo sctlr = { 8041 .name = "SCTLR", .state = ARM_CP_STATE_BOTH, 8042 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, 8043 .access = PL1_RW, .accessfn = access_tvm_trvm, 8044 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s), 8045 offsetof(CPUARMState, cp15.sctlr_ns) }, 8046 .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr, 8047 .raw_writefn = raw_write, 8048 }; 8049 if (arm_feature(env, ARM_FEATURE_XSCALE)) { 8050 /* Normally we would always end the TB on an SCTLR write, but Linux 8051 * arch/arm/mach-pxa/sleep.S expects two instructions following 8052 * an MMU enable to execute from cache. Imitate this behaviour. 8053 */ 8054 sctlr.type |= ARM_CP_SUPPRESS_TB_END; 8055 } 8056 define_one_arm_cp_reg(cpu, &sctlr); 8057 } 8058 8059 if (cpu_isar_feature(aa64_lor, cpu)) { 8060 define_arm_cp_regs(cpu, lor_reginfo); 8061 } 8062 if (cpu_isar_feature(aa64_pan, cpu)) { 8063 define_one_arm_cp_reg(cpu, &pan_reginfo); 8064 } 8065 #ifndef CONFIG_USER_ONLY 8066 if (cpu_isar_feature(aa64_ats1e1, cpu)) { 8067 define_arm_cp_regs(cpu, ats1e1_reginfo); 8068 } 8069 if (cpu_isar_feature(aa32_ats1e1, cpu)) { 8070 define_arm_cp_regs(cpu, ats1cp_reginfo); 8071 } 8072 #endif 8073 if (cpu_isar_feature(aa64_uao, cpu)) { 8074 define_one_arm_cp_reg(cpu, &uao_reginfo); 8075 } 8076 8077 if (cpu_isar_feature(aa64_dit, cpu)) { 8078 define_one_arm_cp_reg(cpu, &dit_reginfo); 8079 } 8080 if (cpu_isar_feature(aa64_ssbs, cpu)) { 8081 define_one_arm_cp_reg(cpu, &ssbs_reginfo); 8082 } 8083 if (cpu_isar_feature(any_ras, cpu)) { 8084 define_arm_cp_regs(cpu, minimal_ras_reginfo); 8085 } 8086 8087 if (cpu_isar_feature(aa64_vh, cpu) || 8088 cpu_isar_feature(aa64_debugv8p2, cpu)) { 8089 define_one_arm_cp_reg(cpu, &contextidr_el2); 8090 } 8091 if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) { 8092 define_arm_cp_regs(cpu, vhe_reginfo); 8093 } 8094 8095 if (cpu_isar_feature(aa64_sve, cpu)) { 8096 define_arm_cp_regs(cpu, zcr_reginfo); 8097 } 8098 8099 if (cpu_isar_feature(aa64_hcx, cpu)) { 8100 define_one_arm_cp_reg(cpu, &hcrx_el2_reginfo); 8101 } 8102 8103 #ifdef TARGET_AARCH64 8104 if (cpu_isar_feature(aa64_sme, cpu)) { 8105 define_arm_cp_regs(cpu, sme_reginfo); 8106 } 8107 if (cpu_isar_feature(aa64_pauth, cpu)) { 8108 define_arm_cp_regs(cpu, pauth_reginfo); 8109 } 8110 if (cpu_isar_feature(aa64_rndr, cpu)) { 8111 define_arm_cp_regs(cpu, rndr_reginfo); 8112 } 8113 if (cpu_isar_feature(aa64_tlbirange, cpu)) { 8114 define_arm_cp_regs(cpu, tlbirange_reginfo); 8115 } 8116 if (cpu_isar_feature(aa64_tlbios, cpu)) { 8117 define_arm_cp_regs(cpu, tlbios_reginfo); 8118 } 8119 #ifndef CONFIG_USER_ONLY 8120 /* Data Cache clean instructions up to PoP */ 8121 if (cpu_isar_feature(aa64_dcpop, cpu)) { 8122 define_one_arm_cp_reg(cpu, dcpop_reg); 8123 8124 if (cpu_isar_feature(aa64_dcpodp, cpu)) { 8125 define_one_arm_cp_reg(cpu, dcpodp_reg); 8126 } 8127 } 8128 #endif /*CONFIG_USER_ONLY*/ 8129 8130 /* 8131 * If full MTE is enabled, add all of the system registers. 8132 * If only "instructions available at EL0" are enabled, 8133 * then define only a RAZ/WI version of PSTATE.TCO. 8134 */ 8135 if (cpu_isar_feature(aa64_mte, cpu)) { 8136 define_arm_cp_regs(cpu, mte_reginfo); 8137 define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo); 8138 } else if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) { 8139 define_arm_cp_regs(cpu, mte_tco_ro_reginfo); 8140 define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo); 8141 } 8142 8143 if (cpu_isar_feature(aa64_scxtnum, cpu)) { 8144 define_arm_cp_regs(cpu, scxtnum_reginfo); 8145 } 8146 #endif 8147 8148 if (cpu_isar_feature(any_predinv, cpu)) { 8149 define_arm_cp_regs(cpu, predinv_reginfo); 8150 } 8151 8152 if (cpu_isar_feature(any_ccidx, cpu)) { 8153 define_arm_cp_regs(cpu, ccsidr2_reginfo); 8154 } 8155 8156 #ifndef CONFIG_USER_ONLY 8157 /* 8158 * Register redirections and aliases must be done last, 8159 * after the registers from the other extensions have been defined. 8160 */ 8161 if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) { 8162 define_arm_vh_e2h_redirects_aliases(cpu); 8163 } 8164 #endif 8165 } 8166 8167 /* Sort alphabetically by type name, except for "any". */ 8168 static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b) 8169 { 8170 ObjectClass *class_a = (ObjectClass *)a; 8171 ObjectClass *class_b = (ObjectClass *)b; 8172 const char *name_a, *name_b; 8173 8174 name_a = object_class_get_name(class_a); 8175 name_b = object_class_get_name(class_b); 8176 if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) { 8177 return 1; 8178 } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) { 8179 return -1; 8180 } else { 8181 return strcmp(name_a, name_b); 8182 } 8183 } 8184 8185 static void arm_cpu_list_entry(gpointer data, gpointer user_data) 8186 { 8187 ObjectClass *oc = data; 8188 CPUClass *cc = CPU_CLASS(oc); 8189 const char *typename; 8190 char *name; 8191 8192 typename = object_class_get_name(oc); 8193 name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU)); 8194 if (cc->deprecation_note) { 8195 qemu_printf(" %s (deprecated)\n", name); 8196 } else { 8197 qemu_printf(" %s\n", name); 8198 } 8199 g_free(name); 8200 } 8201 8202 void arm_cpu_list(void) 8203 { 8204 GSList *list; 8205 8206 list = object_class_get_list(TYPE_ARM_CPU, false); 8207 list = g_slist_sort(list, arm_cpu_list_compare); 8208 qemu_printf("Available CPUs:\n"); 8209 g_slist_foreach(list, arm_cpu_list_entry, NULL); 8210 g_slist_free(list); 8211 } 8212 8213 static void arm_cpu_add_definition(gpointer data, gpointer user_data) 8214 { 8215 ObjectClass *oc = data; 8216 CpuDefinitionInfoList **cpu_list = user_data; 8217 CpuDefinitionInfo *info; 8218 const char *typename; 8219 8220 typename = object_class_get_name(oc); 8221 info = g_malloc0(sizeof(*info)); 8222 info->name = g_strndup(typename, 8223 strlen(typename) - strlen("-" TYPE_ARM_CPU)); 8224 info->q_typename = g_strdup(typename); 8225 8226 QAPI_LIST_PREPEND(*cpu_list, info); 8227 } 8228 8229 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 8230 { 8231 CpuDefinitionInfoList *cpu_list = NULL; 8232 GSList *list; 8233 8234 list = object_class_get_list(TYPE_ARM_CPU, false); 8235 g_slist_foreach(list, arm_cpu_add_definition, &cpu_list); 8236 g_slist_free(list); 8237 8238 return cpu_list; 8239 } 8240 8241 /* 8242 * Private utility function for define_one_arm_cp_reg_with_opaque(): 8243 * add a single reginfo struct to the hash table. 8244 */ 8245 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, 8246 void *opaque, CPState state, 8247 CPSecureState secstate, 8248 int crm, int opc1, int opc2, 8249 const char *name) 8250 { 8251 CPUARMState *env = &cpu->env; 8252 uint32_t key; 8253 ARMCPRegInfo *r2; 8254 bool is64 = r->type & ARM_CP_64BIT; 8255 bool ns = secstate & ARM_CP_SECSTATE_NS; 8256 int cp = r->cp; 8257 size_t name_len; 8258 bool make_const; 8259 8260 switch (state) { 8261 case ARM_CP_STATE_AA32: 8262 /* We assume it is a cp15 register if the .cp field is left unset. */ 8263 if (cp == 0 && r->state == ARM_CP_STATE_BOTH) { 8264 cp = 15; 8265 } 8266 key = ENCODE_CP_REG(cp, is64, ns, r->crn, crm, opc1, opc2); 8267 break; 8268 case ARM_CP_STATE_AA64: 8269 /* 8270 * To allow abbreviation of ARMCPRegInfo definitions, we treat 8271 * cp == 0 as equivalent to the value for "standard guest-visible 8272 * sysreg". STATE_BOTH definitions are also always "standard sysreg" 8273 * in their AArch64 view (the .cp value may be non-zero for the 8274 * benefit of the AArch32 view). 8275 */ 8276 if (cp == 0 || r->state == ARM_CP_STATE_BOTH) { 8277 cp = CP_REG_ARM64_SYSREG_CP; 8278 } 8279 key = ENCODE_AA64_CP_REG(cp, r->crn, crm, r->opc0, opc1, opc2); 8280 break; 8281 default: 8282 g_assert_not_reached(); 8283 } 8284 8285 /* Overriding of an existing definition must be explicitly requested. */ 8286 if (!(r->type & ARM_CP_OVERRIDE)) { 8287 const ARMCPRegInfo *oldreg = get_arm_cp_reginfo(cpu->cp_regs, key); 8288 if (oldreg) { 8289 assert(oldreg->type & ARM_CP_OVERRIDE); 8290 } 8291 } 8292 8293 /* 8294 * Eliminate registers that are not present because the EL is missing. 8295 * Doing this here makes it easier to put all registers for a given 8296 * feature into the same ARMCPRegInfo array and define them all at once. 8297 */ 8298 make_const = false; 8299 if (arm_feature(env, ARM_FEATURE_EL3)) { 8300 /* 8301 * An EL2 register without EL2 but with EL3 is (usually) RES0. 8302 * See rule RJFFP in section D1.1.3 of DDI0487H.a. 8303 */ 8304 int min_el = ctz32(r->access) / 2; 8305 if (min_el == 2 && !arm_feature(env, ARM_FEATURE_EL2)) { 8306 if (r->type & ARM_CP_EL3_NO_EL2_UNDEF) { 8307 return; 8308 } 8309 make_const = !(r->type & ARM_CP_EL3_NO_EL2_KEEP); 8310 } 8311 } else { 8312 CPAccessRights max_el = (arm_feature(env, ARM_FEATURE_EL2) 8313 ? PL2_RW : PL1_RW); 8314 if ((r->access & max_el) == 0) { 8315 return; 8316 } 8317 } 8318 8319 /* Combine cpreg and name into one allocation. */ 8320 name_len = strlen(name) + 1; 8321 r2 = g_malloc(sizeof(*r2) + name_len); 8322 *r2 = *r; 8323 r2->name = memcpy(r2 + 1, name, name_len); 8324 8325 /* 8326 * Update fields to match the instantiation, overwiting wildcards 8327 * such as CP_ANY, ARM_CP_STATE_BOTH, or ARM_CP_SECSTATE_BOTH. 8328 */ 8329 r2->cp = cp; 8330 r2->crm = crm; 8331 r2->opc1 = opc1; 8332 r2->opc2 = opc2; 8333 r2->state = state; 8334 r2->secure = secstate; 8335 if (opaque) { 8336 r2->opaque = opaque; 8337 } 8338 8339 if (make_const) { 8340 /* This should not have been a very special register to begin. */ 8341 int old_special = r2->type & ARM_CP_SPECIAL_MASK; 8342 assert(old_special == 0 || old_special == ARM_CP_NOP); 8343 /* 8344 * Set the special function to CONST, retaining the other flags. 8345 * This is important for e.g. ARM_CP_SVE so that we still 8346 * take the SVE trap if CPTR_EL3.EZ == 0. 8347 */ 8348 r2->type = (r2->type & ~ARM_CP_SPECIAL_MASK) | ARM_CP_CONST; 8349 /* 8350 * Usually, these registers become RES0, but there are a few 8351 * special cases like VPIDR_EL2 which have a constant non-zero 8352 * value with writes ignored. 8353 */ 8354 if (!(r->type & ARM_CP_EL3_NO_EL2_C_NZ)) { 8355 r2->resetvalue = 0; 8356 } 8357 /* 8358 * ARM_CP_CONST has precedence, so removing the callbacks and 8359 * offsets are not strictly necessary, but it is potentially 8360 * less confusing to debug later. 8361 */ 8362 r2->readfn = NULL; 8363 r2->writefn = NULL; 8364 r2->raw_readfn = NULL; 8365 r2->raw_writefn = NULL; 8366 r2->resetfn = NULL; 8367 r2->fieldoffset = 0; 8368 r2->bank_fieldoffsets[0] = 0; 8369 r2->bank_fieldoffsets[1] = 0; 8370 } else { 8371 bool isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]; 8372 8373 if (isbanked) { 8374 /* 8375 * Register is banked (using both entries in array). 8376 * Overwriting fieldoffset as the array is only used to define 8377 * banked registers but later only fieldoffset is used. 8378 */ 8379 r2->fieldoffset = r->bank_fieldoffsets[ns]; 8380 } 8381 if (state == ARM_CP_STATE_AA32) { 8382 if (isbanked) { 8383 /* 8384 * If the register is banked then we don't need to migrate or 8385 * reset the 32-bit instance in certain cases: 8386 * 8387 * 1) If the register has both 32-bit and 64-bit instances 8388 * then we can count on the 64-bit instance taking care 8389 * of the non-secure bank. 8390 * 2) If ARMv8 is enabled then we can count on a 64-bit 8391 * version taking care of the secure bank. This requires 8392 * that separate 32 and 64-bit definitions are provided. 8393 */ 8394 if ((r->state == ARM_CP_STATE_BOTH && ns) || 8395 (arm_feature(env, ARM_FEATURE_V8) && !ns)) { 8396 r2->type |= ARM_CP_ALIAS; 8397 } 8398 } else if ((secstate != r->secure) && !ns) { 8399 /* 8400 * The register is not banked so we only want to allow 8401 * migration of the non-secure instance. 8402 */ 8403 r2->type |= ARM_CP_ALIAS; 8404 } 8405 8406 if (HOST_BIG_ENDIAN && 8407 r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) { 8408 r2->fieldoffset += sizeof(uint32_t); 8409 } 8410 } 8411 } 8412 8413 /* 8414 * By convention, for wildcarded registers only the first 8415 * entry is used for migration; the others are marked as 8416 * ALIAS so we don't try to transfer the register 8417 * multiple times. Special registers (ie NOP/WFI) are 8418 * never migratable and not even raw-accessible. 8419 */ 8420 if (r2->type & ARM_CP_SPECIAL_MASK) { 8421 r2->type |= ARM_CP_NO_RAW; 8422 } 8423 if (((r->crm == CP_ANY) && crm != 0) || 8424 ((r->opc1 == CP_ANY) && opc1 != 0) || 8425 ((r->opc2 == CP_ANY) && opc2 != 0)) { 8426 r2->type |= ARM_CP_ALIAS | ARM_CP_NO_GDB; 8427 } 8428 8429 /* 8430 * Check that raw accesses are either forbidden or handled. Note that 8431 * we can't assert this earlier because the setup of fieldoffset for 8432 * banked registers has to be done first. 8433 */ 8434 if (!(r2->type & ARM_CP_NO_RAW)) { 8435 assert(!raw_accessors_invalid(r2)); 8436 } 8437 8438 g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)key, r2); 8439 } 8440 8441 8442 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, 8443 const ARMCPRegInfo *r, void *opaque) 8444 { 8445 /* Define implementations of coprocessor registers. 8446 * We store these in a hashtable because typically 8447 * there are less than 150 registers in a space which 8448 * is 16*16*16*8*8 = 262144 in size. 8449 * Wildcarding is supported for the crm, opc1 and opc2 fields. 8450 * If a register is defined twice then the second definition is 8451 * used, so this can be used to define some generic registers and 8452 * then override them with implementation specific variations. 8453 * At least one of the original and the second definition should 8454 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard 8455 * against accidental use. 8456 * 8457 * The state field defines whether the register is to be 8458 * visible in the AArch32 or AArch64 execution state. If the 8459 * state is set to ARM_CP_STATE_BOTH then we synthesise a 8460 * reginfo structure for the AArch32 view, which sees the lower 8461 * 32 bits of the 64 bit register. 8462 * 8463 * Only registers visible in AArch64 may set r->opc0; opc0 cannot 8464 * be wildcarded. AArch64 registers are always considered to be 64 8465 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of 8466 * the register, if any. 8467 */ 8468 int crm, opc1, opc2; 8469 int crmmin = (r->crm == CP_ANY) ? 0 : r->crm; 8470 int crmmax = (r->crm == CP_ANY) ? 15 : r->crm; 8471 int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1; 8472 int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1; 8473 int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2; 8474 int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2; 8475 CPState state; 8476 8477 /* 64 bit registers have only CRm and Opc1 fields */ 8478 assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn))); 8479 /* op0 only exists in the AArch64 encodings */ 8480 assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0)); 8481 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */ 8482 assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT)); 8483 /* 8484 * This API is only for Arm's system coprocessors (14 and 15) or 8485 * (M-profile or v7A-and-earlier only) for implementation defined 8486 * coprocessors in the range 0..7. Our decode assumes this, since 8487 * 8..13 can be used for other insns including VFP and Neon. See 8488 * valid_cp() in translate.c. Assert here that we haven't tried 8489 * to use an invalid coprocessor number. 8490 */ 8491 switch (r->state) { 8492 case ARM_CP_STATE_BOTH: 8493 /* 0 has a special meaning, but otherwise the same rules as AA32. */ 8494 if (r->cp == 0) { 8495 break; 8496 } 8497 /* fall through */ 8498 case ARM_CP_STATE_AA32: 8499 if (arm_feature(&cpu->env, ARM_FEATURE_V8) && 8500 !arm_feature(&cpu->env, ARM_FEATURE_M)) { 8501 assert(r->cp >= 14 && r->cp <= 15); 8502 } else { 8503 assert(r->cp < 8 || (r->cp >= 14 && r->cp <= 15)); 8504 } 8505 break; 8506 case ARM_CP_STATE_AA64: 8507 assert(r->cp == 0 || r->cp == CP_REG_ARM64_SYSREG_CP); 8508 break; 8509 default: 8510 g_assert_not_reached(); 8511 } 8512 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1 8513 * encodes a minimum access level for the register. We roll this 8514 * runtime check into our general permission check code, so check 8515 * here that the reginfo's specified permissions are strict enough 8516 * to encompass the generic architectural permission check. 8517 */ 8518 if (r->state != ARM_CP_STATE_AA32) { 8519 CPAccessRights mask; 8520 switch (r->opc1) { 8521 case 0: 8522 /* min_EL EL1, but some accessible to EL0 via kernel ABI */ 8523 mask = PL0U_R | PL1_RW; 8524 break; 8525 case 1: case 2: 8526 /* min_EL EL1 */ 8527 mask = PL1_RW; 8528 break; 8529 case 3: 8530 /* min_EL EL0 */ 8531 mask = PL0_RW; 8532 break; 8533 case 4: 8534 case 5: 8535 /* min_EL EL2 */ 8536 mask = PL2_RW; 8537 break; 8538 case 6: 8539 /* min_EL EL3 */ 8540 mask = PL3_RW; 8541 break; 8542 case 7: 8543 /* min_EL EL1, secure mode only (we don't check the latter) */ 8544 mask = PL1_RW; 8545 break; 8546 default: 8547 /* broken reginfo with out-of-range opc1 */ 8548 g_assert_not_reached(); 8549 } 8550 /* assert our permissions are not too lax (stricter is fine) */ 8551 assert((r->access & ~mask) == 0); 8552 } 8553 8554 /* Check that the register definition has enough info to handle 8555 * reads and writes if they are permitted. 8556 */ 8557 if (!(r->type & (ARM_CP_SPECIAL_MASK | ARM_CP_CONST))) { 8558 if (r->access & PL3_R) { 8559 assert((r->fieldoffset || 8560 (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || 8561 r->readfn); 8562 } 8563 if (r->access & PL3_W) { 8564 assert((r->fieldoffset || 8565 (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || 8566 r->writefn); 8567 } 8568 } 8569 8570 for (crm = crmmin; crm <= crmmax; crm++) { 8571 for (opc1 = opc1min; opc1 <= opc1max; opc1++) { 8572 for (opc2 = opc2min; opc2 <= opc2max; opc2++) { 8573 for (state = ARM_CP_STATE_AA32; 8574 state <= ARM_CP_STATE_AA64; state++) { 8575 if (r->state != state && r->state != ARM_CP_STATE_BOTH) { 8576 continue; 8577 } 8578 if (state == ARM_CP_STATE_AA32) { 8579 /* Under AArch32 CP registers can be common 8580 * (same for secure and non-secure world) or banked. 8581 */ 8582 char *name; 8583 8584 switch (r->secure) { 8585 case ARM_CP_SECSTATE_S: 8586 case ARM_CP_SECSTATE_NS: 8587 add_cpreg_to_hashtable(cpu, r, opaque, state, 8588 r->secure, crm, opc1, opc2, 8589 r->name); 8590 break; 8591 case ARM_CP_SECSTATE_BOTH: 8592 name = g_strdup_printf("%s_S", r->name); 8593 add_cpreg_to_hashtable(cpu, r, opaque, state, 8594 ARM_CP_SECSTATE_S, 8595 crm, opc1, opc2, name); 8596 g_free(name); 8597 add_cpreg_to_hashtable(cpu, r, opaque, state, 8598 ARM_CP_SECSTATE_NS, 8599 crm, opc1, opc2, r->name); 8600 break; 8601 default: 8602 g_assert_not_reached(); 8603 } 8604 } else { 8605 /* AArch64 registers get mapped to non-secure instance 8606 * of AArch32 */ 8607 add_cpreg_to_hashtable(cpu, r, opaque, state, 8608 ARM_CP_SECSTATE_NS, 8609 crm, opc1, opc2, r->name); 8610 } 8611 } 8612 } 8613 } 8614 } 8615 } 8616 8617 /* Define a whole list of registers */ 8618 void define_arm_cp_regs_with_opaque_len(ARMCPU *cpu, const ARMCPRegInfo *regs, 8619 void *opaque, size_t len) 8620 { 8621 size_t i; 8622 for (i = 0; i < len; ++i) { 8623 define_one_arm_cp_reg_with_opaque(cpu, regs + i, opaque); 8624 } 8625 } 8626 8627 /* 8628 * Modify ARMCPRegInfo for access from userspace. 8629 * 8630 * This is a data driven modification directed by 8631 * ARMCPRegUserSpaceInfo. All registers become ARM_CP_CONST as 8632 * user-space cannot alter any values and dynamic values pertaining to 8633 * execution state are hidden from user space view anyway. 8634 */ 8635 void modify_arm_cp_regs_with_len(ARMCPRegInfo *regs, size_t regs_len, 8636 const ARMCPRegUserSpaceInfo *mods, 8637 size_t mods_len) 8638 { 8639 for (size_t mi = 0; mi < mods_len; ++mi) { 8640 const ARMCPRegUserSpaceInfo *m = mods + mi; 8641 GPatternSpec *pat = NULL; 8642 8643 if (m->is_glob) { 8644 pat = g_pattern_spec_new(m->name); 8645 } 8646 for (size_t ri = 0; ri < regs_len; ++ri) { 8647 ARMCPRegInfo *r = regs + ri; 8648 8649 if (pat && g_pattern_match_string(pat, r->name)) { 8650 r->type = ARM_CP_CONST; 8651 r->access = PL0U_R; 8652 r->resetvalue = 0; 8653 /* continue */ 8654 } else if (strcmp(r->name, m->name) == 0) { 8655 r->type = ARM_CP_CONST; 8656 r->access = PL0U_R; 8657 r->resetvalue &= m->exported_bits; 8658 r->resetvalue |= m->fixed_bits; 8659 break; 8660 } 8661 } 8662 if (pat) { 8663 g_pattern_spec_free(pat); 8664 } 8665 } 8666 } 8667 8668 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp) 8669 { 8670 return g_hash_table_lookup(cpregs, (gpointer)(uintptr_t)encoded_cp); 8671 } 8672 8673 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, 8674 uint64_t value) 8675 { 8676 /* Helper coprocessor write function for write-ignore registers */ 8677 } 8678 8679 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri) 8680 { 8681 /* Helper coprocessor write function for read-as-zero registers */ 8682 return 0; 8683 } 8684 8685 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque) 8686 { 8687 /* Helper coprocessor reset function for do-nothing-on-reset registers */ 8688 } 8689 8690 static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type) 8691 { 8692 /* Return true if it is not valid for us to switch to 8693 * this CPU mode (ie all the UNPREDICTABLE cases in 8694 * the ARM ARM CPSRWriteByInstr pseudocode). 8695 */ 8696 8697 /* Changes to or from Hyp via MSR and CPS are illegal. */ 8698 if (write_type == CPSRWriteByInstr && 8699 ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_HYP || 8700 mode == ARM_CPU_MODE_HYP)) { 8701 return 1; 8702 } 8703 8704 switch (mode) { 8705 case ARM_CPU_MODE_USR: 8706 return 0; 8707 case ARM_CPU_MODE_SYS: 8708 case ARM_CPU_MODE_SVC: 8709 case ARM_CPU_MODE_ABT: 8710 case ARM_CPU_MODE_UND: 8711 case ARM_CPU_MODE_IRQ: 8712 case ARM_CPU_MODE_FIQ: 8713 /* Note that we don't implement the IMPDEF NSACR.RFR which in v7 8714 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.) 8715 */ 8716 /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR 8717 * and CPS are treated as illegal mode changes. 8718 */ 8719 if (write_type == CPSRWriteByInstr && 8720 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON && 8721 (arm_hcr_el2_eff(env) & HCR_TGE)) { 8722 return 1; 8723 } 8724 return 0; 8725 case ARM_CPU_MODE_HYP: 8726 return !arm_is_el2_enabled(env) || arm_current_el(env) < 2; 8727 case ARM_CPU_MODE_MON: 8728 return arm_current_el(env) < 3; 8729 default: 8730 return 1; 8731 } 8732 } 8733 8734 uint32_t cpsr_read(CPUARMState *env) 8735 { 8736 int ZF; 8737 ZF = (env->ZF == 0); 8738 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) | 8739 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 8740 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25) 8741 | ((env->condexec_bits & 0xfc) << 8) 8742 | (env->GE << 16) | (env->daif & CPSR_AIF); 8743 } 8744 8745 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 8746 CPSRWriteType write_type) 8747 { 8748 uint32_t changed_daif; 8749 bool rebuild_hflags = (write_type != CPSRWriteRaw) && 8750 (mask & (CPSR_M | CPSR_E | CPSR_IL)); 8751 8752 if (mask & CPSR_NZCV) { 8753 env->ZF = (~val) & CPSR_Z; 8754 env->NF = val; 8755 env->CF = (val >> 29) & 1; 8756 env->VF = (val << 3) & 0x80000000; 8757 } 8758 if (mask & CPSR_Q) 8759 env->QF = ((val & CPSR_Q) != 0); 8760 if (mask & CPSR_T) 8761 env->thumb = ((val & CPSR_T) != 0); 8762 if (mask & CPSR_IT_0_1) { 8763 env->condexec_bits &= ~3; 8764 env->condexec_bits |= (val >> 25) & 3; 8765 } 8766 if (mask & CPSR_IT_2_7) { 8767 env->condexec_bits &= 3; 8768 env->condexec_bits |= (val >> 8) & 0xfc; 8769 } 8770 if (mask & CPSR_GE) { 8771 env->GE = (val >> 16) & 0xf; 8772 } 8773 8774 /* In a V7 implementation that includes the security extensions but does 8775 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control 8776 * whether non-secure software is allowed to change the CPSR_F and CPSR_A 8777 * bits respectively. 8778 * 8779 * In a V8 implementation, it is permitted for privileged software to 8780 * change the CPSR A/F bits regardless of the SCR.AW/FW bits. 8781 */ 8782 if (write_type != CPSRWriteRaw && !arm_feature(env, ARM_FEATURE_V8) && 8783 arm_feature(env, ARM_FEATURE_EL3) && 8784 !arm_feature(env, ARM_FEATURE_EL2) && 8785 !arm_is_secure(env)) { 8786 8787 changed_daif = (env->daif ^ val) & mask; 8788 8789 if (changed_daif & CPSR_A) { 8790 /* Check to see if we are allowed to change the masking of async 8791 * abort exceptions from a non-secure state. 8792 */ 8793 if (!(env->cp15.scr_el3 & SCR_AW)) { 8794 qemu_log_mask(LOG_GUEST_ERROR, 8795 "Ignoring attempt to switch CPSR_A flag from " 8796 "non-secure world with SCR.AW bit clear\n"); 8797 mask &= ~CPSR_A; 8798 } 8799 } 8800 8801 if (changed_daif & CPSR_F) { 8802 /* Check to see if we are allowed to change the masking of FIQ 8803 * exceptions from a non-secure state. 8804 */ 8805 if (!(env->cp15.scr_el3 & SCR_FW)) { 8806 qemu_log_mask(LOG_GUEST_ERROR, 8807 "Ignoring attempt to switch CPSR_F flag from " 8808 "non-secure world with SCR.FW bit clear\n"); 8809 mask &= ~CPSR_F; 8810 } 8811 8812 /* Check whether non-maskable FIQ (NMFI) support is enabled. 8813 * If this bit is set software is not allowed to mask 8814 * FIQs, but is allowed to set CPSR_F to 0. 8815 */ 8816 if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) && 8817 (val & CPSR_F)) { 8818 qemu_log_mask(LOG_GUEST_ERROR, 8819 "Ignoring attempt to enable CPSR_F flag " 8820 "(non-maskable FIQ [NMFI] support enabled)\n"); 8821 mask &= ~CPSR_F; 8822 } 8823 } 8824 } 8825 8826 env->daif &= ~(CPSR_AIF & mask); 8827 env->daif |= val & CPSR_AIF & mask; 8828 8829 if (write_type != CPSRWriteRaw && 8830 ((env->uncached_cpsr ^ val) & mask & CPSR_M)) { 8831 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR) { 8832 /* Note that we can only get here in USR mode if this is a 8833 * gdb stub write; for this case we follow the architectural 8834 * behaviour for guest writes in USR mode of ignoring an attempt 8835 * to switch mode. (Those are caught by translate.c for writes 8836 * triggered by guest instructions.) 8837 */ 8838 mask &= ~CPSR_M; 8839 } else if (bad_mode_switch(env, val & CPSR_M, write_type)) { 8840 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in 8841 * v7, and has defined behaviour in v8: 8842 * + leave CPSR.M untouched 8843 * + allow changes to the other CPSR fields 8844 * + set PSTATE.IL 8845 * For user changes via the GDB stub, we don't set PSTATE.IL, 8846 * as this would be unnecessarily harsh for a user error. 8847 */ 8848 mask &= ~CPSR_M; 8849 if (write_type != CPSRWriteByGDBStub && 8850 arm_feature(env, ARM_FEATURE_V8)) { 8851 mask |= CPSR_IL; 8852 val |= CPSR_IL; 8853 } 8854 qemu_log_mask(LOG_GUEST_ERROR, 8855 "Illegal AArch32 mode switch attempt from %s to %s\n", 8856 aarch32_mode_name(env->uncached_cpsr), 8857 aarch32_mode_name(val)); 8858 } else { 8859 qemu_log_mask(CPU_LOG_INT, "%s %s to %s PC 0x%" PRIx32 "\n", 8860 write_type == CPSRWriteExceptionReturn ? 8861 "Exception return from AArch32" : 8862 "AArch32 mode switch from", 8863 aarch32_mode_name(env->uncached_cpsr), 8864 aarch32_mode_name(val), env->regs[15]); 8865 switch_mode(env, val & CPSR_M); 8866 } 8867 } 8868 mask &= ~CACHED_CPSR_BITS; 8869 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask); 8870 if (rebuild_hflags) { 8871 arm_rebuild_hflags(env); 8872 } 8873 } 8874 8875 /* Sign/zero extend */ 8876 uint32_t HELPER(sxtb16)(uint32_t x) 8877 { 8878 uint32_t res; 8879 res = (uint16_t)(int8_t)x; 8880 res |= (uint32_t)(int8_t)(x >> 16) << 16; 8881 return res; 8882 } 8883 8884 static void handle_possible_div0_trap(CPUARMState *env, uintptr_t ra) 8885 { 8886 /* 8887 * Take a division-by-zero exception if necessary; otherwise return 8888 * to get the usual non-trapping division behaviour (result of 0) 8889 */ 8890 if (arm_feature(env, ARM_FEATURE_M) 8891 && (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_DIV_0_TRP_MASK)) { 8892 raise_exception_ra(env, EXCP_DIVBYZERO, 0, 1, ra); 8893 } 8894 } 8895 8896 uint32_t HELPER(uxtb16)(uint32_t x) 8897 { 8898 uint32_t res; 8899 res = (uint16_t)(uint8_t)x; 8900 res |= (uint32_t)(uint8_t)(x >> 16) << 16; 8901 return res; 8902 } 8903 8904 int32_t HELPER(sdiv)(CPUARMState *env, int32_t num, int32_t den) 8905 { 8906 if (den == 0) { 8907 handle_possible_div0_trap(env, GETPC()); 8908 return 0; 8909 } 8910 if (num == INT_MIN && den == -1) { 8911 return INT_MIN; 8912 } 8913 return num / den; 8914 } 8915 8916 uint32_t HELPER(udiv)(CPUARMState *env, uint32_t num, uint32_t den) 8917 { 8918 if (den == 0) { 8919 handle_possible_div0_trap(env, GETPC()); 8920 return 0; 8921 } 8922 return num / den; 8923 } 8924 8925 uint32_t HELPER(rbit)(uint32_t x) 8926 { 8927 return revbit32(x); 8928 } 8929 8930 #ifdef CONFIG_USER_ONLY 8931 8932 static void switch_mode(CPUARMState *env, int mode) 8933 { 8934 ARMCPU *cpu = env_archcpu(env); 8935 8936 if (mode != ARM_CPU_MODE_USR) { 8937 cpu_abort(CPU(cpu), "Tried to switch out of user mode\n"); 8938 } 8939 } 8940 8941 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 8942 uint32_t cur_el, bool secure) 8943 { 8944 return 1; 8945 } 8946 8947 void aarch64_sync_64_to_32(CPUARMState *env) 8948 { 8949 g_assert_not_reached(); 8950 } 8951 8952 #else 8953 8954 static void switch_mode(CPUARMState *env, int mode) 8955 { 8956 int old_mode; 8957 int i; 8958 8959 old_mode = env->uncached_cpsr & CPSR_M; 8960 if (mode == old_mode) 8961 return; 8962 8963 if (old_mode == ARM_CPU_MODE_FIQ) { 8964 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t)); 8965 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t)); 8966 } else if (mode == ARM_CPU_MODE_FIQ) { 8967 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t)); 8968 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t)); 8969 } 8970 8971 i = bank_number(old_mode); 8972 env->banked_r13[i] = env->regs[13]; 8973 env->banked_spsr[i] = env->spsr; 8974 8975 i = bank_number(mode); 8976 env->regs[13] = env->banked_r13[i]; 8977 env->spsr = env->banked_spsr[i]; 8978 8979 env->banked_r14[r14_bank_number(old_mode)] = env->regs[14]; 8980 env->regs[14] = env->banked_r14[r14_bank_number(mode)]; 8981 } 8982 8983 /* Physical Interrupt Target EL Lookup Table 8984 * 8985 * [ From ARM ARM section G1.13.4 (Table G1-15) ] 8986 * 8987 * The below multi-dimensional table is used for looking up the target 8988 * exception level given numerous condition criteria. Specifically, the 8989 * target EL is based on SCR and HCR routing controls as well as the 8990 * currently executing EL and secure state. 8991 * 8992 * Dimensions: 8993 * target_el_table[2][2][2][2][2][4] 8994 * | | | | | +--- Current EL 8995 * | | | | +------ Non-secure(0)/Secure(1) 8996 * | | | +--------- HCR mask override 8997 * | | +------------ SCR exec state control 8998 * | +--------------- SCR mask override 8999 * +------------------ 32-bit(0)/64-bit(1) EL3 9000 * 9001 * The table values are as such: 9002 * 0-3 = EL0-EL3 9003 * -1 = Cannot occur 9004 * 9005 * The ARM ARM target EL table includes entries indicating that an "exception 9006 * is not taken". The two cases where this is applicable are: 9007 * 1) An exception is taken from EL3 but the SCR does not have the exception 9008 * routed to EL3. 9009 * 2) An exception is taken from EL2 but the HCR does not have the exception 9010 * routed to EL2. 9011 * In these two cases, the below table contain a target of EL1. This value is 9012 * returned as it is expected that the consumer of the table data will check 9013 * for "target EL >= current EL" to ensure the exception is not taken. 9014 * 9015 * SCR HCR 9016 * 64 EA AMO From 9017 * BIT IRQ IMO Non-secure Secure 9018 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3 9019 */ 9020 static const int8_t target_el_table[2][2][2][2][2][4] = { 9021 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },}, 9022 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},}, 9023 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },}, 9024 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},}, 9025 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },}, 9026 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},}, 9027 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },}, 9028 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},}, 9029 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },}, 9030 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 2, 2, -1, 1 },},}, 9031 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, 1, 1 },}, 9032 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 2, 2, 2, 1 },},},}, 9033 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },}, 9034 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},}, 9035 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },}, 9036 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},},},}, 9037 }; 9038 9039 /* 9040 * Determine the target EL for physical exceptions 9041 */ 9042 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 9043 uint32_t cur_el, bool secure) 9044 { 9045 CPUARMState *env = cs->env_ptr; 9046 bool rw; 9047 bool scr; 9048 bool hcr; 9049 int target_el; 9050 /* Is the highest EL AArch64? */ 9051 bool is64 = arm_feature(env, ARM_FEATURE_AARCH64); 9052 uint64_t hcr_el2; 9053 9054 if (arm_feature(env, ARM_FEATURE_EL3)) { 9055 rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW); 9056 } else { 9057 /* Either EL2 is the highest EL (and so the EL2 register width 9058 * is given by is64); or there is no EL2 or EL3, in which case 9059 * the value of 'rw' does not affect the table lookup anyway. 9060 */ 9061 rw = is64; 9062 } 9063 9064 hcr_el2 = arm_hcr_el2_eff(env); 9065 switch (excp_idx) { 9066 case EXCP_IRQ: 9067 scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ); 9068 hcr = hcr_el2 & HCR_IMO; 9069 break; 9070 case EXCP_FIQ: 9071 scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ); 9072 hcr = hcr_el2 & HCR_FMO; 9073 break; 9074 default: 9075 scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA); 9076 hcr = hcr_el2 & HCR_AMO; 9077 break; 9078 }; 9079 9080 /* 9081 * For these purposes, TGE and AMO/IMO/FMO both force the 9082 * interrupt to EL2. Fold TGE into the bit extracted above. 9083 */ 9084 hcr |= (hcr_el2 & HCR_TGE) != 0; 9085 9086 /* Perform a table-lookup for the target EL given the current state */ 9087 target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el]; 9088 9089 assert(target_el > 0); 9090 9091 return target_el; 9092 } 9093 9094 void arm_log_exception(CPUState *cs) 9095 { 9096 int idx = cs->exception_index; 9097 9098 if (qemu_loglevel_mask(CPU_LOG_INT)) { 9099 const char *exc = NULL; 9100 static const char * const excnames[] = { 9101 [EXCP_UDEF] = "Undefined Instruction", 9102 [EXCP_SWI] = "SVC", 9103 [EXCP_PREFETCH_ABORT] = "Prefetch Abort", 9104 [EXCP_DATA_ABORT] = "Data Abort", 9105 [EXCP_IRQ] = "IRQ", 9106 [EXCP_FIQ] = "FIQ", 9107 [EXCP_BKPT] = "Breakpoint", 9108 [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit", 9109 [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage", 9110 [EXCP_HVC] = "Hypervisor Call", 9111 [EXCP_HYP_TRAP] = "Hypervisor Trap", 9112 [EXCP_SMC] = "Secure Monitor Call", 9113 [EXCP_VIRQ] = "Virtual IRQ", 9114 [EXCP_VFIQ] = "Virtual FIQ", 9115 [EXCP_SEMIHOST] = "Semihosting call", 9116 [EXCP_NOCP] = "v7M NOCP UsageFault", 9117 [EXCP_INVSTATE] = "v7M INVSTATE UsageFault", 9118 [EXCP_STKOF] = "v8M STKOF UsageFault", 9119 [EXCP_LAZYFP] = "v7M exception during lazy FP stacking", 9120 [EXCP_LSERR] = "v8M LSERR UsageFault", 9121 [EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault", 9122 [EXCP_DIVBYZERO] = "v7M DIVBYZERO UsageFault", 9123 [EXCP_VSERR] = "Virtual SERR", 9124 }; 9125 9126 if (idx >= 0 && idx < ARRAY_SIZE(excnames)) { 9127 exc = excnames[idx]; 9128 } 9129 if (!exc) { 9130 exc = "unknown"; 9131 } 9132 qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s] on CPU %d\n", 9133 idx, exc, cs->cpu_index); 9134 } 9135 } 9136 9137 /* 9138 * Function used to synchronize QEMU's AArch64 register set with AArch32 9139 * register set. This is necessary when switching between AArch32 and AArch64 9140 * execution state. 9141 */ 9142 void aarch64_sync_32_to_64(CPUARMState *env) 9143 { 9144 int i; 9145 uint32_t mode = env->uncached_cpsr & CPSR_M; 9146 9147 /* We can blanket copy R[0:7] to X[0:7] */ 9148 for (i = 0; i < 8; i++) { 9149 env->xregs[i] = env->regs[i]; 9150 } 9151 9152 /* 9153 * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12. 9154 * Otherwise, they come from the banked user regs. 9155 */ 9156 if (mode == ARM_CPU_MODE_FIQ) { 9157 for (i = 8; i < 13; i++) { 9158 env->xregs[i] = env->usr_regs[i - 8]; 9159 } 9160 } else { 9161 for (i = 8; i < 13; i++) { 9162 env->xregs[i] = env->regs[i]; 9163 } 9164 } 9165 9166 /* 9167 * Registers x13-x23 are the various mode SP and FP registers. Registers 9168 * r13 and r14 are only copied if we are in that mode, otherwise we copy 9169 * from the mode banked register. 9170 */ 9171 if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) { 9172 env->xregs[13] = env->regs[13]; 9173 env->xregs[14] = env->regs[14]; 9174 } else { 9175 env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)]; 9176 /* HYP is an exception in that it is copied from r14 */ 9177 if (mode == ARM_CPU_MODE_HYP) { 9178 env->xregs[14] = env->regs[14]; 9179 } else { 9180 env->xregs[14] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)]; 9181 } 9182 } 9183 9184 if (mode == ARM_CPU_MODE_HYP) { 9185 env->xregs[15] = env->regs[13]; 9186 } else { 9187 env->xregs[15] = env->banked_r13[bank_number(ARM_CPU_MODE_HYP)]; 9188 } 9189 9190 if (mode == ARM_CPU_MODE_IRQ) { 9191 env->xregs[16] = env->regs[14]; 9192 env->xregs[17] = env->regs[13]; 9193 } else { 9194 env->xregs[16] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)]; 9195 env->xregs[17] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)]; 9196 } 9197 9198 if (mode == ARM_CPU_MODE_SVC) { 9199 env->xregs[18] = env->regs[14]; 9200 env->xregs[19] = env->regs[13]; 9201 } else { 9202 env->xregs[18] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)]; 9203 env->xregs[19] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)]; 9204 } 9205 9206 if (mode == ARM_CPU_MODE_ABT) { 9207 env->xregs[20] = env->regs[14]; 9208 env->xregs[21] = env->regs[13]; 9209 } else { 9210 env->xregs[20] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)]; 9211 env->xregs[21] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)]; 9212 } 9213 9214 if (mode == ARM_CPU_MODE_UND) { 9215 env->xregs[22] = env->regs[14]; 9216 env->xregs[23] = env->regs[13]; 9217 } else { 9218 env->xregs[22] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)]; 9219 env->xregs[23] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)]; 9220 } 9221 9222 /* 9223 * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ 9224 * mode, then we can copy from r8-r14. Otherwise, we copy from the 9225 * FIQ bank for r8-r14. 9226 */ 9227 if (mode == ARM_CPU_MODE_FIQ) { 9228 for (i = 24; i < 31; i++) { 9229 env->xregs[i] = env->regs[i - 16]; /* X[24:30] <- R[8:14] */ 9230 } 9231 } else { 9232 for (i = 24; i < 29; i++) { 9233 env->xregs[i] = env->fiq_regs[i - 24]; 9234 } 9235 env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)]; 9236 env->xregs[30] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)]; 9237 } 9238 9239 env->pc = env->regs[15]; 9240 } 9241 9242 /* 9243 * Function used to synchronize QEMU's AArch32 register set with AArch64 9244 * register set. This is necessary when switching between AArch32 and AArch64 9245 * execution state. 9246 */ 9247 void aarch64_sync_64_to_32(CPUARMState *env) 9248 { 9249 int i; 9250 uint32_t mode = env->uncached_cpsr & CPSR_M; 9251 9252 /* We can blanket copy X[0:7] to R[0:7] */ 9253 for (i = 0; i < 8; i++) { 9254 env->regs[i] = env->xregs[i]; 9255 } 9256 9257 /* 9258 * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12. 9259 * Otherwise, we copy x8-x12 into the banked user regs. 9260 */ 9261 if (mode == ARM_CPU_MODE_FIQ) { 9262 for (i = 8; i < 13; i++) { 9263 env->usr_regs[i - 8] = env->xregs[i]; 9264 } 9265 } else { 9266 for (i = 8; i < 13; i++) { 9267 env->regs[i] = env->xregs[i]; 9268 } 9269 } 9270 9271 /* 9272 * Registers r13 & r14 depend on the current mode. 9273 * If we are in a given mode, we copy the corresponding x registers to r13 9274 * and r14. Otherwise, we copy the x register to the banked r13 and r14 9275 * for the mode. 9276 */ 9277 if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) { 9278 env->regs[13] = env->xregs[13]; 9279 env->regs[14] = env->xregs[14]; 9280 } else { 9281 env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13]; 9282 9283 /* 9284 * HYP is an exception in that it does not have its own banked r14 but 9285 * shares the USR r14 9286 */ 9287 if (mode == ARM_CPU_MODE_HYP) { 9288 env->regs[14] = env->xregs[14]; 9289 } else { 9290 env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)] = env->xregs[14]; 9291 } 9292 } 9293 9294 if (mode == ARM_CPU_MODE_HYP) { 9295 env->regs[13] = env->xregs[15]; 9296 } else { 9297 env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] = env->xregs[15]; 9298 } 9299 9300 if (mode == ARM_CPU_MODE_IRQ) { 9301 env->regs[14] = env->xregs[16]; 9302 env->regs[13] = env->xregs[17]; 9303 } else { 9304 env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16]; 9305 env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17]; 9306 } 9307 9308 if (mode == ARM_CPU_MODE_SVC) { 9309 env->regs[14] = env->xregs[18]; 9310 env->regs[13] = env->xregs[19]; 9311 } else { 9312 env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18]; 9313 env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19]; 9314 } 9315 9316 if (mode == ARM_CPU_MODE_ABT) { 9317 env->regs[14] = env->xregs[20]; 9318 env->regs[13] = env->xregs[21]; 9319 } else { 9320 env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20]; 9321 env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21]; 9322 } 9323 9324 if (mode == ARM_CPU_MODE_UND) { 9325 env->regs[14] = env->xregs[22]; 9326 env->regs[13] = env->xregs[23]; 9327 } else { 9328 env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)] = env->xregs[22]; 9329 env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23]; 9330 } 9331 9332 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ 9333 * mode, then we can copy to r8-r14. Otherwise, we copy to the 9334 * FIQ bank for r8-r14. 9335 */ 9336 if (mode == ARM_CPU_MODE_FIQ) { 9337 for (i = 24; i < 31; i++) { 9338 env->regs[i - 16] = env->xregs[i]; /* X[24:30] -> R[8:14] */ 9339 } 9340 } else { 9341 for (i = 24; i < 29; i++) { 9342 env->fiq_regs[i - 24] = env->xregs[i]; 9343 } 9344 env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29]; 9345 env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30]; 9346 } 9347 9348 env->regs[15] = env->pc; 9349 } 9350 9351 static void take_aarch32_exception(CPUARMState *env, int new_mode, 9352 uint32_t mask, uint32_t offset, 9353 uint32_t newpc) 9354 { 9355 int new_el; 9356 9357 /* Change the CPU state so as to actually take the exception. */ 9358 switch_mode(env, new_mode); 9359 9360 /* 9361 * For exceptions taken to AArch32 we must clear the SS bit in both 9362 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now. 9363 */ 9364 env->pstate &= ~PSTATE_SS; 9365 env->spsr = cpsr_read(env); 9366 /* Clear IT bits. */ 9367 env->condexec_bits = 0; 9368 /* Switch to the new mode, and to the correct instruction set. */ 9369 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; 9370 9371 /* This must be after mode switching. */ 9372 new_el = arm_current_el(env); 9373 9374 /* Set new mode endianness */ 9375 env->uncached_cpsr &= ~CPSR_E; 9376 if (env->cp15.sctlr_el[new_el] & SCTLR_EE) { 9377 env->uncached_cpsr |= CPSR_E; 9378 } 9379 /* J and IL must always be cleared for exception entry */ 9380 env->uncached_cpsr &= ~(CPSR_IL | CPSR_J); 9381 env->daif |= mask; 9382 9383 if (cpu_isar_feature(aa32_ssbs, env_archcpu(env))) { 9384 if (env->cp15.sctlr_el[new_el] & SCTLR_DSSBS_32) { 9385 env->uncached_cpsr |= CPSR_SSBS; 9386 } else { 9387 env->uncached_cpsr &= ~CPSR_SSBS; 9388 } 9389 } 9390 9391 if (new_mode == ARM_CPU_MODE_HYP) { 9392 env->thumb = (env->cp15.sctlr_el[2] & SCTLR_TE) != 0; 9393 env->elr_el[2] = env->regs[15]; 9394 } else { 9395 /* CPSR.PAN is normally preserved preserved unless... */ 9396 if (cpu_isar_feature(aa32_pan, env_archcpu(env))) { 9397 switch (new_el) { 9398 case 3: 9399 if (!arm_is_secure_below_el3(env)) { 9400 /* ... the target is EL3, from non-secure state. */ 9401 env->uncached_cpsr &= ~CPSR_PAN; 9402 break; 9403 } 9404 /* ... the target is EL3, from secure state ... */ 9405 /* fall through */ 9406 case 1: 9407 /* ... the target is EL1 and SCTLR.SPAN is 0. */ 9408 if (!(env->cp15.sctlr_el[new_el] & SCTLR_SPAN)) { 9409 env->uncached_cpsr |= CPSR_PAN; 9410 } 9411 break; 9412 } 9413 } 9414 /* 9415 * this is a lie, as there was no c1_sys on V4T/V5, but who cares 9416 * and we should just guard the thumb mode on V4 9417 */ 9418 if (arm_feature(env, ARM_FEATURE_V4T)) { 9419 env->thumb = 9420 (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) != 0; 9421 } 9422 env->regs[14] = env->regs[15] + offset; 9423 } 9424 env->regs[15] = newpc; 9425 arm_rebuild_hflags(env); 9426 } 9427 9428 static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs) 9429 { 9430 /* 9431 * Handle exception entry to Hyp mode; this is sufficiently 9432 * different to entry to other AArch32 modes that we handle it 9433 * separately here. 9434 * 9435 * The vector table entry used is always the 0x14 Hyp mode entry point, 9436 * unless this is an UNDEF/SVC/HVC/abort taken from Hyp to Hyp. 9437 * The offset applied to the preferred return address is always zero 9438 * (see DDI0487C.a section G1.12.3). 9439 * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values. 9440 */ 9441 uint32_t addr, mask; 9442 ARMCPU *cpu = ARM_CPU(cs); 9443 CPUARMState *env = &cpu->env; 9444 9445 switch (cs->exception_index) { 9446 case EXCP_UDEF: 9447 addr = 0x04; 9448 break; 9449 case EXCP_SWI: 9450 addr = 0x08; 9451 break; 9452 case EXCP_BKPT: 9453 /* Fall through to prefetch abort. */ 9454 case EXCP_PREFETCH_ABORT: 9455 env->cp15.ifar_s = env->exception.vaddress; 9456 qemu_log_mask(CPU_LOG_INT, "...with HIFAR 0x%x\n", 9457 (uint32_t)env->exception.vaddress); 9458 addr = 0x0c; 9459 break; 9460 case EXCP_DATA_ABORT: 9461 env->cp15.dfar_s = env->exception.vaddress; 9462 qemu_log_mask(CPU_LOG_INT, "...with HDFAR 0x%x\n", 9463 (uint32_t)env->exception.vaddress); 9464 addr = 0x10; 9465 break; 9466 case EXCP_IRQ: 9467 addr = 0x18; 9468 break; 9469 case EXCP_FIQ: 9470 addr = 0x1c; 9471 break; 9472 case EXCP_HVC: 9473 addr = 0x08; 9474 break; 9475 case EXCP_HYP_TRAP: 9476 addr = 0x14; 9477 break; 9478 default: 9479 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); 9480 } 9481 9482 if (cs->exception_index != EXCP_IRQ && cs->exception_index != EXCP_FIQ) { 9483 if (!arm_feature(env, ARM_FEATURE_V8)) { 9484 /* 9485 * QEMU syndrome values are v8-style. v7 has the IL bit 9486 * UNK/SBZP for "field not valid" cases, where v8 uses RES1. 9487 * If this is a v7 CPU, squash the IL bit in those cases. 9488 */ 9489 if (cs->exception_index == EXCP_PREFETCH_ABORT || 9490 (cs->exception_index == EXCP_DATA_ABORT && 9491 !(env->exception.syndrome & ARM_EL_ISV)) || 9492 syn_get_ec(env->exception.syndrome) == EC_UNCATEGORIZED) { 9493 env->exception.syndrome &= ~ARM_EL_IL; 9494 } 9495 } 9496 env->cp15.esr_el[2] = env->exception.syndrome; 9497 } 9498 9499 if (arm_current_el(env) != 2 && addr < 0x14) { 9500 addr = 0x14; 9501 } 9502 9503 mask = 0; 9504 if (!(env->cp15.scr_el3 & SCR_EA)) { 9505 mask |= CPSR_A; 9506 } 9507 if (!(env->cp15.scr_el3 & SCR_IRQ)) { 9508 mask |= CPSR_I; 9509 } 9510 if (!(env->cp15.scr_el3 & SCR_FIQ)) { 9511 mask |= CPSR_F; 9512 } 9513 9514 addr += env->cp15.hvbar; 9515 9516 take_aarch32_exception(env, ARM_CPU_MODE_HYP, mask, 0, addr); 9517 } 9518 9519 static void arm_cpu_do_interrupt_aarch32(CPUState *cs) 9520 { 9521 ARMCPU *cpu = ARM_CPU(cs); 9522 CPUARMState *env = &cpu->env; 9523 uint32_t addr; 9524 uint32_t mask; 9525 int new_mode; 9526 uint32_t offset; 9527 uint32_t moe; 9528 9529 /* If this is a debug exception we must update the DBGDSCR.MOE bits */ 9530 switch (syn_get_ec(env->exception.syndrome)) { 9531 case EC_BREAKPOINT: 9532 case EC_BREAKPOINT_SAME_EL: 9533 moe = 1; 9534 break; 9535 case EC_WATCHPOINT: 9536 case EC_WATCHPOINT_SAME_EL: 9537 moe = 10; 9538 break; 9539 case EC_AA32_BKPT: 9540 moe = 3; 9541 break; 9542 case EC_VECTORCATCH: 9543 moe = 5; 9544 break; 9545 default: 9546 moe = 0; 9547 break; 9548 } 9549 9550 if (moe) { 9551 env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe); 9552 } 9553 9554 if (env->exception.target_el == 2) { 9555 arm_cpu_do_interrupt_aarch32_hyp(cs); 9556 return; 9557 } 9558 9559 switch (cs->exception_index) { 9560 case EXCP_UDEF: 9561 new_mode = ARM_CPU_MODE_UND; 9562 addr = 0x04; 9563 mask = CPSR_I; 9564 if (env->thumb) 9565 offset = 2; 9566 else 9567 offset = 4; 9568 break; 9569 case EXCP_SWI: 9570 new_mode = ARM_CPU_MODE_SVC; 9571 addr = 0x08; 9572 mask = CPSR_I; 9573 /* The PC already points to the next instruction. */ 9574 offset = 0; 9575 break; 9576 case EXCP_BKPT: 9577 /* Fall through to prefetch abort. */ 9578 case EXCP_PREFETCH_ABORT: 9579 A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr); 9580 A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress); 9581 qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n", 9582 env->exception.fsr, (uint32_t)env->exception.vaddress); 9583 new_mode = ARM_CPU_MODE_ABT; 9584 addr = 0x0c; 9585 mask = CPSR_A | CPSR_I; 9586 offset = 4; 9587 break; 9588 case EXCP_DATA_ABORT: 9589 A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); 9590 A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress); 9591 qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n", 9592 env->exception.fsr, 9593 (uint32_t)env->exception.vaddress); 9594 new_mode = ARM_CPU_MODE_ABT; 9595 addr = 0x10; 9596 mask = CPSR_A | CPSR_I; 9597 offset = 8; 9598 break; 9599 case EXCP_IRQ: 9600 new_mode = ARM_CPU_MODE_IRQ; 9601 addr = 0x18; 9602 /* Disable IRQ and imprecise data aborts. */ 9603 mask = CPSR_A | CPSR_I; 9604 offset = 4; 9605 if (env->cp15.scr_el3 & SCR_IRQ) { 9606 /* IRQ routed to monitor mode */ 9607 new_mode = ARM_CPU_MODE_MON; 9608 mask |= CPSR_F; 9609 } 9610 break; 9611 case EXCP_FIQ: 9612 new_mode = ARM_CPU_MODE_FIQ; 9613 addr = 0x1c; 9614 /* Disable FIQ, IRQ and imprecise data aborts. */ 9615 mask = CPSR_A | CPSR_I | CPSR_F; 9616 if (env->cp15.scr_el3 & SCR_FIQ) { 9617 /* FIQ routed to monitor mode */ 9618 new_mode = ARM_CPU_MODE_MON; 9619 } 9620 offset = 4; 9621 break; 9622 case EXCP_VIRQ: 9623 new_mode = ARM_CPU_MODE_IRQ; 9624 addr = 0x18; 9625 /* Disable IRQ and imprecise data aborts. */ 9626 mask = CPSR_A | CPSR_I; 9627 offset = 4; 9628 break; 9629 case EXCP_VFIQ: 9630 new_mode = ARM_CPU_MODE_FIQ; 9631 addr = 0x1c; 9632 /* Disable FIQ, IRQ and imprecise data aborts. */ 9633 mask = CPSR_A | CPSR_I | CPSR_F; 9634 offset = 4; 9635 break; 9636 case EXCP_VSERR: 9637 { 9638 /* 9639 * Note that this is reported as a data abort, but the DFAR 9640 * has an UNKNOWN value. Construct the SError syndrome from 9641 * AET and ExT fields. 9642 */ 9643 ARMMMUFaultInfo fi = { .type = ARMFault_AsyncExternal, }; 9644 9645 if (extended_addresses_enabled(env)) { 9646 env->exception.fsr = arm_fi_to_lfsc(&fi); 9647 } else { 9648 env->exception.fsr = arm_fi_to_sfsc(&fi); 9649 } 9650 env->exception.fsr |= env->cp15.vsesr_el2 & 0xd000; 9651 A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); 9652 qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x\n", 9653 env->exception.fsr); 9654 9655 new_mode = ARM_CPU_MODE_ABT; 9656 addr = 0x10; 9657 mask = CPSR_A | CPSR_I; 9658 offset = 8; 9659 } 9660 break; 9661 case EXCP_SMC: 9662 new_mode = ARM_CPU_MODE_MON; 9663 addr = 0x08; 9664 mask = CPSR_A | CPSR_I | CPSR_F; 9665 offset = 0; 9666 break; 9667 default: 9668 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); 9669 return; /* Never happens. Keep compiler happy. */ 9670 } 9671 9672 if (new_mode == ARM_CPU_MODE_MON) { 9673 addr += env->cp15.mvbar; 9674 } else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 9675 /* High vectors. When enabled, base address cannot be remapped. */ 9676 addr += 0xffff0000; 9677 } else { 9678 /* ARM v7 architectures provide a vector base address register to remap 9679 * the interrupt vector table. 9680 * This register is only followed in non-monitor mode, and is banked. 9681 * Note: only bits 31:5 are valid. 9682 */ 9683 addr += A32_BANKED_CURRENT_REG_GET(env, vbar); 9684 } 9685 9686 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 9687 env->cp15.scr_el3 &= ~SCR_NS; 9688 } 9689 9690 take_aarch32_exception(env, new_mode, mask, offset, addr); 9691 } 9692 9693 static int aarch64_regnum(CPUARMState *env, int aarch32_reg) 9694 { 9695 /* 9696 * Return the register number of the AArch64 view of the AArch32 9697 * register @aarch32_reg. The CPUARMState CPSR is assumed to still 9698 * be that of the AArch32 mode the exception came from. 9699 */ 9700 int mode = env->uncached_cpsr & CPSR_M; 9701 9702 switch (aarch32_reg) { 9703 case 0 ... 7: 9704 return aarch32_reg; 9705 case 8 ... 12: 9706 return mode == ARM_CPU_MODE_FIQ ? aarch32_reg + 16 : aarch32_reg; 9707 case 13: 9708 switch (mode) { 9709 case ARM_CPU_MODE_USR: 9710 case ARM_CPU_MODE_SYS: 9711 return 13; 9712 case ARM_CPU_MODE_HYP: 9713 return 15; 9714 case ARM_CPU_MODE_IRQ: 9715 return 17; 9716 case ARM_CPU_MODE_SVC: 9717 return 19; 9718 case ARM_CPU_MODE_ABT: 9719 return 21; 9720 case ARM_CPU_MODE_UND: 9721 return 23; 9722 case ARM_CPU_MODE_FIQ: 9723 return 29; 9724 default: 9725 g_assert_not_reached(); 9726 } 9727 case 14: 9728 switch (mode) { 9729 case ARM_CPU_MODE_USR: 9730 case ARM_CPU_MODE_SYS: 9731 case ARM_CPU_MODE_HYP: 9732 return 14; 9733 case ARM_CPU_MODE_IRQ: 9734 return 16; 9735 case ARM_CPU_MODE_SVC: 9736 return 18; 9737 case ARM_CPU_MODE_ABT: 9738 return 20; 9739 case ARM_CPU_MODE_UND: 9740 return 22; 9741 case ARM_CPU_MODE_FIQ: 9742 return 30; 9743 default: 9744 g_assert_not_reached(); 9745 } 9746 case 15: 9747 return 31; 9748 default: 9749 g_assert_not_reached(); 9750 } 9751 } 9752 9753 static uint32_t cpsr_read_for_spsr_elx(CPUARMState *env) 9754 { 9755 uint32_t ret = cpsr_read(env); 9756 9757 /* Move DIT to the correct location for SPSR_ELx */ 9758 if (ret & CPSR_DIT) { 9759 ret &= ~CPSR_DIT; 9760 ret |= PSTATE_DIT; 9761 } 9762 /* Merge PSTATE.SS into SPSR_ELx */ 9763 ret |= env->pstate & PSTATE_SS; 9764 9765 return ret; 9766 } 9767 9768 static bool syndrome_is_sync_extabt(uint32_t syndrome) 9769 { 9770 /* Return true if this syndrome value is a synchronous external abort */ 9771 switch (syn_get_ec(syndrome)) { 9772 case EC_INSNABORT: 9773 case EC_INSNABORT_SAME_EL: 9774 case EC_DATAABORT: 9775 case EC_DATAABORT_SAME_EL: 9776 /* Look at fault status code for all the synchronous ext abort cases */ 9777 switch (syndrome & 0x3f) { 9778 case 0x10: 9779 case 0x13: 9780 case 0x14: 9781 case 0x15: 9782 case 0x16: 9783 case 0x17: 9784 return true; 9785 default: 9786 return false; 9787 } 9788 default: 9789 return false; 9790 } 9791 } 9792 9793 /* Handle exception entry to a target EL which is using AArch64 */ 9794 static void arm_cpu_do_interrupt_aarch64(CPUState *cs) 9795 { 9796 ARMCPU *cpu = ARM_CPU(cs); 9797 CPUARMState *env = &cpu->env; 9798 unsigned int new_el = env->exception.target_el; 9799 target_ulong addr = env->cp15.vbar_el[new_el]; 9800 unsigned int new_mode = aarch64_pstate_mode(new_el, true); 9801 unsigned int old_mode; 9802 unsigned int cur_el = arm_current_el(env); 9803 int rt; 9804 9805 /* 9806 * Note that new_el can never be 0. If cur_el is 0, then 9807 * el0_a64 is is_a64(), else el0_a64 is ignored. 9808 */ 9809 aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); 9810 9811 if (cur_el < new_el) { 9812 /* Entry vector offset depends on whether the implemented EL 9813 * immediately lower than the target level is using AArch32 or AArch64 9814 */ 9815 bool is_aa64; 9816 uint64_t hcr; 9817 9818 switch (new_el) { 9819 case 3: 9820 is_aa64 = (env->cp15.scr_el3 & SCR_RW) != 0; 9821 break; 9822 case 2: 9823 hcr = arm_hcr_el2_eff(env); 9824 if ((hcr & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { 9825 is_aa64 = (hcr & HCR_RW) != 0; 9826 break; 9827 } 9828 /* fall through */ 9829 case 1: 9830 is_aa64 = is_a64(env); 9831 break; 9832 default: 9833 g_assert_not_reached(); 9834 } 9835 9836 if (is_aa64) { 9837 addr += 0x400; 9838 } else { 9839 addr += 0x600; 9840 } 9841 } else if (pstate_read(env) & PSTATE_SP) { 9842 addr += 0x200; 9843 } 9844 9845 switch (cs->exception_index) { 9846 case EXCP_PREFETCH_ABORT: 9847 case EXCP_DATA_ABORT: 9848 /* 9849 * FEAT_DoubleFault allows synchronous external aborts taken to EL3 9850 * to be taken to the SError vector entrypoint. 9851 */ 9852 if (new_el == 3 && (env->cp15.scr_el3 & SCR_EASE) && 9853 syndrome_is_sync_extabt(env->exception.syndrome)) { 9854 addr += 0x180; 9855 } 9856 env->cp15.far_el[new_el] = env->exception.vaddress; 9857 qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n", 9858 env->cp15.far_el[new_el]); 9859 /* fall through */ 9860 case EXCP_BKPT: 9861 case EXCP_UDEF: 9862 case EXCP_SWI: 9863 case EXCP_HVC: 9864 case EXCP_HYP_TRAP: 9865 case EXCP_SMC: 9866 switch (syn_get_ec(env->exception.syndrome)) { 9867 case EC_ADVSIMDFPACCESSTRAP: 9868 /* 9869 * QEMU internal FP/SIMD syndromes from AArch32 include the 9870 * TA and coproc fields which are only exposed if the exception 9871 * is taken to AArch32 Hyp mode. Mask them out to get a valid 9872 * AArch64 format syndrome. 9873 */ 9874 env->exception.syndrome &= ~MAKE_64BIT_MASK(0, 20); 9875 break; 9876 case EC_CP14RTTRAP: 9877 case EC_CP15RTTRAP: 9878 case EC_CP14DTTRAP: 9879 /* 9880 * For a trap on AArch32 MRC/MCR/LDC/STC the Rt field is currently 9881 * the raw register field from the insn; when taking this to 9882 * AArch64 we must convert it to the AArch64 view of the register 9883 * number. Notice that we read a 4-bit AArch32 register number and 9884 * write back a 5-bit AArch64 one. 9885 */ 9886 rt = extract32(env->exception.syndrome, 5, 4); 9887 rt = aarch64_regnum(env, rt); 9888 env->exception.syndrome = deposit32(env->exception.syndrome, 9889 5, 5, rt); 9890 break; 9891 case EC_CP15RRTTRAP: 9892 case EC_CP14RRTTRAP: 9893 /* Similarly for MRRC/MCRR traps for Rt and Rt2 fields */ 9894 rt = extract32(env->exception.syndrome, 5, 4); 9895 rt = aarch64_regnum(env, rt); 9896 env->exception.syndrome = deposit32(env->exception.syndrome, 9897 5, 5, rt); 9898 rt = extract32(env->exception.syndrome, 10, 4); 9899 rt = aarch64_regnum(env, rt); 9900 env->exception.syndrome = deposit32(env->exception.syndrome, 9901 10, 5, rt); 9902 break; 9903 } 9904 env->cp15.esr_el[new_el] = env->exception.syndrome; 9905 break; 9906 case EXCP_IRQ: 9907 case EXCP_VIRQ: 9908 addr += 0x80; 9909 break; 9910 case EXCP_FIQ: 9911 case EXCP_VFIQ: 9912 addr += 0x100; 9913 break; 9914 case EXCP_VSERR: 9915 addr += 0x180; 9916 /* Construct the SError syndrome from IDS and ISS fields. */ 9917 env->exception.syndrome = syn_serror(env->cp15.vsesr_el2 & 0x1ffffff); 9918 env->cp15.esr_el[new_el] = env->exception.syndrome; 9919 break; 9920 default: 9921 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); 9922 } 9923 9924 if (is_a64(env)) { 9925 old_mode = pstate_read(env); 9926 aarch64_save_sp(env, arm_current_el(env)); 9927 env->elr_el[new_el] = env->pc; 9928 } else { 9929 old_mode = cpsr_read_for_spsr_elx(env); 9930 env->elr_el[new_el] = env->regs[15]; 9931 9932 aarch64_sync_32_to_64(env); 9933 9934 env->condexec_bits = 0; 9935 } 9936 env->banked_spsr[aarch64_banked_spsr_index(new_el)] = old_mode; 9937 9938 qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n", 9939 env->elr_el[new_el]); 9940 9941 if (cpu_isar_feature(aa64_pan, cpu)) { 9942 /* The value of PSTATE.PAN is normally preserved, except when ... */ 9943 new_mode |= old_mode & PSTATE_PAN; 9944 switch (new_el) { 9945 case 2: 9946 /* ... the target is EL2 with HCR_EL2.{E2H,TGE} == '11' ... */ 9947 if ((arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) 9948 != (HCR_E2H | HCR_TGE)) { 9949 break; 9950 } 9951 /* fall through */ 9952 case 1: 9953 /* ... the target is EL1 ... */ 9954 /* ... and SCTLR_ELx.SPAN == 0, then set to 1. */ 9955 if ((env->cp15.sctlr_el[new_el] & SCTLR_SPAN) == 0) { 9956 new_mode |= PSTATE_PAN; 9957 } 9958 break; 9959 } 9960 } 9961 if (cpu_isar_feature(aa64_mte, cpu)) { 9962 new_mode |= PSTATE_TCO; 9963 } 9964 9965 if (cpu_isar_feature(aa64_ssbs, cpu)) { 9966 if (env->cp15.sctlr_el[new_el] & SCTLR_DSSBS_64) { 9967 new_mode |= PSTATE_SSBS; 9968 } else { 9969 new_mode &= ~PSTATE_SSBS; 9970 } 9971 } 9972 9973 pstate_write(env, PSTATE_DAIF | new_mode); 9974 env->aarch64 = true; 9975 aarch64_restore_sp(env, new_el); 9976 helper_rebuild_hflags_a64(env, new_el); 9977 9978 env->pc = addr; 9979 9980 qemu_log_mask(CPU_LOG_INT, "...to EL%d PC 0x%" PRIx64 " PSTATE 0x%x\n", 9981 new_el, env->pc, pstate_read(env)); 9982 } 9983 9984 /* 9985 * Do semihosting call and set the appropriate return value. All the 9986 * permission and validity checks have been done at translate time. 9987 * 9988 * We only see semihosting exceptions in TCG only as they are not 9989 * trapped to the hypervisor in KVM. 9990 */ 9991 #ifdef CONFIG_TCG 9992 static void handle_semihosting(CPUState *cs) 9993 { 9994 ARMCPU *cpu = ARM_CPU(cs); 9995 CPUARMState *env = &cpu->env; 9996 9997 if (is_a64(env)) { 9998 qemu_log_mask(CPU_LOG_INT, 9999 "...handling as semihosting call 0x%" PRIx64 "\n", 10000 env->xregs[0]); 10001 do_common_semihosting(cs); 10002 env->pc += 4; 10003 } else { 10004 qemu_log_mask(CPU_LOG_INT, 10005 "...handling as semihosting call 0x%x\n", 10006 env->regs[0]); 10007 do_common_semihosting(cs); 10008 env->regs[15] += env->thumb ? 2 : 4; 10009 } 10010 } 10011 #endif 10012 10013 /* Handle a CPU exception for A and R profile CPUs. 10014 * Do any appropriate logging, handle PSCI calls, and then hand off 10015 * to the AArch64-entry or AArch32-entry function depending on the 10016 * target exception level's register width. 10017 * 10018 * Note: this is used for both TCG (as the do_interrupt tcg op), 10019 * and KVM to re-inject guest debug exceptions, and to 10020 * inject a Synchronous-External-Abort. 10021 */ 10022 void arm_cpu_do_interrupt(CPUState *cs) 10023 { 10024 ARMCPU *cpu = ARM_CPU(cs); 10025 CPUARMState *env = &cpu->env; 10026 unsigned int new_el = env->exception.target_el; 10027 10028 assert(!arm_feature(env, ARM_FEATURE_M)); 10029 10030 arm_log_exception(cs); 10031 qemu_log_mask(CPU_LOG_INT, "...from EL%d to EL%d\n", arm_current_el(env), 10032 new_el); 10033 if (qemu_loglevel_mask(CPU_LOG_INT) 10034 && !excp_is_internal(cs->exception_index)) { 10035 qemu_log_mask(CPU_LOG_INT, "...with ESR 0x%x/0x%" PRIx32 "\n", 10036 syn_get_ec(env->exception.syndrome), 10037 env->exception.syndrome); 10038 } 10039 10040 if (arm_is_psci_call(cpu, cs->exception_index)) { 10041 arm_handle_psci_call(cpu); 10042 qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n"); 10043 return; 10044 } 10045 10046 /* 10047 * Semihosting semantics depend on the register width of the code 10048 * that caused the exception, not the target exception level, so 10049 * must be handled here. 10050 */ 10051 #ifdef CONFIG_TCG 10052 if (cs->exception_index == EXCP_SEMIHOST) { 10053 handle_semihosting(cs); 10054 return; 10055 } 10056 #endif 10057 10058 /* Hooks may change global state so BQL should be held, also the 10059 * BQL needs to be held for any modification of 10060 * cs->interrupt_request. 10061 */ 10062 g_assert(qemu_mutex_iothread_locked()); 10063 10064 arm_call_pre_el_change_hook(cpu); 10065 10066 assert(!excp_is_internal(cs->exception_index)); 10067 if (arm_el_is_aa64(env, new_el)) { 10068 arm_cpu_do_interrupt_aarch64(cs); 10069 } else { 10070 arm_cpu_do_interrupt_aarch32(cs); 10071 } 10072 10073 arm_call_el_change_hook(cpu); 10074 10075 if (!kvm_enabled()) { 10076 cs->interrupt_request |= CPU_INTERRUPT_EXITTB; 10077 } 10078 } 10079 #endif /* !CONFIG_USER_ONLY */ 10080 10081 uint64_t arm_sctlr(CPUARMState *env, int el) 10082 { 10083 /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */ 10084 if (el == 0) { 10085 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, 0); 10086 el = (mmu_idx == ARMMMUIdx_E20_0 || mmu_idx == ARMMMUIdx_SE20_0) 10087 ? 2 : 1; 10088 } 10089 return env->cp15.sctlr_el[el]; 10090 } 10091 10092 int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx) 10093 { 10094 if (regime_has_2_ranges(mmu_idx)) { 10095 return extract64(tcr, 37, 2); 10096 } else if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) { 10097 return 0; /* VTCR_EL2 */ 10098 } else { 10099 /* Replicate the single TBI bit so we always have 2 bits. */ 10100 return extract32(tcr, 20, 1) * 3; 10101 } 10102 } 10103 10104 int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx) 10105 { 10106 if (regime_has_2_ranges(mmu_idx)) { 10107 return extract64(tcr, 51, 2); 10108 } else if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) { 10109 return 0; /* VTCR_EL2 */ 10110 } else { 10111 /* Replicate the single TBID bit so we always have 2 bits. */ 10112 return extract32(tcr, 29, 1) * 3; 10113 } 10114 } 10115 10116 static int aa64_va_parameter_tcma(uint64_t tcr, ARMMMUIdx mmu_idx) 10117 { 10118 if (regime_has_2_ranges(mmu_idx)) { 10119 return extract64(tcr, 57, 2); 10120 } else { 10121 /* Replicate the single TCMA bit so we always have 2 bits. */ 10122 return extract32(tcr, 30, 1) * 3; 10123 } 10124 } 10125 10126 ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, 10127 ARMMMUIdx mmu_idx, bool data) 10128 { 10129 uint64_t tcr = regime_tcr(env, mmu_idx); 10130 bool epd, hpd, using16k, using64k, tsz_oob, ds; 10131 int select, tsz, tbi, max_tsz, min_tsz, ps, sh; 10132 ARMCPU *cpu = env_archcpu(env); 10133 10134 if (!regime_has_2_ranges(mmu_idx)) { 10135 select = 0; 10136 tsz = extract32(tcr, 0, 6); 10137 using64k = extract32(tcr, 14, 1); 10138 using16k = extract32(tcr, 15, 1); 10139 if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) { 10140 /* VTCR_EL2 */ 10141 hpd = false; 10142 } else { 10143 hpd = extract32(tcr, 24, 1); 10144 } 10145 epd = false; 10146 sh = extract32(tcr, 12, 2); 10147 ps = extract32(tcr, 16, 3); 10148 ds = extract64(tcr, 32, 1); 10149 } else { 10150 /* 10151 * Bit 55 is always between the two regions, and is canonical for 10152 * determining if address tagging is enabled. 10153 */ 10154 select = extract64(va, 55, 1); 10155 if (!select) { 10156 tsz = extract32(tcr, 0, 6); 10157 epd = extract32(tcr, 7, 1); 10158 sh = extract32(tcr, 12, 2); 10159 using64k = extract32(tcr, 14, 1); 10160 using16k = extract32(tcr, 15, 1); 10161 hpd = extract64(tcr, 41, 1); 10162 } else { 10163 int tg = extract32(tcr, 30, 2); 10164 using16k = tg == 1; 10165 using64k = tg == 3; 10166 tsz = extract32(tcr, 16, 6); 10167 epd = extract32(tcr, 23, 1); 10168 sh = extract32(tcr, 28, 2); 10169 hpd = extract64(tcr, 42, 1); 10170 } 10171 ps = extract64(tcr, 32, 3); 10172 ds = extract64(tcr, 59, 1); 10173 } 10174 10175 if (cpu_isar_feature(aa64_st, cpu)) { 10176 max_tsz = 48 - using64k; 10177 } else { 10178 max_tsz = 39; 10179 } 10180 10181 /* 10182 * DS is RES0 unless FEAT_LPA2 is supported for the given page size; 10183 * adjust the effective value of DS, as documented. 10184 */ 10185 min_tsz = 16; 10186 if (using64k) { 10187 if (cpu_isar_feature(aa64_lva, cpu)) { 10188 min_tsz = 12; 10189 } 10190 ds = false; 10191 } else if (ds) { 10192 switch (mmu_idx) { 10193 case ARMMMUIdx_Stage2: 10194 case ARMMMUIdx_Stage2_S: 10195 if (using16k) { 10196 ds = cpu_isar_feature(aa64_tgran16_2_lpa2, cpu); 10197 } else { 10198 ds = cpu_isar_feature(aa64_tgran4_2_lpa2, cpu); 10199 } 10200 break; 10201 default: 10202 if (using16k) { 10203 ds = cpu_isar_feature(aa64_tgran16_lpa2, cpu); 10204 } else { 10205 ds = cpu_isar_feature(aa64_tgran4_lpa2, cpu); 10206 } 10207 break; 10208 } 10209 if (ds) { 10210 min_tsz = 12; 10211 } 10212 } 10213 10214 if (tsz > max_tsz) { 10215 tsz = max_tsz; 10216 tsz_oob = true; 10217 } else if (tsz < min_tsz) { 10218 tsz = min_tsz; 10219 tsz_oob = true; 10220 } else { 10221 tsz_oob = false; 10222 } 10223 10224 /* Present TBI as a composite with TBID. */ 10225 tbi = aa64_va_parameter_tbi(tcr, mmu_idx); 10226 if (!data) { 10227 tbi &= ~aa64_va_parameter_tbid(tcr, mmu_idx); 10228 } 10229 tbi = (tbi >> select) & 1; 10230 10231 return (ARMVAParameters) { 10232 .tsz = tsz, 10233 .ps = ps, 10234 .sh = sh, 10235 .select = select, 10236 .tbi = tbi, 10237 .epd = epd, 10238 .hpd = hpd, 10239 .using16k = using16k, 10240 .using64k = using64k, 10241 .tsz_oob = tsz_oob, 10242 .ds = ds, 10243 }; 10244 } 10245 10246 /* Note that signed overflow is undefined in C. The following routines are 10247 careful to use unsigned types where modulo arithmetic is required. 10248 Failure to do so _will_ break on newer gcc. */ 10249 10250 /* Signed saturating arithmetic. */ 10251 10252 /* Perform 16-bit signed saturating addition. */ 10253 static inline uint16_t add16_sat(uint16_t a, uint16_t b) 10254 { 10255 uint16_t res; 10256 10257 res = a + b; 10258 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) { 10259 if (a & 0x8000) 10260 res = 0x8000; 10261 else 10262 res = 0x7fff; 10263 } 10264 return res; 10265 } 10266 10267 /* Perform 8-bit signed saturating addition. */ 10268 static inline uint8_t add8_sat(uint8_t a, uint8_t b) 10269 { 10270 uint8_t res; 10271 10272 res = a + b; 10273 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) { 10274 if (a & 0x80) 10275 res = 0x80; 10276 else 10277 res = 0x7f; 10278 } 10279 return res; 10280 } 10281 10282 /* Perform 16-bit signed saturating subtraction. */ 10283 static inline uint16_t sub16_sat(uint16_t a, uint16_t b) 10284 { 10285 uint16_t res; 10286 10287 res = a - b; 10288 if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) { 10289 if (a & 0x8000) 10290 res = 0x8000; 10291 else 10292 res = 0x7fff; 10293 } 10294 return res; 10295 } 10296 10297 /* Perform 8-bit signed saturating subtraction. */ 10298 static inline uint8_t sub8_sat(uint8_t a, uint8_t b) 10299 { 10300 uint8_t res; 10301 10302 res = a - b; 10303 if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) { 10304 if (a & 0x80) 10305 res = 0x80; 10306 else 10307 res = 0x7f; 10308 } 10309 return res; 10310 } 10311 10312 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16); 10313 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16); 10314 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8); 10315 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8); 10316 #define PFX q 10317 10318 #include "op_addsub.h" 10319 10320 /* Unsigned saturating arithmetic. */ 10321 static inline uint16_t add16_usat(uint16_t a, uint16_t b) 10322 { 10323 uint16_t res; 10324 res = a + b; 10325 if (res < a) 10326 res = 0xffff; 10327 return res; 10328 } 10329 10330 static inline uint16_t sub16_usat(uint16_t a, uint16_t b) 10331 { 10332 if (a > b) 10333 return a - b; 10334 else 10335 return 0; 10336 } 10337 10338 static inline uint8_t add8_usat(uint8_t a, uint8_t b) 10339 { 10340 uint8_t res; 10341 res = a + b; 10342 if (res < a) 10343 res = 0xff; 10344 return res; 10345 } 10346 10347 static inline uint8_t sub8_usat(uint8_t a, uint8_t b) 10348 { 10349 if (a > b) 10350 return a - b; 10351 else 10352 return 0; 10353 } 10354 10355 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16); 10356 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16); 10357 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8); 10358 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8); 10359 #define PFX uq 10360 10361 #include "op_addsub.h" 10362 10363 /* Signed modulo arithmetic. */ 10364 #define SARITH16(a, b, n, op) do { \ 10365 int32_t sum; \ 10366 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \ 10367 RESULT(sum, n, 16); \ 10368 if (sum >= 0) \ 10369 ge |= 3 << (n * 2); \ 10370 } while(0) 10371 10372 #define SARITH8(a, b, n, op) do { \ 10373 int32_t sum; \ 10374 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \ 10375 RESULT(sum, n, 8); \ 10376 if (sum >= 0) \ 10377 ge |= 1 << n; \ 10378 } while(0) 10379 10380 10381 #define ADD16(a, b, n) SARITH16(a, b, n, +) 10382 #define SUB16(a, b, n) SARITH16(a, b, n, -) 10383 #define ADD8(a, b, n) SARITH8(a, b, n, +) 10384 #define SUB8(a, b, n) SARITH8(a, b, n, -) 10385 #define PFX s 10386 #define ARITH_GE 10387 10388 #include "op_addsub.h" 10389 10390 /* Unsigned modulo arithmetic. */ 10391 #define ADD16(a, b, n) do { \ 10392 uint32_t sum; \ 10393 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \ 10394 RESULT(sum, n, 16); \ 10395 if ((sum >> 16) == 1) \ 10396 ge |= 3 << (n * 2); \ 10397 } while(0) 10398 10399 #define ADD8(a, b, n) do { \ 10400 uint32_t sum; \ 10401 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \ 10402 RESULT(sum, n, 8); \ 10403 if ((sum >> 8) == 1) \ 10404 ge |= 1 << n; \ 10405 } while(0) 10406 10407 #define SUB16(a, b, n) do { \ 10408 uint32_t sum; \ 10409 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \ 10410 RESULT(sum, n, 16); \ 10411 if ((sum >> 16) == 0) \ 10412 ge |= 3 << (n * 2); \ 10413 } while(0) 10414 10415 #define SUB8(a, b, n) do { \ 10416 uint32_t sum; \ 10417 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \ 10418 RESULT(sum, n, 8); \ 10419 if ((sum >> 8) == 0) \ 10420 ge |= 1 << n; \ 10421 } while(0) 10422 10423 #define PFX u 10424 #define ARITH_GE 10425 10426 #include "op_addsub.h" 10427 10428 /* Halved signed arithmetic. */ 10429 #define ADD16(a, b, n) \ 10430 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16) 10431 #define SUB16(a, b, n) \ 10432 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16) 10433 #define ADD8(a, b, n) \ 10434 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8) 10435 #define SUB8(a, b, n) \ 10436 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8) 10437 #define PFX sh 10438 10439 #include "op_addsub.h" 10440 10441 /* Halved unsigned arithmetic. */ 10442 #define ADD16(a, b, n) \ 10443 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16) 10444 #define SUB16(a, b, n) \ 10445 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16) 10446 #define ADD8(a, b, n) \ 10447 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8) 10448 #define SUB8(a, b, n) \ 10449 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8) 10450 #define PFX uh 10451 10452 #include "op_addsub.h" 10453 10454 static inline uint8_t do_usad(uint8_t a, uint8_t b) 10455 { 10456 if (a > b) 10457 return a - b; 10458 else 10459 return b - a; 10460 } 10461 10462 /* Unsigned sum of absolute byte differences. */ 10463 uint32_t HELPER(usad8)(uint32_t a, uint32_t b) 10464 { 10465 uint32_t sum; 10466 sum = do_usad(a, b); 10467 sum += do_usad(a >> 8, b >> 8); 10468 sum += do_usad(a >> 16, b >> 16); 10469 sum += do_usad(a >> 24, b >> 24); 10470 return sum; 10471 } 10472 10473 /* For ARMv6 SEL instruction. */ 10474 uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b) 10475 { 10476 uint32_t mask; 10477 10478 mask = 0; 10479 if (flags & 1) 10480 mask |= 0xff; 10481 if (flags & 2) 10482 mask |= 0xff00; 10483 if (flags & 4) 10484 mask |= 0xff0000; 10485 if (flags & 8) 10486 mask |= 0xff000000; 10487 return (a & mask) | (b & ~mask); 10488 } 10489 10490 /* CRC helpers. 10491 * The upper bytes of val (above the number specified by 'bytes') must have 10492 * been zeroed out by the caller. 10493 */ 10494 uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes) 10495 { 10496 uint8_t buf[4]; 10497 10498 stl_le_p(buf, val); 10499 10500 /* zlib crc32 converts the accumulator and output to one's complement. */ 10501 return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff; 10502 } 10503 10504 uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes) 10505 { 10506 uint8_t buf[4]; 10507 10508 stl_le_p(buf, val); 10509 10510 /* Linux crc32c converts the output to one's complement. */ 10511 return crc32c(acc, buf, bytes) ^ 0xffffffff; 10512 } 10513 10514 /* Return the exception level to which FP-disabled exceptions should 10515 * be taken, or 0 if FP is enabled. 10516 */ 10517 int fp_exception_el(CPUARMState *env, int cur_el) 10518 { 10519 #ifndef CONFIG_USER_ONLY 10520 uint64_t hcr_el2; 10521 10522 /* CPACR and the CPTR registers don't exist before v6, so FP is 10523 * always accessible 10524 */ 10525 if (!arm_feature(env, ARM_FEATURE_V6)) { 10526 return 0; 10527 } 10528 10529 if (arm_feature(env, ARM_FEATURE_M)) { 10530 /* CPACR can cause a NOCP UsageFault taken to current security state */ 10531 if (!v7m_cpacr_pass(env, env->v7m.secure, cur_el != 0)) { 10532 return 1; 10533 } 10534 10535 if (arm_feature(env, ARM_FEATURE_M_SECURITY) && !env->v7m.secure) { 10536 if (!extract32(env->v7m.nsacr, 10, 1)) { 10537 /* FP insns cause a NOCP UsageFault taken to Secure */ 10538 return 3; 10539 } 10540 } 10541 10542 return 0; 10543 } 10544 10545 hcr_el2 = arm_hcr_el2_eff(env); 10546 10547 /* The CPACR controls traps to EL1, or PL1 if we're 32 bit: 10548 * 0, 2 : trap EL0 and EL1/PL1 accesses 10549 * 1 : trap only EL0 accesses 10550 * 3 : trap no accesses 10551 * This register is ignored if E2H+TGE are both set. 10552 */ 10553 if ((hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { 10554 int fpen = FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, FPEN); 10555 10556 switch (fpen) { 10557 case 1: 10558 if (cur_el != 0) { 10559 break; 10560 } 10561 /* fall through */ 10562 case 0: 10563 case 2: 10564 /* Trap from Secure PL0 or PL1 to Secure PL1. */ 10565 if (!arm_el_is_aa64(env, 3) 10566 && (cur_el == 3 || arm_is_secure_below_el3(env))) { 10567 return 3; 10568 } 10569 if (cur_el <= 1) { 10570 return 1; 10571 } 10572 break; 10573 } 10574 } 10575 10576 /* 10577 * The NSACR allows A-profile AArch32 EL3 and M-profile secure mode 10578 * to control non-secure access to the FPU. It doesn't have any 10579 * effect if EL3 is AArch64 or if EL3 doesn't exist at all. 10580 */ 10581 if ((arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && 10582 cur_el <= 2 && !arm_is_secure_below_el3(env))) { 10583 if (!extract32(env->cp15.nsacr, 10, 1)) { 10584 /* FP insns act as UNDEF */ 10585 return cur_el == 2 ? 2 : 1; 10586 } 10587 } 10588 10589 /* 10590 * CPTR_EL2 is present in v7VE or v8, and changes format 10591 * with HCR_EL2.E2H (regardless of TGE). 10592 */ 10593 if (cur_el <= 2) { 10594 if (hcr_el2 & HCR_E2H) { 10595 switch (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, FPEN)) { 10596 case 1: 10597 if (cur_el != 0 || !(hcr_el2 & HCR_TGE)) { 10598 break; 10599 } 10600 /* fall through */ 10601 case 0: 10602 case 2: 10603 return 2; 10604 } 10605 } else if (arm_is_el2_enabled(env)) { 10606 if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TFP)) { 10607 return 2; 10608 } 10609 } 10610 } 10611 10612 /* CPTR_EL3 : present in v8 */ 10613 if (FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, TFP)) { 10614 /* Trap all FP ops to EL3 */ 10615 return 3; 10616 } 10617 #endif 10618 return 0; 10619 } 10620 10621 /* Return the exception level we're running at if this is our mmu_idx */ 10622 int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) 10623 { 10624 if (mmu_idx & ARM_MMU_IDX_M) { 10625 return mmu_idx & ARM_MMU_IDX_M_PRIV; 10626 } 10627 10628 switch (mmu_idx) { 10629 case ARMMMUIdx_E10_0: 10630 case ARMMMUIdx_E20_0: 10631 case ARMMMUIdx_SE10_0: 10632 case ARMMMUIdx_SE20_0: 10633 return 0; 10634 case ARMMMUIdx_E10_1: 10635 case ARMMMUIdx_E10_1_PAN: 10636 case ARMMMUIdx_SE10_1: 10637 case ARMMMUIdx_SE10_1_PAN: 10638 return 1; 10639 case ARMMMUIdx_E2: 10640 case ARMMMUIdx_E20_2: 10641 case ARMMMUIdx_E20_2_PAN: 10642 case ARMMMUIdx_SE2: 10643 case ARMMMUIdx_SE20_2: 10644 case ARMMMUIdx_SE20_2_PAN: 10645 return 2; 10646 case ARMMMUIdx_SE3: 10647 return 3; 10648 default: 10649 g_assert_not_reached(); 10650 } 10651 } 10652 10653 #ifndef CONFIG_TCG 10654 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) 10655 { 10656 g_assert_not_reached(); 10657 } 10658 #endif 10659 10660 ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) 10661 { 10662 ARMMMUIdx idx; 10663 uint64_t hcr; 10664 10665 if (arm_feature(env, ARM_FEATURE_M)) { 10666 return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); 10667 } 10668 10669 /* See ARM pseudo-function ELIsInHost. */ 10670 switch (el) { 10671 case 0: 10672 hcr = arm_hcr_el2_eff(env); 10673 if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { 10674 idx = ARMMMUIdx_E20_0; 10675 } else { 10676 idx = ARMMMUIdx_E10_0; 10677 } 10678 break; 10679 case 1: 10680 if (env->pstate & PSTATE_PAN) { 10681 idx = ARMMMUIdx_E10_1_PAN; 10682 } else { 10683 idx = ARMMMUIdx_E10_1; 10684 } 10685 break; 10686 case 2: 10687 /* Note that TGE does not apply at EL2. */ 10688 if (arm_hcr_el2_eff(env) & HCR_E2H) { 10689 if (env->pstate & PSTATE_PAN) { 10690 idx = ARMMMUIdx_E20_2_PAN; 10691 } else { 10692 idx = ARMMMUIdx_E20_2; 10693 } 10694 } else { 10695 idx = ARMMMUIdx_E2; 10696 } 10697 break; 10698 case 3: 10699 return ARMMMUIdx_SE3; 10700 default: 10701 g_assert_not_reached(); 10702 } 10703 10704 if (arm_is_secure_below_el3(env)) { 10705 idx &= ~ARM_MMU_IDX_A_NS; 10706 } 10707 10708 return idx; 10709 } 10710 10711 ARMMMUIdx arm_mmu_idx(CPUARMState *env) 10712 { 10713 return arm_mmu_idx_el(env, arm_current_el(env)); 10714 } 10715 10716 static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el, 10717 ARMMMUIdx mmu_idx, 10718 CPUARMTBFlags flags) 10719 { 10720 DP_TBFLAG_ANY(flags, FPEXC_EL, fp_el); 10721 DP_TBFLAG_ANY(flags, MMUIDX, arm_to_core_mmu_idx(mmu_idx)); 10722 10723 if (arm_singlestep_active(env)) { 10724 DP_TBFLAG_ANY(flags, SS_ACTIVE, 1); 10725 } 10726 return flags; 10727 } 10728 10729 static CPUARMTBFlags rebuild_hflags_common_32(CPUARMState *env, int fp_el, 10730 ARMMMUIdx mmu_idx, 10731 CPUARMTBFlags flags) 10732 { 10733 bool sctlr_b = arm_sctlr_b(env); 10734 10735 if (sctlr_b) { 10736 DP_TBFLAG_A32(flags, SCTLR__B, 1); 10737 } 10738 if (arm_cpu_data_is_big_endian_a32(env, sctlr_b)) { 10739 DP_TBFLAG_ANY(flags, BE_DATA, 1); 10740 } 10741 DP_TBFLAG_A32(flags, NS, !access_secure_reg(env)); 10742 10743 return rebuild_hflags_common(env, fp_el, mmu_idx, flags); 10744 } 10745 10746 static CPUARMTBFlags rebuild_hflags_m32(CPUARMState *env, int fp_el, 10747 ARMMMUIdx mmu_idx) 10748 { 10749 CPUARMTBFlags flags = {}; 10750 uint32_t ccr = env->v7m.ccr[env->v7m.secure]; 10751 10752 /* Without HaveMainExt, CCR.UNALIGN_TRP is RES1. */ 10753 if (ccr & R_V7M_CCR_UNALIGN_TRP_MASK) { 10754 DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); 10755 } 10756 10757 if (arm_v7m_is_handler_mode(env)) { 10758 DP_TBFLAG_M32(flags, HANDLER, 1); 10759 } 10760 10761 /* 10762 * v8M always applies stack limit checks unless CCR.STKOFHFNMIGN 10763 * is suppressing them because the requested execution priority 10764 * is less than 0. 10765 */ 10766 if (arm_feature(env, ARM_FEATURE_V8) && 10767 !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) && 10768 (ccr & R_V7M_CCR_STKOFHFNMIGN_MASK))) { 10769 DP_TBFLAG_M32(flags, STACKCHECK, 1); 10770 } 10771 10772 return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); 10773 } 10774 10775 static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el, 10776 ARMMMUIdx mmu_idx) 10777 { 10778 CPUARMTBFlags flags = {}; 10779 int el = arm_current_el(env); 10780 10781 if (arm_sctlr(env, el) & SCTLR_A) { 10782 DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); 10783 } 10784 10785 if (arm_el_is_aa64(env, 1)) { 10786 DP_TBFLAG_A32(flags, VFPEN, 1); 10787 } 10788 10789 if (el < 2 && env->cp15.hstr_el2 && 10790 (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { 10791 DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1); 10792 } 10793 10794 if (env->uncached_cpsr & CPSR_IL) { 10795 DP_TBFLAG_ANY(flags, PSTATE__IL, 1); 10796 } 10797 10798 /* 10799 * The SME exception we are testing for is raised via 10800 * AArch64.CheckFPAdvSIMDEnabled(), as called from 10801 * AArch32.CheckAdvSIMDOrFPEnabled(). 10802 */ 10803 if (el == 0 10804 && FIELD_EX64(env->svcr, SVCR, SM) 10805 && (!arm_is_el2_enabled(env) 10806 || (arm_el_is_aa64(env, 2) && !(env->cp15.hcr_el2 & HCR_TGE))) 10807 && arm_el_is_aa64(env, 1) 10808 && !sme_fa64(env, el)) { 10809 DP_TBFLAG_A32(flags, SME_TRAP_NONSTREAMING, 1); 10810 } 10811 10812 return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); 10813 } 10814 10815 static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, 10816 ARMMMUIdx mmu_idx) 10817 { 10818 CPUARMTBFlags flags = {}; 10819 ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); 10820 uint64_t tcr = regime_tcr(env, mmu_idx); 10821 uint64_t sctlr; 10822 int tbii, tbid; 10823 10824 DP_TBFLAG_ANY(flags, AARCH64_STATE, 1); 10825 10826 /* Get control bits for tagged addresses. */ 10827 tbid = aa64_va_parameter_tbi(tcr, mmu_idx); 10828 tbii = tbid & ~aa64_va_parameter_tbid(tcr, mmu_idx); 10829 10830 DP_TBFLAG_A64(flags, TBII, tbii); 10831 DP_TBFLAG_A64(flags, TBID, tbid); 10832 10833 if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { 10834 int sve_el = sve_exception_el(env, el); 10835 10836 /* 10837 * If either FP or SVE are disabled, translator does not need len. 10838 * If SVE EL > FP EL, FP exception has precedence, and translator 10839 * does not need SVE EL. Save potential re-translations by forcing 10840 * the unneeded data to zero. 10841 */ 10842 if (fp_el != 0) { 10843 if (sve_el > fp_el) { 10844 sve_el = 0; 10845 } 10846 } else if (sve_el == 0) { 10847 DP_TBFLAG_A64(flags, VL, sve_vqm1_for_el(env, el)); 10848 } 10849 DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el); 10850 } 10851 if (cpu_isar_feature(aa64_sme, env_archcpu(env))) { 10852 int sme_el = sme_exception_el(env, el); 10853 bool sm = FIELD_EX64(env->svcr, SVCR, SM); 10854 10855 DP_TBFLAG_A64(flags, SMEEXC_EL, sme_el); 10856 if (sme_el == 0) { 10857 /* Similarly, do not compute SVL if SME is disabled. */ 10858 int svl = sve_vqm1_for_el_sm(env, el, true); 10859 DP_TBFLAG_A64(flags, SVL, svl); 10860 if (sm) { 10861 /* If SVE is disabled, we will not have set VL above. */ 10862 DP_TBFLAG_A64(flags, VL, svl); 10863 } 10864 } 10865 if (sm) { 10866 DP_TBFLAG_A64(flags, PSTATE_SM, 1); 10867 DP_TBFLAG_A64(flags, SME_TRAP_NONSTREAMING, !sme_fa64(env, el)); 10868 } 10869 DP_TBFLAG_A64(flags, PSTATE_ZA, FIELD_EX64(env->svcr, SVCR, ZA)); 10870 } 10871 10872 sctlr = regime_sctlr(env, stage1); 10873 10874 if (sctlr & SCTLR_A) { 10875 DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); 10876 } 10877 10878 if (arm_cpu_data_is_big_endian_a64(el, sctlr)) { 10879 DP_TBFLAG_ANY(flags, BE_DATA, 1); 10880 } 10881 10882 if (cpu_isar_feature(aa64_pauth, env_archcpu(env))) { 10883 /* 10884 * In order to save space in flags, we record only whether 10885 * pauth is "inactive", meaning all insns are implemented as 10886 * a nop, or "active" when some action must be performed. 10887 * The decision of which action to take is left to a helper. 10888 */ 10889 if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) { 10890 DP_TBFLAG_A64(flags, PAUTH_ACTIVE, 1); 10891 } 10892 } 10893 10894 if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { 10895 /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */ 10896 if (sctlr & (el == 0 ? SCTLR_BT0 : SCTLR_BT1)) { 10897 DP_TBFLAG_A64(flags, BT, 1); 10898 } 10899 } 10900 10901 /* Compute the condition for using AccType_UNPRIV for LDTR et al. */ 10902 if (!(env->pstate & PSTATE_UAO)) { 10903 switch (mmu_idx) { 10904 case ARMMMUIdx_E10_1: 10905 case ARMMMUIdx_E10_1_PAN: 10906 case ARMMMUIdx_SE10_1: 10907 case ARMMMUIdx_SE10_1_PAN: 10908 /* TODO: ARMv8.3-NV */ 10909 DP_TBFLAG_A64(flags, UNPRIV, 1); 10910 break; 10911 case ARMMMUIdx_E20_2: 10912 case ARMMMUIdx_E20_2_PAN: 10913 case ARMMMUIdx_SE20_2: 10914 case ARMMMUIdx_SE20_2_PAN: 10915 /* 10916 * Note that EL20_2 is gated by HCR_EL2.E2H == 1, but EL20_0 is 10917 * gated by HCR_EL2.<E2H,TGE> == '11', and so is LDTR. 10918 */ 10919 if (env->cp15.hcr_el2 & HCR_TGE) { 10920 DP_TBFLAG_A64(flags, UNPRIV, 1); 10921 } 10922 break; 10923 default: 10924 break; 10925 } 10926 } 10927 10928 if (env->pstate & PSTATE_IL) { 10929 DP_TBFLAG_ANY(flags, PSTATE__IL, 1); 10930 } 10931 10932 if (cpu_isar_feature(aa64_mte, env_archcpu(env))) { 10933 /* 10934 * Set MTE_ACTIVE if any access may be Checked, and leave clear 10935 * if all accesses must be Unchecked: 10936 * 1) If no TBI, then there are no tags in the address to check, 10937 * 2) If Tag Check Override, then all accesses are Unchecked, 10938 * 3) If Tag Check Fail == 0, then Checked access have no effect, 10939 * 4) If no Allocation Tag Access, then all accesses are Unchecked. 10940 */ 10941 if (allocation_tag_access_enabled(env, el, sctlr)) { 10942 DP_TBFLAG_A64(flags, ATA, 1); 10943 if (tbid 10944 && !(env->pstate & PSTATE_TCO) 10945 && (sctlr & (el == 0 ? SCTLR_TCF0 : SCTLR_TCF))) { 10946 DP_TBFLAG_A64(flags, MTE_ACTIVE, 1); 10947 } 10948 } 10949 /* And again for unprivileged accesses, if required. */ 10950 if (EX_TBFLAG_A64(flags, UNPRIV) 10951 && tbid 10952 && !(env->pstate & PSTATE_TCO) 10953 && (sctlr & SCTLR_TCF0) 10954 && allocation_tag_access_enabled(env, 0, sctlr)) { 10955 DP_TBFLAG_A64(flags, MTE0_ACTIVE, 1); 10956 } 10957 /* Cache TCMA as well as TBI. */ 10958 DP_TBFLAG_A64(flags, TCMA, aa64_va_parameter_tcma(tcr, mmu_idx)); 10959 } 10960 10961 return rebuild_hflags_common(env, fp_el, mmu_idx, flags); 10962 } 10963 10964 static CPUARMTBFlags rebuild_hflags_internal(CPUARMState *env) 10965 { 10966 int el = arm_current_el(env); 10967 int fp_el = fp_exception_el(env, el); 10968 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); 10969 10970 if (is_a64(env)) { 10971 return rebuild_hflags_a64(env, el, fp_el, mmu_idx); 10972 } else if (arm_feature(env, ARM_FEATURE_M)) { 10973 return rebuild_hflags_m32(env, fp_el, mmu_idx); 10974 } else { 10975 return rebuild_hflags_a32(env, fp_el, mmu_idx); 10976 } 10977 } 10978 10979 void arm_rebuild_hflags(CPUARMState *env) 10980 { 10981 env->hflags = rebuild_hflags_internal(env); 10982 } 10983 10984 /* 10985 * If we have triggered a EL state change we can't rely on the 10986 * translator having passed it to us, we need to recompute. 10987 */ 10988 void HELPER(rebuild_hflags_m32_newel)(CPUARMState *env) 10989 { 10990 int el = arm_current_el(env); 10991 int fp_el = fp_exception_el(env, el); 10992 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); 10993 10994 env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx); 10995 } 10996 10997 void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el) 10998 { 10999 int fp_el = fp_exception_el(env, el); 11000 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); 11001 11002 env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx); 11003 } 11004 11005 /* 11006 * If we have triggered a EL state change we can't rely on the 11007 * translator having passed it to us, we need to recompute. 11008 */ 11009 void HELPER(rebuild_hflags_a32_newel)(CPUARMState *env) 11010 { 11011 int el = arm_current_el(env); 11012 int fp_el = fp_exception_el(env, el); 11013 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); 11014 env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx); 11015 } 11016 11017 void HELPER(rebuild_hflags_a32)(CPUARMState *env, int el) 11018 { 11019 int fp_el = fp_exception_el(env, el); 11020 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); 11021 11022 env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx); 11023 } 11024 11025 void HELPER(rebuild_hflags_a64)(CPUARMState *env, int el) 11026 { 11027 int fp_el = fp_exception_el(env, el); 11028 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); 11029 11030 env->hflags = rebuild_hflags_a64(env, el, fp_el, mmu_idx); 11031 } 11032 11033 static inline void assert_hflags_rebuild_correctly(CPUARMState *env) 11034 { 11035 #ifdef CONFIG_DEBUG_TCG 11036 CPUARMTBFlags c = env->hflags; 11037 CPUARMTBFlags r = rebuild_hflags_internal(env); 11038 11039 if (unlikely(c.flags != r.flags || c.flags2 != r.flags2)) { 11040 fprintf(stderr, "TCG hflags mismatch " 11041 "(current:(0x%08x,0x" TARGET_FMT_lx ")" 11042 " rebuilt:(0x%08x,0x" TARGET_FMT_lx ")\n", 11043 c.flags, c.flags2, r.flags, r.flags2); 11044 abort(); 11045 } 11046 #endif 11047 } 11048 11049 static bool mve_no_pred(CPUARMState *env) 11050 { 11051 /* 11052 * Return true if there is definitely no predication of MVE 11053 * instructions by VPR or LTPSIZE. (Returning false even if there 11054 * isn't any predication is OK; generated code will just be 11055 * a little worse.) 11056 * If the CPU does not implement MVE then this TB flag is always 0. 11057 * 11058 * NOTE: if you change this logic, the "recalculate s->mve_no_pred" 11059 * logic in gen_update_fp_context() needs to be updated to match. 11060 * 11061 * We do not include the effect of the ECI bits here -- they are 11062 * tracked in other TB flags. This simplifies the logic for 11063 * "when did we emit code that changes the MVE_NO_PRED TB flag 11064 * and thus need to end the TB?". 11065 */ 11066 if (cpu_isar_feature(aa32_mve, env_archcpu(env))) { 11067 return false; 11068 } 11069 if (env->v7m.vpr) { 11070 return false; 11071 } 11072 if (env->v7m.ltpsize < 4) { 11073 return false; 11074 } 11075 return true; 11076 } 11077 11078 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 11079 target_ulong *cs_base, uint32_t *pflags) 11080 { 11081 CPUARMTBFlags flags; 11082 11083 assert_hflags_rebuild_correctly(env); 11084 flags = env->hflags; 11085 11086 if (EX_TBFLAG_ANY(flags, AARCH64_STATE)) { 11087 *pc = env->pc; 11088 if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { 11089 DP_TBFLAG_A64(flags, BTYPE, env->btype); 11090 } 11091 } else { 11092 *pc = env->regs[15]; 11093 11094 if (arm_feature(env, ARM_FEATURE_M)) { 11095 if (arm_feature(env, ARM_FEATURE_M_SECURITY) && 11096 FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) 11097 != env->v7m.secure) { 11098 DP_TBFLAG_M32(flags, FPCCR_S_WRONG, 1); 11099 } 11100 11101 if ((env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK) && 11102 (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) || 11103 (env->v7m.secure && 11104 !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)))) { 11105 /* 11106 * ASPEN is set, but FPCA/SFPA indicate that there is no 11107 * active FP context; we must create a new FP context before 11108 * executing any FP insn. 11109 */ 11110 DP_TBFLAG_M32(flags, NEW_FP_CTXT_NEEDED, 1); 11111 } 11112 11113 bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; 11114 if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) { 11115 DP_TBFLAG_M32(flags, LSPACT, 1); 11116 } 11117 11118 if (mve_no_pred(env)) { 11119 DP_TBFLAG_M32(flags, MVE_NO_PRED, 1); 11120 } 11121 } else { 11122 /* 11123 * Note that XSCALE_CPAR shares bits with VECSTRIDE. 11124 * Note that VECLEN+VECSTRIDE are RES0 for M-profile. 11125 */ 11126 if (arm_feature(env, ARM_FEATURE_XSCALE)) { 11127 DP_TBFLAG_A32(flags, XSCALE_CPAR, env->cp15.c15_cpar); 11128 } else { 11129 DP_TBFLAG_A32(flags, VECLEN, env->vfp.vec_len); 11130 DP_TBFLAG_A32(flags, VECSTRIDE, env->vfp.vec_stride); 11131 } 11132 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) { 11133 DP_TBFLAG_A32(flags, VFPEN, 1); 11134 } 11135 } 11136 11137 DP_TBFLAG_AM32(flags, THUMB, env->thumb); 11138 DP_TBFLAG_AM32(flags, CONDEXEC, env->condexec_bits); 11139 } 11140 11141 /* 11142 * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine 11143 * states defined in the ARM ARM for software singlestep: 11144 * SS_ACTIVE PSTATE.SS State 11145 * 0 x Inactive (the TB flag for SS is always 0) 11146 * 1 0 Active-pending 11147 * 1 1 Active-not-pending 11148 * SS_ACTIVE is set in hflags; PSTATE__SS is computed every TB. 11149 */ 11150 if (EX_TBFLAG_ANY(flags, SS_ACTIVE) && (env->pstate & PSTATE_SS)) { 11151 DP_TBFLAG_ANY(flags, PSTATE__SS, 1); 11152 } 11153 11154 *pflags = flags.flags; 11155 *cs_base = flags.flags2; 11156 } 11157 11158 #ifdef TARGET_AARCH64 11159 /* 11160 * The manual says that when SVE is enabled and VQ is widened the 11161 * implementation is allowed to zero the previously inaccessible 11162 * portion of the registers. The corollary to that is that when 11163 * SVE is enabled and VQ is narrowed we are also allowed to zero 11164 * the now inaccessible portion of the registers. 11165 * 11166 * The intent of this is that no predicate bit beyond VQ is ever set. 11167 * Which means that some operations on predicate registers themselves 11168 * may operate on full uint64_t or even unrolled across the maximum 11169 * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally 11170 * may well be cheaper than conditionals to restrict the operation 11171 * to the relevant portion of a uint16_t[16]. 11172 */ 11173 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) 11174 { 11175 int i, j; 11176 uint64_t pmask; 11177 11178 assert(vq >= 1 && vq <= ARM_MAX_VQ); 11179 assert(vq <= env_archcpu(env)->sve_max_vq); 11180 11181 /* Zap the high bits of the zregs. */ 11182 for (i = 0; i < 32; i++) { 11183 memset(&env->vfp.zregs[i].d[2 * vq], 0, 16 * (ARM_MAX_VQ - vq)); 11184 } 11185 11186 /* Zap the high bits of the pregs and ffr. */ 11187 pmask = 0; 11188 if (vq & 3) { 11189 pmask = ~(-1ULL << (16 * (vq & 3))); 11190 } 11191 for (j = vq / 4; j < ARM_MAX_VQ / 4; j++) { 11192 for (i = 0; i < 17; ++i) { 11193 env->vfp.pregs[i].p[j] &= pmask; 11194 } 11195 pmask = 0; 11196 } 11197 } 11198 11199 static uint32_t sve_vqm1_for_el_sm_ena(CPUARMState *env, int el, bool sm) 11200 { 11201 int exc_el; 11202 11203 if (sm) { 11204 exc_el = sme_exception_el(env, el); 11205 } else { 11206 exc_el = sve_exception_el(env, el); 11207 } 11208 if (exc_el) { 11209 return 0; /* disabled */ 11210 } 11211 return sve_vqm1_for_el_sm(env, el, sm); 11212 } 11213 11214 /* 11215 * Notice a change in SVE vector size when changing EL. 11216 */ 11217 void aarch64_sve_change_el(CPUARMState *env, int old_el, 11218 int new_el, bool el0_a64) 11219 { 11220 ARMCPU *cpu = env_archcpu(env); 11221 int old_len, new_len; 11222 bool old_a64, new_a64, sm; 11223 11224 /* Nothing to do if no SVE. */ 11225 if (!cpu_isar_feature(aa64_sve, cpu)) { 11226 return; 11227 } 11228 11229 /* Nothing to do if FP is disabled in either EL. */ 11230 if (fp_exception_el(env, old_el) || fp_exception_el(env, new_el)) { 11231 return; 11232 } 11233 11234 old_a64 = old_el ? arm_el_is_aa64(env, old_el) : el0_a64; 11235 new_a64 = new_el ? arm_el_is_aa64(env, new_el) : el0_a64; 11236 11237 /* 11238 * Both AArch64.TakeException and AArch64.ExceptionReturn 11239 * invoke ResetSVEState when taking an exception from, or 11240 * returning to, AArch32 state when PSTATE.SM is enabled. 11241 */ 11242 sm = FIELD_EX64(env->svcr, SVCR, SM); 11243 if (old_a64 != new_a64 && sm) { 11244 arm_reset_sve_state(env); 11245 return; 11246 } 11247 11248 /* 11249 * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped 11250 * at ELx, or not available because the EL is in AArch32 state, then 11251 * for all purposes other than a direct read, the ZCR_ELx.LEN field 11252 * has an effective value of 0". 11253 * 11254 * Consider EL2 (aa64, vq=4) -> EL0 (aa32) -> EL1 (aa64, vq=0). 11255 * If we ignore aa32 state, we would fail to see the vq4->vq0 transition 11256 * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so that 11257 * we already have the correct register contents when encountering the 11258 * vq0->vq0 transition between EL0->EL1. 11259 */ 11260 old_len = new_len = 0; 11261 if (old_a64) { 11262 old_len = sve_vqm1_for_el_sm_ena(env, old_el, sm); 11263 } 11264 if (new_a64) { 11265 new_len = sve_vqm1_for_el_sm_ena(env, new_el, sm); 11266 } 11267 11268 /* When changing vector length, clear inaccessible state. */ 11269 if (new_len < old_len) { 11270 aarch64_sve_narrow_vq(env, new_len + 1); 11271 } 11272 } 11273 #endif 11274