1 #include "qemu/osdep.h" 2 #include "trace.h" 3 #include "cpu.h" 4 #include "internals.h" 5 #include "exec/gdbstub.h" 6 #include "exec/helper-proto.h" 7 #include "qemu/host-utils.h" 8 #include "sysemu/arch_init.h" 9 #include "sysemu/sysemu.h" 10 #include "qemu/bitops.h" 11 #include "qemu/crc32c.h" 12 #include "exec/exec-all.h" 13 #include "exec/cpu_ldst.h" 14 #include "arm_ldst.h" 15 #include <zlib.h> /* For crc32 */ 16 #include "exec/semihost.h" 17 #include "sysemu/kvm.h" 18 19 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ 20 21 #ifndef CONFIG_USER_ONLY 22 static bool get_phys_addr(CPUARMState *env, target_ulong address, 23 int access_type, ARMMMUIdx mmu_idx, 24 hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, 25 target_ulong *page_size, uint32_t *fsr, 26 ARMMMUFaultInfo *fi); 27 28 static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, 29 int access_type, ARMMMUIdx mmu_idx, 30 hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, 31 target_ulong *page_size_ptr, uint32_t *fsr, 32 ARMMMUFaultInfo *fi); 33 34 /* Definitions for the PMCCNTR and PMCR registers */ 35 #define PMCRD 0x8 36 #define PMCRC 0x4 37 #define PMCRE 0x1 38 #endif 39 40 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) 41 { 42 int nregs; 43 44 /* VFP data registers are always little-endian. */ 45 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; 46 if (reg < nregs) { 47 stfq_le_p(buf, env->vfp.regs[reg]); 48 return 8; 49 } 50 if (arm_feature(env, ARM_FEATURE_NEON)) { 51 /* Aliases for Q regs. */ 52 nregs += 16; 53 if (reg < nregs) { 54 stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]); 55 stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]); 56 return 16; 57 } 58 } 59 switch (reg - nregs) { 60 case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4; 61 case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4; 62 case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4; 63 } 64 return 0; 65 } 66 67 static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) 68 { 69 int nregs; 70 71 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; 72 if (reg < nregs) { 73 env->vfp.regs[reg] = ldfq_le_p(buf); 74 return 8; 75 } 76 if (arm_feature(env, ARM_FEATURE_NEON)) { 77 nregs += 16; 78 if (reg < nregs) { 79 env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf); 80 env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8); 81 return 16; 82 } 83 } 84 switch (reg - nregs) { 85 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4; 86 case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4; 87 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4; 88 } 89 return 0; 90 } 91 92 static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) 93 { 94 switch (reg) { 95 case 0 ... 31: 96 /* 128 bit FP register */ 97 stfq_le_p(buf, env->vfp.regs[reg * 2]); 98 stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]); 99 return 16; 100 case 32: 101 /* FPSR */ 102 stl_p(buf, vfp_get_fpsr(env)); 103 return 4; 104 case 33: 105 /* FPCR */ 106 stl_p(buf, vfp_get_fpcr(env)); 107 return 4; 108 default: 109 return 0; 110 } 111 } 112 113 static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) 114 { 115 switch (reg) { 116 case 0 ... 31: 117 /* 128 bit FP register */ 118 env->vfp.regs[reg * 2] = ldfq_le_p(buf); 119 env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8); 120 return 16; 121 case 32: 122 /* FPSR */ 123 vfp_set_fpsr(env, ldl_p(buf)); 124 return 4; 125 case 33: 126 /* FPCR */ 127 vfp_set_fpcr(env, ldl_p(buf)); 128 return 4; 129 default: 130 return 0; 131 } 132 } 133 134 static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri) 135 { 136 assert(ri->fieldoffset); 137 if (cpreg_field_is_64bit(ri)) { 138 return CPREG_FIELD64(env, ri); 139 } else { 140 return CPREG_FIELD32(env, ri); 141 } 142 } 143 144 static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, 145 uint64_t value) 146 { 147 assert(ri->fieldoffset); 148 if (cpreg_field_is_64bit(ri)) { 149 CPREG_FIELD64(env, ri) = value; 150 } else { 151 CPREG_FIELD32(env, ri) = value; 152 } 153 } 154 155 static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri) 156 { 157 return (char *)env + ri->fieldoffset; 158 } 159 160 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri) 161 { 162 /* Raw read of a coprocessor register (as needed for migration, etc). */ 163 if (ri->type & ARM_CP_CONST) { 164 return ri->resetvalue; 165 } else if (ri->raw_readfn) { 166 return ri->raw_readfn(env, ri); 167 } else if (ri->readfn) { 168 return ri->readfn(env, ri); 169 } else { 170 return raw_read(env, ri); 171 } 172 } 173 174 static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri, 175 uint64_t v) 176 { 177 /* Raw write of a coprocessor register (as needed for migration, etc). 178 * Note that constant registers are treated as write-ignored; the 179 * caller should check for success by whether a readback gives the 180 * value written. 181 */ 182 if (ri->type & ARM_CP_CONST) { 183 return; 184 } else if (ri->raw_writefn) { 185 ri->raw_writefn(env, ri, v); 186 } else if (ri->writefn) { 187 ri->writefn(env, ri, v); 188 } else { 189 raw_write(env, ri, v); 190 } 191 } 192 193 static bool raw_accessors_invalid(const ARMCPRegInfo *ri) 194 { 195 /* Return true if the regdef would cause an assertion if you called 196 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a 197 * program bug for it not to have the NO_RAW flag). 198 * NB that returning false here doesn't necessarily mean that calling 199 * read/write_raw_cp_reg() is safe, because we can't distinguish "has 200 * read/write access functions which are safe for raw use" from "has 201 * read/write access functions which have side effects but has forgotten 202 * to provide raw access functions". 203 * The tests here line up with the conditions in read/write_raw_cp_reg() 204 * and assertions in raw_read()/raw_write(). 205 */ 206 if ((ri->type & ARM_CP_CONST) || 207 ri->fieldoffset || 208 ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) { 209 return false; 210 } 211 return true; 212 } 213 214 bool write_cpustate_to_list(ARMCPU *cpu) 215 { 216 /* Write the coprocessor state from cpu->env to the (index,value) list. */ 217 int i; 218 bool ok = true; 219 220 for (i = 0; i < cpu->cpreg_array_len; i++) { 221 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); 222 const ARMCPRegInfo *ri; 223 224 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); 225 if (!ri) { 226 ok = false; 227 continue; 228 } 229 if (ri->type & ARM_CP_NO_RAW) { 230 continue; 231 } 232 cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri); 233 } 234 return ok; 235 } 236 237 bool write_list_to_cpustate(ARMCPU *cpu) 238 { 239 int i; 240 bool ok = true; 241 242 for (i = 0; i < cpu->cpreg_array_len; i++) { 243 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); 244 uint64_t v = cpu->cpreg_values[i]; 245 const ARMCPRegInfo *ri; 246 247 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); 248 if (!ri) { 249 ok = false; 250 continue; 251 } 252 if (ri->type & ARM_CP_NO_RAW) { 253 continue; 254 } 255 /* Write value and confirm it reads back as written 256 * (to catch read-only registers and partially read-only 257 * registers where the incoming migration value doesn't match) 258 */ 259 write_raw_cp_reg(&cpu->env, ri, v); 260 if (read_raw_cp_reg(&cpu->env, ri) != v) { 261 ok = false; 262 } 263 } 264 return ok; 265 } 266 267 static void add_cpreg_to_list(gpointer key, gpointer opaque) 268 { 269 ARMCPU *cpu = opaque; 270 uint64_t regidx; 271 const ARMCPRegInfo *ri; 272 273 regidx = *(uint32_t *)key; 274 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); 275 276 if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { 277 cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx); 278 /* The value array need not be initialized at this point */ 279 cpu->cpreg_array_len++; 280 } 281 } 282 283 static void count_cpreg(gpointer key, gpointer opaque) 284 { 285 ARMCPU *cpu = opaque; 286 uint64_t regidx; 287 const ARMCPRegInfo *ri; 288 289 regidx = *(uint32_t *)key; 290 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); 291 292 if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { 293 cpu->cpreg_array_len++; 294 } 295 } 296 297 static gint cpreg_key_compare(gconstpointer a, gconstpointer b) 298 { 299 uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a); 300 uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b); 301 302 if (aidx > bidx) { 303 return 1; 304 } 305 if (aidx < bidx) { 306 return -1; 307 } 308 return 0; 309 } 310 311 void init_cpreg_list(ARMCPU *cpu) 312 { 313 /* Initialise the cpreg_tuples[] array based on the cp_regs hash. 314 * Note that we require cpreg_tuples[] to be sorted by key ID. 315 */ 316 GList *keys; 317 int arraylen; 318 319 keys = g_hash_table_get_keys(cpu->cp_regs); 320 keys = g_list_sort(keys, cpreg_key_compare); 321 322 cpu->cpreg_array_len = 0; 323 324 g_list_foreach(keys, count_cpreg, cpu); 325 326 arraylen = cpu->cpreg_array_len; 327 cpu->cpreg_indexes = g_new(uint64_t, arraylen); 328 cpu->cpreg_values = g_new(uint64_t, arraylen); 329 cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen); 330 cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen); 331 cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len; 332 cpu->cpreg_array_len = 0; 333 334 g_list_foreach(keys, add_cpreg_to_list, cpu); 335 336 assert(cpu->cpreg_array_len == arraylen); 337 338 g_list_free(keys); 339 } 340 341 /* 342 * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but 343 * they are accessible when EL3 is using AArch64 regardless of EL3.NS. 344 * 345 * access_el3_aa32ns: Used to check AArch32 register views. 346 * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views. 347 */ 348 static CPAccessResult access_el3_aa32ns(CPUARMState *env, 349 const ARMCPRegInfo *ri, 350 bool isread) 351 { 352 bool secure = arm_is_secure_below_el3(env); 353 354 assert(!arm_el_is_aa64(env, 3)); 355 if (secure) { 356 return CP_ACCESS_TRAP_UNCATEGORIZED; 357 } 358 return CP_ACCESS_OK; 359 } 360 361 static CPAccessResult access_el3_aa32ns_aa64any(CPUARMState *env, 362 const ARMCPRegInfo *ri, 363 bool isread) 364 { 365 if (!arm_el_is_aa64(env, 3)) { 366 return access_el3_aa32ns(env, ri, isread); 367 } 368 return CP_ACCESS_OK; 369 } 370 371 /* Some secure-only AArch32 registers trap to EL3 if used from 372 * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts). 373 * Note that an access from Secure EL1 can only happen if EL3 is AArch64. 374 * We assume that the .access field is set to PL1_RW. 375 */ 376 static CPAccessResult access_trap_aa32s_el1(CPUARMState *env, 377 const ARMCPRegInfo *ri, 378 bool isread) 379 { 380 if (arm_current_el(env) == 3) { 381 return CP_ACCESS_OK; 382 } 383 if (arm_is_secure_below_el3(env)) { 384 return CP_ACCESS_TRAP_EL3; 385 } 386 /* This will be EL1 NS and EL2 NS, which just UNDEF */ 387 return CP_ACCESS_TRAP_UNCATEGORIZED; 388 } 389 390 /* Check for traps to "powerdown debug" registers, which are controlled 391 * by MDCR.TDOSA 392 */ 393 static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *ri, 394 bool isread) 395 { 396 int el = arm_current_el(env); 397 398 if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDOSA) 399 && !arm_is_secure_below_el3(env)) { 400 return CP_ACCESS_TRAP_EL2; 401 } 402 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDOSA)) { 403 return CP_ACCESS_TRAP_EL3; 404 } 405 return CP_ACCESS_OK; 406 } 407 408 /* Check for traps to "debug ROM" registers, which are controlled 409 * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3. 410 */ 411 static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri, 412 bool isread) 413 { 414 int el = arm_current_el(env); 415 416 if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDRA) 417 && !arm_is_secure_below_el3(env)) { 418 return CP_ACCESS_TRAP_EL2; 419 } 420 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { 421 return CP_ACCESS_TRAP_EL3; 422 } 423 return CP_ACCESS_OK; 424 } 425 426 /* Check for traps to general debug registers, which are controlled 427 * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3. 428 */ 429 static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri, 430 bool isread) 431 { 432 int el = arm_current_el(env); 433 434 if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDA) 435 && !arm_is_secure_below_el3(env)) { 436 return CP_ACCESS_TRAP_EL2; 437 } 438 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { 439 return CP_ACCESS_TRAP_EL3; 440 } 441 return CP_ACCESS_OK; 442 } 443 444 /* Check for traps to performance monitor registers, which are controlled 445 * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3. 446 */ 447 static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri, 448 bool isread) 449 { 450 int el = arm_current_el(env); 451 452 if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM) 453 && !arm_is_secure_below_el3(env)) { 454 return CP_ACCESS_TRAP_EL2; 455 } 456 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { 457 return CP_ACCESS_TRAP_EL3; 458 } 459 return CP_ACCESS_OK; 460 } 461 462 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) 463 { 464 ARMCPU *cpu = arm_env_get_cpu(env); 465 466 raw_write(env, ri, value); 467 tlb_flush(CPU(cpu)); /* Flush TLB as domain not tracked in TLB */ 468 } 469 470 static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) 471 { 472 ARMCPU *cpu = arm_env_get_cpu(env); 473 474 if (raw_read(env, ri) != value) { 475 /* Unlike real hardware the qemu TLB uses virtual addresses, 476 * not modified virtual addresses, so this causes a TLB flush. 477 */ 478 tlb_flush(CPU(cpu)); 479 raw_write(env, ri, value); 480 } 481 } 482 483 static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, 484 uint64_t value) 485 { 486 ARMCPU *cpu = arm_env_get_cpu(env); 487 488 if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_PMSA) 489 && !extended_addresses_enabled(env)) { 490 /* For VMSA (when not using the LPAE long descriptor page table 491 * format) this register includes the ASID, so do a TLB flush. 492 * For PMSA it is purely a process ID and no action is needed. 493 */ 494 tlb_flush(CPU(cpu)); 495 } 496 raw_write(env, ri, value); 497 } 498 499 static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri, 500 uint64_t value) 501 { 502 /* Invalidate all (TLBIALL) */ 503 ARMCPU *cpu = arm_env_get_cpu(env); 504 505 tlb_flush(CPU(cpu)); 506 } 507 508 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, 509 uint64_t value) 510 { 511 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ 512 ARMCPU *cpu = arm_env_get_cpu(env); 513 514 tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); 515 } 516 517 static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, 518 uint64_t value) 519 { 520 /* Invalidate by ASID (TLBIASID) */ 521 ARMCPU *cpu = arm_env_get_cpu(env); 522 523 tlb_flush(CPU(cpu)); 524 } 525 526 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, 527 uint64_t value) 528 { 529 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ 530 ARMCPU *cpu = arm_env_get_cpu(env); 531 532 tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); 533 } 534 535 /* IS variants of TLB operations must affect all cores */ 536 static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri, 537 uint64_t value) 538 { 539 CPUState *cs = ENV_GET_CPU(env); 540 541 tlb_flush_all_cpus_synced(cs); 542 } 543 544 static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri, 545 uint64_t value) 546 { 547 CPUState *cs = ENV_GET_CPU(env); 548 549 tlb_flush_all_cpus_synced(cs); 550 } 551 552 static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri, 553 uint64_t value) 554 { 555 CPUState *cs = ENV_GET_CPU(env); 556 557 tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK); 558 } 559 560 static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri, 561 uint64_t value) 562 { 563 CPUState *cs = ENV_GET_CPU(env); 564 565 tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK); 566 } 567 568 static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri, 569 uint64_t value) 570 { 571 CPUState *cs = ENV_GET_CPU(env); 572 573 tlb_flush_by_mmuidx(cs, 574 ARMMMUIdxBit_S12NSE1 | 575 ARMMMUIdxBit_S12NSE0 | 576 ARMMMUIdxBit_S2NS); 577 } 578 579 static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri, 580 uint64_t value) 581 { 582 CPUState *cs = ENV_GET_CPU(env); 583 584 tlb_flush_by_mmuidx_all_cpus_synced(cs, 585 ARMMMUIdxBit_S12NSE1 | 586 ARMMMUIdxBit_S12NSE0 | 587 ARMMMUIdxBit_S2NS); 588 } 589 590 static void tlbiipas2_write(CPUARMState *env, const ARMCPRegInfo *ri, 591 uint64_t value) 592 { 593 /* Invalidate by IPA. This has to invalidate any structures that 594 * contain only stage 2 translation information, but does not need 595 * to apply to structures that contain combined stage 1 and stage 2 596 * translation information. 597 * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero. 598 */ 599 CPUState *cs = ENV_GET_CPU(env); 600 uint64_t pageaddr; 601 602 if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { 603 return; 604 } 605 606 pageaddr = sextract64(value << 12, 0, 40); 607 608 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S2NS); 609 } 610 611 static void tlbiipas2_is_write(CPUARMState *env, const ARMCPRegInfo *ri, 612 uint64_t value) 613 { 614 CPUState *cs = ENV_GET_CPU(env); 615 uint64_t pageaddr; 616 617 if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { 618 return; 619 } 620 621 pageaddr = sextract64(value << 12, 0, 40); 622 623 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, 624 ARMMMUIdxBit_S2NS); 625 } 626 627 static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, 628 uint64_t value) 629 { 630 CPUState *cs = ENV_GET_CPU(env); 631 632 tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2); 633 } 634 635 static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, 636 uint64_t value) 637 { 638 CPUState *cs = ENV_GET_CPU(env); 639 640 tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2); 641 } 642 643 static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, 644 uint64_t value) 645 { 646 CPUState *cs = ENV_GET_CPU(env); 647 uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12); 648 649 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E2); 650 } 651 652 static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, 653 uint64_t value) 654 { 655 CPUState *cs = ENV_GET_CPU(env); 656 uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12); 657 658 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, 659 ARMMMUIdxBit_S1E2); 660 } 661 662 static const ARMCPRegInfo cp_reginfo[] = { 663 /* Define the secure and non-secure FCSE identifier CP registers 664 * separately because there is no secure bank in V8 (no _EL3). This allows 665 * the secure register to be properly reset and migrated. There is also no 666 * v8 EL1 version of the register so the non-secure instance stands alone. 667 */ 668 { .name = "FCSEIDR(NS)", 669 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0, 670 .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS, 671 .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_ns), 672 .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, }, 673 { .name = "FCSEIDR(S)", 674 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0, 675 .access = PL1_RW, .secure = ARM_CP_SECSTATE_S, 676 .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s), 677 .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, }, 678 /* Define the secure and non-secure context identifier CP registers 679 * separately because there is no secure bank in V8 (no _EL3). This allows 680 * the secure register to be properly reset and migrated. In the 681 * non-secure case, the 32-bit register will have reset and migration 682 * disabled during registration as it is handled by the 64-bit instance. 683 */ 684 { .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH, 685 .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, 686 .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS, 687 .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]), 688 .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, 689 { .name = "CONTEXTIDR(S)", .state = ARM_CP_STATE_AA32, 690 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, 691 .access = PL1_RW, .secure = ARM_CP_SECSTATE_S, 692 .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s), 693 .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, 694 REGINFO_SENTINEL 695 }; 696 697 static const ARMCPRegInfo not_v8_cp_reginfo[] = { 698 /* NB: Some of these registers exist in v8 but with more precise 699 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]). 700 */ 701 /* MMU Domain access control / MPU write buffer control */ 702 { .name = "DACR", 703 .cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY, 704 .access = PL1_RW, .resetvalue = 0, 705 .writefn = dacr_write, .raw_writefn = raw_write, 706 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s), 707 offsetoflow32(CPUARMState, cp15.dacr_ns) } }, 708 /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs. 709 * For v6 and v5, these mappings are overly broad. 710 */ 711 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 0, 712 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, 713 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 1, 714 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, 715 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 4, 716 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, 717 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 8, 718 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, 719 /* Cache maintenance ops; some of this space may be overridden later. */ 720 { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, 721 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, 722 .type = ARM_CP_NOP | ARM_CP_OVERRIDE }, 723 REGINFO_SENTINEL 724 }; 725 726 static const ARMCPRegInfo not_v6_cp_reginfo[] = { 727 /* Not all pre-v6 cores implemented this WFI, so this is slightly 728 * over-broad. 729 */ 730 { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2, 731 .access = PL1_W, .type = ARM_CP_WFI }, 732 REGINFO_SENTINEL 733 }; 734 735 static const ARMCPRegInfo not_v7_cp_reginfo[] = { 736 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which 737 * is UNPREDICTABLE; we choose to NOP as most implementations do). 738 */ 739 { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, 740 .access = PL1_W, .type = ARM_CP_WFI }, 741 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice 742 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and 743 * OMAPCP will override this space. 744 */ 745 { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0, 746 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data), 747 .resetvalue = 0 }, 748 { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1, 749 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn), 750 .resetvalue = 0 }, 751 /* v6 doesn't have the cache ID registers but Linux reads them anyway */ 752 { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY, 753 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, 754 .resetvalue = 0 }, 755 /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR; 756 * implementing it as RAZ means the "debug architecture version" bits 757 * will read as a reserved value, which should cause Linux to not try 758 * to use the debug hardware. 759 */ 760 { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, 761 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 762 /* MMU TLB control. Note that the wildcarding means we cover not just 763 * the unified TLB ops but also the dside/iside/inner-shareable variants. 764 */ 765 { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY, 766 .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write, 767 .type = ARM_CP_NO_RAW }, 768 { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY, 769 .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write, 770 .type = ARM_CP_NO_RAW }, 771 { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY, 772 .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write, 773 .type = ARM_CP_NO_RAW }, 774 { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY, 775 .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write, 776 .type = ARM_CP_NO_RAW }, 777 { .name = "PRRR", .cp = 15, .crn = 10, .crm = 2, 778 .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP }, 779 { .name = "NMRR", .cp = 15, .crn = 10, .crm = 2, 780 .opc1 = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_NOP }, 781 REGINFO_SENTINEL 782 }; 783 784 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, 785 uint64_t value) 786 { 787 uint32_t mask = 0; 788 789 /* In ARMv8 most bits of CPACR_EL1 are RES0. */ 790 if (!arm_feature(env, ARM_FEATURE_V8)) { 791 /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI. 792 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP. 793 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell. 794 */ 795 if (arm_feature(env, ARM_FEATURE_VFP)) { 796 /* VFP coprocessor: cp10 & cp11 [23:20] */ 797 mask |= (1 << 31) | (1 << 30) | (0xf << 20); 798 799 if (!arm_feature(env, ARM_FEATURE_NEON)) { 800 /* ASEDIS [31] bit is RAO/WI */ 801 value |= (1 << 31); 802 } 803 804 /* VFPv3 and upwards with NEON implement 32 double precision 805 * registers (D0-D31). 806 */ 807 if (!arm_feature(env, ARM_FEATURE_NEON) || 808 !arm_feature(env, ARM_FEATURE_VFP3)) { 809 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */ 810 value |= (1 << 30); 811 } 812 } 813 value &= mask; 814 } 815 env->cp15.cpacr_el1 = value; 816 } 817 818 static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri, 819 bool isread) 820 { 821 if (arm_feature(env, ARM_FEATURE_V8)) { 822 /* Check if CPACR accesses are to be trapped to EL2 */ 823 if (arm_current_el(env) == 1 && 824 (env->cp15.cptr_el[2] & CPTR_TCPAC) && !arm_is_secure(env)) { 825 return CP_ACCESS_TRAP_EL2; 826 /* Check if CPACR accesses are to be trapped to EL3 */ 827 } else if (arm_current_el(env) < 3 && 828 (env->cp15.cptr_el[3] & CPTR_TCPAC)) { 829 return CP_ACCESS_TRAP_EL3; 830 } 831 } 832 833 return CP_ACCESS_OK; 834 } 835 836 static CPAccessResult cptr_access(CPUARMState *env, const ARMCPRegInfo *ri, 837 bool isread) 838 { 839 /* Check if CPTR accesses are set to trap to EL3 */ 840 if (arm_current_el(env) == 2 && (env->cp15.cptr_el[3] & CPTR_TCPAC)) { 841 return CP_ACCESS_TRAP_EL3; 842 } 843 844 return CP_ACCESS_OK; 845 } 846 847 static const ARMCPRegInfo v6_cp_reginfo[] = { 848 /* prefetch by MVA in v6, NOP in v7 */ 849 { .name = "MVA_prefetch", 850 .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1, 851 .access = PL1_W, .type = ARM_CP_NOP }, 852 /* We need to break the TB after ISB to execute self-modifying code 853 * correctly and also to take any pending interrupts immediately. 854 * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag. 855 */ 856 { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4, 857 .access = PL0_W, .type = ARM_CP_NO_RAW, .writefn = arm_cp_write_ignore }, 858 { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4, 859 .access = PL0_W, .type = ARM_CP_NOP }, 860 { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5, 861 .access = PL0_W, .type = ARM_CP_NOP }, 862 { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2, 863 .access = PL1_RW, 864 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s), 865 offsetof(CPUARMState, cp15.ifar_ns) }, 866 .resetvalue = 0, }, 867 /* Watchpoint Fault Address Register : should actually only be present 868 * for 1136, 1176, 11MPCore. 869 */ 870 { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, 871 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, }, 872 { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, 873 .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access, 874 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1), 875 .resetvalue = 0, .writefn = cpacr_write }, 876 REGINFO_SENTINEL 877 }; 878 879 static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri, 880 bool isread) 881 { 882 /* Performance monitor registers user accessibility is controlled 883 * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable 884 * trapping to EL2 or EL3 for other accesses. 885 */ 886 int el = arm_current_el(env); 887 888 if (el == 0 && !(env->cp15.c9_pmuserenr & 1)) { 889 return CP_ACCESS_TRAP; 890 } 891 if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM) 892 && !arm_is_secure_below_el3(env)) { 893 return CP_ACCESS_TRAP_EL2; 894 } 895 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { 896 return CP_ACCESS_TRAP_EL3; 897 } 898 899 return CP_ACCESS_OK; 900 } 901 902 static CPAccessResult pmreg_access_xevcntr(CPUARMState *env, 903 const ARMCPRegInfo *ri, 904 bool isread) 905 { 906 /* ER: event counter read trap control */ 907 if (arm_feature(env, ARM_FEATURE_V8) 908 && arm_current_el(env) == 0 909 && (env->cp15.c9_pmuserenr & (1 << 3)) != 0 910 && isread) { 911 return CP_ACCESS_OK; 912 } 913 914 return pmreg_access(env, ri, isread); 915 } 916 917 static CPAccessResult pmreg_access_swinc(CPUARMState *env, 918 const ARMCPRegInfo *ri, 919 bool isread) 920 { 921 /* SW: software increment write trap control */ 922 if (arm_feature(env, ARM_FEATURE_V8) 923 && arm_current_el(env) == 0 924 && (env->cp15.c9_pmuserenr & (1 << 1)) != 0 925 && !isread) { 926 return CP_ACCESS_OK; 927 } 928 929 return pmreg_access(env, ri, isread); 930 } 931 932 #ifndef CONFIG_USER_ONLY 933 934 static CPAccessResult pmreg_access_selr(CPUARMState *env, 935 const ARMCPRegInfo *ri, 936 bool isread) 937 { 938 /* ER: event counter read trap control */ 939 if (arm_feature(env, ARM_FEATURE_V8) 940 && arm_current_el(env) == 0 941 && (env->cp15.c9_pmuserenr & (1 << 3)) != 0) { 942 return CP_ACCESS_OK; 943 } 944 945 return pmreg_access(env, ri, isread); 946 } 947 948 static CPAccessResult pmreg_access_ccntr(CPUARMState *env, 949 const ARMCPRegInfo *ri, 950 bool isread) 951 { 952 /* CR: cycle counter read trap control */ 953 if (arm_feature(env, ARM_FEATURE_V8) 954 && arm_current_el(env) == 0 955 && (env->cp15.c9_pmuserenr & (1 << 2)) != 0 956 && isread) { 957 return CP_ACCESS_OK; 958 } 959 960 return pmreg_access(env, ri, isread); 961 } 962 963 static inline bool arm_ccnt_enabled(CPUARMState *env) 964 { 965 /* This does not support checking PMCCFILTR_EL0 register */ 966 967 if (!(env->cp15.c9_pmcr & PMCRE)) { 968 return false; 969 } 970 971 return true; 972 } 973 974 void pmccntr_sync(CPUARMState *env) 975 { 976 uint64_t temp_ticks; 977 978 temp_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 979 ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); 980 981 if (env->cp15.c9_pmcr & PMCRD) { 982 /* Increment once every 64 processor clock cycles */ 983 temp_ticks /= 64; 984 } 985 986 if (arm_ccnt_enabled(env)) { 987 env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt; 988 } 989 } 990 991 static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, 992 uint64_t value) 993 { 994 pmccntr_sync(env); 995 996 if (value & PMCRC) { 997 /* The counter has been reset */ 998 env->cp15.c15_ccnt = 0; 999 } 1000 1001 /* only the DP, X, D and E bits are writable */ 1002 env->cp15.c9_pmcr &= ~0x39; 1003 env->cp15.c9_pmcr |= (value & 0x39); 1004 1005 pmccntr_sync(env); 1006 } 1007 1008 static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) 1009 { 1010 uint64_t total_ticks; 1011 1012 if (!arm_ccnt_enabled(env)) { 1013 /* Counter is disabled, do not change value */ 1014 return env->cp15.c15_ccnt; 1015 } 1016 1017 total_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 1018 ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); 1019 1020 if (env->cp15.c9_pmcr & PMCRD) { 1021 /* Increment once every 64 processor clock cycles */ 1022 total_ticks /= 64; 1023 } 1024 return total_ticks - env->cp15.c15_ccnt; 1025 } 1026 1027 static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1028 uint64_t value) 1029 { 1030 /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and 1031 * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the 1032 * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are 1033 * accessed. 1034 */ 1035 env->cp15.c9_pmselr = value & 0x1f; 1036 } 1037 1038 static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1039 uint64_t value) 1040 { 1041 uint64_t total_ticks; 1042 1043 if (!arm_ccnt_enabled(env)) { 1044 /* Counter is disabled, set the absolute value */ 1045 env->cp15.c15_ccnt = value; 1046 return; 1047 } 1048 1049 total_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 1050 ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); 1051 1052 if (env->cp15.c9_pmcr & PMCRD) { 1053 /* Increment once every 64 processor clock cycles */ 1054 total_ticks /= 64; 1055 } 1056 env->cp15.c15_ccnt = total_ticks - value; 1057 } 1058 1059 static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri, 1060 uint64_t value) 1061 { 1062 uint64_t cur_val = pmccntr_read(env, NULL); 1063 1064 pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value)); 1065 } 1066 1067 #else /* CONFIG_USER_ONLY */ 1068 1069 void pmccntr_sync(CPUARMState *env) 1070 { 1071 } 1072 1073 #endif 1074 1075 static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1076 uint64_t value) 1077 { 1078 pmccntr_sync(env); 1079 env->cp15.pmccfiltr_el0 = value & 0x7E000000; 1080 pmccntr_sync(env); 1081 } 1082 1083 static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, 1084 uint64_t value) 1085 { 1086 value &= (1 << 31); 1087 env->cp15.c9_pmcnten |= value; 1088 } 1089 1090 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1091 uint64_t value) 1092 { 1093 value &= (1 << 31); 1094 env->cp15.c9_pmcnten &= ~value; 1095 } 1096 1097 static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1098 uint64_t value) 1099 { 1100 env->cp15.c9_pmovsr &= ~value; 1101 } 1102 1103 static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, 1104 uint64_t value) 1105 { 1106 /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when 1107 * PMSELR value is equal to or greater than the number of implemented 1108 * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI. 1109 */ 1110 if (env->cp15.c9_pmselr == 0x1f) { 1111 pmccfiltr_write(env, ri, value); 1112 } 1113 } 1114 1115 static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri) 1116 { 1117 /* We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER 1118 * are CONSTRAINED UNPREDICTABLE. See comments in pmxevtyper_write(). 1119 */ 1120 if (env->cp15.c9_pmselr == 0x1f) { 1121 return env->cp15.pmccfiltr_el0; 1122 } else { 1123 return 0; 1124 } 1125 } 1126 1127 static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1128 uint64_t value) 1129 { 1130 if (arm_feature(env, ARM_FEATURE_V8)) { 1131 env->cp15.c9_pmuserenr = value & 0xf; 1132 } else { 1133 env->cp15.c9_pmuserenr = value & 1; 1134 } 1135 } 1136 1137 static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri, 1138 uint64_t value) 1139 { 1140 /* We have no event counters so only the C bit can be changed */ 1141 value &= (1 << 31); 1142 env->cp15.c9_pminten |= value; 1143 } 1144 1145 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1146 uint64_t value) 1147 { 1148 value &= (1 << 31); 1149 env->cp15.c9_pminten &= ~value; 1150 } 1151 1152 static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, 1153 uint64_t value) 1154 { 1155 /* Note that even though the AArch64 view of this register has bits 1156 * [10:0] all RES0 we can only mask the bottom 5, to comply with the 1157 * architectural requirements for bits which are RES0 only in some 1158 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7 1159 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.) 1160 */ 1161 raw_write(env, ri, value & ~0x1FULL); 1162 } 1163 1164 static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) 1165 { 1166 /* We only mask off bits that are RES0 both for AArch64 and AArch32. 1167 * For bits that vary between AArch32/64, code needs to check the 1168 * current execution mode before directly using the feature bit. 1169 */ 1170 uint32_t valid_mask = SCR_AARCH64_MASK | SCR_AARCH32_MASK; 1171 1172 if (!arm_feature(env, ARM_FEATURE_EL2)) { 1173 valid_mask &= ~SCR_HCE; 1174 1175 /* On ARMv7, SMD (or SCD as it is called in v7) is only 1176 * supported if EL2 exists. The bit is UNK/SBZP when 1177 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero 1178 * when EL2 is unavailable. 1179 * On ARMv8, this bit is always available. 1180 */ 1181 if (arm_feature(env, ARM_FEATURE_V7) && 1182 !arm_feature(env, ARM_FEATURE_V8)) { 1183 valid_mask &= ~SCR_SMD; 1184 } 1185 } 1186 1187 /* Clear all-context RES0 bits. */ 1188 value &= valid_mask; 1189 raw_write(env, ri, value); 1190 } 1191 1192 static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) 1193 { 1194 ARMCPU *cpu = arm_env_get_cpu(env); 1195 1196 /* Acquire the CSSELR index from the bank corresponding to the CCSIDR 1197 * bank 1198 */ 1199 uint32_t index = A32_BANKED_REG_GET(env, csselr, 1200 ri->secure & ARM_CP_SECSTATE_S); 1201 1202 return cpu->ccsidr[index]; 1203 } 1204 1205 static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1206 uint64_t value) 1207 { 1208 raw_write(env, ri, value & 0xf); 1209 } 1210 1211 static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) 1212 { 1213 CPUState *cs = ENV_GET_CPU(env); 1214 uint64_t ret = 0; 1215 1216 if (cs->interrupt_request & CPU_INTERRUPT_HARD) { 1217 ret |= CPSR_I; 1218 } 1219 if (cs->interrupt_request & CPU_INTERRUPT_FIQ) { 1220 ret |= CPSR_F; 1221 } 1222 /* External aborts are not possible in QEMU so A bit is always clear */ 1223 return ret; 1224 } 1225 1226 static const ARMCPRegInfo v7_cp_reginfo[] = { 1227 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */ 1228 { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, 1229 .access = PL1_W, .type = ARM_CP_NOP }, 1230 /* Performance monitors are implementation defined in v7, 1231 * but with an ARM recommended set of registers, which we 1232 * follow (although we don't actually implement any counters) 1233 * 1234 * Performance registers fall into three categories: 1235 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR) 1236 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR) 1237 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others) 1238 * For the cases controlled by PMUSERENR we must set .access to PL0_RW 1239 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn. 1240 */ 1241 { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1, 1242 .access = PL0_RW, .type = ARM_CP_ALIAS, 1243 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten), 1244 .writefn = pmcntenset_write, 1245 .accessfn = pmreg_access, 1246 .raw_writefn = raw_write }, 1247 { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64, 1248 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1, 1249 .access = PL0_RW, .accessfn = pmreg_access, 1250 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0, 1251 .writefn = pmcntenset_write, .raw_writefn = raw_write }, 1252 { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2, 1253 .access = PL0_RW, 1254 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten), 1255 .accessfn = pmreg_access, 1256 .writefn = pmcntenclr_write, 1257 .type = ARM_CP_ALIAS }, 1258 { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64, 1259 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2, 1260 .access = PL0_RW, .accessfn = pmreg_access, 1261 .type = ARM_CP_ALIAS, 1262 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), 1263 .writefn = pmcntenclr_write }, 1264 { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3, 1265 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), 1266 .accessfn = pmreg_access, 1267 .writefn = pmovsr_write, 1268 .raw_writefn = raw_write }, 1269 { .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64, 1270 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 3, 1271 .access = PL0_RW, .accessfn = pmreg_access, 1272 .type = ARM_CP_ALIAS, 1273 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), 1274 .writefn = pmovsr_write, 1275 .raw_writefn = raw_write }, 1276 /* Unimplemented so WI. */ 1277 { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4, 1278 .access = PL0_W, .accessfn = pmreg_access_swinc, .type = ARM_CP_NOP }, 1279 #ifndef CONFIG_USER_ONLY 1280 { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5, 1281 .access = PL0_RW, .type = ARM_CP_ALIAS, 1282 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr), 1283 .accessfn = pmreg_access_selr, .writefn = pmselr_write, 1284 .raw_writefn = raw_write}, 1285 { .name = "PMSELR_EL0", .state = ARM_CP_STATE_AA64, 1286 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 5, 1287 .access = PL0_RW, .accessfn = pmreg_access_selr, 1288 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmselr), 1289 .writefn = pmselr_write, .raw_writefn = raw_write, }, 1290 { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0, 1291 .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO, 1292 .readfn = pmccntr_read, .writefn = pmccntr_write32, 1293 .accessfn = pmreg_access_ccntr }, 1294 { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64, 1295 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0, 1296 .access = PL0_RW, .accessfn = pmreg_access_ccntr, 1297 .type = ARM_CP_IO, 1298 .readfn = pmccntr_read, .writefn = pmccntr_write, }, 1299 #endif 1300 { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64, 1301 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7, 1302 .writefn = pmccfiltr_write, 1303 .access = PL0_RW, .accessfn = pmreg_access, 1304 .type = ARM_CP_IO, 1305 .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0), 1306 .resetvalue = 0, }, 1307 { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1, 1308 .access = PL0_RW, .type = ARM_CP_NO_RAW, .accessfn = pmreg_access, 1309 .writefn = pmxevtyper_write, .readfn = pmxevtyper_read }, 1310 { .name = "PMXEVTYPER_EL0", .state = ARM_CP_STATE_AA64, 1311 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 1, 1312 .access = PL0_RW, .type = ARM_CP_NO_RAW, .accessfn = pmreg_access, 1313 .writefn = pmxevtyper_write, .readfn = pmxevtyper_read }, 1314 /* Unimplemented, RAZ/WI. */ 1315 { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2, 1316 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0, 1317 .accessfn = pmreg_access_xevcntr }, 1318 { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0, 1319 .access = PL0_R | PL1_RW, .accessfn = access_tpm, 1320 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr), 1321 .resetvalue = 0, 1322 .writefn = pmuserenr_write, .raw_writefn = raw_write }, 1323 { .name = "PMUSERENR_EL0", .state = ARM_CP_STATE_AA64, 1324 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 0, 1325 .access = PL0_R | PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS, 1326 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr), 1327 .resetvalue = 0, 1328 .writefn = pmuserenr_write, .raw_writefn = raw_write }, 1329 { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1, 1330 .access = PL1_RW, .accessfn = access_tpm, 1331 .type = ARM_CP_ALIAS, 1332 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pminten), 1333 .resetvalue = 0, 1334 .writefn = pmintenset_write, .raw_writefn = raw_write }, 1335 { .name = "PMINTENSET_EL1", .state = ARM_CP_STATE_AA64, 1336 .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 1, 1337 .access = PL1_RW, .accessfn = access_tpm, 1338 .type = ARM_CP_IO, 1339 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), 1340 .writefn = pmintenset_write, .raw_writefn = raw_write, 1341 .resetvalue = 0x0 }, 1342 { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2, 1343 .access = PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS, 1344 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), 1345 .writefn = pmintenclr_write, }, 1346 { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64, 1347 .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2, 1348 .access = PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS, 1349 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), 1350 .writefn = pmintenclr_write }, 1351 { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, 1352 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, 1353 .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_RAW }, 1354 { .name = "CSSELR", .state = ARM_CP_STATE_BOTH, 1355 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0, 1356 .access = PL1_RW, .writefn = csselr_write, .resetvalue = 0, 1357 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s), 1358 offsetof(CPUARMState, cp15.csselr_ns) } }, 1359 /* Auxiliary ID register: this actually has an IMPDEF value but for now 1360 * just RAZ for all cores: 1361 */ 1362 { .name = "AIDR", .state = ARM_CP_STATE_BOTH, 1363 .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7, 1364 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 1365 /* Auxiliary fault status registers: these also are IMPDEF, and we 1366 * choose to RAZ/WI for all cores. 1367 */ 1368 { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH, 1369 .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0, 1370 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1371 { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH, 1372 .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1, 1373 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1374 /* MAIR can just read-as-written because we don't implement caches 1375 * and so don't need to care about memory attributes. 1376 */ 1377 { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64, 1378 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, 1379 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]), 1380 .resetvalue = 0 }, 1381 { .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64, 1382 .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0, 1383 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]), 1384 .resetvalue = 0 }, 1385 /* For non-long-descriptor page tables these are PRRR and NMRR; 1386 * regardless they still act as reads-as-written for QEMU. 1387 */ 1388 /* MAIR0/1 are defined separately from their 64-bit counterpart which 1389 * allows them to assign the correct fieldoffset based on the endianness 1390 * handled in the field definitions. 1391 */ 1392 { .name = "MAIR0", .state = ARM_CP_STATE_AA32, 1393 .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW, 1394 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair0_s), 1395 offsetof(CPUARMState, cp15.mair0_ns) }, 1396 .resetfn = arm_cp_reset_ignore }, 1397 { .name = "MAIR1", .state = ARM_CP_STATE_AA32, 1398 .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW, 1399 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair1_s), 1400 offsetof(CPUARMState, cp15.mair1_ns) }, 1401 .resetfn = arm_cp_reset_ignore }, 1402 { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH, 1403 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0, 1404 .type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read }, 1405 /* 32 bit ITLB invalidates */ 1406 { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0, 1407 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write }, 1408 { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1, 1409 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, 1410 { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2, 1411 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write }, 1412 /* 32 bit DTLB invalidates */ 1413 { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0, 1414 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write }, 1415 { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1, 1416 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, 1417 { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2, 1418 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write }, 1419 /* 32 bit TLB invalidates */ 1420 { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, 1421 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write }, 1422 { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, 1423 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, 1424 { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, 1425 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write }, 1426 { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, 1427 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write }, 1428 REGINFO_SENTINEL 1429 }; 1430 1431 static const ARMCPRegInfo v7mp_cp_reginfo[] = { 1432 /* 32 bit TLB invalidates, Inner Shareable */ 1433 { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, 1434 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_is_write }, 1435 { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, 1436 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write }, 1437 { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, 1438 .type = ARM_CP_NO_RAW, .access = PL1_W, 1439 .writefn = tlbiasid_is_write }, 1440 { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, 1441 .type = ARM_CP_NO_RAW, .access = PL1_W, 1442 .writefn = tlbimvaa_is_write }, 1443 REGINFO_SENTINEL 1444 }; 1445 1446 static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1447 uint64_t value) 1448 { 1449 value &= 1; 1450 env->teecr = value; 1451 } 1452 1453 static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri, 1454 bool isread) 1455 { 1456 if (arm_current_el(env) == 0 && (env->teecr & 1)) { 1457 return CP_ACCESS_TRAP; 1458 } 1459 return CP_ACCESS_OK; 1460 } 1461 1462 static const ARMCPRegInfo t2ee_cp_reginfo[] = { 1463 { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0, 1464 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr), 1465 .resetvalue = 0, 1466 .writefn = teecr_write }, 1467 { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0, 1468 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr), 1469 .accessfn = teehbr_access, .resetvalue = 0 }, 1470 REGINFO_SENTINEL 1471 }; 1472 1473 static const ARMCPRegInfo v6k_cp_reginfo[] = { 1474 { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64, 1475 .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0, 1476 .access = PL0_RW, 1477 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 }, 1478 { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2, 1479 .access = PL0_RW, 1480 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s), 1481 offsetoflow32(CPUARMState, cp15.tpidrurw_ns) }, 1482 .resetfn = arm_cp_reset_ignore }, 1483 { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64, 1484 .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0, 1485 .access = PL0_R|PL1_W, 1486 .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]), 1487 .resetvalue = 0}, 1488 { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3, 1489 .access = PL0_R|PL1_W, 1490 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s), 1491 offsetoflow32(CPUARMState, cp15.tpidruro_ns) }, 1492 .resetfn = arm_cp_reset_ignore }, 1493 { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64, 1494 .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0, 1495 .access = PL1_RW, 1496 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 }, 1497 { .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4, 1498 .access = PL1_RW, 1499 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s), 1500 offsetoflow32(CPUARMState, cp15.tpidrprw_ns) }, 1501 .resetvalue = 0 }, 1502 REGINFO_SENTINEL 1503 }; 1504 1505 #ifndef CONFIG_USER_ONLY 1506 1507 static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri, 1508 bool isread) 1509 { 1510 /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero. 1511 * Writable only at the highest implemented exception level. 1512 */ 1513 int el = arm_current_el(env); 1514 1515 switch (el) { 1516 case 0: 1517 if (!extract32(env->cp15.c14_cntkctl, 0, 2)) { 1518 return CP_ACCESS_TRAP; 1519 } 1520 break; 1521 case 1: 1522 if (!isread && ri->state == ARM_CP_STATE_AA32 && 1523 arm_is_secure_below_el3(env)) { 1524 /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */ 1525 return CP_ACCESS_TRAP_UNCATEGORIZED; 1526 } 1527 break; 1528 case 2: 1529 case 3: 1530 break; 1531 } 1532 1533 if (!isread && el < arm_highest_el(env)) { 1534 return CP_ACCESS_TRAP_UNCATEGORIZED; 1535 } 1536 1537 return CP_ACCESS_OK; 1538 } 1539 1540 static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx, 1541 bool isread) 1542 { 1543 unsigned int cur_el = arm_current_el(env); 1544 bool secure = arm_is_secure(env); 1545 1546 /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */ 1547 if (cur_el == 0 && 1548 !extract32(env->cp15.c14_cntkctl, timeridx, 1)) { 1549 return CP_ACCESS_TRAP; 1550 } 1551 1552 if (arm_feature(env, ARM_FEATURE_EL2) && 1553 timeridx == GTIMER_PHYS && !secure && cur_el < 2 && 1554 !extract32(env->cp15.cnthctl_el2, 0, 1)) { 1555 return CP_ACCESS_TRAP_EL2; 1556 } 1557 return CP_ACCESS_OK; 1558 } 1559 1560 static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx, 1561 bool isread) 1562 { 1563 unsigned int cur_el = arm_current_el(env); 1564 bool secure = arm_is_secure(env); 1565 1566 /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if 1567 * EL0[PV]TEN is zero. 1568 */ 1569 if (cur_el == 0 && 1570 !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) { 1571 return CP_ACCESS_TRAP; 1572 } 1573 1574 if (arm_feature(env, ARM_FEATURE_EL2) && 1575 timeridx == GTIMER_PHYS && !secure && cur_el < 2 && 1576 !extract32(env->cp15.cnthctl_el2, 1, 1)) { 1577 return CP_ACCESS_TRAP_EL2; 1578 } 1579 return CP_ACCESS_OK; 1580 } 1581 1582 static CPAccessResult gt_pct_access(CPUARMState *env, 1583 const ARMCPRegInfo *ri, 1584 bool isread) 1585 { 1586 return gt_counter_access(env, GTIMER_PHYS, isread); 1587 } 1588 1589 static CPAccessResult gt_vct_access(CPUARMState *env, 1590 const ARMCPRegInfo *ri, 1591 bool isread) 1592 { 1593 return gt_counter_access(env, GTIMER_VIRT, isread); 1594 } 1595 1596 static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri, 1597 bool isread) 1598 { 1599 return gt_timer_access(env, GTIMER_PHYS, isread); 1600 } 1601 1602 static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri, 1603 bool isread) 1604 { 1605 return gt_timer_access(env, GTIMER_VIRT, isread); 1606 } 1607 1608 static CPAccessResult gt_stimer_access(CPUARMState *env, 1609 const ARMCPRegInfo *ri, 1610 bool isread) 1611 { 1612 /* The AArch64 register view of the secure physical timer is 1613 * always accessible from EL3, and configurably accessible from 1614 * Secure EL1. 1615 */ 1616 switch (arm_current_el(env)) { 1617 case 1: 1618 if (!arm_is_secure(env)) { 1619 return CP_ACCESS_TRAP; 1620 } 1621 if (!(env->cp15.scr_el3 & SCR_ST)) { 1622 return CP_ACCESS_TRAP_EL3; 1623 } 1624 return CP_ACCESS_OK; 1625 case 0: 1626 case 2: 1627 return CP_ACCESS_TRAP; 1628 case 3: 1629 return CP_ACCESS_OK; 1630 default: 1631 g_assert_not_reached(); 1632 } 1633 } 1634 1635 static uint64_t gt_get_countervalue(CPUARMState *env) 1636 { 1637 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE; 1638 } 1639 1640 static void gt_recalc_timer(ARMCPU *cpu, int timeridx) 1641 { 1642 ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx]; 1643 1644 if (gt->ctl & 1) { 1645 /* Timer enabled: calculate and set current ISTATUS, irq, and 1646 * reset timer to when ISTATUS next has to change 1647 */ 1648 uint64_t offset = timeridx == GTIMER_VIRT ? 1649 cpu->env.cp15.cntvoff_el2 : 0; 1650 uint64_t count = gt_get_countervalue(&cpu->env); 1651 /* Note that this must be unsigned 64 bit arithmetic: */ 1652 int istatus = count - offset >= gt->cval; 1653 uint64_t nexttick; 1654 int irqstate; 1655 1656 gt->ctl = deposit32(gt->ctl, 2, 1, istatus); 1657 1658 irqstate = (istatus && !(gt->ctl & 2)); 1659 qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate); 1660 1661 if (istatus) { 1662 /* Next transition is when count rolls back over to zero */ 1663 nexttick = UINT64_MAX; 1664 } else { 1665 /* Next transition is when we hit cval */ 1666 nexttick = gt->cval + offset; 1667 } 1668 /* Note that the desired next expiry time might be beyond the 1669 * signed-64-bit range of a QEMUTimer -- in this case we just 1670 * set the timer for as far in the future as possible. When the 1671 * timer expires we will reset the timer for any remaining period. 1672 */ 1673 if (nexttick > INT64_MAX / GTIMER_SCALE) { 1674 nexttick = INT64_MAX / GTIMER_SCALE; 1675 } 1676 timer_mod(cpu->gt_timer[timeridx], nexttick); 1677 trace_arm_gt_recalc(timeridx, irqstate, nexttick); 1678 } else { 1679 /* Timer disabled: ISTATUS and timer output always clear */ 1680 gt->ctl &= ~4; 1681 qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0); 1682 timer_del(cpu->gt_timer[timeridx]); 1683 trace_arm_gt_recalc_disabled(timeridx); 1684 } 1685 } 1686 1687 static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri, 1688 int timeridx) 1689 { 1690 ARMCPU *cpu = arm_env_get_cpu(env); 1691 1692 timer_del(cpu->gt_timer[timeridx]); 1693 } 1694 1695 static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) 1696 { 1697 return gt_get_countervalue(env); 1698 } 1699 1700 static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) 1701 { 1702 return gt_get_countervalue(env) - env->cp15.cntvoff_el2; 1703 } 1704 1705 static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1706 int timeridx, 1707 uint64_t value) 1708 { 1709 trace_arm_gt_cval_write(timeridx, value); 1710 env->cp15.c14_timer[timeridx].cval = value; 1711 gt_recalc_timer(arm_env_get_cpu(env), timeridx); 1712 } 1713 1714 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri, 1715 int timeridx) 1716 { 1717 uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0; 1718 1719 return (uint32_t)(env->cp15.c14_timer[timeridx].cval - 1720 (gt_get_countervalue(env) - offset)); 1721 } 1722 1723 static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1724 int timeridx, 1725 uint64_t value) 1726 { 1727 uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0; 1728 1729 trace_arm_gt_tval_write(timeridx, value); 1730 env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset + 1731 sextract64(value, 0, 32); 1732 gt_recalc_timer(arm_env_get_cpu(env), timeridx); 1733 } 1734 1735 static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, 1736 int timeridx, 1737 uint64_t value) 1738 { 1739 ARMCPU *cpu = arm_env_get_cpu(env); 1740 uint32_t oldval = env->cp15.c14_timer[timeridx].ctl; 1741 1742 trace_arm_gt_ctl_write(timeridx, value); 1743 env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value); 1744 if ((oldval ^ value) & 1) { 1745 /* Enable toggled */ 1746 gt_recalc_timer(cpu, timeridx); 1747 } else if ((oldval ^ value) & 2) { 1748 /* IMASK toggled: don't need to recalculate, 1749 * just set the interrupt line based on ISTATUS 1750 */ 1751 int irqstate = (oldval & 4) && !(value & 2); 1752 1753 trace_arm_gt_imask_toggle(timeridx, irqstate); 1754 qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate); 1755 } 1756 } 1757 1758 static void gt_phys_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) 1759 { 1760 gt_timer_reset(env, ri, GTIMER_PHYS); 1761 } 1762 1763 static void gt_phys_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1764 uint64_t value) 1765 { 1766 gt_cval_write(env, ri, GTIMER_PHYS, value); 1767 } 1768 1769 static uint64_t gt_phys_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) 1770 { 1771 return gt_tval_read(env, ri, GTIMER_PHYS); 1772 } 1773 1774 static void gt_phys_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1775 uint64_t value) 1776 { 1777 gt_tval_write(env, ri, GTIMER_PHYS, value); 1778 } 1779 1780 static void gt_phys_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, 1781 uint64_t value) 1782 { 1783 gt_ctl_write(env, ri, GTIMER_PHYS, value); 1784 } 1785 1786 static void gt_virt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) 1787 { 1788 gt_timer_reset(env, ri, GTIMER_VIRT); 1789 } 1790 1791 static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1792 uint64_t value) 1793 { 1794 gt_cval_write(env, ri, GTIMER_VIRT, value); 1795 } 1796 1797 static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) 1798 { 1799 return gt_tval_read(env, ri, GTIMER_VIRT); 1800 } 1801 1802 static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1803 uint64_t value) 1804 { 1805 gt_tval_write(env, ri, GTIMER_VIRT, value); 1806 } 1807 1808 static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, 1809 uint64_t value) 1810 { 1811 gt_ctl_write(env, ri, GTIMER_VIRT, value); 1812 } 1813 1814 static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri, 1815 uint64_t value) 1816 { 1817 ARMCPU *cpu = arm_env_get_cpu(env); 1818 1819 trace_arm_gt_cntvoff_write(value); 1820 raw_write(env, ri, value); 1821 gt_recalc_timer(cpu, GTIMER_VIRT); 1822 } 1823 1824 static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) 1825 { 1826 gt_timer_reset(env, ri, GTIMER_HYP); 1827 } 1828 1829 static void gt_hyp_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1830 uint64_t value) 1831 { 1832 gt_cval_write(env, ri, GTIMER_HYP, value); 1833 } 1834 1835 static uint64_t gt_hyp_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) 1836 { 1837 return gt_tval_read(env, ri, GTIMER_HYP); 1838 } 1839 1840 static void gt_hyp_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1841 uint64_t value) 1842 { 1843 gt_tval_write(env, ri, GTIMER_HYP, value); 1844 } 1845 1846 static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, 1847 uint64_t value) 1848 { 1849 gt_ctl_write(env, ri, GTIMER_HYP, value); 1850 } 1851 1852 static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) 1853 { 1854 gt_timer_reset(env, ri, GTIMER_SEC); 1855 } 1856 1857 static void gt_sec_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1858 uint64_t value) 1859 { 1860 gt_cval_write(env, ri, GTIMER_SEC, value); 1861 } 1862 1863 static uint64_t gt_sec_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) 1864 { 1865 return gt_tval_read(env, ri, GTIMER_SEC); 1866 } 1867 1868 static void gt_sec_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1869 uint64_t value) 1870 { 1871 gt_tval_write(env, ri, GTIMER_SEC, value); 1872 } 1873 1874 static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, 1875 uint64_t value) 1876 { 1877 gt_ctl_write(env, ri, GTIMER_SEC, value); 1878 } 1879 1880 void arm_gt_ptimer_cb(void *opaque) 1881 { 1882 ARMCPU *cpu = opaque; 1883 1884 gt_recalc_timer(cpu, GTIMER_PHYS); 1885 } 1886 1887 void arm_gt_vtimer_cb(void *opaque) 1888 { 1889 ARMCPU *cpu = opaque; 1890 1891 gt_recalc_timer(cpu, GTIMER_VIRT); 1892 } 1893 1894 void arm_gt_htimer_cb(void *opaque) 1895 { 1896 ARMCPU *cpu = opaque; 1897 1898 gt_recalc_timer(cpu, GTIMER_HYP); 1899 } 1900 1901 void arm_gt_stimer_cb(void *opaque) 1902 { 1903 ARMCPU *cpu = opaque; 1904 1905 gt_recalc_timer(cpu, GTIMER_SEC); 1906 } 1907 1908 static const ARMCPRegInfo generic_timer_cp_reginfo[] = { 1909 /* Note that CNTFRQ is purely reads-as-written for the benefit 1910 * of software; writing it doesn't actually change the timer frequency. 1911 * Our reset value matches the fixed frequency we implement the timer at. 1912 */ 1913 { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0, 1914 .type = ARM_CP_ALIAS, 1915 .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, 1916 .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq), 1917 }, 1918 { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64, 1919 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0, 1920 .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, 1921 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq), 1922 .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE, 1923 }, 1924 /* overall control: mostly access permissions */ 1925 { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH, 1926 .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0, 1927 .access = PL1_RW, 1928 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl), 1929 .resetvalue = 0, 1930 }, 1931 /* per-timer control */ 1932 { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1, 1933 .secure = ARM_CP_SECSTATE_NS, 1934 .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R, 1935 .accessfn = gt_ptimer_access, 1936 .fieldoffset = offsetoflow32(CPUARMState, 1937 cp15.c14_timer[GTIMER_PHYS].ctl), 1938 .writefn = gt_phys_ctl_write, .raw_writefn = raw_write, 1939 }, 1940 { .name = "CNTP_CTL(S)", 1941 .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1, 1942 .secure = ARM_CP_SECSTATE_S, 1943 .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R, 1944 .accessfn = gt_ptimer_access, 1945 .fieldoffset = offsetoflow32(CPUARMState, 1946 cp15.c14_timer[GTIMER_SEC].ctl), 1947 .writefn = gt_sec_ctl_write, .raw_writefn = raw_write, 1948 }, 1949 { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64, 1950 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1, 1951 .type = ARM_CP_IO, .access = PL1_RW | PL0_R, 1952 .accessfn = gt_ptimer_access, 1953 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl), 1954 .resetvalue = 0, 1955 .writefn = gt_phys_ctl_write, .raw_writefn = raw_write, 1956 }, 1957 { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1, 1958 .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R, 1959 .accessfn = gt_vtimer_access, 1960 .fieldoffset = offsetoflow32(CPUARMState, 1961 cp15.c14_timer[GTIMER_VIRT].ctl), 1962 .writefn = gt_virt_ctl_write, .raw_writefn = raw_write, 1963 }, 1964 { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64, 1965 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1, 1966 .type = ARM_CP_IO, .access = PL1_RW | PL0_R, 1967 .accessfn = gt_vtimer_access, 1968 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl), 1969 .resetvalue = 0, 1970 .writefn = gt_virt_ctl_write, .raw_writefn = raw_write, 1971 }, 1972 /* TimerValue views: a 32 bit downcounting view of the underlying state */ 1973 { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0, 1974 .secure = ARM_CP_SECSTATE_NS, 1975 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R, 1976 .accessfn = gt_ptimer_access, 1977 .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write, 1978 }, 1979 { .name = "CNTP_TVAL(S)", 1980 .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0, 1981 .secure = ARM_CP_SECSTATE_S, 1982 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R, 1983 .accessfn = gt_ptimer_access, 1984 .readfn = gt_sec_tval_read, .writefn = gt_sec_tval_write, 1985 }, 1986 { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64, 1987 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0, 1988 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R, 1989 .accessfn = gt_ptimer_access, .resetfn = gt_phys_timer_reset, 1990 .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write, 1991 }, 1992 { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0, 1993 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R, 1994 .accessfn = gt_vtimer_access, 1995 .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write, 1996 }, 1997 { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64, 1998 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0, 1999 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R, 2000 .accessfn = gt_vtimer_access, .resetfn = gt_virt_timer_reset, 2001 .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write, 2002 }, 2003 /* The counter itself */ 2004 { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0, 2005 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, 2006 .accessfn = gt_pct_access, 2007 .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore, 2008 }, 2009 { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64, 2010 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1, 2011 .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, 2012 .accessfn = gt_pct_access, .readfn = gt_cnt_read, 2013 }, 2014 { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1, 2015 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, 2016 .accessfn = gt_vct_access, 2017 .readfn = gt_virt_cnt_read, .resetfn = arm_cp_reset_ignore, 2018 }, 2019 { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64, 2020 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2, 2021 .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, 2022 .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read, 2023 }, 2024 /* Comparison value, indicating when the timer goes off */ 2025 { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2, 2026 .secure = ARM_CP_SECSTATE_NS, 2027 .access = PL1_RW | PL0_R, 2028 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, 2029 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), 2030 .accessfn = gt_ptimer_access, 2031 .writefn = gt_phys_cval_write, .raw_writefn = raw_write, 2032 }, 2033 { .name = "CNTP_CVAL(S)", .cp = 15, .crm = 14, .opc1 = 2, 2034 .secure = ARM_CP_SECSTATE_S, 2035 .access = PL1_RW | PL0_R, 2036 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, 2037 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval), 2038 .accessfn = gt_ptimer_access, 2039 .writefn = gt_sec_cval_write, .raw_writefn = raw_write, 2040 }, 2041 { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64, 2042 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2, 2043 .access = PL1_RW | PL0_R, 2044 .type = ARM_CP_IO, 2045 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), 2046 .resetvalue = 0, .accessfn = gt_ptimer_access, 2047 .writefn = gt_phys_cval_write, .raw_writefn = raw_write, 2048 }, 2049 { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3, 2050 .access = PL1_RW | PL0_R, 2051 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, 2052 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), 2053 .accessfn = gt_vtimer_access, 2054 .writefn = gt_virt_cval_write, .raw_writefn = raw_write, 2055 }, 2056 { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64, 2057 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2, 2058 .access = PL1_RW | PL0_R, 2059 .type = ARM_CP_IO, 2060 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), 2061 .resetvalue = 0, .accessfn = gt_vtimer_access, 2062 .writefn = gt_virt_cval_write, .raw_writefn = raw_write, 2063 }, 2064 /* Secure timer -- this is actually restricted to only EL3 2065 * and configurably Secure-EL1 via the accessfn. 2066 */ 2067 { .name = "CNTPS_TVAL_EL1", .state = ARM_CP_STATE_AA64, 2068 .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 0, 2069 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW, 2070 .accessfn = gt_stimer_access, 2071 .readfn = gt_sec_tval_read, 2072 .writefn = gt_sec_tval_write, 2073 .resetfn = gt_sec_timer_reset, 2074 }, 2075 { .name = "CNTPS_CTL_EL1", .state = ARM_CP_STATE_AA64, 2076 .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 1, 2077 .type = ARM_CP_IO, .access = PL1_RW, 2078 .accessfn = gt_stimer_access, 2079 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].ctl), 2080 .resetvalue = 0, 2081 .writefn = gt_sec_ctl_write, .raw_writefn = raw_write, 2082 }, 2083 { .name = "CNTPS_CVAL_EL1", .state = ARM_CP_STATE_AA64, 2084 .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 2, 2085 .type = ARM_CP_IO, .access = PL1_RW, 2086 .accessfn = gt_stimer_access, 2087 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval), 2088 .writefn = gt_sec_cval_write, .raw_writefn = raw_write, 2089 }, 2090 REGINFO_SENTINEL 2091 }; 2092 2093 #else 2094 /* In user-mode none of the generic timer registers are accessible, 2095 * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs, 2096 * so instead just don't register any of them. 2097 */ 2098 static const ARMCPRegInfo generic_timer_cp_reginfo[] = { 2099 REGINFO_SENTINEL 2100 }; 2101 2102 #endif 2103 2104 static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) 2105 { 2106 if (arm_feature(env, ARM_FEATURE_LPAE)) { 2107 raw_write(env, ri, value); 2108 } else if (arm_feature(env, ARM_FEATURE_V7)) { 2109 raw_write(env, ri, value & 0xfffff6ff); 2110 } else { 2111 raw_write(env, ri, value & 0xfffff1ff); 2112 } 2113 } 2114 2115 #ifndef CONFIG_USER_ONLY 2116 /* get_phys_addr() isn't present for user-mode-only targets */ 2117 2118 static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri, 2119 bool isread) 2120 { 2121 if (ri->opc2 & 4) { 2122 /* The ATS12NSO* operations must trap to EL3 if executed in 2123 * Secure EL1 (which can only happen if EL3 is AArch64). 2124 * They are simply UNDEF if executed from NS EL1. 2125 * They function normally from EL2 or EL3. 2126 */ 2127 if (arm_current_el(env) == 1) { 2128 if (arm_is_secure_below_el3(env)) { 2129 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3; 2130 } 2131 return CP_ACCESS_TRAP_UNCATEGORIZED; 2132 } 2133 } 2134 return CP_ACCESS_OK; 2135 } 2136 2137 static uint64_t do_ats_write(CPUARMState *env, uint64_t value, 2138 int access_type, ARMMMUIdx mmu_idx) 2139 { 2140 hwaddr phys_addr; 2141 target_ulong page_size; 2142 int prot; 2143 uint32_t fsr; 2144 bool ret; 2145 uint64_t par64; 2146 MemTxAttrs attrs = {}; 2147 ARMMMUFaultInfo fi = {}; 2148 2149 ret = get_phys_addr(env, value, access_type, mmu_idx, 2150 &phys_addr, &attrs, &prot, &page_size, &fsr, &fi); 2151 if (extended_addresses_enabled(env)) { 2152 /* fsr is a DFSR/IFSR value for the long descriptor 2153 * translation table format, but with WnR always clear. 2154 * Convert it to a 64-bit PAR. 2155 */ 2156 par64 = (1 << 11); /* LPAE bit always set */ 2157 if (!ret) { 2158 par64 |= phys_addr & ~0xfffULL; 2159 if (!attrs.secure) { 2160 par64 |= (1 << 9); /* NS */ 2161 } 2162 /* We don't set the ATTR or SH fields in the PAR. */ 2163 } else { 2164 par64 |= 1; /* F */ 2165 par64 |= (fsr & 0x3f) << 1; /* FS */ 2166 /* Note that S2WLK and FSTAGE are always zero, because we don't 2167 * implement virtualization and therefore there can't be a stage 2 2168 * fault. 2169 */ 2170 } 2171 } else { 2172 /* fsr is a DFSR/IFSR value for the short descriptor 2173 * translation table format (with WnR always clear). 2174 * Convert it to a 32-bit PAR. 2175 */ 2176 if (!ret) { 2177 /* We do not set any attribute bits in the PAR */ 2178 if (page_size == (1 << 24) 2179 && arm_feature(env, ARM_FEATURE_V7)) { 2180 par64 = (phys_addr & 0xff000000) | (1 << 1); 2181 } else { 2182 par64 = phys_addr & 0xfffff000; 2183 } 2184 if (!attrs.secure) { 2185 par64 |= (1 << 9); /* NS */ 2186 } 2187 } else { 2188 par64 = ((fsr & (1 << 10)) >> 5) | ((fsr & (1 << 12)) >> 6) | 2189 ((fsr & 0xf) << 1) | 1; 2190 } 2191 } 2192 return par64; 2193 } 2194 2195 static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) 2196 { 2197 int access_type = ri->opc2 & 1; 2198 uint64_t par64; 2199 ARMMMUIdx mmu_idx; 2200 int el = arm_current_el(env); 2201 bool secure = arm_is_secure_below_el3(env); 2202 2203 switch (ri->opc2 & 6) { 2204 case 0: 2205 /* stage 1 current state PL1: ATS1CPR, ATS1CPW */ 2206 switch (el) { 2207 case 3: 2208 mmu_idx = ARMMMUIdx_S1E3; 2209 break; 2210 case 2: 2211 mmu_idx = ARMMMUIdx_S1NSE1; 2212 break; 2213 case 1: 2214 mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1; 2215 break; 2216 default: 2217 g_assert_not_reached(); 2218 } 2219 break; 2220 case 2: 2221 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */ 2222 switch (el) { 2223 case 3: 2224 mmu_idx = ARMMMUIdx_S1SE0; 2225 break; 2226 case 2: 2227 mmu_idx = ARMMMUIdx_S1NSE0; 2228 break; 2229 case 1: 2230 mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0; 2231 break; 2232 default: 2233 g_assert_not_reached(); 2234 } 2235 break; 2236 case 4: 2237 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */ 2238 mmu_idx = ARMMMUIdx_S12NSE1; 2239 break; 2240 case 6: 2241 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */ 2242 mmu_idx = ARMMMUIdx_S12NSE0; 2243 break; 2244 default: 2245 g_assert_not_reached(); 2246 } 2247 2248 par64 = do_ats_write(env, value, access_type, mmu_idx); 2249 2250 A32_BANKED_CURRENT_REG_SET(env, par, par64); 2251 } 2252 2253 static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri, 2254 uint64_t value) 2255 { 2256 int access_type = ri->opc2 & 1; 2257 uint64_t par64; 2258 2259 par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S2NS); 2260 2261 A32_BANKED_CURRENT_REG_SET(env, par, par64); 2262 } 2263 2264 static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri, 2265 bool isread) 2266 { 2267 if (arm_current_el(env) == 3 && !(env->cp15.scr_el3 & SCR_NS)) { 2268 return CP_ACCESS_TRAP; 2269 } 2270 return CP_ACCESS_OK; 2271 } 2272 2273 static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, 2274 uint64_t value) 2275 { 2276 int access_type = ri->opc2 & 1; 2277 ARMMMUIdx mmu_idx; 2278 int secure = arm_is_secure_below_el3(env); 2279 2280 switch (ri->opc2 & 6) { 2281 case 0: 2282 switch (ri->opc1) { 2283 case 0: /* AT S1E1R, AT S1E1W */ 2284 mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1; 2285 break; 2286 case 4: /* AT S1E2R, AT S1E2W */ 2287 mmu_idx = ARMMMUIdx_S1E2; 2288 break; 2289 case 6: /* AT S1E3R, AT S1E3W */ 2290 mmu_idx = ARMMMUIdx_S1E3; 2291 break; 2292 default: 2293 g_assert_not_reached(); 2294 } 2295 break; 2296 case 2: /* AT S1E0R, AT S1E0W */ 2297 mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0; 2298 break; 2299 case 4: /* AT S12E1R, AT S12E1W */ 2300 mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S12NSE1; 2301 break; 2302 case 6: /* AT S12E0R, AT S12E0W */ 2303 mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S12NSE0; 2304 break; 2305 default: 2306 g_assert_not_reached(); 2307 } 2308 2309 env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx); 2310 } 2311 #endif 2312 2313 static const ARMCPRegInfo vapa_cp_reginfo[] = { 2314 { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0, 2315 .access = PL1_RW, .resetvalue = 0, 2316 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s), 2317 offsetoflow32(CPUARMState, cp15.par_ns) }, 2318 .writefn = par_write }, 2319 #ifndef CONFIG_USER_ONLY 2320 /* This underdecoding is safe because the reginfo is NO_RAW. */ 2321 { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY, 2322 .access = PL1_W, .accessfn = ats_access, 2323 .writefn = ats_write, .type = ARM_CP_NO_RAW }, 2324 #endif 2325 REGINFO_SENTINEL 2326 }; 2327 2328 /* Return basic MPU access permission bits. */ 2329 static uint32_t simple_mpu_ap_bits(uint32_t val) 2330 { 2331 uint32_t ret; 2332 uint32_t mask; 2333 int i; 2334 ret = 0; 2335 mask = 3; 2336 for (i = 0; i < 16; i += 2) { 2337 ret |= (val >> i) & mask; 2338 mask <<= 2; 2339 } 2340 return ret; 2341 } 2342 2343 /* Pad basic MPU access permission bits to extended format. */ 2344 static uint32_t extended_mpu_ap_bits(uint32_t val) 2345 { 2346 uint32_t ret; 2347 uint32_t mask; 2348 int i; 2349 ret = 0; 2350 mask = 3; 2351 for (i = 0; i < 16; i += 2) { 2352 ret |= (val & mask) << i; 2353 mask <<= 2; 2354 } 2355 return ret; 2356 } 2357 2358 static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, 2359 uint64_t value) 2360 { 2361 env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value); 2362 } 2363 2364 static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) 2365 { 2366 return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap); 2367 } 2368 2369 static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, 2370 uint64_t value) 2371 { 2372 env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value); 2373 } 2374 2375 static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) 2376 { 2377 return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap); 2378 } 2379 2380 static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri) 2381 { 2382 uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri); 2383 2384 if (!u32p) { 2385 return 0; 2386 } 2387 2388 u32p += env->cp15.c6_rgnr; 2389 return *u32p; 2390 } 2391 2392 static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri, 2393 uint64_t value) 2394 { 2395 ARMCPU *cpu = arm_env_get_cpu(env); 2396 uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri); 2397 2398 if (!u32p) { 2399 return; 2400 } 2401 2402 u32p += env->cp15.c6_rgnr; 2403 tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ 2404 *u32p = value; 2405 } 2406 2407 static void pmsav7_reset(CPUARMState *env, const ARMCPRegInfo *ri) 2408 { 2409 ARMCPU *cpu = arm_env_get_cpu(env); 2410 uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri); 2411 2412 if (!u32p) { 2413 return; 2414 } 2415 2416 memset(u32p, 0, sizeof(*u32p) * cpu->pmsav7_dregion); 2417 } 2418 2419 static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri, 2420 uint64_t value) 2421 { 2422 ARMCPU *cpu = arm_env_get_cpu(env); 2423 uint32_t nrgs = cpu->pmsav7_dregion; 2424 2425 if (value >= nrgs) { 2426 qemu_log_mask(LOG_GUEST_ERROR, 2427 "PMSAv7 RGNR write >= # supported regions, %" PRIu32 2428 " > %" PRIu32 "\n", (uint32_t)value, nrgs); 2429 return; 2430 } 2431 2432 raw_write(env, ri, value); 2433 } 2434 2435 static const ARMCPRegInfo pmsav7_cp_reginfo[] = { 2436 { .name = "DRBAR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 0, 2437 .access = PL1_RW, .type = ARM_CP_NO_RAW, 2438 .fieldoffset = offsetof(CPUARMState, pmsav7.drbar), 2439 .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset }, 2440 { .name = "DRSR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 2, 2441 .access = PL1_RW, .type = ARM_CP_NO_RAW, 2442 .fieldoffset = offsetof(CPUARMState, pmsav7.drsr), 2443 .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset }, 2444 { .name = "DRACR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 4, 2445 .access = PL1_RW, .type = ARM_CP_NO_RAW, 2446 .fieldoffset = offsetof(CPUARMState, pmsav7.dracr), 2447 .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset }, 2448 { .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0, 2449 .access = PL1_RW, 2450 .fieldoffset = offsetof(CPUARMState, cp15.c6_rgnr), 2451 .writefn = pmsav7_rgnr_write }, 2452 REGINFO_SENTINEL 2453 }; 2454 2455 static const ARMCPRegInfo pmsav5_cp_reginfo[] = { 2456 { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, 2457 .access = PL1_RW, .type = ARM_CP_ALIAS, 2458 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap), 2459 .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, }, 2460 { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, 2461 .access = PL1_RW, .type = ARM_CP_ALIAS, 2462 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap), 2463 .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, }, 2464 { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2, 2465 .access = PL1_RW, 2466 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap), 2467 .resetvalue = 0, }, 2468 { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3, 2469 .access = PL1_RW, 2470 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap), 2471 .resetvalue = 0, }, 2472 { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, 2473 .access = PL1_RW, 2474 .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, }, 2475 { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1, 2476 .access = PL1_RW, 2477 .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, }, 2478 /* Protection region base and size registers */ 2479 { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, 2480 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, 2481 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) }, 2482 { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0, 2483 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, 2484 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) }, 2485 { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0, 2486 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, 2487 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) }, 2488 { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0, 2489 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, 2490 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) }, 2491 { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0, 2492 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, 2493 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) }, 2494 { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0, 2495 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, 2496 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) }, 2497 { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0, 2498 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, 2499 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) }, 2500 { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0, 2501 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, 2502 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) }, 2503 REGINFO_SENTINEL 2504 }; 2505 2506 static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, 2507 uint64_t value) 2508 { 2509 TCR *tcr = raw_ptr(env, ri); 2510 int maskshift = extract32(value, 0, 3); 2511 2512 if (!arm_feature(env, ARM_FEATURE_V8)) { 2513 if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) { 2514 /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when 2515 * using Long-desciptor translation table format */ 2516 value &= ~((7 << 19) | (3 << 14) | (0xf << 3)); 2517 } else if (arm_feature(env, ARM_FEATURE_EL3)) { 2518 /* In an implementation that includes the Security Extensions 2519 * TTBCR has additional fields PD0 [4] and PD1 [5] for 2520 * Short-descriptor translation table format. 2521 */ 2522 value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N; 2523 } else { 2524 value &= TTBCR_N; 2525 } 2526 } 2527 2528 /* Update the masks corresponding to the TCR bank being written 2529 * Note that we always calculate mask and base_mask, but 2530 * they are only used for short-descriptor tables (ie if EAE is 0); 2531 * for long-descriptor tables the TCR fields are used differently 2532 * and the mask and base_mask values are meaningless. 2533 */ 2534 tcr->raw_tcr = value; 2535 tcr->mask = ~(((uint32_t)0xffffffffu) >> maskshift); 2536 tcr->base_mask = ~((uint32_t)0x3fffu >> maskshift); 2537 } 2538 2539 static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, 2540 uint64_t value) 2541 { 2542 ARMCPU *cpu = arm_env_get_cpu(env); 2543 2544 if (arm_feature(env, ARM_FEATURE_LPAE)) { 2545 /* With LPAE the TTBCR could result in a change of ASID 2546 * via the TTBCR.A1 bit, so do a TLB flush. 2547 */ 2548 tlb_flush(CPU(cpu)); 2549 } 2550 vmsa_ttbcr_raw_write(env, ri, value); 2551 } 2552 2553 static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri) 2554 { 2555 TCR *tcr = raw_ptr(env, ri); 2556 2557 /* Reset both the TCR as well as the masks corresponding to the bank of 2558 * the TCR being reset. 2559 */ 2560 tcr->raw_tcr = 0; 2561 tcr->mask = 0; 2562 tcr->base_mask = 0xffffc000u; 2563 } 2564 2565 static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, 2566 uint64_t value) 2567 { 2568 ARMCPU *cpu = arm_env_get_cpu(env); 2569 TCR *tcr = raw_ptr(env, ri); 2570 2571 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */ 2572 tlb_flush(CPU(cpu)); 2573 tcr->raw_tcr = value; 2574 } 2575 2576 static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, 2577 uint64_t value) 2578 { 2579 /* 64 bit accesses to the TTBRs can change the ASID and so we 2580 * must flush the TLB. 2581 */ 2582 if (cpreg_field_is_64bit(ri)) { 2583 ARMCPU *cpu = arm_env_get_cpu(env); 2584 2585 tlb_flush(CPU(cpu)); 2586 } 2587 raw_write(env, ri, value); 2588 } 2589 2590 static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, 2591 uint64_t value) 2592 { 2593 ARMCPU *cpu = arm_env_get_cpu(env); 2594 CPUState *cs = CPU(cpu); 2595 2596 /* Accesses to VTTBR may change the VMID so we must flush the TLB. */ 2597 if (raw_read(env, ri) != value) { 2598 tlb_flush_by_mmuidx(cs, 2599 ARMMMUIdxBit_S12NSE1 | 2600 ARMMMUIdxBit_S12NSE0 | 2601 ARMMMUIdxBit_S2NS); 2602 raw_write(env, ri, value); 2603 } 2604 } 2605 2606 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = { 2607 { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, 2608 .access = PL1_RW, .type = ARM_CP_ALIAS, 2609 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s), 2610 offsetoflow32(CPUARMState, cp15.dfsr_ns) }, }, 2611 { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, 2612 .access = PL1_RW, .resetvalue = 0, 2613 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s), 2614 offsetoflow32(CPUARMState, cp15.ifsr_ns) } }, 2615 { .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0, 2616 .access = PL1_RW, .resetvalue = 0, 2617 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s), 2618 offsetof(CPUARMState, cp15.dfar_ns) } }, 2619 { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64, 2620 .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, 2621 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]), 2622 .resetvalue = 0, }, 2623 REGINFO_SENTINEL 2624 }; 2625 2626 static const ARMCPRegInfo vmsa_cp_reginfo[] = { 2627 { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64, 2628 .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0, 2629 .access = PL1_RW, 2630 .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, }, 2631 { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH, 2632 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0, 2633 .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0, 2634 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), 2635 offsetof(CPUARMState, cp15.ttbr0_ns) } }, 2636 { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH, 2637 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1, 2638 .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0, 2639 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), 2640 offsetof(CPUARMState, cp15.ttbr1_ns) } }, 2641 { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64, 2642 .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, 2643 .access = PL1_RW, .writefn = vmsa_tcr_el1_write, 2644 .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write, 2645 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) }, 2646 { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, 2647 .access = PL1_RW, .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write, 2648 .raw_writefn = vmsa_ttbcr_raw_write, 2649 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]), 2650 offsetoflow32(CPUARMState, cp15.tcr_el[1])} }, 2651 REGINFO_SENTINEL 2652 }; 2653 2654 static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri, 2655 uint64_t value) 2656 { 2657 env->cp15.c15_ticonfig = value & 0xe7; 2658 /* The OS_TYPE bit in this register changes the reported CPUID! */ 2659 env->cp15.c0_cpuid = (value & (1 << 5)) ? 2660 ARM_CPUID_TI915T : ARM_CPUID_TI925T; 2661 } 2662 2663 static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri, 2664 uint64_t value) 2665 { 2666 env->cp15.c15_threadid = value & 0xffff; 2667 } 2668 2669 static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri, 2670 uint64_t value) 2671 { 2672 /* Wait-for-interrupt (deprecated) */ 2673 cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT); 2674 } 2675 2676 static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri, 2677 uint64_t value) 2678 { 2679 /* On OMAP there are registers indicating the max/min index of dcache lines 2680 * containing a dirty line; cache flush operations have to reset these. 2681 */ 2682 env->cp15.c15_i_max = 0x000; 2683 env->cp15.c15_i_min = 0xff0; 2684 } 2685 2686 static const ARMCPRegInfo omap_cp_reginfo[] = { 2687 { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY, 2688 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE, 2689 .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]), 2690 .resetvalue = 0, }, 2691 { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, 2692 .access = PL1_RW, .type = ARM_CP_NOP }, 2693 { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, 2694 .access = PL1_RW, 2695 .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0, 2696 .writefn = omap_ticonfig_write }, 2697 { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0, 2698 .access = PL1_RW, 2699 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, }, 2700 { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0, 2701 .access = PL1_RW, .resetvalue = 0xff0, 2702 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) }, 2703 { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0, 2704 .access = PL1_RW, 2705 .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0, 2706 .writefn = omap_threadid_write }, 2707 { .name = "TI925T_STATUS", .cp = 15, .crn = 15, 2708 .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW, 2709 .type = ARM_CP_NO_RAW, 2710 .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, }, 2711 /* TODO: Peripheral port remap register: 2712 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller 2713 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff), 2714 * when MMU is off. 2715 */ 2716 { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, 2717 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, 2718 .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW, 2719 .writefn = omap_cachemaint_write }, 2720 { .name = "C9", .cp = 15, .crn = 9, 2721 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, 2722 .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 }, 2723 REGINFO_SENTINEL 2724 }; 2725 2726 static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri, 2727 uint64_t value) 2728 { 2729 env->cp15.c15_cpar = value & 0x3fff; 2730 } 2731 2732 static const ARMCPRegInfo xscale_cp_reginfo[] = { 2733 { .name = "XSCALE_CPAR", 2734 .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW, 2735 .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0, 2736 .writefn = xscale_cpar_write, }, 2737 { .name = "XSCALE_AUXCR", 2738 .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW, 2739 .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr), 2740 .resetvalue = 0, }, 2741 /* XScale specific cache-lockdown: since we have no cache we NOP these 2742 * and hope the guest does not really rely on cache behaviour. 2743 */ 2744 { .name = "XSCALE_LOCK_ICACHE_LINE", 2745 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, 2746 .access = PL1_W, .type = ARM_CP_NOP }, 2747 { .name = "XSCALE_UNLOCK_ICACHE", 2748 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, 2749 .access = PL1_W, .type = ARM_CP_NOP }, 2750 { .name = "XSCALE_DCACHE_LOCK", 2751 .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0, 2752 .access = PL1_RW, .type = ARM_CP_NOP }, 2753 { .name = "XSCALE_UNLOCK_DCACHE", 2754 .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1, 2755 .access = PL1_W, .type = ARM_CP_NOP }, 2756 REGINFO_SENTINEL 2757 }; 2758 2759 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = { 2760 /* RAZ/WI the whole crn=15 space, when we don't have a more specific 2761 * implementation of this implementation-defined space. 2762 * Ideally this should eventually disappear in favour of actually 2763 * implementing the correct behaviour for all cores. 2764 */ 2765 { .name = "C15_IMPDEF", .cp = 15, .crn = 15, 2766 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, 2767 .access = PL1_RW, 2768 .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE, 2769 .resetvalue = 0 }, 2770 REGINFO_SENTINEL 2771 }; 2772 2773 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = { 2774 /* Cache status: RAZ because we have no cache so it's always clean */ 2775 { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6, 2776 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, 2777 .resetvalue = 0 }, 2778 REGINFO_SENTINEL 2779 }; 2780 2781 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = { 2782 /* We never have a a block transfer operation in progress */ 2783 { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4, 2784 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, 2785 .resetvalue = 0 }, 2786 /* The cache ops themselves: these all NOP for QEMU */ 2787 { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0, 2788 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, 2789 { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0, 2790 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, 2791 { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0, 2792 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, 2793 { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1, 2794 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, 2795 { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2, 2796 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, 2797 { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0, 2798 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, 2799 REGINFO_SENTINEL 2800 }; 2801 2802 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = { 2803 /* The cache test-and-clean instructions always return (1 << 30) 2804 * to indicate that there are no dirty cache lines. 2805 */ 2806 { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3, 2807 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, 2808 .resetvalue = (1 << 30) }, 2809 { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3, 2810 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, 2811 .resetvalue = (1 << 30) }, 2812 REGINFO_SENTINEL 2813 }; 2814 2815 static const ARMCPRegInfo strongarm_cp_reginfo[] = { 2816 /* Ignore ReadBuffer accesses */ 2817 { .name = "C9_READBUFFER", .cp = 15, .crn = 9, 2818 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, 2819 .access = PL1_RW, .resetvalue = 0, 2820 .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW }, 2821 REGINFO_SENTINEL 2822 }; 2823 2824 static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri) 2825 { 2826 ARMCPU *cpu = arm_env_get_cpu(env); 2827 unsigned int cur_el = arm_current_el(env); 2828 bool secure = arm_is_secure(env); 2829 2830 if (arm_feature(&cpu->env, ARM_FEATURE_EL2) && !secure && cur_el == 1) { 2831 return env->cp15.vpidr_el2; 2832 } 2833 return raw_read(env, ri); 2834 } 2835 2836 static uint64_t mpidr_read_val(CPUARMState *env) 2837 { 2838 ARMCPU *cpu = ARM_CPU(arm_env_get_cpu(env)); 2839 uint64_t mpidr = cpu->mp_affinity; 2840 2841 if (arm_feature(env, ARM_FEATURE_V7MP)) { 2842 mpidr |= (1U << 31); 2843 /* Cores which are uniprocessor (non-coherent) 2844 * but still implement the MP extensions set 2845 * bit 30. (For instance, Cortex-R5). 2846 */ 2847 if (cpu->mp_is_up) { 2848 mpidr |= (1u << 30); 2849 } 2850 } 2851 return mpidr; 2852 } 2853 2854 static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri) 2855 { 2856 unsigned int cur_el = arm_current_el(env); 2857 bool secure = arm_is_secure(env); 2858 2859 if (arm_feature(env, ARM_FEATURE_EL2) && !secure && cur_el == 1) { 2860 return env->cp15.vmpidr_el2; 2861 } 2862 return mpidr_read_val(env); 2863 } 2864 2865 static const ARMCPRegInfo mpidr_cp_reginfo[] = { 2866 { .name = "MPIDR", .state = ARM_CP_STATE_BOTH, 2867 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5, 2868 .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW }, 2869 REGINFO_SENTINEL 2870 }; 2871 2872 static const ARMCPRegInfo lpae_cp_reginfo[] = { 2873 /* NOP AMAIR0/1 */ 2874 { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH, 2875 .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0, 2876 .access = PL1_RW, .type = ARM_CP_CONST, 2877 .resetvalue = 0 }, 2878 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */ 2879 { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1, 2880 .access = PL1_RW, .type = ARM_CP_CONST, 2881 .resetvalue = 0 }, 2882 { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0, 2883 .access = PL1_RW, .type = ARM_CP_64BIT, .resetvalue = 0, 2884 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.par_s), 2885 offsetof(CPUARMState, cp15.par_ns)} }, 2886 { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0, 2887 .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, 2888 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), 2889 offsetof(CPUARMState, cp15.ttbr0_ns) }, 2890 .writefn = vmsa_ttbr_write, }, 2891 { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1, 2892 .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, 2893 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), 2894 offsetof(CPUARMState, cp15.ttbr1_ns) }, 2895 .writefn = vmsa_ttbr_write, }, 2896 REGINFO_SENTINEL 2897 }; 2898 2899 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri) 2900 { 2901 return vfp_get_fpcr(env); 2902 } 2903 2904 static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri, 2905 uint64_t value) 2906 { 2907 vfp_set_fpcr(env, value); 2908 } 2909 2910 static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri) 2911 { 2912 return vfp_get_fpsr(env); 2913 } 2914 2915 static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri, 2916 uint64_t value) 2917 { 2918 vfp_set_fpsr(env, value); 2919 } 2920 2921 static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri, 2922 bool isread) 2923 { 2924 if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) { 2925 return CP_ACCESS_TRAP; 2926 } 2927 return CP_ACCESS_OK; 2928 } 2929 2930 static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri, 2931 uint64_t value) 2932 { 2933 env->daif = value & PSTATE_DAIF; 2934 } 2935 2936 static CPAccessResult aa64_cacheop_access(CPUARMState *env, 2937 const ARMCPRegInfo *ri, 2938 bool isread) 2939 { 2940 /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless 2941 * SCTLR_EL1.UCI is set. 2942 */ 2943 if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCI)) { 2944 return CP_ACCESS_TRAP; 2945 } 2946 return CP_ACCESS_OK; 2947 } 2948 2949 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions 2950 * Page D4-1736 (DDI0487A.b) 2951 */ 2952 2953 static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri, 2954 uint64_t value) 2955 { 2956 CPUState *cs = ENV_GET_CPU(env); 2957 2958 if (arm_is_secure_below_el3(env)) { 2959 tlb_flush_by_mmuidx(cs, 2960 ARMMMUIdxBit_S1SE1 | 2961 ARMMMUIdxBit_S1SE0); 2962 } else { 2963 tlb_flush_by_mmuidx(cs, 2964 ARMMMUIdxBit_S12NSE1 | 2965 ARMMMUIdxBit_S12NSE0); 2966 } 2967 } 2968 2969 static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, 2970 uint64_t value) 2971 { 2972 CPUState *cs = ENV_GET_CPU(env); 2973 bool sec = arm_is_secure_below_el3(env); 2974 2975 if (sec) { 2976 tlb_flush_by_mmuidx_all_cpus_synced(cs, 2977 ARMMMUIdxBit_S1SE1 | 2978 ARMMMUIdxBit_S1SE0); 2979 } else { 2980 tlb_flush_by_mmuidx_all_cpus_synced(cs, 2981 ARMMMUIdxBit_S12NSE1 | 2982 ARMMMUIdxBit_S12NSE0); 2983 } 2984 } 2985 2986 static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, 2987 uint64_t value) 2988 { 2989 /* Note that the 'ALL' scope must invalidate both stage 1 and 2990 * stage 2 translations, whereas most other scopes only invalidate 2991 * stage 1 translations. 2992 */ 2993 ARMCPU *cpu = arm_env_get_cpu(env); 2994 CPUState *cs = CPU(cpu); 2995 2996 if (arm_is_secure_below_el3(env)) { 2997 tlb_flush_by_mmuidx(cs, 2998 ARMMMUIdxBit_S1SE1 | 2999 ARMMMUIdxBit_S1SE0); 3000 } else { 3001 if (arm_feature(env, ARM_FEATURE_EL2)) { 3002 tlb_flush_by_mmuidx(cs, 3003 ARMMMUIdxBit_S12NSE1 | 3004 ARMMMUIdxBit_S12NSE0 | 3005 ARMMMUIdxBit_S2NS); 3006 } else { 3007 tlb_flush_by_mmuidx(cs, 3008 ARMMMUIdxBit_S12NSE1 | 3009 ARMMMUIdxBit_S12NSE0); 3010 } 3011 } 3012 } 3013 3014 static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri, 3015 uint64_t value) 3016 { 3017 ARMCPU *cpu = arm_env_get_cpu(env); 3018 CPUState *cs = CPU(cpu); 3019 3020 tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2); 3021 } 3022 3023 static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri, 3024 uint64_t value) 3025 { 3026 ARMCPU *cpu = arm_env_get_cpu(env); 3027 CPUState *cs = CPU(cpu); 3028 3029 tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E3); 3030 } 3031 3032 static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, 3033 uint64_t value) 3034 { 3035 /* Note that the 'ALL' scope must invalidate both stage 1 and 3036 * stage 2 translations, whereas most other scopes only invalidate 3037 * stage 1 translations. 3038 */ 3039 CPUState *cs = ENV_GET_CPU(env); 3040 bool sec = arm_is_secure_below_el3(env); 3041 bool has_el2 = arm_feature(env, ARM_FEATURE_EL2); 3042 3043 if (sec) { 3044 tlb_flush_by_mmuidx_all_cpus_synced(cs, 3045 ARMMMUIdxBit_S1SE1 | 3046 ARMMMUIdxBit_S1SE0); 3047 } else if (has_el2) { 3048 tlb_flush_by_mmuidx_all_cpus_synced(cs, 3049 ARMMMUIdxBit_S12NSE1 | 3050 ARMMMUIdxBit_S12NSE0 | 3051 ARMMMUIdxBit_S2NS); 3052 } else { 3053 tlb_flush_by_mmuidx_all_cpus_synced(cs, 3054 ARMMMUIdxBit_S12NSE1 | 3055 ARMMMUIdxBit_S12NSE0); 3056 } 3057 } 3058 3059 static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri, 3060 uint64_t value) 3061 { 3062 CPUState *cs = ENV_GET_CPU(env); 3063 3064 tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2); 3065 } 3066 3067 static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri, 3068 uint64_t value) 3069 { 3070 CPUState *cs = ENV_GET_CPU(env); 3071 3072 tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E3); 3073 } 3074 3075 static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri, 3076 uint64_t value) 3077 { 3078 /* Invalidate by VA, EL1&0 (AArch64 version). 3079 * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1, 3080 * since we don't support flush-for-specific-ASID-only or 3081 * flush-last-level-only. 3082 */ 3083 ARMCPU *cpu = arm_env_get_cpu(env); 3084 CPUState *cs = CPU(cpu); 3085 uint64_t pageaddr = sextract64(value << 12, 0, 56); 3086 3087 if (arm_is_secure_below_el3(env)) { 3088 tlb_flush_page_by_mmuidx(cs, pageaddr, 3089 ARMMMUIdxBit_S1SE1 | 3090 ARMMMUIdxBit_S1SE0); 3091 } else { 3092 tlb_flush_page_by_mmuidx(cs, pageaddr, 3093 ARMMMUIdxBit_S12NSE1 | 3094 ARMMMUIdxBit_S12NSE0); 3095 } 3096 } 3097 3098 static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri, 3099 uint64_t value) 3100 { 3101 /* Invalidate by VA, EL2 3102 * Currently handles both VAE2 and VALE2, since we don't support 3103 * flush-last-level-only. 3104 */ 3105 ARMCPU *cpu = arm_env_get_cpu(env); 3106 CPUState *cs = CPU(cpu); 3107 uint64_t pageaddr = sextract64(value << 12, 0, 56); 3108 3109 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E2); 3110 } 3111 3112 static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri, 3113 uint64_t value) 3114 { 3115 /* Invalidate by VA, EL3 3116 * Currently handles both VAE3 and VALE3, since we don't support 3117 * flush-last-level-only. 3118 */ 3119 ARMCPU *cpu = arm_env_get_cpu(env); 3120 CPUState *cs = CPU(cpu); 3121 uint64_t pageaddr = sextract64(value << 12, 0, 56); 3122 3123 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E3); 3124 } 3125 3126 static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri, 3127 uint64_t value) 3128 { 3129 ARMCPU *cpu = arm_env_get_cpu(env); 3130 CPUState *cs = CPU(cpu); 3131 bool sec = arm_is_secure_below_el3(env); 3132 uint64_t pageaddr = sextract64(value << 12, 0, 56); 3133 3134 if (sec) { 3135 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, 3136 ARMMMUIdxBit_S1SE1 | 3137 ARMMMUIdxBit_S1SE0); 3138 } else { 3139 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, 3140 ARMMMUIdxBit_S12NSE1 | 3141 ARMMMUIdxBit_S12NSE0); 3142 } 3143 } 3144 3145 static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri, 3146 uint64_t value) 3147 { 3148 CPUState *cs = ENV_GET_CPU(env); 3149 uint64_t pageaddr = sextract64(value << 12, 0, 56); 3150 3151 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, 3152 ARMMMUIdxBit_S1E2); 3153 } 3154 3155 static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri, 3156 uint64_t value) 3157 { 3158 CPUState *cs = ENV_GET_CPU(env); 3159 uint64_t pageaddr = sextract64(value << 12, 0, 56); 3160 3161 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, 3162 ARMMMUIdxBit_S1E3); 3163 } 3164 3165 static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri, 3166 uint64_t value) 3167 { 3168 /* Invalidate by IPA. This has to invalidate any structures that 3169 * contain only stage 2 translation information, but does not need 3170 * to apply to structures that contain combined stage 1 and stage 2 3171 * translation information. 3172 * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero. 3173 */ 3174 ARMCPU *cpu = arm_env_get_cpu(env); 3175 CPUState *cs = CPU(cpu); 3176 uint64_t pageaddr; 3177 3178 if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { 3179 return; 3180 } 3181 3182 pageaddr = sextract64(value << 12, 0, 48); 3183 3184 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S2NS); 3185 } 3186 3187 static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri, 3188 uint64_t value) 3189 { 3190 CPUState *cs = ENV_GET_CPU(env); 3191 uint64_t pageaddr; 3192 3193 if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { 3194 return; 3195 } 3196 3197 pageaddr = sextract64(value << 12, 0, 48); 3198 3199 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, 3200 ARMMMUIdxBit_S2NS); 3201 } 3202 3203 static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri, 3204 bool isread) 3205 { 3206 /* We don't implement EL2, so the only control on DC ZVA is the 3207 * bit in the SCTLR which can prohibit access for EL0. 3208 */ 3209 if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_DZE)) { 3210 return CP_ACCESS_TRAP; 3211 } 3212 return CP_ACCESS_OK; 3213 } 3214 3215 static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri) 3216 { 3217 ARMCPU *cpu = arm_env_get_cpu(env); 3218 int dzp_bit = 1 << 4; 3219 3220 /* DZP indicates whether DC ZVA access is allowed */ 3221 if (aa64_zva_access(env, NULL, false) == CP_ACCESS_OK) { 3222 dzp_bit = 0; 3223 } 3224 return cpu->dcz_blocksize | dzp_bit; 3225 } 3226 3227 static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri, 3228 bool isread) 3229 { 3230 if (!(env->pstate & PSTATE_SP)) { 3231 /* Access to SP_EL0 is undefined if it's being used as 3232 * the stack pointer. 3233 */ 3234 return CP_ACCESS_TRAP_UNCATEGORIZED; 3235 } 3236 return CP_ACCESS_OK; 3237 } 3238 3239 static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri) 3240 { 3241 return env->pstate & PSTATE_SP; 3242 } 3243 3244 static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) 3245 { 3246 update_spsel(env, val); 3247 } 3248 3249 static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, 3250 uint64_t value) 3251 { 3252 ARMCPU *cpu = arm_env_get_cpu(env); 3253 3254 if (raw_read(env, ri) == value) { 3255 /* Skip the TLB flush if nothing actually changed; Linux likes 3256 * to do a lot of pointless SCTLR writes. 3257 */ 3258 return; 3259 } 3260 3261 if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) { 3262 /* M bit is RAZ/WI for PMSA with no MPU implemented */ 3263 value &= ~SCTLR_M; 3264 } 3265 3266 raw_write(env, ri, value); 3267 /* ??? Lots of these bits are not implemented. */ 3268 /* This may enable/disable the MMU, so do a TLB flush. */ 3269 tlb_flush(CPU(cpu)); 3270 } 3271 3272 static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri, 3273 bool isread) 3274 { 3275 if ((env->cp15.cptr_el[2] & CPTR_TFP) && arm_current_el(env) == 2) { 3276 return CP_ACCESS_TRAP_FP_EL2; 3277 } 3278 if (env->cp15.cptr_el[3] & CPTR_TFP) { 3279 return CP_ACCESS_TRAP_FP_EL3; 3280 } 3281 return CP_ACCESS_OK; 3282 } 3283 3284 static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri, 3285 uint64_t value) 3286 { 3287 env->cp15.mdcr_el3 = value & SDCR_VALID_MASK; 3288 } 3289 3290 static const ARMCPRegInfo v8_cp_reginfo[] = { 3291 /* Minimal set of EL0-visible registers. This will need to be expanded 3292 * significantly for system emulation of AArch64 CPUs. 3293 */ 3294 { .name = "NZCV", .state = ARM_CP_STATE_AA64, 3295 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2, 3296 .access = PL0_RW, .type = ARM_CP_NZCV }, 3297 { .name = "DAIF", .state = ARM_CP_STATE_AA64, 3298 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2, 3299 .type = ARM_CP_NO_RAW, 3300 .access = PL0_RW, .accessfn = aa64_daif_access, 3301 .fieldoffset = offsetof(CPUARMState, daif), 3302 .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore }, 3303 { .name = "FPCR", .state = ARM_CP_STATE_AA64, 3304 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4, 3305 .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write }, 3306 { .name = "FPSR", .state = ARM_CP_STATE_AA64, 3307 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4, 3308 .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write }, 3309 { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64, 3310 .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0, 3311 .access = PL0_R, .type = ARM_CP_NO_RAW, 3312 .readfn = aa64_dczid_read }, 3313 { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64, 3314 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1, 3315 .access = PL0_W, .type = ARM_CP_DC_ZVA, 3316 #ifndef CONFIG_USER_ONLY 3317 /* Avoid overhead of an access check that always passes in user-mode */ 3318 .accessfn = aa64_zva_access, 3319 #endif 3320 }, 3321 { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64, 3322 .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2, 3323 .access = PL1_R, .type = ARM_CP_CURRENTEL }, 3324 /* Cache ops: all NOPs since we don't emulate caches */ 3325 { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64, 3326 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, 3327 .access = PL1_W, .type = ARM_CP_NOP }, 3328 { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64, 3329 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, 3330 .access = PL1_W, .type = ARM_CP_NOP }, 3331 { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64, 3332 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1, 3333 .access = PL0_W, .type = ARM_CP_NOP, 3334 .accessfn = aa64_cacheop_access }, 3335 { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64, 3336 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, 3337 .access = PL1_W, .type = ARM_CP_NOP }, 3338 { .name = "DC_ISW", .state = ARM_CP_STATE_AA64, 3339 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, 3340 .access = PL1_W, .type = ARM_CP_NOP }, 3341 { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64, 3342 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1, 3343 .access = PL0_W, .type = ARM_CP_NOP, 3344 .accessfn = aa64_cacheop_access }, 3345 { .name = "DC_CSW", .state = ARM_CP_STATE_AA64, 3346 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, 3347 .access = PL1_W, .type = ARM_CP_NOP }, 3348 { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64, 3349 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1, 3350 .access = PL0_W, .type = ARM_CP_NOP, 3351 .accessfn = aa64_cacheop_access }, 3352 { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64, 3353 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1, 3354 .access = PL0_W, .type = ARM_CP_NOP, 3355 .accessfn = aa64_cacheop_access }, 3356 { .name = "DC_CISW", .state = ARM_CP_STATE_AA64, 3357 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, 3358 .access = PL1_W, .type = ARM_CP_NOP }, 3359 /* TLBI operations */ 3360 { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64, 3361 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, 3362 .access = PL1_W, .type = ARM_CP_NO_RAW, 3363 .writefn = tlbi_aa64_vmalle1is_write }, 3364 { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64, 3365 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, 3366 .access = PL1_W, .type = ARM_CP_NO_RAW, 3367 .writefn = tlbi_aa64_vae1is_write }, 3368 { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64, 3369 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, 3370 .access = PL1_W, .type = ARM_CP_NO_RAW, 3371 .writefn = tlbi_aa64_vmalle1is_write }, 3372 { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64, 3373 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, 3374 .access = PL1_W, .type = ARM_CP_NO_RAW, 3375 .writefn = tlbi_aa64_vae1is_write }, 3376 { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64, 3377 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, 3378 .access = PL1_W, .type = ARM_CP_NO_RAW, 3379 .writefn = tlbi_aa64_vae1is_write }, 3380 { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64, 3381 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, 3382 .access = PL1_W, .type = ARM_CP_NO_RAW, 3383 .writefn = tlbi_aa64_vae1is_write }, 3384 { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64, 3385 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, 3386 .access = PL1_W, .type = ARM_CP_NO_RAW, 3387 .writefn = tlbi_aa64_vmalle1_write }, 3388 { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64, 3389 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, 3390 .access = PL1_W, .type = ARM_CP_NO_RAW, 3391 .writefn = tlbi_aa64_vae1_write }, 3392 { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64, 3393 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, 3394 .access = PL1_W, .type = ARM_CP_NO_RAW, 3395 .writefn = tlbi_aa64_vmalle1_write }, 3396 { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64, 3397 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, 3398 .access = PL1_W, .type = ARM_CP_NO_RAW, 3399 .writefn = tlbi_aa64_vae1_write }, 3400 { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64, 3401 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, 3402 .access = PL1_W, .type = ARM_CP_NO_RAW, 3403 .writefn = tlbi_aa64_vae1_write }, 3404 { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64, 3405 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, 3406 .access = PL1_W, .type = ARM_CP_NO_RAW, 3407 .writefn = tlbi_aa64_vae1_write }, 3408 { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64, 3409 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1, 3410 .access = PL2_W, .type = ARM_CP_NO_RAW, 3411 .writefn = tlbi_aa64_ipas2e1is_write }, 3412 { .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64, 3413 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5, 3414 .access = PL2_W, .type = ARM_CP_NO_RAW, 3415 .writefn = tlbi_aa64_ipas2e1is_write }, 3416 { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64, 3417 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4, 3418 .access = PL2_W, .type = ARM_CP_NO_RAW, 3419 .writefn = tlbi_aa64_alle1is_write }, 3420 { .name = "TLBI_VMALLS12E1IS", .state = ARM_CP_STATE_AA64, 3421 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 6, 3422 .access = PL2_W, .type = ARM_CP_NO_RAW, 3423 .writefn = tlbi_aa64_alle1is_write }, 3424 { .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64, 3425 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1, 3426 .access = PL2_W, .type = ARM_CP_NO_RAW, 3427 .writefn = tlbi_aa64_ipas2e1_write }, 3428 { .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64, 3429 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5, 3430 .access = PL2_W, .type = ARM_CP_NO_RAW, 3431 .writefn = tlbi_aa64_ipas2e1_write }, 3432 { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64, 3433 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4, 3434 .access = PL2_W, .type = ARM_CP_NO_RAW, 3435 .writefn = tlbi_aa64_alle1_write }, 3436 { .name = "TLBI_VMALLS12E1", .state = ARM_CP_STATE_AA64, 3437 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6, 3438 .access = PL2_W, .type = ARM_CP_NO_RAW, 3439 .writefn = tlbi_aa64_alle1is_write }, 3440 #ifndef CONFIG_USER_ONLY 3441 /* 64 bit address translation operations */ 3442 { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64, 3443 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0, 3444 .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3445 { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64, 3446 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1, 3447 .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3448 { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64, 3449 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2, 3450 .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3451 { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64, 3452 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3, 3453 .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3454 { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64, 3455 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4, 3456 .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3457 { .name = "AT_S12E1W", .state = ARM_CP_STATE_AA64, 3458 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 5, 3459 .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3460 { .name = "AT_S12E0R", .state = ARM_CP_STATE_AA64, 3461 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 6, 3462 .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3463 { .name = "AT_S12E0W", .state = ARM_CP_STATE_AA64, 3464 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 7, 3465 .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3466 /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */ 3467 { .name = "AT_S1E3R", .state = ARM_CP_STATE_AA64, 3468 .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 0, 3469 .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3470 { .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64, 3471 .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1, 3472 .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3473 { .name = "PAR_EL1", .state = ARM_CP_STATE_AA64, 3474 .type = ARM_CP_ALIAS, 3475 .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0, 3476 .access = PL1_RW, .resetvalue = 0, 3477 .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]), 3478 .writefn = par_write }, 3479 #endif 3480 /* TLB invalidate last level of translation table walk */ 3481 { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, 3482 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write }, 3483 { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, 3484 .type = ARM_CP_NO_RAW, .access = PL1_W, 3485 .writefn = tlbimvaa_is_write }, 3486 { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, 3487 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, 3488 { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, 3489 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write }, 3490 { .name = "TLBIMVALH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5, 3491 .type = ARM_CP_NO_RAW, .access = PL2_W, 3492 .writefn = tlbimva_hyp_write }, 3493 { .name = "TLBIMVALHIS", 3494 .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5, 3495 .type = ARM_CP_NO_RAW, .access = PL2_W, 3496 .writefn = tlbimva_hyp_is_write }, 3497 { .name = "TLBIIPAS2", 3498 .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1, 3499 .type = ARM_CP_NO_RAW, .access = PL2_W, 3500 .writefn = tlbiipas2_write }, 3501 { .name = "TLBIIPAS2IS", 3502 .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1, 3503 .type = ARM_CP_NO_RAW, .access = PL2_W, 3504 .writefn = tlbiipas2_is_write }, 3505 { .name = "TLBIIPAS2L", 3506 .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5, 3507 .type = ARM_CP_NO_RAW, .access = PL2_W, 3508 .writefn = tlbiipas2_write }, 3509 { .name = "TLBIIPAS2LIS", 3510 .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5, 3511 .type = ARM_CP_NO_RAW, .access = PL2_W, 3512 .writefn = tlbiipas2_is_write }, 3513 /* 32 bit cache operations */ 3514 { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, 3515 .type = ARM_CP_NOP, .access = PL1_W }, 3516 { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6, 3517 .type = ARM_CP_NOP, .access = PL1_W }, 3518 { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, 3519 .type = ARM_CP_NOP, .access = PL1_W }, 3520 { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1, 3521 .type = ARM_CP_NOP, .access = PL1_W }, 3522 { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6, 3523 .type = ARM_CP_NOP, .access = PL1_W }, 3524 { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7, 3525 .type = ARM_CP_NOP, .access = PL1_W }, 3526 { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, 3527 .type = ARM_CP_NOP, .access = PL1_W }, 3528 { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, 3529 .type = ARM_CP_NOP, .access = PL1_W }, 3530 { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1, 3531 .type = ARM_CP_NOP, .access = PL1_W }, 3532 { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, 3533 .type = ARM_CP_NOP, .access = PL1_W }, 3534 { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1, 3535 .type = ARM_CP_NOP, .access = PL1_W }, 3536 { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1, 3537 .type = ARM_CP_NOP, .access = PL1_W }, 3538 { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, 3539 .type = ARM_CP_NOP, .access = PL1_W }, 3540 /* MMU Domain access control / MPU write buffer control */ 3541 { .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0, 3542 .access = PL1_RW, .resetvalue = 0, 3543 .writefn = dacr_write, .raw_writefn = raw_write, 3544 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s), 3545 offsetoflow32(CPUARMState, cp15.dacr_ns) } }, 3546 { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64, 3547 .type = ARM_CP_ALIAS, 3548 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1, 3549 .access = PL1_RW, 3550 .fieldoffset = offsetof(CPUARMState, elr_el[1]) }, 3551 { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64, 3552 .type = ARM_CP_ALIAS, 3553 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0, 3554 .access = PL1_RW, 3555 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_SVC]) }, 3556 /* We rely on the access checks not allowing the guest to write to the 3557 * state field when SPSel indicates that it's being used as the stack 3558 * pointer. 3559 */ 3560 { .name = "SP_EL0", .state = ARM_CP_STATE_AA64, 3561 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0, 3562 .access = PL1_RW, .accessfn = sp_el0_access, 3563 .type = ARM_CP_ALIAS, 3564 .fieldoffset = offsetof(CPUARMState, sp_el[0]) }, 3565 { .name = "SP_EL1", .state = ARM_CP_STATE_AA64, 3566 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0, 3567 .access = PL2_RW, .type = ARM_CP_ALIAS, 3568 .fieldoffset = offsetof(CPUARMState, sp_el[1]) }, 3569 { .name = "SPSel", .state = ARM_CP_STATE_AA64, 3570 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0, 3571 .type = ARM_CP_NO_RAW, 3572 .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write }, 3573 { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64, 3574 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0, 3575 .type = ARM_CP_ALIAS, 3576 .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]), 3577 .access = PL2_RW, .accessfn = fpexc32_access }, 3578 { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64, 3579 .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0, 3580 .access = PL2_RW, .resetvalue = 0, 3581 .writefn = dacr_write, .raw_writefn = raw_write, 3582 .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) }, 3583 { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64, 3584 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1, 3585 .access = PL2_RW, .resetvalue = 0, 3586 .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) }, 3587 { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64, 3588 .type = ARM_CP_ALIAS, 3589 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 0, 3590 .access = PL2_RW, 3591 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_IRQ]) }, 3592 { .name = "SPSR_ABT", .state = ARM_CP_STATE_AA64, 3593 .type = ARM_CP_ALIAS, 3594 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 1, 3595 .access = PL2_RW, 3596 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_ABT]) }, 3597 { .name = "SPSR_UND", .state = ARM_CP_STATE_AA64, 3598 .type = ARM_CP_ALIAS, 3599 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 2, 3600 .access = PL2_RW, 3601 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_UND]) }, 3602 { .name = "SPSR_FIQ", .state = ARM_CP_STATE_AA64, 3603 .type = ARM_CP_ALIAS, 3604 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 3, 3605 .access = PL2_RW, 3606 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) }, 3607 { .name = "MDCR_EL3", .state = ARM_CP_STATE_AA64, 3608 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1, 3609 .resetvalue = 0, 3610 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) }, 3611 { .name = "SDCR", .type = ARM_CP_ALIAS, 3612 .cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1, 3613 .access = PL1_RW, .accessfn = access_trap_aa32s_el1, 3614 .writefn = sdcr_write, 3615 .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) }, 3616 REGINFO_SENTINEL 3617 }; 3618 3619 /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */ 3620 static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { 3621 { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64, 3622 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, 3623 .access = PL2_RW, 3624 .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, 3625 { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64, 3626 .type = ARM_CP_NO_RAW, 3627 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, 3628 .access = PL2_RW, 3629 .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, 3630 { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH, 3631 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, 3632 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3633 { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH, 3634 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0, 3635 .access = PL2_RW, .type = ARM_CP_CONST, 3636 .resetvalue = 0 }, 3637 { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, 3638 .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, 3639 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3640 { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH, 3641 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0, 3642 .access = PL2_RW, .type = ARM_CP_CONST, 3643 .resetvalue = 0 }, 3644 { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, 3645 .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, 3646 .access = PL2_RW, .type = ARM_CP_CONST, 3647 .resetvalue = 0 }, 3648 { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH, 3649 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0, 3650 .access = PL2_RW, .type = ARM_CP_CONST, 3651 .resetvalue = 0 }, 3652 { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH, 3653 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1, 3654 .access = PL2_RW, .type = ARM_CP_CONST, 3655 .resetvalue = 0 }, 3656 { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, 3657 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, 3658 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3659 { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH, 3660 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, 3661 .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, 3662 .type = ARM_CP_CONST, .resetvalue = 0 }, 3663 { .name = "VTTBR", .state = ARM_CP_STATE_AA32, 3664 .cp = 15, .opc1 = 6, .crm = 2, 3665 .access = PL2_RW, .accessfn = access_el3_aa32ns, 3666 .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 3667 { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64, 3668 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0, 3669 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3670 { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH, 3671 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, 3672 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3673 { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH, 3674 .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2, 3675 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3676 { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64, 3677 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, 3678 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3679 { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2, 3680 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, 3681 .resetvalue = 0 }, 3682 { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH, 3683 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0, 3684 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3685 { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64, 3686 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3, 3687 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3688 { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14, 3689 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, 3690 .resetvalue = 0 }, 3691 { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64, 3692 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2, 3693 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3694 { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14, 3695 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, 3696 .resetvalue = 0 }, 3697 { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH, 3698 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0, 3699 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3700 { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, 3701 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, 3702 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3703 { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, 3704 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1, 3705 .access = PL2_RW, .accessfn = access_tda, 3706 .type = ARM_CP_CONST, .resetvalue = 0 }, 3707 { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH, 3708 .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, 3709 .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, 3710 .type = ARM_CP_CONST, .resetvalue = 0 }, 3711 { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH, 3712 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3, 3713 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3714 REGINFO_SENTINEL 3715 }; 3716 3717 static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) 3718 { 3719 ARMCPU *cpu = arm_env_get_cpu(env); 3720 uint64_t valid_mask = HCR_MASK; 3721 3722 if (arm_feature(env, ARM_FEATURE_EL3)) { 3723 valid_mask &= ~HCR_HCD; 3724 } else { 3725 valid_mask &= ~HCR_TSC; 3726 } 3727 3728 /* Clear RES0 bits. */ 3729 value &= valid_mask; 3730 3731 /* These bits change the MMU setup: 3732 * HCR_VM enables stage 2 translation 3733 * HCR_PTW forbids certain page-table setups 3734 * HCR_DC Disables stage1 and enables stage2 translation 3735 */ 3736 if ((raw_read(env, ri) ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) { 3737 tlb_flush(CPU(cpu)); 3738 } 3739 raw_write(env, ri, value); 3740 } 3741 3742 static const ARMCPRegInfo el2_cp_reginfo[] = { 3743 { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64, 3744 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, 3745 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), 3746 .writefn = hcr_write }, 3747 { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64, 3748 .type = ARM_CP_ALIAS, 3749 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1, 3750 .access = PL2_RW, 3751 .fieldoffset = offsetof(CPUARMState, elr_el[2]) }, 3752 { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64, 3753 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, 3754 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) }, 3755 { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64, 3756 .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, 3757 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) }, 3758 { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64, 3759 .type = ARM_CP_ALIAS, 3760 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0, 3761 .access = PL2_RW, 3762 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_HYP]) }, 3763 { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64, 3764 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, 3765 .access = PL2_RW, .writefn = vbar_write, 3766 .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]), 3767 .resetvalue = 0 }, 3768 { .name = "SP_EL2", .state = ARM_CP_STATE_AA64, 3769 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0, 3770 .access = PL3_RW, .type = ARM_CP_ALIAS, 3771 .fieldoffset = offsetof(CPUARMState, sp_el[2]) }, 3772 { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH, 3773 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, 3774 .access = PL2_RW, .accessfn = cptr_access, .resetvalue = 0, 3775 .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[2]) }, 3776 { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH, 3777 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0, 3778 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[2]), 3779 .resetvalue = 0 }, 3780 { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, 3781 .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, 3782 .access = PL2_RW, .type = ARM_CP_ALIAS, 3783 .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el[2]) }, 3784 { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH, 3785 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0, 3786 .access = PL2_RW, .type = ARM_CP_CONST, 3787 .resetvalue = 0 }, 3788 /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */ 3789 { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, 3790 .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, 3791 .access = PL2_RW, .type = ARM_CP_CONST, 3792 .resetvalue = 0 }, 3793 { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH, 3794 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0, 3795 .access = PL2_RW, .type = ARM_CP_CONST, 3796 .resetvalue = 0 }, 3797 { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH, 3798 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1, 3799 .access = PL2_RW, .type = ARM_CP_CONST, 3800 .resetvalue = 0 }, 3801 { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, 3802 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, 3803 .access = PL2_RW, 3804 /* no .writefn needed as this can't cause an ASID change; 3805 * no .raw_writefn or .resetfn needed as we never use mask/base_mask 3806 */ 3807 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) }, 3808 { .name = "VTCR", .state = ARM_CP_STATE_AA32, 3809 .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, 3810 .type = ARM_CP_ALIAS, 3811 .access = PL2_RW, .accessfn = access_el3_aa32ns, 3812 .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) }, 3813 { .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64, 3814 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, 3815 .access = PL2_RW, 3816 /* no .writefn needed as this can't cause an ASID change; 3817 * no .raw_writefn or .resetfn needed as we never use mask/base_mask 3818 */ 3819 .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) }, 3820 { .name = "VTTBR", .state = ARM_CP_STATE_AA32, 3821 .cp = 15, .opc1 = 6, .crm = 2, 3822 .type = ARM_CP_64BIT | ARM_CP_ALIAS, 3823 .access = PL2_RW, .accessfn = access_el3_aa32ns, 3824 .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2), 3825 .writefn = vttbr_write }, 3826 { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64, 3827 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0, 3828 .access = PL2_RW, .writefn = vttbr_write, 3829 .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2) }, 3830 { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH, 3831 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, 3832 .access = PL2_RW, .raw_writefn = raw_write, .writefn = sctlr_write, 3833 .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[2]) }, 3834 { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH, 3835 .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2, 3836 .access = PL2_RW, .resetvalue = 0, 3837 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) }, 3838 { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64, 3839 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, 3840 .access = PL2_RW, .resetvalue = 0, 3841 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) }, 3842 { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2, 3843 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, 3844 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) }, 3845 { .name = "TLBIALLNSNH", 3846 .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4, 3847 .type = ARM_CP_NO_RAW, .access = PL2_W, 3848 .writefn = tlbiall_nsnh_write }, 3849 { .name = "TLBIALLNSNHIS", 3850 .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4, 3851 .type = ARM_CP_NO_RAW, .access = PL2_W, 3852 .writefn = tlbiall_nsnh_is_write }, 3853 { .name = "TLBIALLH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0, 3854 .type = ARM_CP_NO_RAW, .access = PL2_W, 3855 .writefn = tlbiall_hyp_write }, 3856 { .name = "TLBIALLHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0, 3857 .type = ARM_CP_NO_RAW, .access = PL2_W, 3858 .writefn = tlbiall_hyp_is_write }, 3859 { .name = "TLBIMVAH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1, 3860 .type = ARM_CP_NO_RAW, .access = PL2_W, 3861 .writefn = tlbimva_hyp_write }, 3862 { .name = "TLBIMVAHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1, 3863 .type = ARM_CP_NO_RAW, .access = PL2_W, 3864 .writefn = tlbimva_hyp_is_write }, 3865 { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64, 3866 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0, 3867 .type = ARM_CP_NO_RAW, .access = PL2_W, 3868 .writefn = tlbi_aa64_alle2_write }, 3869 { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64, 3870 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1, 3871 .type = ARM_CP_NO_RAW, .access = PL2_W, 3872 .writefn = tlbi_aa64_vae2_write }, 3873 { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64, 3874 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5, 3875 .access = PL2_W, .type = ARM_CP_NO_RAW, 3876 .writefn = tlbi_aa64_vae2_write }, 3877 { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64, 3878 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0, 3879 .access = PL2_W, .type = ARM_CP_NO_RAW, 3880 .writefn = tlbi_aa64_alle2is_write }, 3881 { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64, 3882 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1, 3883 .type = ARM_CP_NO_RAW, .access = PL2_W, 3884 .writefn = tlbi_aa64_vae2is_write }, 3885 { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64, 3886 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5, 3887 .access = PL2_W, .type = ARM_CP_NO_RAW, 3888 .writefn = tlbi_aa64_vae2is_write }, 3889 #ifndef CONFIG_USER_ONLY 3890 /* Unlike the other EL2-related AT operations, these must 3891 * UNDEF from EL3 if EL2 is not implemented, which is why we 3892 * define them here rather than with the rest of the AT ops. 3893 */ 3894 { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64, 3895 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, 3896 .access = PL2_W, .accessfn = at_s1e2_access, 3897 .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3898 { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64, 3899 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, 3900 .access = PL2_W, .accessfn = at_s1e2_access, 3901 .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3902 /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE 3903 * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3 3904 * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose 3905 * to behave as if SCR.NS was 1. 3906 */ 3907 { .name = "ATS1HR", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, 3908 .access = PL2_W, 3909 .writefn = ats1h_write, .type = ARM_CP_NO_RAW }, 3910 { .name = "ATS1HW", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, 3911 .access = PL2_W, 3912 .writefn = ats1h_write, .type = ARM_CP_NO_RAW }, 3913 { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH, 3914 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0, 3915 /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the 3916 * reset values as IMPDEF. We choose to reset to 3 to comply with 3917 * both ARMv7 and ARMv8. 3918 */ 3919 .access = PL2_RW, .resetvalue = 3, 3920 .fieldoffset = offsetof(CPUARMState, cp15.cnthctl_el2) }, 3921 { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64, 3922 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3, 3923 .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0, 3924 .writefn = gt_cntvoff_write, 3925 .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) }, 3926 { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14, 3927 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS | ARM_CP_IO, 3928 .writefn = gt_cntvoff_write, 3929 .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) }, 3930 { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64, 3931 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2, 3932 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval), 3933 .type = ARM_CP_IO, .access = PL2_RW, 3934 .writefn = gt_hyp_cval_write, .raw_writefn = raw_write }, 3935 { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14, 3936 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval), 3937 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_IO, 3938 .writefn = gt_hyp_cval_write, .raw_writefn = raw_write }, 3939 { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH, 3940 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0, 3941 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW, 3942 .resetfn = gt_hyp_timer_reset, 3943 .readfn = gt_hyp_tval_read, .writefn = gt_hyp_tval_write }, 3944 { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, 3945 .type = ARM_CP_IO, 3946 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, 3947 .access = PL2_RW, 3948 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].ctl), 3949 .resetvalue = 0, 3950 .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write }, 3951 #endif 3952 /* The only field of MDCR_EL2 that has a defined architectural reset value 3953 * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but we 3954 * don't impelment any PMU event counters, so using zero as a reset 3955 * value for MDCR_EL2 is okay 3956 */ 3957 { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, 3958 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1, 3959 .access = PL2_RW, .resetvalue = 0, 3960 .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), }, 3961 { .name = "HPFAR", .state = ARM_CP_STATE_AA32, 3962 .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, 3963 .access = PL2_RW, .accessfn = access_el3_aa32ns, 3964 .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, 3965 { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64, 3966 .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, 3967 .access = PL2_RW, 3968 .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, 3969 { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH, 3970 .cp = 15, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3, 3971 .access = PL2_RW, 3972 .fieldoffset = offsetof(CPUARMState, cp15.hstr_el2) }, 3973 REGINFO_SENTINEL 3974 }; 3975 3976 static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri, 3977 bool isread) 3978 { 3979 /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2. 3980 * At Secure EL1 it traps to EL3. 3981 */ 3982 if (arm_current_el(env) == 3) { 3983 return CP_ACCESS_OK; 3984 } 3985 if (arm_is_secure_below_el3(env)) { 3986 return CP_ACCESS_TRAP_EL3; 3987 } 3988 /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */ 3989 if (isread) { 3990 return CP_ACCESS_OK; 3991 } 3992 return CP_ACCESS_TRAP_UNCATEGORIZED; 3993 } 3994 3995 static const ARMCPRegInfo el3_cp_reginfo[] = { 3996 { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64, 3997 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0, 3998 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), 3999 .resetvalue = 0, .writefn = scr_write }, 4000 { .name = "SCR", .type = ARM_CP_ALIAS, 4001 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0, 4002 .access = PL1_RW, .accessfn = access_trap_aa32s_el1, 4003 .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3), 4004 .writefn = scr_write }, 4005 { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64, 4006 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1, 4007 .access = PL3_RW, .resetvalue = 0, 4008 .fieldoffset = offsetof(CPUARMState, cp15.sder) }, 4009 { .name = "SDER", 4010 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1, 4011 .access = PL3_RW, .resetvalue = 0, 4012 .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) }, 4013 { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, 4014 .access = PL1_RW, .accessfn = access_trap_aa32s_el1, 4015 .writefn = vbar_write, .resetvalue = 0, 4016 .fieldoffset = offsetof(CPUARMState, cp15.mvbar) }, 4017 { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64, 4018 .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0, 4019 .access = PL3_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0, 4020 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) }, 4021 { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64, 4022 .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2, 4023 .access = PL3_RW, 4024 /* no .writefn needed as this can't cause an ASID change; 4025 * we must provide a .raw_writefn and .resetfn because we handle 4026 * reset and migration for the AArch32 TTBCR(S), which might be 4027 * using mask and base_mask. 4028 */ 4029 .resetfn = vmsa_ttbcr_reset, .raw_writefn = vmsa_ttbcr_raw_write, 4030 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) }, 4031 { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64, 4032 .type = ARM_CP_ALIAS, 4033 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1, 4034 .access = PL3_RW, 4035 .fieldoffset = offsetof(CPUARMState, elr_el[3]) }, 4036 { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64, 4037 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0, 4038 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) }, 4039 { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64, 4040 .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0, 4041 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) }, 4042 { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64, 4043 .type = ARM_CP_ALIAS, 4044 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0, 4045 .access = PL3_RW, 4046 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_MON]) }, 4047 { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64, 4048 .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0, 4049 .access = PL3_RW, .writefn = vbar_write, 4050 .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]), 4051 .resetvalue = 0 }, 4052 { .name = "CPTR_EL3", .state = ARM_CP_STATE_AA64, 4053 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 2, 4054 .access = PL3_RW, .accessfn = cptr_access, .resetvalue = 0, 4055 .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[3]) }, 4056 { .name = "TPIDR_EL3", .state = ARM_CP_STATE_AA64, 4057 .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 2, 4058 .access = PL3_RW, .resetvalue = 0, 4059 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[3]) }, 4060 { .name = "AMAIR_EL3", .state = ARM_CP_STATE_AA64, 4061 .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0, 4062 .access = PL3_RW, .type = ARM_CP_CONST, 4063 .resetvalue = 0 }, 4064 { .name = "AFSR0_EL3", .state = ARM_CP_STATE_BOTH, 4065 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 0, 4066 .access = PL3_RW, .type = ARM_CP_CONST, 4067 .resetvalue = 0 }, 4068 { .name = "AFSR1_EL3", .state = ARM_CP_STATE_BOTH, 4069 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 1, 4070 .access = PL3_RW, .type = ARM_CP_CONST, 4071 .resetvalue = 0 }, 4072 { .name = "TLBI_ALLE3IS", .state = ARM_CP_STATE_AA64, 4073 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 0, 4074 .access = PL3_W, .type = ARM_CP_NO_RAW, 4075 .writefn = tlbi_aa64_alle3is_write }, 4076 { .name = "TLBI_VAE3IS", .state = ARM_CP_STATE_AA64, 4077 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 1, 4078 .access = PL3_W, .type = ARM_CP_NO_RAW, 4079 .writefn = tlbi_aa64_vae3is_write }, 4080 { .name = "TLBI_VALE3IS", .state = ARM_CP_STATE_AA64, 4081 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 5, 4082 .access = PL3_W, .type = ARM_CP_NO_RAW, 4083 .writefn = tlbi_aa64_vae3is_write }, 4084 { .name = "TLBI_ALLE3", .state = ARM_CP_STATE_AA64, 4085 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 0, 4086 .access = PL3_W, .type = ARM_CP_NO_RAW, 4087 .writefn = tlbi_aa64_alle3_write }, 4088 { .name = "TLBI_VAE3", .state = ARM_CP_STATE_AA64, 4089 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 1, 4090 .access = PL3_W, .type = ARM_CP_NO_RAW, 4091 .writefn = tlbi_aa64_vae3_write }, 4092 { .name = "TLBI_VALE3", .state = ARM_CP_STATE_AA64, 4093 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5, 4094 .access = PL3_W, .type = ARM_CP_NO_RAW, 4095 .writefn = tlbi_aa64_vae3_write }, 4096 REGINFO_SENTINEL 4097 }; 4098 4099 static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri, 4100 bool isread) 4101 { 4102 /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64, 4103 * but the AArch32 CTR has its own reginfo struct) 4104 */ 4105 if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCT)) { 4106 return CP_ACCESS_TRAP; 4107 } 4108 return CP_ACCESS_OK; 4109 } 4110 4111 static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri, 4112 uint64_t value) 4113 { 4114 /* Writes to OSLAR_EL1 may update the OS lock status, which can be 4115 * read via a bit in OSLSR_EL1. 4116 */ 4117 int oslock; 4118 4119 if (ri->state == ARM_CP_STATE_AA32) { 4120 oslock = (value == 0xC5ACCE55); 4121 } else { 4122 oslock = value & 1; 4123 } 4124 4125 env->cp15.oslsr_el1 = deposit32(env->cp15.oslsr_el1, 1, 1, oslock); 4126 } 4127 4128 static const ARMCPRegInfo debug_cp_reginfo[] = { 4129 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped 4130 * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1; 4131 * unlike DBGDRAR it is never accessible from EL0. 4132 * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64 4133 * accessor. 4134 */ 4135 { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0, 4136 .access = PL0_R, .accessfn = access_tdra, 4137 .type = ARM_CP_CONST, .resetvalue = 0 }, 4138 { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64, 4139 .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, 4140 .access = PL1_R, .accessfn = access_tdra, 4141 .type = ARM_CP_CONST, .resetvalue = 0 }, 4142 { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, 4143 .access = PL0_R, .accessfn = access_tdra, 4144 .type = ARM_CP_CONST, .resetvalue = 0 }, 4145 /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */ 4146 { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH, 4147 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, 4148 .access = PL1_RW, .accessfn = access_tda, 4149 .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), 4150 .resetvalue = 0 }, 4151 /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1. 4152 * We don't implement the configurable EL0 access. 4153 */ 4154 { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH, 4155 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, 4156 .type = ARM_CP_ALIAS, 4157 .access = PL1_R, .accessfn = access_tda, 4158 .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), }, 4159 { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH, 4160 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4, 4161 .access = PL1_W, .type = ARM_CP_NO_RAW, 4162 .accessfn = access_tdosa, 4163 .writefn = oslar_write }, 4164 { .name = "OSLSR_EL1", .state = ARM_CP_STATE_BOTH, 4165 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 4, 4166 .access = PL1_R, .resetvalue = 10, 4167 .accessfn = access_tdosa, 4168 .fieldoffset = offsetof(CPUARMState, cp15.oslsr_el1) }, 4169 /* Dummy OSDLR_EL1: 32-bit Linux will read this */ 4170 { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH, 4171 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4, 4172 .access = PL1_RW, .accessfn = access_tdosa, 4173 .type = ARM_CP_NOP }, 4174 /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't 4175 * implement vector catch debug events yet. 4176 */ 4177 { .name = "DBGVCR", 4178 .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, 4179 .access = PL1_RW, .accessfn = access_tda, 4180 .type = ARM_CP_NOP }, 4181 /* Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor 4182 * to save and restore a 32-bit guest's DBGVCR) 4183 */ 4184 { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64, 4185 .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0, 4186 .access = PL2_RW, .accessfn = access_tda, 4187 .type = ARM_CP_NOP }, 4188 /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications 4189 * Channel but Linux may try to access this register. The 32-bit 4190 * alias is DBGDCCINT. 4191 */ 4192 { .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH, 4193 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, 4194 .access = PL1_RW, .accessfn = access_tda, 4195 .type = ARM_CP_NOP }, 4196 REGINFO_SENTINEL 4197 }; 4198 4199 static const ARMCPRegInfo debug_lpae_cp_reginfo[] = { 4200 /* 64 bit access versions of the (dummy) debug registers */ 4201 { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0, 4202 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, 4203 { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0, 4204 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, 4205 REGINFO_SENTINEL 4206 }; 4207 4208 void hw_watchpoint_update(ARMCPU *cpu, int n) 4209 { 4210 CPUARMState *env = &cpu->env; 4211 vaddr len = 0; 4212 vaddr wvr = env->cp15.dbgwvr[n]; 4213 uint64_t wcr = env->cp15.dbgwcr[n]; 4214 int mask; 4215 int flags = BP_CPU | BP_STOP_BEFORE_ACCESS; 4216 4217 if (env->cpu_watchpoint[n]) { 4218 cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]); 4219 env->cpu_watchpoint[n] = NULL; 4220 } 4221 4222 if (!extract64(wcr, 0, 1)) { 4223 /* E bit clear : watchpoint disabled */ 4224 return; 4225 } 4226 4227 switch (extract64(wcr, 3, 2)) { 4228 case 0: 4229 /* LSC 00 is reserved and must behave as if the wp is disabled */ 4230 return; 4231 case 1: 4232 flags |= BP_MEM_READ; 4233 break; 4234 case 2: 4235 flags |= BP_MEM_WRITE; 4236 break; 4237 case 3: 4238 flags |= BP_MEM_ACCESS; 4239 break; 4240 } 4241 4242 /* Attempts to use both MASK and BAS fields simultaneously are 4243 * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case, 4244 * thus generating a watchpoint for every byte in the masked region. 4245 */ 4246 mask = extract64(wcr, 24, 4); 4247 if (mask == 1 || mask == 2) { 4248 /* Reserved values of MASK; we must act as if the mask value was 4249 * some non-reserved value, or as if the watchpoint were disabled. 4250 * We choose the latter. 4251 */ 4252 return; 4253 } else if (mask) { 4254 /* Watchpoint covers an aligned area up to 2GB in size */ 4255 len = 1ULL << mask; 4256 /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE 4257 * whether the watchpoint fires when the unmasked bits match; we opt 4258 * to generate the exceptions. 4259 */ 4260 wvr &= ~(len - 1); 4261 } else { 4262 /* Watchpoint covers bytes defined by the byte address select bits */ 4263 int bas = extract64(wcr, 5, 8); 4264 int basstart; 4265 4266 if (bas == 0) { 4267 /* This must act as if the watchpoint is disabled */ 4268 return; 4269 } 4270 4271 if (extract64(wvr, 2, 1)) { 4272 /* Deprecated case of an only 4-aligned address. BAS[7:4] are 4273 * ignored, and BAS[3:0] define which bytes to watch. 4274 */ 4275 bas &= 0xf; 4276 } 4277 /* The BAS bits are supposed to be programmed to indicate a contiguous 4278 * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether 4279 * we fire for each byte in the word/doubleword addressed by the WVR. 4280 * We choose to ignore any non-zero bits after the first range of 1s. 4281 */ 4282 basstart = ctz32(bas); 4283 len = cto32(bas >> basstart); 4284 wvr += basstart; 4285 } 4286 4287 cpu_watchpoint_insert(CPU(cpu), wvr, len, flags, 4288 &env->cpu_watchpoint[n]); 4289 } 4290 4291 void hw_watchpoint_update_all(ARMCPU *cpu) 4292 { 4293 int i; 4294 CPUARMState *env = &cpu->env; 4295 4296 /* Completely clear out existing QEMU watchpoints and our array, to 4297 * avoid possible stale entries following migration load. 4298 */ 4299 cpu_watchpoint_remove_all(CPU(cpu), BP_CPU); 4300 memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint)); 4301 4302 for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) { 4303 hw_watchpoint_update(cpu, i); 4304 } 4305 } 4306 4307 static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri, 4308 uint64_t value) 4309 { 4310 ARMCPU *cpu = arm_env_get_cpu(env); 4311 int i = ri->crm; 4312 4313 /* Bits [63:49] are hardwired to the value of bit [48]; that is, the 4314 * register reads and behaves as if values written are sign extended. 4315 * Bits [1:0] are RES0. 4316 */ 4317 value = sextract64(value, 0, 49) & ~3ULL; 4318 4319 raw_write(env, ri, value); 4320 hw_watchpoint_update(cpu, i); 4321 } 4322 4323 static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri, 4324 uint64_t value) 4325 { 4326 ARMCPU *cpu = arm_env_get_cpu(env); 4327 int i = ri->crm; 4328 4329 raw_write(env, ri, value); 4330 hw_watchpoint_update(cpu, i); 4331 } 4332 4333 void hw_breakpoint_update(ARMCPU *cpu, int n) 4334 { 4335 CPUARMState *env = &cpu->env; 4336 uint64_t bvr = env->cp15.dbgbvr[n]; 4337 uint64_t bcr = env->cp15.dbgbcr[n]; 4338 vaddr addr; 4339 int bt; 4340 int flags = BP_CPU; 4341 4342 if (env->cpu_breakpoint[n]) { 4343 cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]); 4344 env->cpu_breakpoint[n] = NULL; 4345 } 4346 4347 if (!extract64(bcr, 0, 1)) { 4348 /* E bit clear : watchpoint disabled */ 4349 return; 4350 } 4351 4352 bt = extract64(bcr, 20, 4); 4353 4354 switch (bt) { 4355 case 4: /* unlinked address mismatch (reserved if AArch64) */ 4356 case 5: /* linked address mismatch (reserved if AArch64) */ 4357 qemu_log_mask(LOG_UNIMP, 4358 "arm: address mismatch breakpoint types not implemented"); 4359 return; 4360 case 0: /* unlinked address match */ 4361 case 1: /* linked address match */ 4362 { 4363 /* Bits [63:49] are hardwired to the value of bit [48]; that is, 4364 * we behave as if the register was sign extended. Bits [1:0] are 4365 * RES0. The BAS field is used to allow setting breakpoints on 16 4366 * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether 4367 * a bp will fire if the addresses covered by the bp and the addresses 4368 * covered by the insn overlap but the insn doesn't start at the 4369 * start of the bp address range. We choose to require the insn and 4370 * the bp to have the same address. The constraints on writing to 4371 * BAS enforced in dbgbcr_write mean we have only four cases: 4372 * 0b0000 => no breakpoint 4373 * 0b0011 => breakpoint on addr 4374 * 0b1100 => breakpoint on addr + 2 4375 * 0b1111 => breakpoint on addr 4376 * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c). 4377 */ 4378 int bas = extract64(bcr, 5, 4); 4379 addr = sextract64(bvr, 0, 49) & ~3ULL; 4380 if (bas == 0) { 4381 return; 4382 } 4383 if (bas == 0xc) { 4384 addr += 2; 4385 } 4386 break; 4387 } 4388 case 2: /* unlinked context ID match */ 4389 case 8: /* unlinked VMID match (reserved if no EL2) */ 4390 case 10: /* unlinked context ID and VMID match (reserved if no EL2) */ 4391 qemu_log_mask(LOG_UNIMP, 4392 "arm: unlinked context breakpoint types not implemented"); 4393 return; 4394 case 9: /* linked VMID match (reserved if no EL2) */ 4395 case 11: /* linked context ID and VMID match (reserved if no EL2) */ 4396 case 3: /* linked context ID match */ 4397 default: 4398 /* We must generate no events for Linked context matches (unless 4399 * they are linked to by some other bp/wp, which is handled in 4400 * updates for the linking bp/wp). We choose to also generate no events 4401 * for reserved values. 4402 */ 4403 return; 4404 } 4405 4406 cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]); 4407 } 4408 4409 void hw_breakpoint_update_all(ARMCPU *cpu) 4410 { 4411 int i; 4412 CPUARMState *env = &cpu->env; 4413 4414 /* Completely clear out existing QEMU breakpoints and our array, to 4415 * avoid possible stale entries following migration load. 4416 */ 4417 cpu_breakpoint_remove_all(CPU(cpu), BP_CPU); 4418 memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint)); 4419 4420 for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) { 4421 hw_breakpoint_update(cpu, i); 4422 } 4423 } 4424 4425 static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri, 4426 uint64_t value) 4427 { 4428 ARMCPU *cpu = arm_env_get_cpu(env); 4429 int i = ri->crm; 4430 4431 raw_write(env, ri, value); 4432 hw_breakpoint_update(cpu, i); 4433 } 4434 4435 static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, 4436 uint64_t value) 4437 { 4438 ARMCPU *cpu = arm_env_get_cpu(env); 4439 int i = ri->crm; 4440 4441 /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only 4442 * copy of BAS[0]. 4443 */ 4444 value = deposit64(value, 6, 1, extract64(value, 5, 1)); 4445 value = deposit64(value, 8, 1, extract64(value, 7, 1)); 4446 4447 raw_write(env, ri, value); 4448 hw_breakpoint_update(cpu, i); 4449 } 4450 4451 static void define_debug_regs(ARMCPU *cpu) 4452 { 4453 /* Define v7 and v8 architectural debug registers. 4454 * These are just dummy implementations for now. 4455 */ 4456 int i; 4457 int wrps, brps, ctx_cmps; 4458 ARMCPRegInfo dbgdidr = { 4459 .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, 4460 .access = PL0_R, .accessfn = access_tda, 4461 .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr, 4462 }; 4463 4464 /* Note that all these register fields hold "number of Xs minus 1". */ 4465 brps = extract32(cpu->dbgdidr, 24, 4); 4466 wrps = extract32(cpu->dbgdidr, 28, 4); 4467 ctx_cmps = extract32(cpu->dbgdidr, 20, 4); 4468 4469 assert(ctx_cmps <= brps); 4470 4471 /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties 4472 * of the debug registers such as number of breakpoints; 4473 * check that if they both exist then they agree. 4474 */ 4475 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 4476 assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps); 4477 assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps); 4478 assert(extract32(cpu->id_aa64dfr0, 28, 4) == ctx_cmps); 4479 } 4480 4481 define_one_arm_cp_reg(cpu, &dbgdidr); 4482 define_arm_cp_regs(cpu, debug_cp_reginfo); 4483 4484 if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) { 4485 define_arm_cp_regs(cpu, debug_lpae_cp_reginfo); 4486 } 4487 4488 for (i = 0; i < brps + 1; i++) { 4489 ARMCPRegInfo dbgregs[] = { 4490 { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH, 4491 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4, 4492 .access = PL1_RW, .accessfn = access_tda, 4493 .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]), 4494 .writefn = dbgbvr_write, .raw_writefn = raw_write 4495 }, 4496 { .name = "DBGBCR", .state = ARM_CP_STATE_BOTH, 4497 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5, 4498 .access = PL1_RW, .accessfn = access_tda, 4499 .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]), 4500 .writefn = dbgbcr_write, .raw_writefn = raw_write 4501 }, 4502 REGINFO_SENTINEL 4503 }; 4504 define_arm_cp_regs(cpu, dbgregs); 4505 } 4506 4507 for (i = 0; i < wrps + 1; i++) { 4508 ARMCPRegInfo dbgregs[] = { 4509 { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH, 4510 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6, 4511 .access = PL1_RW, .accessfn = access_tda, 4512 .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]), 4513 .writefn = dbgwvr_write, .raw_writefn = raw_write 4514 }, 4515 { .name = "DBGWCR", .state = ARM_CP_STATE_BOTH, 4516 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7, 4517 .access = PL1_RW, .accessfn = access_tda, 4518 .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]), 4519 .writefn = dbgwcr_write, .raw_writefn = raw_write 4520 }, 4521 REGINFO_SENTINEL 4522 }; 4523 define_arm_cp_regs(cpu, dbgregs); 4524 } 4525 } 4526 4527 void register_cp_regs_for_features(ARMCPU *cpu) 4528 { 4529 /* Register all the coprocessor registers based on feature bits */ 4530 CPUARMState *env = &cpu->env; 4531 if (arm_feature(env, ARM_FEATURE_M)) { 4532 /* M profile has no coprocessor registers */ 4533 return; 4534 } 4535 4536 define_arm_cp_regs(cpu, cp_reginfo); 4537 if (!arm_feature(env, ARM_FEATURE_V8)) { 4538 /* Must go early as it is full of wildcards that may be 4539 * overridden by later definitions. 4540 */ 4541 define_arm_cp_regs(cpu, not_v8_cp_reginfo); 4542 } 4543 4544 if (arm_feature(env, ARM_FEATURE_V6)) { 4545 /* The ID registers all have impdef reset values */ 4546 ARMCPRegInfo v6_idregs[] = { 4547 { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH, 4548 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, 4549 .access = PL1_R, .type = ARM_CP_CONST, 4550 .resetvalue = cpu->id_pfr0 }, 4551 { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH, 4552 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1, 4553 .access = PL1_R, .type = ARM_CP_CONST, 4554 .resetvalue = cpu->id_pfr1 }, 4555 { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH, 4556 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2, 4557 .access = PL1_R, .type = ARM_CP_CONST, 4558 .resetvalue = cpu->id_dfr0 }, 4559 { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH, 4560 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3, 4561 .access = PL1_R, .type = ARM_CP_CONST, 4562 .resetvalue = cpu->id_afr0 }, 4563 { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH, 4564 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4, 4565 .access = PL1_R, .type = ARM_CP_CONST, 4566 .resetvalue = cpu->id_mmfr0 }, 4567 { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH, 4568 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5, 4569 .access = PL1_R, .type = ARM_CP_CONST, 4570 .resetvalue = cpu->id_mmfr1 }, 4571 { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH, 4572 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6, 4573 .access = PL1_R, .type = ARM_CP_CONST, 4574 .resetvalue = cpu->id_mmfr2 }, 4575 { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH, 4576 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7, 4577 .access = PL1_R, .type = ARM_CP_CONST, 4578 .resetvalue = cpu->id_mmfr3 }, 4579 { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH, 4580 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, 4581 .access = PL1_R, .type = ARM_CP_CONST, 4582 .resetvalue = cpu->id_isar0 }, 4583 { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH, 4584 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1, 4585 .access = PL1_R, .type = ARM_CP_CONST, 4586 .resetvalue = cpu->id_isar1 }, 4587 { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH, 4588 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, 4589 .access = PL1_R, .type = ARM_CP_CONST, 4590 .resetvalue = cpu->id_isar2 }, 4591 { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH, 4592 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3, 4593 .access = PL1_R, .type = ARM_CP_CONST, 4594 .resetvalue = cpu->id_isar3 }, 4595 { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH, 4596 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4, 4597 .access = PL1_R, .type = ARM_CP_CONST, 4598 .resetvalue = cpu->id_isar4 }, 4599 { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH, 4600 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5, 4601 .access = PL1_R, .type = ARM_CP_CONST, 4602 .resetvalue = cpu->id_isar5 }, 4603 { .name = "ID_MMFR4", .state = ARM_CP_STATE_BOTH, 4604 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6, 4605 .access = PL1_R, .type = ARM_CP_CONST, 4606 .resetvalue = cpu->id_mmfr4 }, 4607 /* 7 is as yet unallocated and must RAZ */ 4608 { .name = "ID_ISAR7_RESERVED", .state = ARM_CP_STATE_BOTH, 4609 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7, 4610 .access = PL1_R, .type = ARM_CP_CONST, 4611 .resetvalue = 0 }, 4612 REGINFO_SENTINEL 4613 }; 4614 define_arm_cp_regs(cpu, v6_idregs); 4615 define_arm_cp_regs(cpu, v6_cp_reginfo); 4616 } else { 4617 define_arm_cp_regs(cpu, not_v6_cp_reginfo); 4618 } 4619 if (arm_feature(env, ARM_FEATURE_V6K)) { 4620 define_arm_cp_regs(cpu, v6k_cp_reginfo); 4621 } 4622 if (arm_feature(env, ARM_FEATURE_V7MP) && 4623 !arm_feature(env, ARM_FEATURE_PMSA)) { 4624 define_arm_cp_regs(cpu, v7mp_cp_reginfo); 4625 } 4626 if (arm_feature(env, ARM_FEATURE_V7)) { 4627 /* v7 performance monitor control register: same implementor 4628 * field as main ID register, and we implement only the cycle 4629 * count register. 4630 */ 4631 #ifndef CONFIG_USER_ONLY 4632 ARMCPRegInfo pmcr = { 4633 .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0, 4634 .access = PL0_RW, 4635 .type = ARM_CP_IO | ARM_CP_ALIAS, 4636 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr), 4637 .accessfn = pmreg_access, .writefn = pmcr_write, 4638 .raw_writefn = raw_write, 4639 }; 4640 ARMCPRegInfo pmcr64 = { 4641 .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64, 4642 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0, 4643 .access = PL0_RW, .accessfn = pmreg_access, 4644 .type = ARM_CP_IO, 4645 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr), 4646 .resetvalue = cpu->midr & 0xff000000, 4647 .writefn = pmcr_write, .raw_writefn = raw_write, 4648 }; 4649 define_one_arm_cp_reg(cpu, &pmcr); 4650 define_one_arm_cp_reg(cpu, &pmcr64); 4651 #endif 4652 ARMCPRegInfo clidr = { 4653 .name = "CLIDR", .state = ARM_CP_STATE_BOTH, 4654 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1, 4655 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr 4656 }; 4657 define_one_arm_cp_reg(cpu, &clidr); 4658 define_arm_cp_regs(cpu, v7_cp_reginfo); 4659 define_debug_regs(cpu); 4660 } else { 4661 define_arm_cp_regs(cpu, not_v7_cp_reginfo); 4662 } 4663 if (arm_feature(env, ARM_FEATURE_V8)) { 4664 /* AArch64 ID registers, which all have impdef reset values. 4665 * Note that within the ID register ranges the unused slots 4666 * must all RAZ, not UNDEF; future architecture versions may 4667 * define new registers here. 4668 */ 4669 ARMCPRegInfo v8_idregs[] = { 4670 { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64, 4671 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0, 4672 .access = PL1_R, .type = ARM_CP_CONST, 4673 .resetvalue = cpu->id_aa64pfr0 }, 4674 { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64, 4675 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1, 4676 .access = PL1_R, .type = ARM_CP_CONST, 4677 .resetvalue = cpu->id_aa64pfr1}, 4678 { .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4679 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2, 4680 .access = PL1_R, .type = ARM_CP_CONST, 4681 .resetvalue = 0 }, 4682 { .name = "ID_AA64PFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4683 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3, 4684 .access = PL1_R, .type = ARM_CP_CONST, 4685 .resetvalue = 0 }, 4686 { .name = "ID_AA64PFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4687 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4, 4688 .access = PL1_R, .type = ARM_CP_CONST, 4689 .resetvalue = 0 }, 4690 { .name = "ID_AA64PFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4691 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5, 4692 .access = PL1_R, .type = ARM_CP_CONST, 4693 .resetvalue = 0 }, 4694 { .name = "ID_AA64PFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4695 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6, 4696 .access = PL1_R, .type = ARM_CP_CONST, 4697 .resetvalue = 0 }, 4698 { .name = "ID_AA64PFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4699 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 7, 4700 .access = PL1_R, .type = ARM_CP_CONST, 4701 .resetvalue = 0 }, 4702 { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64, 4703 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0, 4704 .access = PL1_R, .type = ARM_CP_CONST, 4705 .resetvalue = cpu->id_aa64dfr0 }, 4706 { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64, 4707 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1, 4708 .access = PL1_R, .type = ARM_CP_CONST, 4709 .resetvalue = cpu->id_aa64dfr1 }, 4710 { .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4711 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2, 4712 .access = PL1_R, .type = ARM_CP_CONST, 4713 .resetvalue = 0 }, 4714 { .name = "ID_AA64DFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4715 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 3, 4716 .access = PL1_R, .type = ARM_CP_CONST, 4717 .resetvalue = 0 }, 4718 { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64, 4719 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4, 4720 .access = PL1_R, .type = ARM_CP_CONST, 4721 .resetvalue = cpu->id_aa64afr0 }, 4722 { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64, 4723 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5, 4724 .access = PL1_R, .type = ARM_CP_CONST, 4725 .resetvalue = cpu->id_aa64afr1 }, 4726 { .name = "ID_AA64AFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4727 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 6, 4728 .access = PL1_R, .type = ARM_CP_CONST, 4729 .resetvalue = 0 }, 4730 { .name = "ID_AA64AFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4731 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 7, 4732 .access = PL1_R, .type = ARM_CP_CONST, 4733 .resetvalue = 0 }, 4734 { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64, 4735 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0, 4736 .access = PL1_R, .type = ARM_CP_CONST, 4737 .resetvalue = cpu->id_aa64isar0 }, 4738 { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64, 4739 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1, 4740 .access = PL1_R, .type = ARM_CP_CONST, 4741 .resetvalue = cpu->id_aa64isar1 }, 4742 { .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4743 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2, 4744 .access = PL1_R, .type = ARM_CP_CONST, 4745 .resetvalue = 0 }, 4746 { .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4747 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3, 4748 .access = PL1_R, .type = ARM_CP_CONST, 4749 .resetvalue = 0 }, 4750 { .name = "ID_AA64ISAR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4751 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 4, 4752 .access = PL1_R, .type = ARM_CP_CONST, 4753 .resetvalue = 0 }, 4754 { .name = "ID_AA64ISAR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4755 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 5, 4756 .access = PL1_R, .type = ARM_CP_CONST, 4757 .resetvalue = 0 }, 4758 { .name = "ID_AA64ISAR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4759 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 6, 4760 .access = PL1_R, .type = ARM_CP_CONST, 4761 .resetvalue = 0 }, 4762 { .name = "ID_AA64ISAR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4763 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 7, 4764 .access = PL1_R, .type = ARM_CP_CONST, 4765 .resetvalue = 0 }, 4766 { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64, 4767 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, 4768 .access = PL1_R, .type = ARM_CP_CONST, 4769 .resetvalue = cpu->id_aa64mmfr0 }, 4770 { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64, 4771 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1, 4772 .access = PL1_R, .type = ARM_CP_CONST, 4773 .resetvalue = cpu->id_aa64mmfr1 }, 4774 { .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4775 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2, 4776 .access = PL1_R, .type = ARM_CP_CONST, 4777 .resetvalue = 0 }, 4778 { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4779 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3, 4780 .access = PL1_R, .type = ARM_CP_CONST, 4781 .resetvalue = 0 }, 4782 { .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4783 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4, 4784 .access = PL1_R, .type = ARM_CP_CONST, 4785 .resetvalue = 0 }, 4786 { .name = "ID_AA64MMFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4787 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5, 4788 .access = PL1_R, .type = ARM_CP_CONST, 4789 .resetvalue = 0 }, 4790 { .name = "ID_AA64MMFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4791 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 6, 4792 .access = PL1_R, .type = ARM_CP_CONST, 4793 .resetvalue = 0 }, 4794 { .name = "ID_AA64MMFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4795 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 7, 4796 .access = PL1_R, .type = ARM_CP_CONST, 4797 .resetvalue = 0 }, 4798 { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64, 4799 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0, 4800 .access = PL1_R, .type = ARM_CP_CONST, 4801 .resetvalue = cpu->mvfr0 }, 4802 { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64, 4803 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1, 4804 .access = PL1_R, .type = ARM_CP_CONST, 4805 .resetvalue = cpu->mvfr1 }, 4806 { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64, 4807 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2, 4808 .access = PL1_R, .type = ARM_CP_CONST, 4809 .resetvalue = cpu->mvfr2 }, 4810 { .name = "MVFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4811 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3, 4812 .access = PL1_R, .type = ARM_CP_CONST, 4813 .resetvalue = 0 }, 4814 { .name = "MVFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4815 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4, 4816 .access = PL1_R, .type = ARM_CP_CONST, 4817 .resetvalue = 0 }, 4818 { .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4819 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5, 4820 .access = PL1_R, .type = ARM_CP_CONST, 4821 .resetvalue = 0 }, 4822 { .name = "MVFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4823 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6, 4824 .access = PL1_R, .type = ARM_CP_CONST, 4825 .resetvalue = 0 }, 4826 { .name = "MVFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4827 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7, 4828 .access = PL1_R, .type = ARM_CP_CONST, 4829 .resetvalue = 0 }, 4830 { .name = "PMCEID0", .state = ARM_CP_STATE_AA32, 4831 .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6, 4832 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, 4833 .resetvalue = cpu->pmceid0 }, 4834 { .name = "PMCEID0_EL0", .state = ARM_CP_STATE_AA64, 4835 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 6, 4836 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, 4837 .resetvalue = cpu->pmceid0 }, 4838 { .name = "PMCEID1", .state = ARM_CP_STATE_AA32, 4839 .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 7, 4840 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, 4841 .resetvalue = cpu->pmceid1 }, 4842 { .name = "PMCEID1_EL0", .state = ARM_CP_STATE_AA64, 4843 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7, 4844 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, 4845 .resetvalue = cpu->pmceid1 }, 4846 REGINFO_SENTINEL 4847 }; 4848 /* RVBAR_EL1 is only implemented if EL1 is the highest EL */ 4849 if (!arm_feature(env, ARM_FEATURE_EL3) && 4850 !arm_feature(env, ARM_FEATURE_EL2)) { 4851 ARMCPRegInfo rvbar = { 4852 .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64, 4853 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, 4854 .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar 4855 }; 4856 define_one_arm_cp_reg(cpu, &rvbar); 4857 } 4858 define_arm_cp_regs(cpu, v8_idregs); 4859 define_arm_cp_regs(cpu, v8_cp_reginfo); 4860 } 4861 if (arm_feature(env, ARM_FEATURE_EL2)) { 4862 uint64_t vmpidr_def = mpidr_read_val(env); 4863 ARMCPRegInfo vpidr_regs[] = { 4864 { .name = "VPIDR", .state = ARM_CP_STATE_AA32, 4865 .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, 4866 .access = PL2_RW, .accessfn = access_el3_aa32ns, 4867 .resetvalue = cpu->midr, 4868 .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, 4869 { .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64, 4870 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, 4871 .access = PL2_RW, .resetvalue = cpu->midr, 4872 .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, 4873 { .name = "VMPIDR", .state = ARM_CP_STATE_AA32, 4874 .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, 4875 .access = PL2_RW, .accessfn = access_el3_aa32ns, 4876 .resetvalue = vmpidr_def, 4877 .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) }, 4878 { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64, 4879 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, 4880 .access = PL2_RW, 4881 .resetvalue = vmpidr_def, 4882 .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) }, 4883 REGINFO_SENTINEL 4884 }; 4885 define_arm_cp_regs(cpu, vpidr_regs); 4886 define_arm_cp_regs(cpu, el2_cp_reginfo); 4887 /* RVBAR_EL2 is only implemented if EL2 is the highest EL */ 4888 if (!arm_feature(env, ARM_FEATURE_EL3)) { 4889 ARMCPRegInfo rvbar = { 4890 .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64, 4891 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1, 4892 .type = ARM_CP_CONST, .access = PL2_R, .resetvalue = cpu->rvbar 4893 }; 4894 define_one_arm_cp_reg(cpu, &rvbar); 4895 } 4896 } else { 4897 /* If EL2 is missing but higher ELs are enabled, we need to 4898 * register the no_el2 reginfos. 4899 */ 4900 if (arm_feature(env, ARM_FEATURE_EL3)) { 4901 /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value 4902 * of MIDR_EL1 and MPIDR_EL1. 4903 */ 4904 ARMCPRegInfo vpidr_regs[] = { 4905 { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH, 4906 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, 4907 .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, 4908 .type = ARM_CP_CONST, .resetvalue = cpu->midr, 4909 .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, 4910 { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH, 4911 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, 4912 .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, 4913 .type = ARM_CP_NO_RAW, 4914 .writefn = arm_cp_write_ignore, .readfn = mpidr_read }, 4915 REGINFO_SENTINEL 4916 }; 4917 define_arm_cp_regs(cpu, vpidr_regs); 4918 define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo); 4919 } 4920 } 4921 if (arm_feature(env, ARM_FEATURE_EL3)) { 4922 define_arm_cp_regs(cpu, el3_cp_reginfo); 4923 ARMCPRegInfo el3_regs[] = { 4924 { .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64, 4925 .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1, 4926 .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar }, 4927 { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64, 4928 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0, 4929 .access = PL3_RW, 4930 .raw_writefn = raw_write, .writefn = sctlr_write, 4931 .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]), 4932 .resetvalue = cpu->reset_sctlr }, 4933 REGINFO_SENTINEL 4934 }; 4935 4936 define_arm_cp_regs(cpu, el3_regs); 4937 } 4938 /* The behaviour of NSACR is sufficiently various that we don't 4939 * try to describe it in a single reginfo: 4940 * if EL3 is 64 bit, then trap to EL3 from S EL1, 4941 * reads as constant 0xc00 from NS EL1 and NS EL2 4942 * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2 4943 * if v7 without EL3, register doesn't exist 4944 * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2 4945 */ 4946 if (arm_feature(env, ARM_FEATURE_EL3)) { 4947 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 4948 ARMCPRegInfo nsacr = { 4949 .name = "NSACR", .type = ARM_CP_CONST, 4950 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, 4951 .access = PL1_RW, .accessfn = nsacr_access, 4952 .resetvalue = 0xc00 4953 }; 4954 define_one_arm_cp_reg(cpu, &nsacr); 4955 } else { 4956 ARMCPRegInfo nsacr = { 4957 .name = "NSACR", 4958 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, 4959 .access = PL3_RW | PL1_R, 4960 .resetvalue = 0, 4961 .fieldoffset = offsetof(CPUARMState, cp15.nsacr) 4962 }; 4963 define_one_arm_cp_reg(cpu, &nsacr); 4964 } 4965 } else { 4966 if (arm_feature(env, ARM_FEATURE_V8)) { 4967 ARMCPRegInfo nsacr = { 4968 .name = "NSACR", .type = ARM_CP_CONST, 4969 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, 4970 .access = PL1_R, 4971 .resetvalue = 0xc00 4972 }; 4973 define_one_arm_cp_reg(cpu, &nsacr); 4974 } 4975 } 4976 4977 if (arm_feature(env, ARM_FEATURE_PMSA)) { 4978 if (arm_feature(env, ARM_FEATURE_V6)) { 4979 /* PMSAv6 not implemented */ 4980 assert(arm_feature(env, ARM_FEATURE_V7)); 4981 define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); 4982 define_arm_cp_regs(cpu, pmsav7_cp_reginfo); 4983 } else { 4984 define_arm_cp_regs(cpu, pmsav5_cp_reginfo); 4985 } 4986 } else { 4987 define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); 4988 define_arm_cp_regs(cpu, vmsa_cp_reginfo); 4989 } 4990 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { 4991 define_arm_cp_regs(cpu, t2ee_cp_reginfo); 4992 } 4993 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { 4994 define_arm_cp_regs(cpu, generic_timer_cp_reginfo); 4995 } 4996 if (arm_feature(env, ARM_FEATURE_VAPA)) { 4997 define_arm_cp_regs(cpu, vapa_cp_reginfo); 4998 } 4999 if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) { 5000 define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo); 5001 } 5002 if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) { 5003 define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo); 5004 } 5005 if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) { 5006 define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo); 5007 } 5008 if (arm_feature(env, ARM_FEATURE_OMAPCP)) { 5009 define_arm_cp_regs(cpu, omap_cp_reginfo); 5010 } 5011 if (arm_feature(env, ARM_FEATURE_STRONGARM)) { 5012 define_arm_cp_regs(cpu, strongarm_cp_reginfo); 5013 } 5014 if (arm_feature(env, ARM_FEATURE_XSCALE)) { 5015 define_arm_cp_regs(cpu, xscale_cp_reginfo); 5016 } 5017 if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) { 5018 define_arm_cp_regs(cpu, dummy_c15_cp_reginfo); 5019 } 5020 if (arm_feature(env, ARM_FEATURE_LPAE)) { 5021 define_arm_cp_regs(cpu, lpae_cp_reginfo); 5022 } 5023 /* Slightly awkwardly, the OMAP and StrongARM cores need all of 5024 * cp15 crn=0 to be writes-ignored, whereas for other cores they should 5025 * be read-only (ie write causes UNDEF exception). 5026 */ 5027 { 5028 ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = { 5029 /* Pre-v8 MIDR space. 5030 * Note that the MIDR isn't a simple constant register because 5031 * of the TI925 behaviour where writes to another register can 5032 * cause the MIDR value to change. 5033 * 5034 * Unimplemented registers in the c15 0 0 0 space default to 5035 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR 5036 * and friends override accordingly. 5037 */ 5038 { .name = "MIDR", 5039 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY, 5040 .access = PL1_R, .resetvalue = cpu->midr, 5041 .writefn = arm_cp_write_ignore, .raw_writefn = raw_write, 5042 .readfn = midr_read, 5043 .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), 5044 .type = ARM_CP_OVERRIDE }, 5045 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */ 5046 { .name = "DUMMY", 5047 .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY, 5048 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 5049 { .name = "DUMMY", 5050 .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY, 5051 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 5052 { .name = "DUMMY", 5053 .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY, 5054 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 5055 { .name = "DUMMY", 5056 .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY, 5057 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 5058 { .name = "DUMMY", 5059 .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY, 5060 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 5061 REGINFO_SENTINEL 5062 }; 5063 ARMCPRegInfo id_v8_midr_cp_reginfo[] = { 5064 { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH, 5065 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0, 5066 .access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr, 5067 .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), 5068 .readfn = midr_read }, 5069 /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */ 5070 { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST, 5071 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4, 5072 .access = PL1_R, .resetvalue = cpu->midr }, 5073 { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST, 5074 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7, 5075 .access = PL1_R, .resetvalue = cpu->midr }, 5076 { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH, 5077 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6, 5078 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->revidr }, 5079 REGINFO_SENTINEL 5080 }; 5081 ARMCPRegInfo id_cp_reginfo[] = { 5082 /* These are common to v8 and pre-v8 */ 5083 { .name = "CTR", 5084 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1, 5085 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, 5086 { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64, 5087 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0, 5088 .access = PL0_R, .accessfn = ctr_el0_access, 5089 .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, 5090 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */ 5091 { .name = "TCMTR", 5092 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2, 5093 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 5094 REGINFO_SENTINEL 5095 }; 5096 /* TLBTR is specific to VMSA */ 5097 ARMCPRegInfo id_tlbtr_reginfo = { 5098 .name = "TLBTR", 5099 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3, 5100 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0, 5101 }; 5102 /* MPUIR is specific to PMSA V6+ */ 5103 ARMCPRegInfo id_mpuir_reginfo = { 5104 .name = "MPUIR", 5105 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4, 5106 .access = PL1_R, .type = ARM_CP_CONST, 5107 .resetvalue = cpu->pmsav7_dregion << 8 5108 }; 5109 ARMCPRegInfo crn0_wi_reginfo = { 5110 .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY, 5111 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W, 5112 .type = ARM_CP_NOP | ARM_CP_OVERRIDE 5113 }; 5114 if (arm_feature(env, ARM_FEATURE_OMAPCP) || 5115 arm_feature(env, ARM_FEATURE_STRONGARM)) { 5116 ARMCPRegInfo *r; 5117 /* Register the blanket "writes ignored" value first to cover the 5118 * whole space. Then update the specific ID registers to allow write 5119 * access, so that they ignore writes rather than causing them to 5120 * UNDEF. 5121 */ 5122 define_one_arm_cp_reg(cpu, &crn0_wi_reginfo); 5123 for (r = id_pre_v8_midr_cp_reginfo; 5124 r->type != ARM_CP_SENTINEL; r++) { 5125 r->access = PL1_RW; 5126 } 5127 for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) { 5128 r->access = PL1_RW; 5129 } 5130 id_tlbtr_reginfo.access = PL1_RW; 5131 id_tlbtr_reginfo.access = PL1_RW; 5132 } 5133 if (arm_feature(env, ARM_FEATURE_V8)) { 5134 define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo); 5135 } else { 5136 define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo); 5137 } 5138 define_arm_cp_regs(cpu, id_cp_reginfo); 5139 if (!arm_feature(env, ARM_FEATURE_PMSA)) { 5140 define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo); 5141 } else if (arm_feature(env, ARM_FEATURE_V7)) { 5142 define_one_arm_cp_reg(cpu, &id_mpuir_reginfo); 5143 } 5144 } 5145 5146 if (arm_feature(env, ARM_FEATURE_MPIDR)) { 5147 define_arm_cp_regs(cpu, mpidr_cp_reginfo); 5148 } 5149 5150 if (arm_feature(env, ARM_FEATURE_AUXCR)) { 5151 ARMCPRegInfo auxcr_reginfo[] = { 5152 { .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH, 5153 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1, 5154 .access = PL1_RW, .type = ARM_CP_CONST, 5155 .resetvalue = cpu->reset_auxcr }, 5156 { .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH, 5157 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1, 5158 .access = PL2_RW, .type = ARM_CP_CONST, 5159 .resetvalue = 0 }, 5160 { .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64, 5161 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1, 5162 .access = PL3_RW, .type = ARM_CP_CONST, 5163 .resetvalue = 0 }, 5164 REGINFO_SENTINEL 5165 }; 5166 define_arm_cp_regs(cpu, auxcr_reginfo); 5167 } 5168 5169 if (arm_feature(env, ARM_FEATURE_CBAR)) { 5170 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 5171 /* 32 bit view is [31:18] 0...0 [43:32]. */ 5172 uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18) 5173 | extract64(cpu->reset_cbar, 32, 12); 5174 ARMCPRegInfo cbar_reginfo[] = { 5175 { .name = "CBAR", 5176 .type = ARM_CP_CONST, 5177 .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0, 5178 .access = PL1_R, .resetvalue = cpu->reset_cbar }, 5179 { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64, 5180 .type = ARM_CP_CONST, 5181 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0, 5182 .access = PL1_R, .resetvalue = cbar32 }, 5183 REGINFO_SENTINEL 5184 }; 5185 /* We don't implement a r/w 64 bit CBAR currently */ 5186 assert(arm_feature(env, ARM_FEATURE_CBAR_RO)); 5187 define_arm_cp_regs(cpu, cbar_reginfo); 5188 } else { 5189 ARMCPRegInfo cbar = { 5190 .name = "CBAR", 5191 .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0, 5192 .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar, 5193 .fieldoffset = offsetof(CPUARMState, 5194 cp15.c15_config_base_address) 5195 }; 5196 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 5197 cbar.access = PL1_R; 5198 cbar.fieldoffset = 0; 5199 cbar.type = ARM_CP_CONST; 5200 } 5201 define_one_arm_cp_reg(cpu, &cbar); 5202 } 5203 } 5204 5205 if (arm_feature(env, ARM_FEATURE_VBAR)) { 5206 ARMCPRegInfo vbar_cp_reginfo[] = { 5207 { .name = "VBAR", .state = ARM_CP_STATE_BOTH, 5208 .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0, 5209 .access = PL1_RW, .writefn = vbar_write, 5210 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s), 5211 offsetof(CPUARMState, cp15.vbar_ns) }, 5212 .resetvalue = 0 }, 5213 REGINFO_SENTINEL 5214 }; 5215 define_arm_cp_regs(cpu, vbar_cp_reginfo); 5216 } 5217 5218 /* Generic registers whose values depend on the implementation */ 5219 { 5220 ARMCPRegInfo sctlr = { 5221 .name = "SCTLR", .state = ARM_CP_STATE_BOTH, 5222 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, 5223 .access = PL1_RW, 5224 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s), 5225 offsetof(CPUARMState, cp15.sctlr_ns) }, 5226 .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr, 5227 .raw_writefn = raw_write, 5228 }; 5229 if (arm_feature(env, ARM_FEATURE_XSCALE)) { 5230 /* Normally we would always end the TB on an SCTLR write, but Linux 5231 * arch/arm/mach-pxa/sleep.S expects two instructions following 5232 * an MMU enable to execute from cache. Imitate this behaviour. 5233 */ 5234 sctlr.type |= ARM_CP_SUPPRESS_TB_END; 5235 } 5236 define_one_arm_cp_reg(cpu, &sctlr); 5237 } 5238 } 5239 5240 ARMCPU *cpu_arm_init(const char *cpu_model) 5241 { 5242 return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model)); 5243 } 5244 5245 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) 5246 { 5247 CPUState *cs = CPU(cpu); 5248 CPUARMState *env = &cpu->env; 5249 5250 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 5251 gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg, 5252 aarch64_fpu_gdb_set_reg, 5253 34, "aarch64-fpu.xml", 0); 5254 } else if (arm_feature(env, ARM_FEATURE_NEON)) { 5255 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 5256 51, "arm-neon.xml", 0); 5257 } else if (arm_feature(env, ARM_FEATURE_VFP3)) { 5258 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 5259 35, "arm-vfp3.xml", 0); 5260 } else if (arm_feature(env, ARM_FEATURE_VFP)) { 5261 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 5262 19, "arm-vfp.xml", 0); 5263 } 5264 } 5265 5266 /* Sort alphabetically by type name, except for "any". */ 5267 static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b) 5268 { 5269 ObjectClass *class_a = (ObjectClass *)a; 5270 ObjectClass *class_b = (ObjectClass *)b; 5271 const char *name_a, *name_b; 5272 5273 name_a = object_class_get_name(class_a); 5274 name_b = object_class_get_name(class_b); 5275 if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) { 5276 return 1; 5277 } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) { 5278 return -1; 5279 } else { 5280 return strcmp(name_a, name_b); 5281 } 5282 } 5283 5284 static void arm_cpu_list_entry(gpointer data, gpointer user_data) 5285 { 5286 ObjectClass *oc = data; 5287 CPUListState *s = user_data; 5288 const char *typename; 5289 char *name; 5290 5291 typename = object_class_get_name(oc); 5292 name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU)); 5293 (*s->cpu_fprintf)(s->file, " %s\n", 5294 name); 5295 g_free(name); 5296 } 5297 5298 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf) 5299 { 5300 CPUListState s = { 5301 .file = f, 5302 .cpu_fprintf = cpu_fprintf, 5303 }; 5304 GSList *list; 5305 5306 list = object_class_get_list(TYPE_ARM_CPU, false); 5307 list = g_slist_sort(list, arm_cpu_list_compare); 5308 (*cpu_fprintf)(f, "Available CPUs:\n"); 5309 g_slist_foreach(list, arm_cpu_list_entry, &s); 5310 g_slist_free(list); 5311 #ifdef CONFIG_KVM 5312 /* The 'host' CPU type is dynamically registered only if KVM is 5313 * enabled, so we have to special-case it here: 5314 */ 5315 (*cpu_fprintf)(f, " host (only available in KVM mode)\n"); 5316 #endif 5317 } 5318 5319 static void arm_cpu_add_definition(gpointer data, gpointer user_data) 5320 { 5321 ObjectClass *oc = data; 5322 CpuDefinitionInfoList **cpu_list = user_data; 5323 CpuDefinitionInfoList *entry; 5324 CpuDefinitionInfo *info; 5325 const char *typename; 5326 5327 typename = object_class_get_name(oc); 5328 info = g_malloc0(sizeof(*info)); 5329 info->name = g_strndup(typename, 5330 strlen(typename) - strlen("-" TYPE_ARM_CPU)); 5331 info->q_typename = g_strdup(typename); 5332 5333 entry = g_malloc0(sizeof(*entry)); 5334 entry->value = info; 5335 entry->next = *cpu_list; 5336 *cpu_list = entry; 5337 } 5338 5339 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp) 5340 { 5341 CpuDefinitionInfoList *cpu_list = NULL; 5342 GSList *list; 5343 5344 list = object_class_get_list(TYPE_ARM_CPU, false); 5345 g_slist_foreach(list, arm_cpu_add_definition, &cpu_list); 5346 g_slist_free(list); 5347 5348 return cpu_list; 5349 } 5350 5351 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, 5352 void *opaque, int state, int secstate, 5353 int crm, int opc1, int opc2) 5354 { 5355 /* Private utility function for define_one_arm_cp_reg_with_opaque(): 5356 * add a single reginfo struct to the hash table. 5357 */ 5358 uint32_t *key = g_new(uint32_t, 1); 5359 ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo)); 5360 int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0; 5361 int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; 5362 5363 /* Reset the secure state to the specific incoming state. This is 5364 * necessary as the register may have been defined with both states. 5365 */ 5366 r2->secure = secstate; 5367 5368 if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { 5369 /* Register is banked (using both entries in array). 5370 * Overwriting fieldoffset as the array is only used to define 5371 * banked registers but later only fieldoffset is used. 5372 */ 5373 r2->fieldoffset = r->bank_fieldoffsets[ns]; 5374 } 5375 5376 if (state == ARM_CP_STATE_AA32) { 5377 if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { 5378 /* If the register is banked then we don't need to migrate or 5379 * reset the 32-bit instance in certain cases: 5380 * 5381 * 1) If the register has both 32-bit and 64-bit instances then we 5382 * can count on the 64-bit instance taking care of the 5383 * non-secure bank. 5384 * 2) If ARMv8 is enabled then we can count on a 64-bit version 5385 * taking care of the secure bank. This requires that separate 5386 * 32 and 64-bit definitions are provided. 5387 */ 5388 if ((r->state == ARM_CP_STATE_BOTH && ns) || 5389 (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) { 5390 r2->type |= ARM_CP_ALIAS; 5391 } 5392 } else if ((secstate != r->secure) && !ns) { 5393 /* The register is not banked so we only want to allow migration of 5394 * the non-secure instance. 5395 */ 5396 r2->type |= ARM_CP_ALIAS; 5397 } 5398 5399 if (r->state == ARM_CP_STATE_BOTH) { 5400 /* We assume it is a cp15 register if the .cp field is left unset. 5401 */ 5402 if (r2->cp == 0) { 5403 r2->cp = 15; 5404 } 5405 5406 #ifdef HOST_WORDS_BIGENDIAN 5407 if (r2->fieldoffset) { 5408 r2->fieldoffset += sizeof(uint32_t); 5409 } 5410 #endif 5411 } 5412 } 5413 if (state == ARM_CP_STATE_AA64) { 5414 /* To allow abbreviation of ARMCPRegInfo 5415 * definitions, we treat cp == 0 as equivalent to 5416 * the value for "standard guest-visible sysreg". 5417 * STATE_BOTH definitions are also always "standard 5418 * sysreg" in their AArch64 view (the .cp value may 5419 * be non-zero for the benefit of the AArch32 view). 5420 */ 5421 if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) { 5422 r2->cp = CP_REG_ARM64_SYSREG_CP; 5423 } 5424 *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm, 5425 r2->opc0, opc1, opc2); 5426 } else { 5427 *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2); 5428 } 5429 if (opaque) { 5430 r2->opaque = opaque; 5431 } 5432 /* reginfo passed to helpers is correct for the actual access, 5433 * and is never ARM_CP_STATE_BOTH: 5434 */ 5435 r2->state = state; 5436 /* Make sure reginfo passed to helpers for wildcarded regs 5437 * has the correct crm/opc1/opc2 for this reg, not CP_ANY: 5438 */ 5439 r2->crm = crm; 5440 r2->opc1 = opc1; 5441 r2->opc2 = opc2; 5442 /* By convention, for wildcarded registers only the first 5443 * entry is used for migration; the others are marked as 5444 * ALIAS so we don't try to transfer the register 5445 * multiple times. Special registers (ie NOP/WFI) are 5446 * never migratable and not even raw-accessible. 5447 */ 5448 if ((r->type & ARM_CP_SPECIAL)) { 5449 r2->type |= ARM_CP_NO_RAW; 5450 } 5451 if (((r->crm == CP_ANY) && crm != 0) || 5452 ((r->opc1 == CP_ANY) && opc1 != 0) || 5453 ((r->opc2 == CP_ANY) && opc2 != 0)) { 5454 r2->type |= ARM_CP_ALIAS; 5455 } 5456 5457 /* Check that raw accesses are either forbidden or handled. Note that 5458 * we can't assert this earlier because the setup of fieldoffset for 5459 * banked registers has to be done first. 5460 */ 5461 if (!(r2->type & ARM_CP_NO_RAW)) { 5462 assert(!raw_accessors_invalid(r2)); 5463 } 5464 5465 /* Overriding of an existing definition must be explicitly 5466 * requested. 5467 */ 5468 if (!(r->type & ARM_CP_OVERRIDE)) { 5469 ARMCPRegInfo *oldreg; 5470 oldreg = g_hash_table_lookup(cpu->cp_regs, key); 5471 if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) { 5472 fprintf(stderr, "Register redefined: cp=%d %d bit " 5473 "crn=%d crm=%d opc1=%d opc2=%d, " 5474 "was %s, now %s\n", r2->cp, 32 + 32 * is64, 5475 r2->crn, r2->crm, r2->opc1, r2->opc2, 5476 oldreg->name, r2->name); 5477 g_assert_not_reached(); 5478 } 5479 } 5480 g_hash_table_insert(cpu->cp_regs, key, r2); 5481 } 5482 5483 5484 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, 5485 const ARMCPRegInfo *r, void *opaque) 5486 { 5487 /* Define implementations of coprocessor registers. 5488 * We store these in a hashtable because typically 5489 * there are less than 150 registers in a space which 5490 * is 16*16*16*8*8 = 262144 in size. 5491 * Wildcarding is supported for the crm, opc1 and opc2 fields. 5492 * If a register is defined twice then the second definition is 5493 * used, so this can be used to define some generic registers and 5494 * then override them with implementation specific variations. 5495 * At least one of the original and the second definition should 5496 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard 5497 * against accidental use. 5498 * 5499 * The state field defines whether the register is to be 5500 * visible in the AArch32 or AArch64 execution state. If the 5501 * state is set to ARM_CP_STATE_BOTH then we synthesise a 5502 * reginfo structure for the AArch32 view, which sees the lower 5503 * 32 bits of the 64 bit register. 5504 * 5505 * Only registers visible in AArch64 may set r->opc0; opc0 cannot 5506 * be wildcarded. AArch64 registers are always considered to be 64 5507 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of 5508 * the register, if any. 5509 */ 5510 int crm, opc1, opc2, state; 5511 int crmmin = (r->crm == CP_ANY) ? 0 : r->crm; 5512 int crmmax = (r->crm == CP_ANY) ? 15 : r->crm; 5513 int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1; 5514 int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1; 5515 int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2; 5516 int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2; 5517 /* 64 bit registers have only CRm and Opc1 fields */ 5518 assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn))); 5519 /* op0 only exists in the AArch64 encodings */ 5520 assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0)); 5521 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */ 5522 assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT)); 5523 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1 5524 * encodes a minimum access level for the register. We roll this 5525 * runtime check into our general permission check code, so check 5526 * here that the reginfo's specified permissions are strict enough 5527 * to encompass the generic architectural permission check. 5528 */ 5529 if (r->state != ARM_CP_STATE_AA32) { 5530 int mask = 0; 5531 switch (r->opc1) { 5532 case 0: case 1: case 2: 5533 /* min_EL EL1 */ 5534 mask = PL1_RW; 5535 break; 5536 case 3: 5537 /* min_EL EL0 */ 5538 mask = PL0_RW; 5539 break; 5540 case 4: 5541 /* min_EL EL2 */ 5542 mask = PL2_RW; 5543 break; 5544 case 5: 5545 /* unallocated encoding, so not possible */ 5546 assert(false); 5547 break; 5548 case 6: 5549 /* min_EL EL3 */ 5550 mask = PL3_RW; 5551 break; 5552 case 7: 5553 /* min_EL EL1, secure mode only (we don't check the latter) */ 5554 mask = PL1_RW; 5555 break; 5556 default: 5557 /* broken reginfo with out-of-range opc1 */ 5558 assert(false); 5559 break; 5560 } 5561 /* assert our permissions are not too lax (stricter is fine) */ 5562 assert((r->access & ~mask) == 0); 5563 } 5564 5565 /* Check that the register definition has enough info to handle 5566 * reads and writes if they are permitted. 5567 */ 5568 if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) { 5569 if (r->access & PL3_R) { 5570 assert((r->fieldoffset || 5571 (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || 5572 r->readfn); 5573 } 5574 if (r->access & PL3_W) { 5575 assert((r->fieldoffset || 5576 (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || 5577 r->writefn); 5578 } 5579 } 5580 /* Bad type field probably means missing sentinel at end of reg list */ 5581 assert(cptype_valid(r->type)); 5582 for (crm = crmmin; crm <= crmmax; crm++) { 5583 for (opc1 = opc1min; opc1 <= opc1max; opc1++) { 5584 for (opc2 = opc2min; opc2 <= opc2max; opc2++) { 5585 for (state = ARM_CP_STATE_AA32; 5586 state <= ARM_CP_STATE_AA64; state++) { 5587 if (r->state != state && r->state != ARM_CP_STATE_BOTH) { 5588 continue; 5589 } 5590 if (state == ARM_CP_STATE_AA32) { 5591 /* Under AArch32 CP registers can be common 5592 * (same for secure and non-secure world) or banked. 5593 */ 5594 switch (r->secure) { 5595 case ARM_CP_SECSTATE_S: 5596 case ARM_CP_SECSTATE_NS: 5597 add_cpreg_to_hashtable(cpu, r, opaque, state, 5598 r->secure, crm, opc1, opc2); 5599 break; 5600 default: 5601 add_cpreg_to_hashtable(cpu, r, opaque, state, 5602 ARM_CP_SECSTATE_S, 5603 crm, opc1, opc2); 5604 add_cpreg_to_hashtable(cpu, r, opaque, state, 5605 ARM_CP_SECSTATE_NS, 5606 crm, opc1, opc2); 5607 break; 5608 } 5609 } else { 5610 /* AArch64 registers get mapped to non-secure instance 5611 * of AArch32 */ 5612 add_cpreg_to_hashtable(cpu, r, opaque, state, 5613 ARM_CP_SECSTATE_NS, 5614 crm, opc1, opc2); 5615 } 5616 } 5617 } 5618 } 5619 } 5620 } 5621 5622 void define_arm_cp_regs_with_opaque(ARMCPU *cpu, 5623 const ARMCPRegInfo *regs, void *opaque) 5624 { 5625 /* Define a whole list of registers */ 5626 const ARMCPRegInfo *r; 5627 for (r = regs; r->type != ARM_CP_SENTINEL; r++) { 5628 define_one_arm_cp_reg_with_opaque(cpu, r, opaque); 5629 } 5630 } 5631 5632 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp) 5633 { 5634 return g_hash_table_lookup(cpregs, &encoded_cp); 5635 } 5636 5637 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, 5638 uint64_t value) 5639 { 5640 /* Helper coprocessor write function for write-ignore registers */ 5641 } 5642 5643 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri) 5644 { 5645 /* Helper coprocessor write function for read-as-zero registers */ 5646 return 0; 5647 } 5648 5649 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque) 5650 { 5651 /* Helper coprocessor reset function for do-nothing-on-reset registers */ 5652 } 5653 5654 static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type) 5655 { 5656 /* Return true if it is not valid for us to switch to 5657 * this CPU mode (ie all the UNPREDICTABLE cases in 5658 * the ARM ARM CPSRWriteByInstr pseudocode). 5659 */ 5660 5661 /* Changes to or from Hyp via MSR and CPS are illegal. */ 5662 if (write_type == CPSRWriteByInstr && 5663 ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_HYP || 5664 mode == ARM_CPU_MODE_HYP)) { 5665 return 1; 5666 } 5667 5668 switch (mode) { 5669 case ARM_CPU_MODE_USR: 5670 return 0; 5671 case ARM_CPU_MODE_SYS: 5672 case ARM_CPU_MODE_SVC: 5673 case ARM_CPU_MODE_ABT: 5674 case ARM_CPU_MODE_UND: 5675 case ARM_CPU_MODE_IRQ: 5676 case ARM_CPU_MODE_FIQ: 5677 /* Note that we don't implement the IMPDEF NSACR.RFR which in v7 5678 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.) 5679 */ 5680 /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR 5681 * and CPS are treated as illegal mode changes. 5682 */ 5683 if (write_type == CPSRWriteByInstr && 5684 (env->cp15.hcr_el2 & HCR_TGE) && 5685 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON && 5686 !arm_is_secure_below_el3(env)) { 5687 return 1; 5688 } 5689 return 0; 5690 case ARM_CPU_MODE_HYP: 5691 return !arm_feature(env, ARM_FEATURE_EL2) 5692 || arm_current_el(env) < 2 || arm_is_secure(env); 5693 case ARM_CPU_MODE_MON: 5694 return arm_current_el(env) < 3; 5695 default: 5696 return 1; 5697 } 5698 } 5699 5700 uint32_t cpsr_read(CPUARMState *env) 5701 { 5702 int ZF; 5703 ZF = (env->ZF == 0); 5704 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) | 5705 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 5706 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25) 5707 | ((env->condexec_bits & 0xfc) << 8) 5708 | (env->GE << 16) | (env->daif & CPSR_AIF); 5709 } 5710 5711 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 5712 CPSRWriteType write_type) 5713 { 5714 uint32_t changed_daif; 5715 5716 if (mask & CPSR_NZCV) { 5717 env->ZF = (~val) & CPSR_Z; 5718 env->NF = val; 5719 env->CF = (val >> 29) & 1; 5720 env->VF = (val << 3) & 0x80000000; 5721 } 5722 if (mask & CPSR_Q) 5723 env->QF = ((val & CPSR_Q) != 0); 5724 if (mask & CPSR_T) 5725 env->thumb = ((val & CPSR_T) != 0); 5726 if (mask & CPSR_IT_0_1) { 5727 env->condexec_bits &= ~3; 5728 env->condexec_bits |= (val >> 25) & 3; 5729 } 5730 if (mask & CPSR_IT_2_7) { 5731 env->condexec_bits &= 3; 5732 env->condexec_bits |= (val >> 8) & 0xfc; 5733 } 5734 if (mask & CPSR_GE) { 5735 env->GE = (val >> 16) & 0xf; 5736 } 5737 5738 /* In a V7 implementation that includes the security extensions but does 5739 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control 5740 * whether non-secure software is allowed to change the CPSR_F and CPSR_A 5741 * bits respectively. 5742 * 5743 * In a V8 implementation, it is permitted for privileged software to 5744 * change the CPSR A/F bits regardless of the SCR.AW/FW bits. 5745 */ 5746 if (write_type != CPSRWriteRaw && !arm_feature(env, ARM_FEATURE_V8) && 5747 arm_feature(env, ARM_FEATURE_EL3) && 5748 !arm_feature(env, ARM_FEATURE_EL2) && 5749 !arm_is_secure(env)) { 5750 5751 changed_daif = (env->daif ^ val) & mask; 5752 5753 if (changed_daif & CPSR_A) { 5754 /* Check to see if we are allowed to change the masking of async 5755 * abort exceptions from a non-secure state. 5756 */ 5757 if (!(env->cp15.scr_el3 & SCR_AW)) { 5758 qemu_log_mask(LOG_GUEST_ERROR, 5759 "Ignoring attempt to switch CPSR_A flag from " 5760 "non-secure world with SCR.AW bit clear\n"); 5761 mask &= ~CPSR_A; 5762 } 5763 } 5764 5765 if (changed_daif & CPSR_F) { 5766 /* Check to see if we are allowed to change the masking of FIQ 5767 * exceptions from a non-secure state. 5768 */ 5769 if (!(env->cp15.scr_el3 & SCR_FW)) { 5770 qemu_log_mask(LOG_GUEST_ERROR, 5771 "Ignoring attempt to switch CPSR_F flag from " 5772 "non-secure world with SCR.FW bit clear\n"); 5773 mask &= ~CPSR_F; 5774 } 5775 5776 /* Check whether non-maskable FIQ (NMFI) support is enabled. 5777 * If this bit is set software is not allowed to mask 5778 * FIQs, but is allowed to set CPSR_F to 0. 5779 */ 5780 if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) && 5781 (val & CPSR_F)) { 5782 qemu_log_mask(LOG_GUEST_ERROR, 5783 "Ignoring attempt to enable CPSR_F flag " 5784 "(non-maskable FIQ [NMFI] support enabled)\n"); 5785 mask &= ~CPSR_F; 5786 } 5787 } 5788 } 5789 5790 env->daif &= ~(CPSR_AIF & mask); 5791 env->daif |= val & CPSR_AIF & mask; 5792 5793 if (write_type != CPSRWriteRaw && 5794 ((env->uncached_cpsr ^ val) & mask & CPSR_M)) { 5795 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR) { 5796 /* Note that we can only get here in USR mode if this is a 5797 * gdb stub write; for this case we follow the architectural 5798 * behaviour for guest writes in USR mode of ignoring an attempt 5799 * to switch mode. (Those are caught by translate.c for writes 5800 * triggered by guest instructions.) 5801 */ 5802 mask &= ~CPSR_M; 5803 } else if (bad_mode_switch(env, val & CPSR_M, write_type)) { 5804 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in 5805 * v7, and has defined behaviour in v8: 5806 * + leave CPSR.M untouched 5807 * + allow changes to the other CPSR fields 5808 * + set PSTATE.IL 5809 * For user changes via the GDB stub, we don't set PSTATE.IL, 5810 * as this would be unnecessarily harsh for a user error. 5811 */ 5812 mask &= ~CPSR_M; 5813 if (write_type != CPSRWriteByGDBStub && 5814 arm_feature(env, ARM_FEATURE_V8)) { 5815 mask |= CPSR_IL; 5816 val |= CPSR_IL; 5817 } 5818 } else { 5819 switch_mode(env, val & CPSR_M); 5820 } 5821 } 5822 mask &= ~CACHED_CPSR_BITS; 5823 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask); 5824 } 5825 5826 /* Sign/zero extend */ 5827 uint32_t HELPER(sxtb16)(uint32_t x) 5828 { 5829 uint32_t res; 5830 res = (uint16_t)(int8_t)x; 5831 res |= (uint32_t)(int8_t)(x >> 16) << 16; 5832 return res; 5833 } 5834 5835 uint32_t HELPER(uxtb16)(uint32_t x) 5836 { 5837 uint32_t res; 5838 res = (uint16_t)(uint8_t)x; 5839 res |= (uint32_t)(uint8_t)(x >> 16) << 16; 5840 return res; 5841 } 5842 5843 int32_t HELPER(sdiv)(int32_t num, int32_t den) 5844 { 5845 if (den == 0) 5846 return 0; 5847 if (num == INT_MIN && den == -1) 5848 return INT_MIN; 5849 return num / den; 5850 } 5851 5852 uint32_t HELPER(udiv)(uint32_t num, uint32_t den) 5853 { 5854 if (den == 0) 5855 return 0; 5856 return num / den; 5857 } 5858 5859 uint32_t HELPER(rbit)(uint32_t x) 5860 { 5861 return revbit32(x); 5862 } 5863 5864 #if defined(CONFIG_USER_ONLY) 5865 5866 /* These should probably raise undefined insn exceptions. */ 5867 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) 5868 { 5869 ARMCPU *cpu = arm_env_get_cpu(env); 5870 5871 cpu_abort(CPU(cpu), "v7m_msr %d\n", reg); 5872 } 5873 5874 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) 5875 { 5876 ARMCPU *cpu = arm_env_get_cpu(env); 5877 5878 cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg); 5879 return 0; 5880 } 5881 5882 void switch_mode(CPUARMState *env, int mode) 5883 { 5884 ARMCPU *cpu = arm_env_get_cpu(env); 5885 5886 if (mode != ARM_CPU_MODE_USR) { 5887 cpu_abort(CPU(cpu), "Tried to switch out of user mode\n"); 5888 } 5889 } 5890 5891 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 5892 uint32_t cur_el, bool secure) 5893 { 5894 return 1; 5895 } 5896 5897 void aarch64_sync_64_to_32(CPUARMState *env) 5898 { 5899 g_assert_not_reached(); 5900 } 5901 5902 #else 5903 5904 void switch_mode(CPUARMState *env, int mode) 5905 { 5906 int old_mode; 5907 int i; 5908 5909 old_mode = env->uncached_cpsr & CPSR_M; 5910 if (mode == old_mode) 5911 return; 5912 5913 if (old_mode == ARM_CPU_MODE_FIQ) { 5914 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t)); 5915 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t)); 5916 } else if (mode == ARM_CPU_MODE_FIQ) { 5917 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t)); 5918 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t)); 5919 } 5920 5921 i = bank_number(old_mode); 5922 env->banked_r13[i] = env->regs[13]; 5923 env->banked_r14[i] = env->regs[14]; 5924 env->banked_spsr[i] = env->spsr; 5925 5926 i = bank_number(mode); 5927 env->regs[13] = env->banked_r13[i]; 5928 env->regs[14] = env->banked_r14[i]; 5929 env->spsr = env->banked_spsr[i]; 5930 } 5931 5932 /* Physical Interrupt Target EL Lookup Table 5933 * 5934 * [ From ARM ARM section G1.13.4 (Table G1-15) ] 5935 * 5936 * The below multi-dimensional table is used for looking up the target 5937 * exception level given numerous condition criteria. Specifically, the 5938 * target EL is based on SCR and HCR routing controls as well as the 5939 * currently executing EL and secure state. 5940 * 5941 * Dimensions: 5942 * target_el_table[2][2][2][2][2][4] 5943 * | | | | | +--- Current EL 5944 * | | | | +------ Non-secure(0)/Secure(1) 5945 * | | | +--------- HCR mask override 5946 * | | +------------ SCR exec state control 5947 * | +--------------- SCR mask override 5948 * +------------------ 32-bit(0)/64-bit(1) EL3 5949 * 5950 * The table values are as such: 5951 * 0-3 = EL0-EL3 5952 * -1 = Cannot occur 5953 * 5954 * The ARM ARM target EL table includes entries indicating that an "exception 5955 * is not taken". The two cases where this is applicable are: 5956 * 1) An exception is taken from EL3 but the SCR does not have the exception 5957 * routed to EL3. 5958 * 2) An exception is taken from EL2 but the HCR does not have the exception 5959 * routed to EL2. 5960 * In these two cases, the below table contain a target of EL1. This value is 5961 * returned as it is expected that the consumer of the table data will check 5962 * for "target EL >= current EL" to ensure the exception is not taken. 5963 * 5964 * SCR HCR 5965 * 64 EA AMO From 5966 * BIT IRQ IMO Non-secure Secure 5967 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3 5968 */ 5969 static const int8_t target_el_table[2][2][2][2][2][4] = { 5970 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },}, 5971 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},}, 5972 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },}, 5973 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},}, 5974 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },}, 5975 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},}, 5976 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },}, 5977 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},}, 5978 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },}, 5979 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},}, 5980 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, -1, 1 },}, 5981 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},}, 5982 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },}, 5983 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},}, 5984 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },}, 5985 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},},}, 5986 }; 5987 5988 /* 5989 * Determine the target EL for physical exceptions 5990 */ 5991 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 5992 uint32_t cur_el, bool secure) 5993 { 5994 CPUARMState *env = cs->env_ptr; 5995 int rw; 5996 int scr; 5997 int hcr; 5998 int target_el; 5999 /* Is the highest EL AArch64? */ 6000 int is64 = arm_feature(env, ARM_FEATURE_AARCH64); 6001 6002 if (arm_feature(env, ARM_FEATURE_EL3)) { 6003 rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW); 6004 } else { 6005 /* Either EL2 is the highest EL (and so the EL2 register width 6006 * is given by is64); or there is no EL2 or EL3, in which case 6007 * the value of 'rw' does not affect the table lookup anyway. 6008 */ 6009 rw = is64; 6010 } 6011 6012 switch (excp_idx) { 6013 case EXCP_IRQ: 6014 scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ); 6015 hcr = ((env->cp15.hcr_el2 & HCR_IMO) == HCR_IMO); 6016 break; 6017 case EXCP_FIQ: 6018 scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ); 6019 hcr = ((env->cp15.hcr_el2 & HCR_FMO) == HCR_FMO); 6020 break; 6021 default: 6022 scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA); 6023 hcr = ((env->cp15.hcr_el2 & HCR_AMO) == HCR_AMO); 6024 break; 6025 }; 6026 6027 /* If HCR.TGE is set then HCR is treated as being 1 */ 6028 hcr |= ((env->cp15.hcr_el2 & HCR_TGE) == HCR_TGE); 6029 6030 /* Perform a table-lookup for the target EL given the current state */ 6031 target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el]; 6032 6033 assert(target_el > 0); 6034 6035 return target_el; 6036 } 6037 6038 static void v7m_push(CPUARMState *env, uint32_t val) 6039 { 6040 CPUState *cs = CPU(arm_env_get_cpu(env)); 6041 6042 env->regs[13] -= 4; 6043 stl_phys(cs->as, env->regs[13], val); 6044 } 6045 6046 static uint32_t v7m_pop(CPUARMState *env) 6047 { 6048 CPUState *cs = CPU(arm_env_get_cpu(env)); 6049 uint32_t val; 6050 6051 val = ldl_phys(cs->as, env->regs[13]); 6052 env->regs[13] += 4; 6053 return val; 6054 } 6055 6056 /* Switch to V7M main or process stack pointer. */ 6057 static void switch_v7m_sp(CPUARMState *env, bool new_spsel) 6058 { 6059 uint32_t tmp; 6060 bool old_spsel = env->v7m.control & R_V7M_CONTROL_SPSEL_MASK; 6061 6062 if (old_spsel != new_spsel) { 6063 tmp = env->v7m.other_sp; 6064 env->v7m.other_sp = env->regs[13]; 6065 env->regs[13] = tmp; 6066 6067 env->v7m.control = deposit32(env->v7m.control, 6068 R_V7M_CONTROL_SPSEL_SHIFT, 6069 R_V7M_CONTROL_SPSEL_LENGTH, new_spsel); 6070 } 6071 } 6072 6073 static uint32_t arm_v7m_load_vector(ARMCPU *cpu) 6074 { 6075 CPUState *cs = CPU(cpu); 6076 CPUARMState *env = &cpu->env; 6077 MemTxResult result; 6078 hwaddr vec = env->v7m.vecbase + env->v7m.exception * 4; 6079 uint32_t addr; 6080 6081 addr = address_space_ldl(cs->as, vec, 6082 MEMTXATTRS_UNSPECIFIED, &result); 6083 if (result != MEMTX_OK) { 6084 /* Architecturally this should cause a HardFault setting HSFR.VECTTBL, 6085 * which would then be immediately followed by our failing to load 6086 * the entry vector for that HardFault, which is a Lockup case. 6087 * Since we don't model Lockup, we just report this guest error 6088 * via cpu_abort(). 6089 */ 6090 cpu_abort(cs, "Failed to read from exception vector table " 6091 "entry %08x\n", (unsigned)vec); 6092 } 6093 return addr; 6094 } 6095 6096 static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr) 6097 { 6098 /* Do the "take the exception" parts of exception entry, 6099 * but not the pushing of state to the stack. This is 6100 * similar to the pseudocode ExceptionTaken() function. 6101 */ 6102 CPUARMState *env = &cpu->env; 6103 uint32_t addr; 6104 6105 armv7m_nvic_acknowledge_irq(env->nvic); 6106 switch_v7m_sp(env, 0); 6107 /* Clear IT bits */ 6108 env->condexec_bits = 0; 6109 env->regs[14] = lr; 6110 addr = arm_v7m_load_vector(cpu); 6111 env->regs[15] = addr & 0xfffffffe; 6112 env->thumb = addr & 1; 6113 } 6114 6115 static void v7m_push_stack(ARMCPU *cpu) 6116 { 6117 /* Do the "set up stack frame" part of exception entry, 6118 * similar to pseudocode PushStack(). 6119 */ 6120 CPUARMState *env = &cpu->env; 6121 uint32_t xpsr = xpsr_read(env); 6122 6123 /* Align stack pointer if the guest wants that */ 6124 if ((env->regs[13] & 4) && (env->v7m.ccr & R_V7M_CCR_STKALIGN_MASK)) { 6125 env->regs[13] -= 4; 6126 xpsr |= 0x200; 6127 } 6128 /* Switch to the handler mode. */ 6129 v7m_push(env, xpsr); 6130 v7m_push(env, env->regs[15]); 6131 v7m_push(env, env->regs[14]); 6132 v7m_push(env, env->regs[12]); 6133 v7m_push(env, env->regs[3]); 6134 v7m_push(env, env->regs[2]); 6135 v7m_push(env, env->regs[1]); 6136 v7m_push(env, env->regs[0]); 6137 } 6138 6139 static void do_v7m_exception_exit(ARMCPU *cpu) 6140 { 6141 CPUARMState *env = &cpu->env; 6142 uint32_t type; 6143 uint32_t xpsr; 6144 bool ufault = false; 6145 bool return_to_sp_process = false; 6146 bool return_to_handler = false; 6147 bool rettobase = false; 6148 6149 /* We can only get here from an EXCP_EXCEPTION_EXIT, and 6150 * arm_v7m_do_unassigned_access() enforces the architectural rule 6151 * that jumps to magic addresses don't have magic behaviour unless 6152 * we're in Handler mode (compare pseudocode BXWritePC()). 6153 */ 6154 assert(env->v7m.exception != 0); 6155 6156 /* In the spec pseudocode ExceptionReturn() is called directly 6157 * from BXWritePC() and gets the full target PC value including 6158 * bit zero. In QEMU's implementation we treat it as a normal 6159 * jump-to-register (which is then caught later on), and so split 6160 * the target value up between env->regs[15] and env->thumb in 6161 * gen_bx(). Reconstitute it. 6162 */ 6163 type = env->regs[15]; 6164 if (env->thumb) { 6165 type |= 1; 6166 } 6167 6168 qemu_log_mask(CPU_LOG_INT, "Exception return: magic PC %" PRIx32 6169 " previous exception %d\n", 6170 type, env->v7m.exception); 6171 6172 if (extract32(type, 5, 23) != extract32(-1, 5, 23)) { 6173 qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero high bits in exception " 6174 "exit PC value 0x%" PRIx32 " are UNPREDICTABLE\n", type); 6175 } 6176 6177 if (env->v7m.exception != ARMV7M_EXCP_NMI) { 6178 /* Auto-clear FAULTMASK on return from other than NMI */ 6179 env->daif &= ~PSTATE_F; 6180 } 6181 6182 switch (armv7m_nvic_complete_irq(env->nvic, env->v7m.exception)) { 6183 case -1: 6184 /* attempt to exit an exception that isn't active */ 6185 ufault = true; 6186 break; 6187 case 0: 6188 /* still an irq active now */ 6189 break; 6190 case 1: 6191 /* we returned to base exception level, no nesting. 6192 * (In the pseudocode this is written using "NestedActivation != 1" 6193 * where we have 'rettobase == false'.) 6194 */ 6195 rettobase = true; 6196 break; 6197 default: 6198 g_assert_not_reached(); 6199 } 6200 6201 switch (type & 0xf) { 6202 case 1: /* Return to Handler */ 6203 return_to_handler = true; 6204 break; 6205 case 13: /* Return to Thread using Process stack */ 6206 return_to_sp_process = true; 6207 /* fall through */ 6208 case 9: /* Return to Thread using Main stack */ 6209 if (!rettobase && 6210 !(env->v7m.ccr & R_V7M_CCR_NONBASETHRDENA_MASK)) { 6211 ufault = true; 6212 } 6213 break; 6214 default: 6215 ufault = true; 6216 } 6217 6218 if (ufault) { 6219 /* Bad exception return: instead of popping the exception 6220 * stack, directly take a usage fault on the current stack. 6221 */ 6222 env->v7m.cfsr |= R_V7M_CFSR_INVPC_MASK; 6223 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); 6224 v7m_exception_taken(cpu, type | 0xf0000000); 6225 qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing " 6226 "stackframe: failed exception return integrity check\n"); 6227 return; 6228 } 6229 6230 /* Switch to the target stack. */ 6231 switch_v7m_sp(env, return_to_sp_process); 6232 /* Pop registers. */ 6233 env->regs[0] = v7m_pop(env); 6234 env->regs[1] = v7m_pop(env); 6235 env->regs[2] = v7m_pop(env); 6236 env->regs[3] = v7m_pop(env); 6237 env->regs[12] = v7m_pop(env); 6238 env->regs[14] = v7m_pop(env); 6239 env->regs[15] = v7m_pop(env); 6240 if (env->regs[15] & 1) { 6241 qemu_log_mask(LOG_GUEST_ERROR, 6242 "M profile return from interrupt with misaligned " 6243 "PC is UNPREDICTABLE\n"); 6244 /* Actual hardware seems to ignore the lsbit, and there are several 6245 * RTOSes out there which incorrectly assume the r15 in the stack 6246 * frame should be a Thumb-style "lsbit indicates ARM/Thumb" value. 6247 */ 6248 env->regs[15] &= ~1U; 6249 } 6250 xpsr = v7m_pop(env); 6251 xpsr_write(env, xpsr, 0xfffffdff); 6252 /* Undo stack alignment. */ 6253 if (xpsr & 0x200) 6254 env->regs[13] |= 4; 6255 6256 /* The restored xPSR exception field will be zero if we're 6257 * resuming in Thread mode. If that doesn't match what the 6258 * exception return type specified then this is a UsageFault. 6259 */ 6260 if (return_to_handler == (env->v7m.exception == 0)) { 6261 /* Take an INVPC UsageFault by pushing the stack again. */ 6262 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); 6263 env->v7m.cfsr |= R_V7M_CFSR_INVPC_MASK; 6264 v7m_push_stack(cpu); 6265 v7m_exception_taken(cpu, type | 0xf0000000); 6266 qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on new stackframe: " 6267 "failed exception return integrity check\n"); 6268 return; 6269 } 6270 6271 /* Otherwise, we have a successful exception exit. */ 6272 qemu_log_mask(CPU_LOG_INT, "...successful exception return\n"); 6273 } 6274 6275 static void arm_log_exception(int idx) 6276 { 6277 if (qemu_loglevel_mask(CPU_LOG_INT)) { 6278 const char *exc = NULL; 6279 static const char * const excnames[] = { 6280 [EXCP_UDEF] = "Undefined Instruction", 6281 [EXCP_SWI] = "SVC", 6282 [EXCP_PREFETCH_ABORT] = "Prefetch Abort", 6283 [EXCP_DATA_ABORT] = "Data Abort", 6284 [EXCP_IRQ] = "IRQ", 6285 [EXCP_FIQ] = "FIQ", 6286 [EXCP_BKPT] = "Breakpoint", 6287 [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit", 6288 [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage", 6289 [EXCP_HVC] = "Hypervisor Call", 6290 [EXCP_HYP_TRAP] = "Hypervisor Trap", 6291 [EXCP_SMC] = "Secure Monitor Call", 6292 [EXCP_VIRQ] = "Virtual IRQ", 6293 [EXCP_VFIQ] = "Virtual FIQ", 6294 [EXCP_SEMIHOST] = "Semihosting call", 6295 [EXCP_NOCP] = "v7M NOCP UsageFault", 6296 [EXCP_INVSTATE] = "v7M INVSTATE UsageFault", 6297 }; 6298 6299 if (idx >= 0 && idx < ARRAY_SIZE(excnames)) { 6300 exc = excnames[idx]; 6301 } 6302 if (!exc) { 6303 exc = "unknown"; 6304 } 6305 qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc); 6306 } 6307 } 6308 6309 void arm_v7m_cpu_do_interrupt(CPUState *cs) 6310 { 6311 ARMCPU *cpu = ARM_CPU(cs); 6312 CPUARMState *env = &cpu->env; 6313 uint32_t lr; 6314 6315 arm_log_exception(cs->exception_index); 6316 6317 lr = 0xfffffff1; 6318 if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) { 6319 lr |= 4; 6320 } 6321 if (env->v7m.exception == 0) 6322 lr |= 8; 6323 6324 /* For exceptions we just mark as pending on the NVIC, and let that 6325 handle it. */ 6326 switch (cs->exception_index) { 6327 case EXCP_UDEF: 6328 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); 6329 env->v7m.cfsr |= R_V7M_CFSR_UNDEFINSTR_MASK; 6330 break; 6331 case EXCP_NOCP: 6332 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); 6333 env->v7m.cfsr |= R_V7M_CFSR_NOCP_MASK; 6334 break; 6335 case EXCP_INVSTATE: 6336 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); 6337 env->v7m.cfsr |= R_V7M_CFSR_INVSTATE_MASK; 6338 break; 6339 case EXCP_SWI: 6340 /* The PC already points to the next instruction. */ 6341 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC); 6342 break; 6343 case EXCP_PREFETCH_ABORT: 6344 case EXCP_DATA_ABORT: 6345 /* Note that for M profile we don't have a guest facing FSR, but 6346 * the env->exception.fsr will be populated by the code that 6347 * raises the fault, in the A profile short-descriptor format. 6348 */ 6349 switch (env->exception.fsr & 0xf) { 6350 case 0x8: /* External Abort */ 6351 switch (cs->exception_index) { 6352 case EXCP_PREFETCH_ABORT: 6353 env->v7m.cfsr |= R_V7M_CFSR_PRECISERR_MASK; 6354 qemu_log_mask(CPU_LOG_INT, "...with CFSR.PRECISERR\n"); 6355 break; 6356 case EXCP_DATA_ABORT: 6357 env->v7m.cfsr |= 6358 (R_V7M_CFSR_IBUSERR_MASK | R_V7M_CFSR_BFARVALID_MASK); 6359 env->v7m.bfar = env->exception.vaddress; 6360 qemu_log_mask(CPU_LOG_INT, 6361 "...with CFSR.IBUSERR and BFAR 0x%x\n", 6362 env->v7m.bfar); 6363 break; 6364 } 6365 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS); 6366 break; 6367 default: 6368 /* All other FSR values are either MPU faults or "can't happen 6369 * for M profile" cases. 6370 */ 6371 switch (cs->exception_index) { 6372 case EXCP_PREFETCH_ABORT: 6373 env->v7m.cfsr |= R_V7M_CFSR_IACCVIOL_MASK; 6374 qemu_log_mask(CPU_LOG_INT, "...with CFSR.IACCVIOL\n"); 6375 break; 6376 case EXCP_DATA_ABORT: 6377 env->v7m.cfsr |= 6378 (R_V7M_CFSR_DACCVIOL_MASK | R_V7M_CFSR_MMARVALID_MASK); 6379 env->v7m.mmfar = env->exception.vaddress; 6380 qemu_log_mask(CPU_LOG_INT, 6381 "...with CFSR.DACCVIOL and MMFAR 0x%x\n", 6382 env->v7m.mmfar); 6383 break; 6384 } 6385 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM); 6386 break; 6387 } 6388 break; 6389 case EXCP_BKPT: 6390 if (semihosting_enabled()) { 6391 int nr; 6392 nr = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env)) & 0xff; 6393 if (nr == 0xab) { 6394 env->regs[15] += 2; 6395 qemu_log_mask(CPU_LOG_INT, 6396 "...handling as semihosting call 0x%x\n", 6397 env->regs[0]); 6398 env->regs[0] = do_arm_semihosting(env); 6399 return; 6400 } 6401 } 6402 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG); 6403 break; 6404 case EXCP_IRQ: 6405 break; 6406 case EXCP_EXCEPTION_EXIT: 6407 do_v7m_exception_exit(cpu); 6408 return; 6409 default: 6410 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); 6411 return; /* Never happens. Keep compiler happy. */ 6412 } 6413 6414 v7m_push_stack(cpu); 6415 v7m_exception_taken(cpu, lr); 6416 qemu_log_mask(CPU_LOG_INT, "... as %d\n", env->v7m.exception); 6417 } 6418 6419 /* Function used to synchronize QEMU's AArch64 register set with AArch32 6420 * register set. This is necessary when switching between AArch32 and AArch64 6421 * execution state. 6422 */ 6423 void aarch64_sync_32_to_64(CPUARMState *env) 6424 { 6425 int i; 6426 uint32_t mode = env->uncached_cpsr & CPSR_M; 6427 6428 /* We can blanket copy R[0:7] to X[0:7] */ 6429 for (i = 0; i < 8; i++) { 6430 env->xregs[i] = env->regs[i]; 6431 } 6432 6433 /* Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12. 6434 * Otherwise, they come from the banked user regs. 6435 */ 6436 if (mode == ARM_CPU_MODE_FIQ) { 6437 for (i = 8; i < 13; i++) { 6438 env->xregs[i] = env->usr_regs[i - 8]; 6439 } 6440 } else { 6441 for (i = 8; i < 13; i++) { 6442 env->xregs[i] = env->regs[i]; 6443 } 6444 } 6445 6446 /* Registers x13-x23 are the various mode SP and FP registers. Registers 6447 * r13 and r14 are only copied if we are in that mode, otherwise we copy 6448 * from the mode banked register. 6449 */ 6450 if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) { 6451 env->xregs[13] = env->regs[13]; 6452 env->xregs[14] = env->regs[14]; 6453 } else { 6454 env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)]; 6455 /* HYP is an exception in that it is copied from r14 */ 6456 if (mode == ARM_CPU_MODE_HYP) { 6457 env->xregs[14] = env->regs[14]; 6458 } else { 6459 env->xregs[14] = env->banked_r14[bank_number(ARM_CPU_MODE_USR)]; 6460 } 6461 } 6462 6463 if (mode == ARM_CPU_MODE_HYP) { 6464 env->xregs[15] = env->regs[13]; 6465 } else { 6466 env->xregs[15] = env->banked_r13[bank_number(ARM_CPU_MODE_HYP)]; 6467 } 6468 6469 if (mode == ARM_CPU_MODE_IRQ) { 6470 env->xregs[16] = env->regs[14]; 6471 env->xregs[17] = env->regs[13]; 6472 } else { 6473 env->xregs[16] = env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)]; 6474 env->xregs[17] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)]; 6475 } 6476 6477 if (mode == ARM_CPU_MODE_SVC) { 6478 env->xregs[18] = env->regs[14]; 6479 env->xregs[19] = env->regs[13]; 6480 } else { 6481 env->xregs[18] = env->banked_r14[bank_number(ARM_CPU_MODE_SVC)]; 6482 env->xregs[19] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)]; 6483 } 6484 6485 if (mode == ARM_CPU_MODE_ABT) { 6486 env->xregs[20] = env->regs[14]; 6487 env->xregs[21] = env->regs[13]; 6488 } else { 6489 env->xregs[20] = env->banked_r14[bank_number(ARM_CPU_MODE_ABT)]; 6490 env->xregs[21] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)]; 6491 } 6492 6493 if (mode == ARM_CPU_MODE_UND) { 6494 env->xregs[22] = env->regs[14]; 6495 env->xregs[23] = env->regs[13]; 6496 } else { 6497 env->xregs[22] = env->banked_r14[bank_number(ARM_CPU_MODE_UND)]; 6498 env->xregs[23] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)]; 6499 } 6500 6501 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ 6502 * mode, then we can copy from r8-r14. Otherwise, we copy from the 6503 * FIQ bank for r8-r14. 6504 */ 6505 if (mode == ARM_CPU_MODE_FIQ) { 6506 for (i = 24; i < 31; i++) { 6507 env->xregs[i] = env->regs[i - 16]; /* X[24:30] <- R[8:14] */ 6508 } 6509 } else { 6510 for (i = 24; i < 29; i++) { 6511 env->xregs[i] = env->fiq_regs[i - 24]; 6512 } 6513 env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)]; 6514 env->xregs[30] = env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)]; 6515 } 6516 6517 env->pc = env->regs[15]; 6518 } 6519 6520 /* Function used to synchronize QEMU's AArch32 register set with AArch64 6521 * register set. This is necessary when switching between AArch32 and AArch64 6522 * execution state. 6523 */ 6524 void aarch64_sync_64_to_32(CPUARMState *env) 6525 { 6526 int i; 6527 uint32_t mode = env->uncached_cpsr & CPSR_M; 6528 6529 /* We can blanket copy X[0:7] to R[0:7] */ 6530 for (i = 0; i < 8; i++) { 6531 env->regs[i] = env->xregs[i]; 6532 } 6533 6534 /* Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12. 6535 * Otherwise, we copy x8-x12 into the banked user regs. 6536 */ 6537 if (mode == ARM_CPU_MODE_FIQ) { 6538 for (i = 8; i < 13; i++) { 6539 env->usr_regs[i - 8] = env->xregs[i]; 6540 } 6541 } else { 6542 for (i = 8; i < 13; i++) { 6543 env->regs[i] = env->xregs[i]; 6544 } 6545 } 6546 6547 /* Registers r13 & r14 depend on the current mode. 6548 * If we are in a given mode, we copy the corresponding x registers to r13 6549 * and r14. Otherwise, we copy the x register to the banked r13 and r14 6550 * for the mode. 6551 */ 6552 if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) { 6553 env->regs[13] = env->xregs[13]; 6554 env->regs[14] = env->xregs[14]; 6555 } else { 6556 env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13]; 6557 6558 /* HYP is an exception in that it does not have its own banked r14 but 6559 * shares the USR r14 6560 */ 6561 if (mode == ARM_CPU_MODE_HYP) { 6562 env->regs[14] = env->xregs[14]; 6563 } else { 6564 env->banked_r14[bank_number(ARM_CPU_MODE_USR)] = env->xregs[14]; 6565 } 6566 } 6567 6568 if (mode == ARM_CPU_MODE_HYP) { 6569 env->regs[13] = env->xregs[15]; 6570 } else { 6571 env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] = env->xregs[15]; 6572 } 6573 6574 if (mode == ARM_CPU_MODE_IRQ) { 6575 env->regs[14] = env->xregs[16]; 6576 env->regs[13] = env->xregs[17]; 6577 } else { 6578 env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16]; 6579 env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17]; 6580 } 6581 6582 if (mode == ARM_CPU_MODE_SVC) { 6583 env->regs[14] = env->xregs[18]; 6584 env->regs[13] = env->xregs[19]; 6585 } else { 6586 env->banked_r14[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18]; 6587 env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19]; 6588 } 6589 6590 if (mode == ARM_CPU_MODE_ABT) { 6591 env->regs[14] = env->xregs[20]; 6592 env->regs[13] = env->xregs[21]; 6593 } else { 6594 env->banked_r14[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20]; 6595 env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21]; 6596 } 6597 6598 if (mode == ARM_CPU_MODE_UND) { 6599 env->regs[14] = env->xregs[22]; 6600 env->regs[13] = env->xregs[23]; 6601 } else { 6602 env->banked_r14[bank_number(ARM_CPU_MODE_UND)] = env->xregs[22]; 6603 env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23]; 6604 } 6605 6606 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ 6607 * mode, then we can copy to r8-r14. Otherwise, we copy to the 6608 * FIQ bank for r8-r14. 6609 */ 6610 if (mode == ARM_CPU_MODE_FIQ) { 6611 for (i = 24; i < 31; i++) { 6612 env->regs[i - 16] = env->xregs[i]; /* X[24:30] -> R[8:14] */ 6613 } 6614 } else { 6615 for (i = 24; i < 29; i++) { 6616 env->fiq_regs[i - 24] = env->xregs[i]; 6617 } 6618 env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29]; 6619 env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30]; 6620 } 6621 6622 env->regs[15] = env->pc; 6623 } 6624 6625 static void arm_cpu_do_interrupt_aarch32(CPUState *cs) 6626 { 6627 ARMCPU *cpu = ARM_CPU(cs); 6628 CPUARMState *env = &cpu->env; 6629 uint32_t addr; 6630 uint32_t mask; 6631 int new_mode; 6632 uint32_t offset; 6633 uint32_t moe; 6634 6635 /* If this is a debug exception we must update the DBGDSCR.MOE bits */ 6636 switch (env->exception.syndrome >> ARM_EL_EC_SHIFT) { 6637 case EC_BREAKPOINT: 6638 case EC_BREAKPOINT_SAME_EL: 6639 moe = 1; 6640 break; 6641 case EC_WATCHPOINT: 6642 case EC_WATCHPOINT_SAME_EL: 6643 moe = 10; 6644 break; 6645 case EC_AA32_BKPT: 6646 moe = 3; 6647 break; 6648 case EC_VECTORCATCH: 6649 moe = 5; 6650 break; 6651 default: 6652 moe = 0; 6653 break; 6654 } 6655 6656 if (moe) { 6657 env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe); 6658 } 6659 6660 /* TODO: Vectored interrupt controller. */ 6661 switch (cs->exception_index) { 6662 case EXCP_UDEF: 6663 new_mode = ARM_CPU_MODE_UND; 6664 addr = 0x04; 6665 mask = CPSR_I; 6666 if (env->thumb) 6667 offset = 2; 6668 else 6669 offset = 4; 6670 break; 6671 case EXCP_SWI: 6672 new_mode = ARM_CPU_MODE_SVC; 6673 addr = 0x08; 6674 mask = CPSR_I; 6675 /* The PC already points to the next instruction. */ 6676 offset = 0; 6677 break; 6678 case EXCP_BKPT: 6679 env->exception.fsr = 2; 6680 /* Fall through to prefetch abort. */ 6681 case EXCP_PREFETCH_ABORT: 6682 A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr); 6683 A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress); 6684 qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n", 6685 env->exception.fsr, (uint32_t)env->exception.vaddress); 6686 new_mode = ARM_CPU_MODE_ABT; 6687 addr = 0x0c; 6688 mask = CPSR_A | CPSR_I; 6689 offset = 4; 6690 break; 6691 case EXCP_DATA_ABORT: 6692 A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); 6693 A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress); 6694 qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n", 6695 env->exception.fsr, 6696 (uint32_t)env->exception.vaddress); 6697 new_mode = ARM_CPU_MODE_ABT; 6698 addr = 0x10; 6699 mask = CPSR_A | CPSR_I; 6700 offset = 8; 6701 break; 6702 case EXCP_IRQ: 6703 new_mode = ARM_CPU_MODE_IRQ; 6704 addr = 0x18; 6705 /* Disable IRQ and imprecise data aborts. */ 6706 mask = CPSR_A | CPSR_I; 6707 offset = 4; 6708 if (env->cp15.scr_el3 & SCR_IRQ) { 6709 /* IRQ routed to monitor mode */ 6710 new_mode = ARM_CPU_MODE_MON; 6711 mask |= CPSR_F; 6712 } 6713 break; 6714 case EXCP_FIQ: 6715 new_mode = ARM_CPU_MODE_FIQ; 6716 addr = 0x1c; 6717 /* Disable FIQ, IRQ and imprecise data aborts. */ 6718 mask = CPSR_A | CPSR_I | CPSR_F; 6719 if (env->cp15.scr_el3 & SCR_FIQ) { 6720 /* FIQ routed to monitor mode */ 6721 new_mode = ARM_CPU_MODE_MON; 6722 } 6723 offset = 4; 6724 break; 6725 case EXCP_VIRQ: 6726 new_mode = ARM_CPU_MODE_IRQ; 6727 addr = 0x18; 6728 /* Disable IRQ and imprecise data aborts. */ 6729 mask = CPSR_A | CPSR_I; 6730 offset = 4; 6731 break; 6732 case EXCP_VFIQ: 6733 new_mode = ARM_CPU_MODE_FIQ; 6734 addr = 0x1c; 6735 /* Disable FIQ, IRQ and imprecise data aborts. */ 6736 mask = CPSR_A | CPSR_I | CPSR_F; 6737 offset = 4; 6738 break; 6739 case EXCP_SMC: 6740 new_mode = ARM_CPU_MODE_MON; 6741 addr = 0x08; 6742 mask = CPSR_A | CPSR_I | CPSR_F; 6743 offset = 0; 6744 break; 6745 default: 6746 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); 6747 return; /* Never happens. Keep compiler happy. */ 6748 } 6749 6750 if (new_mode == ARM_CPU_MODE_MON) { 6751 addr += env->cp15.mvbar; 6752 } else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 6753 /* High vectors. When enabled, base address cannot be remapped. */ 6754 addr += 0xffff0000; 6755 } else { 6756 /* ARM v7 architectures provide a vector base address register to remap 6757 * the interrupt vector table. 6758 * This register is only followed in non-monitor mode, and is banked. 6759 * Note: only bits 31:5 are valid. 6760 */ 6761 addr += A32_BANKED_CURRENT_REG_GET(env, vbar); 6762 } 6763 6764 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 6765 env->cp15.scr_el3 &= ~SCR_NS; 6766 } 6767 6768 switch_mode (env, new_mode); 6769 /* For exceptions taken to AArch32 we must clear the SS bit in both 6770 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now. 6771 */ 6772 env->uncached_cpsr &= ~PSTATE_SS; 6773 env->spsr = cpsr_read(env); 6774 /* Clear IT bits. */ 6775 env->condexec_bits = 0; 6776 /* Switch to the new mode, and to the correct instruction set. */ 6777 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; 6778 /* Set new mode endianness */ 6779 env->uncached_cpsr &= ~CPSR_E; 6780 if (env->cp15.sctlr_el[arm_current_el(env)] & SCTLR_EE) { 6781 env->uncached_cpsr |= CPSR_E; 6782 } 6783 env->daif |= mask; 6784 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares 6785 * and we should just guard the thumb mode on V4 */ 6786 if (arm_feature(env, ARM_FEATURE_V4T)) { 6787 env->thumb = (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) != 0; 6788 } 6789 env->regs[14] = env->regs[15] + offset; 6790 env->regs[15] = addr; 6791 } 6792 6793 /* Handle exception entry to a target EL which is using AArch64 */ 6794 static void arm_cpu_do_interrupt_aarch64(CPUState *cs) 6795 { 6796 ARMCPU *cpu = ARM_CPU(cs); 6797 CPUARMState *env = &cpu->env; 6798 unsigned int new_el = env->exception.target_el; 6799 target_ulong addr = env->cp15.vbar_el[new_el]; 6800 unsigned int new_mode = aarch64_pstate_mode(new_el, true); 6801 6802 if (arm_current_el(env) < new_el) { 6803 /* Entry vector offset depends on whether the implemented EL 6804 * immediately lower than the target level is using AArch32 or AArch64 6805 */ 6806 bool is_aa64; 6807 6808 switch (new_el) { 6809 case 3: 6810 is_aa64 = (env->cp15.scr_el3 & SCR_RW) != 0; 6811 break; 6812 case 2: 6813 is_aa64 = (env->cp15.hcr_el2 & HCR_RW) != 0; 6814 break; 6815 case 1: 6816 is_aa64 = is_a64(env); 6817 break; 6818 default: 6819 g_assert_not_reached(); 6820 } 6821 6822 if (is_aa64) { 6823 addr += 0x400; 6824 } else { 6825 addr += 0x600; 6826 } 6827 } else if (pstate_read(env) & PSTATE_SP) { 6828 addr += 0x200; 6829 } 6830 6831 switch (cs->exception_index) { 6832 case EXCP_PREFETCH_ABORT: 6833 case EXCP_DATA_ABORT: 6834 env->cp15.far_el[new_el] = env->exception.vaddress; 6835 qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n", 6836 env->cp15.far_el[new_el]); 6837 /* fall through */ 6838 case EXCP_BKPT: 6839 case EXCP_UDEF: 6840 case EXCP_SWI: 6841 case EXCP_HVC: 6842 case EXCP_HYP_TRAP: 6843 case EXCP_SMC: 6844 env->cp15.esr_el[new_el] = env->exception.syndrome; 6845 break; 6846 case EXCP_IRQ: 6847 case EXCP_VIRQ: 6848 addr += 0x80; 6849 break; 6850 case EXCP_FIQ: 6851 case EXCP_VFIQ: 6852 addr += 0x100; 6853 break; 6854 case EXCP_SEMIHOST: 6855 qemu_log_mask(CPU_LOG_INT, 6856 "...handling as semihosting call 0x%" PRIx64 "\n", 6857 env->xregs[0]); 6858 env->xregs[0] = do_arm_semihosting(env); 6859 return; 6860 default: 6861 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); 6862 } 6863 6864 if (is_a64(env)) { 6865 env->banked_spsr[aarch64_banked_spsr_index(new_el)] = pstate_read(env); 6866 aarch64_save_sp(env, arm_current_el(env)); 6867 env->elr_el[new_el] = env->pc; 6868 } else { 6869 env->banked_spsr[aarch64_banked_spsr_index(new_el)] = cpsr_read(env); 6870 env->elr_el[new_el] = env->regs[15]; 6871 6872 aarch64_sync_32_to_64(env); 6873 6874 env->condexec_bits = 0; 6875 } 6876 qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n", 6877 env->elr_el[new_el]); 6878 6879 pstate_write(env, PSTATE_DAIF | new_mode); 6880 env->aarch64 = 1; 6881 aarch64_restore_sp(env, new_el); 6882 6883 env->pc = addr; 6884 6885 qemu_log_mask(CPU_LOG_INT, "...to EL%d PC 0x%" PRIx64 " PSTATE 0x%x\n", 6886 new_el, env->pc, pstate_read(env)); 6887 } 6888 6889 static inline bool check_for_semihosting(CPUState *cs) 6890 { 6891 /* Check whether this exception is a semihosting call; if so 6892 * then handle it and return true; otherwise return false. 6893 */ 6894 ARMCPU *cpu = ARM_CPU(cs); 6895 CPUARMState *env = &cpu->env; 6896 6897 if (is_a64(env)) { 6898 if (cs->exception_index == EXCP_SEMIHOST) { 6899 /* This is always the 64-bit semihosting exception. 6900 * The "is this usermode" and "is semihosting enabled" 6901 * checks have been done at translate time. 6902 */ 6903 qemu_log_mask(CPU_LOG_INT, 6904 "...handling as semihosting call 0x%" PRIx64 "\n", 6905 env->xregs[0]); 6906 env->xregs[0] = do_arm_semihosting(env); 6907 return true; 6908 } 6909 return false; 6910 } else { 6911 uint32_t imm; 6912 6913 /* Only intercept calls from privileged modes, to provide some 6914 * semblance of security. 6915 */ 6916 if (cs->exception_index != EXCP_SEMIHOST && 6917 (!semihosting_enabled() || 6918 ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR))) { 6919 return false; 6920 } 6921 6922 switch (cs->exception_index) { 6923 case EXCP_SEMIHOST: 6924 /* This is always a semihosting call; the "is this usermode" 6925 * and "is semihosting enabled" checks have been done at 6926 * translate time. 6927 */ 6928 break; 6929 case EXCP_SWI: 6930 /* Check for semihosting interrupt. */ 6931 if (env->thumb) { 6932 imm = arm_lduw_code(env, env->regs[15] - 2, arm_sctlr_b(env)) 6933 & 0xff; 6934 if (imm == 0xab) { 6935 break; 6936 } 6937 } else { 6938 imm = arm_ldl_code(env, env->regs[15] - 4, arm_sctlr_b(env)) 6939 & 0xffffff; 6940 if (imm == 0x123456) { 6941 break; 6942 } 6943 } 6944 return false; 6945 case EXCP_BKPT: 6946 /* See if this is a semihosting syscall. */ 6947 if (env->thumb) { 6948 imm = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env)) 6949 & 0xff; 6950 if (imm == 0xab) { 6951 env->regs[15] += 2; 6952 break; 6953 } 6954 } 6955 return false; 6956 default: 6957 return false; 6958 } 6959 6960 qemu_log_mask(CPU_LOG_INT, 6961 "...handling as semihosting call 0x%x\n", 6962 env->regs[0]); 6963 env->regs[0] = do_arm_semihosting(env); 6964 return true; 6965 } 6966 } 6967 6968 /* Handle a CPU exception for A and R profile CPUs. 6969 * Do any appropriate logging, handle PSCI calls, and then hand off 6970 * to the AArch64-entry or AArch32-entry function depending on the 6971 * target exception level's register width. 6972 */ 6973 void arm_cpu_do_interrupt(CPUState *cs) 6974 { 6975 ARMCPU *cpu = ARM_CPU(cs); 6976 CPUARMState *env = &cpu->env; 6977 unsigned int new_el = env->exception.target_el; 6978 6979 assert(!arm_feature(env, ARM_FEATURE_M)); 6980 6981 arm_log_exception(cs->exception_index); 6982 qemu_log_mask(CPU_LOG_INT, "...from EL%d to EL%d\n", arm_current_el(env), 6983 new_el); 6984 if (qemu_loglevel_mask(CPU_LOG_INT) 6985 && !excp_is_internal(cs->exception_index)) { 6986 qemu_log_mask(CPU_LOG_INT, "...with ESR 0x%x/0x%" PRIx32 "\n", 6987 env->exception.syndrome >> ARM_EL_EC_SHIFT, 6988 env->exception.syndrome); 6989 } 6990 6991 if (arm_is_psci_call(cpu, cs->exception_index)) { 6992 arm_handle_psci_call(cpu); 6993 qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n"); 6994 return; 6995 } 6996 6997 /* Semihosting semantics depend on the register width of the 6998 * code that caused the exception, not the target exception level, 6999 * so must be handled here. 7000 */ 7001 if (check_for_semihosting(cs)) { 7002 return; 7003 } 7004 7005 assert(!excp_is_internal(cs->exception_index)); 7006 if (arm_el_is_aa64(env, new_el)) { 7007 arm_cpu_do_interrupt_aarch64(cs); 7008 } else { 7009 arm_cpu_do_interrupt_aarch32(cs); 7010 } 7011 7012 /* Hooks may change global state so BQL should be held, also the 7013 * BQL needs to be held for any modification of 7014 * cs->interrupt_request. 7015 */ 7016 g_assert(qemu_mutex_iothread_locked()); 7017 7018 arm_call_el_change_hook(cpu); 7019 7020 if (!kvm_enabled()) { 7021 cs->interrupt_request |= CPU_INTERRUPT_EXITTB; 7022 } 7023 } 7024 7025 /* Return the exception level which controls this address translation regime */ 7026 static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) 7027 { 7028 switch (mmu_idx) { 7029 case ARMMMUIdx_S2NS: 7030 case ARMMMUIdx_S1E2: 7031 return 2; 7032 case ARMMMUIdx_S1E3: 7033 return 3; 7034 case ARMMMUIdx_S1SE0: 7035 return arm_el_is_aa64(env, 3) ? 1 : 3; 7036 case ARMMMUIdx_S1SE1: 7037 case ARMMMUIdx_S1NSE0: 7038 case ARMMMUIdx_S1NSE1: 7039 case ARMMMUIdx_MPriv: 7040 case ARMMMUIdx_MNegPri: 7041 case ARMMMUIdx_MUser: 7042 return 1; 7043 default: 7044 g_assert_not_reached(); 7045 } 7046 } 7047 7048 /* Return true if this address translation regime is secure */ 7049 static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) 7050 { 7051 switch (mmu_idx) { 7052 case ARMMMUIdx_S12NSE0: 7053 case ARMMMUIdx_S12NSE1: 7054 case ARMMMUIdx_S1NSE0: 7055 case ARMMMUIdx_S1NSE1: 7056 case ARMMMUIdx_S1E2: 7057 case ARMMMUIdx_S2NS: 7058 case ARMMMUIdx_MPriv: 7059 case ARMMMUIdx_MNegPri: 7060 case ARMMMUIdx_MUser: 7061 return false; 7062 case ARMMMUIdx_S1E3: 7063 case ARMMMUIdx_S1SE0: 7064 case ARMMMUIdx_S1SE1: 7065 return true; 7066 default: 7067 g_assert_not_reached(); 7068 } 7069 } 7070 7071 /* Return the SCTLR value which controls this address translation regime */ 7072 static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) 7073 { 7074 return env->cp15.sctlr_el[regime_el(env, mmu_idx)]; 7075 } 7076 7077 /* Return true if the specified stage of address translation is disabled */ 7078 static inline bool regime_translation_disabled(CPUARMState *env, 7079 ARMMMUIdx mmu_idx) 7080 { 7081 if (arm_feature(env, ARM_FEATURE_M)) { 7082 switch (env->v7m.mpu_ctrl & 7083 (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK)) { 7084 case R_V7M_MPU_CTRL_ENABLE_MASK: 7085 /* Enabled, but not for HardFault and NMI */ 7086 return mmu_idx == ARMMMUIdx_MNegPri; 7087 case R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK: 7088 /* Enabled for all cases */ 7089 return false; 7090 case 0: 7091 default: 7092 /* HFNMIENA set and ENABLE clear is UNPREDICTABLE, but 7093 * we warned about that in armv7m_nvic.c when the guest set it. 7094 */ 7095 return true; 7096 } 7097 } 7098 7099 if (mmu_idx == ARMMMUIdx_S2NS) { 7100 return (env->cp15.hcr_el2 & HCR_VM) == 0; 7101 } 7102 return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0; 7103 } 7104 7105 static inline bool regime_translation_big_endian(CPUARMState *env, 7106 ARMMMUIdx mmu_idx) 7107 { 7108 return (regime_sctlr(env, mmu_idx) & SCTLR_EE) != 0; 7109 } 7110 7111 /* Return the TCR controlling this translation regime */ 7112 static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) 7113 { 7114 if (mmu_idx == ARMMMUIdx_S2NS) { 7115 return &env->cp15.vtcr_el2; 7116 } 7117 return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; 7118 } 7119 7120 /* Convert a possible stage1+2 MMU index into the appropriate 7121 * stage 1 MMU index 7122 */ 7123 static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) 7124 { 7125 if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { 7126 mmu_idx += (ARMMMUIdx_S1NSE0 - ARMMMUIdx_S12NSE0); 7127 } 7128 return mmu_idx; 7129 } 7130 7131 /* Returns TBI0 value for current regime el */ 7132 uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx) 7133 { 7134 TCR *tcr; 7135 uint32_t el; 7136 7137 /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert 7138 * a stage 1+2 mmu index into the appropriate stage 1 mmu index. 7139 */ 7140 mmu_idx = stage_1_mmu_idx(mmu_idx); 7141 7142 tcr = regime_tcr(env, mmu_idx); 7143 el = regime_el(env, mmu_idx); 7144 7145 if (el > 1) { 7146 return extract64(tcr->raw_tcr, 20, 1); 7147 } else { 7148 return extract64(tcr->raw_tcr, 37, 1); 7149 } 7150 } 7151 7152 /* Returns TBI1 value for current regime el */ 7153 uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx) 7154 { 7155 TCR *tcr; 7156 uint32_t el; 7157 7158 /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert 7159 * a stage 1+2 mmu index into the appropriate stage 1 mmu index. 7160 */ 7161 mmu_idx = stage_1_mmu_idx(mmu_idx); 7162 7163 tcr = regime_tcr(env, mmu_idx); 7164 el = regime_el(env, mmu_idx); 7165 7166 if (el > 1) { 7167 return 0; 7168 } else { 7169 return extract64(tcr->raw_tcr, 38, 1); 7170 } 7171 } 7172 7173 /* Return the TTBR associated with this translation regime */ 7174 static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, 7175 int ttbrn) 7176 { 7177 if (mmu_idx == ARMMMUIdx_S2NS) { 7178 return env->cp15.vttbr_el2; 7179 } 7180 if (ttbrn == 0) { 7181 return env->cp15.ttbr0_el[regime_el(env, mmu_idx)]; 7182 } else { 7183 return env->cp15.ttbr1_el[regime_el(env, mmu_idx)]; 7184 } 7185 } 7186 7187 /* Return true if the translation regime is using LPAE format page tables */ 7188 static inline bool regime_using_lpae_format(CPUARMState *env, 7189 ARMMMUIdx mmu_idx) 7190 { 7191 int el = regime_el(env, mmu_idx); 7192 if (el == 2 || arm_el_is_aa64(env, el)) { 7193 return true; 7194 } 7195 if (arm_feature(env, ARM_FEATURE_LPAE) 7196 && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) { 7197 return true; 7198 } 7199 return false; 7200 } 7201 7202 /* Returns true if the stage 1 translation regime is using LPAE format page 7203 * tables. Used when raising alignment exceptions, whose FSR changes depending 7204 * on whether the long or short descriptor format is in use. */ 7205 bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) 7206 { 7207 mmu_idx = stage_1_mmu_idx(mmu_idx); 7208 7209 return regime_using_lpae_format(env, mmu_idx); 7210 } 7211 7212 static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) 7213 { 7214 switch (mmu_idx) { 7215 case ARMMMUIdx_S1SE0: 7216 case ARMMMUIdx_S1NSE0: 7217 case ARMMMUIdx_MUser: 7218 return true; 7219 default: 7220 return false; 7221 case ARMMMUIdx_S12NSE0: 7222 case ARMMMUIdx_S12NSE1: 7223 g_assert_not_reached(); 7224 } 7225 } 7226 7227 /* Translate section/page access permissions to page 7228 * R/W protection flags 7229 * 7230 * @env: CPUARMState 7231 * @mmu_idx: MMU index indicating required translation regime 7232 * @ap: The 3-bit access permissions (AP[2:0]) 7233 * @domain_prot: The 2-bit domain access permissions 7234 */ 7235 static inline int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, 7236 int ap, int domain_prot) 7237 { 7238 bool is_user = regime_is_user(env, mmu_idx); 7239 7240 if (domain_prot == 3) { 7241 return PAGE_READ | PAGE_WRITE; 7242 } 7243 7244 switch (ap) { 7245 case 0: 7246 if (arm_feature(env, ARM_FEATURE_V7)) { 7247 return 0; 7248 } 7249 switch (regime_sctlr(env, mmu_idx) & (SCTLR_S | SCTLR_R)) { 7250 case SCTLR_S: 7251 return is_user ? 0 : PAGE_READ; 7252 case SCTLR_R: 7253 return PAGE_READ; 7254 default: 7255 return 0; 7256 } 7257 case 1: 7258 return is_user ? 0 : PAGE_READ | PAGE_WRITE; 7259 case 2: 7260 if (is_user) { 7261 return PAGE_READ; 7262 } else { 7263 return PAGE_READ | PAGE_WRITE; 7264 } 7265 case 3: 7266 return PAGE_READ | PAGE_WRITE; 7267 case 4: /* Reserved. */ 7268 return 0; 7269 case 5: 7270 return is_user ? 0 : PAGE_READ; 7271 case 6: 7272 return PAGE_READ; 7273 case 7: 7274 if (!arm_feature(env, ARM_FEATURE_V6K)) { 7275 return 0; 7276 } 7277 return PAGE_READ; 7278 default: 7279 g_assert_not_reached(); 7280 } 7281 } 7282 7283 /* Translate section/page access permissions to page 7284 * R/W protection flags. 7285 * 7286 * @ap: The 2-bit simple AP (AP[2:1]) 7287 * @is_user: TRUE if accessing from PL0 7288 */ 7289 static inline int simple_ap_to_rw_prot_is_user(int ap, bool is_user) 7290 { 7291 switch (ap) { 7292 case 0: 7293 return is_user ? 0 : PAGE_READ | PAGE_WRITE; 7294 case 1: 7295 return PAGE_READ | PAGE_WRITE; 7296 case 2: 7297 return is_user ? 0 : PAGE_READ; 7298 case 3: 7299 return PAGE_READ; 7300 default: 7301 g_assert_not_reached(); 7302 } 7303 } 7304 7305 static inline int 7306 simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap) 7307 { 7308 return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx)); 7309 } 7310 7311 /* Translate S2 section/page access permissions to protection flags 7312 * 7313 * @env: CPUARMState 7314 * @s2ap: The 2-bit stage2 access permissions (S2AP) 7315 * @xn: XN (execute-never) bit 7316 */ 7317 static int get_S2prot(CPUARMState *env, int s2ap, int xn) 7318 { 7319 int prot = 0; 7320 7321 if (s2ap & 1) { 7322 prot |= PAGE_READ; 7323 } 7324 if (s2ap & 2) { 7325 prot |= PAGE_WRITE; 7326 } 7327 if (!xn) { 7328 if (arm_el_is_aa64(env, 2) || prot & PAGE_READ) { 7329 prot |= PAGE_EXEC; 7330 } 7331 } 7332 return prot; 7333 } 7334 7335 /* Translate section/page access permissions to protection flags 7336 * 7337 * @env: CPUARMState 7338 * @mmu_idx: MMU index indicating required translation regime 7339 * @is_aa64: TRUE if AArch64 7340 * @ap: The 2-bit simple AP (AP[2:1]) 7341 * @ns: NS (non-secure) bit 7342 * @xn: XN (execute-never) bit 7343 * @pxn: PXN (privileged execute-never) bit 7344 */ 7345 static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, 7346 int ap, int ns, int xn, int pxn) 7347 { 7348 bool is_user = regime_is_user(env, mmu_idx); 7349 int prot_rw, user_rw; 7350 bool have_wxn; 7351 int wxn = 0; 7352 7353 assert(mmu_idx != ARMMMUIdx_S2NS); 7354 7355 user_rw = simple_ap_to_rw_prot_is_user(ap, true); 7356 if (is_user) { 7357 prot_rw = user_rw; 7358 } else { 7359 prot_rw = simple_ap_to_rw_prot_is_user(ap, false); 7360 } 7361 7362 if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) { 7363 return prot_rw; 7364 } 7365 7366 /* TODO have_wxn should be replaced with 7367 * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2) 7368 * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE 7369 * compatible processors have EL2, which is required for [U]WXN. 7370 */ 7371 have_wxn = arm_feature(env, ARM_FEATURE_LPAE); 7372 7373 if (have_wxn) { 7374 wxn = regime_sctlr(env, mmu_idx) & SCTLR_WXN; 7375 } 7376 7377 if (is_aa64) { 7378 switch (regime_el(env, mmu_idx)) { 7379 case 1: 7380 if (!is_user) { 7381 xn = pxn || (user_rw & PAGE_WRITE); 7382 } 7383 break; 7384 case 2: 7385 case 3: 7386 break; 7387 } 7388 } else if (arm_feature(env, ARM_FEATURE_V7)) { 7389 switch (regime_el(env, mmu_idx)) { 7390 case 1: 7391 case 3: 7392 if (is_user) { 7393 xn = xn || !(user_rw & PAGE_READ); 7394 } else { 7395 int uwxn = 0; 7396 if (have_wxn) { 7397 uwxn = regime_sctlr(env, mmu_idx) & SCTLR_UWXN; 7398 } 7399 xn = xn || !(prot_rw & PAGE_READ) || pxn || 7400 (uwxn && (user_rw & PAGE_WRITE)); 7401 } 7402 break; 7403 case 2: 7404 break; 7405 } 7406 } else { 7407 xn = wxn = 0; 7408 } 7409 7410 if (xn || (wxn && (prot_rw & PAGE_WRITE))) { 7411 return prot_rw; 7412 } 7413 return prot_rw | PAGE_EXEC; 7414 } 7415 7416 static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, 7417 uint32_t *table, uint32_t address) 7418 { 7419 /* Note that we can only get here for an AArch32 PL0/PL1 lookup */ 7420 TCR *tcr = regime_tcr(env, mmu_idx); 7421 7422 if (address & tcr->mask) { 7423 if (tcr->raw_tcr & TTBCR_PD1) { 7424 /* Translation table walk disabled for TTBR1 */ 7425 return false; 7426 } 7427 *table = regime_ttbr(env, mmu_idx, 1) & 0xffffc000; 7428 } else { 7429 if (tcr->raw_tcr & TTBCR_PD0) { 7430 /* Translation table walk disabled for TTBR0 */ 7431 return false; 7432 } 7433 *table = regime_ttbr(env, mmu_idx, 0) & tcr->base_mask; 7434 } 7435 *table |= (address >> 18) & 0x3ffc; 7436 return true; 7437 } 7438 7439 /* Translate a S1 pagetable walk through S2 if needed. */ 7440 static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, 7441 hwaddr addr, MemTxAttrs txattrs, 7442 uint32_t *fsr, 7443 ARMMMUFaultInfo *fi) 7444 { 7445 if ((mmu_idx == ARMMMUIdx_S1NSE0 || mmu_idx == ARMMMUIdx_S1NSE1) && 7446 !regime_translation_disabled(env, ARMMMUIdx_S2NS)) { 7447 target_ulong s2size; 7448 hwaddr s2pa; 7449 int s2prot; 7450 int ret; 7451 7452 ret = get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_S2NS, &s2pa, 7453 &txattrs, &s2prot, &s2size, fsr, fi); 7454 if (ret) { 7455 fi->s2addr = addr; 7456 fi->stage2 = true; 7457 fi->s1ptw = true; 7458 return ~0; 7459 } 7460 addr = s2pa; 7461 } 7462 return addr; 7463 } 7464 7465 /* All loads done in the course of a page table walk go through here. 7466 * TODO: rather than ignoring errors from physical memory reads (which 7467 * are external aborts in ARM terminology) we should propagate this 7468 * error out so that we can turn it into a Data Abort if this walk 7469 * was being done for a CPU load/store or an address translation instruction 7470 * (but not if it was for a debug access). 7471 */ 7472 static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure, 7473 ARMMMUIdx mmu_idx, uint32_t *fsr, 7474 ARMMMUFaultInfo *fi) 7475 { 7476 ARMCPU *cpu = ARM_CPU(cs); 7477 CPUARMState *env = &cpu->env; 7478 MemTxAttrs attrs = {}; 7479 AddressSpace *as; 7480 7481 attrs.secure = is_secure; 7482 as = arm_addressspace(cs, attrs); 7483 addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi); 7484 if (fi->s1ptw) { 7485 return 0; 7486 } 7487 if (regime_translation_big_endian(env, mmu_idx)) { 7488 return address_space_ldl_be(as, addr, attrs, NULL); 7489 } else { 7490 return address_space_ldl_le(as, addr, attrs, NULL); 7491 } 7492 } 7493 7494 static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, 7495 ARMMMUIdx mmu_idx, uint32_t *fsr, 7496 ARMMMUFaultInfo *fi) 7497 { 7498 ARMCPU *cpu = ARM_CPU(cs); 7499 CPUARMState *env = &cpu->env; 7500 MemTxAttrs attrs = {}; 7501 AddressSpace *as; 7502 7503 attrs.secure = is_secure; 7504 as = arm_addressspace(cs, attrs); 7505 addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi); 7506 if (fi->s1ptw) { 7507 return 0; 7508 } 7509 if (regime_translation_big_endian(env, mmu_idx)) { 7510 return address_space_ldq_be(as, addr, attrs, NULL); 7511 } else { 7512 return address_space_ldq_le(as, addr, attrs, NULL); 7513 } 7514 } 7515 7516 static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, 7517 int access_type, ARMMMUIdx mmu_idx, 7518 hwaddr *phys_ptr, int *prot, 7519 target_ulong *page_size, uint32_t *fsr, 7520 ARMMMUFaultInfo *fi) 7521 { 7522 CPUState *cs = CPU(arm_env_get_cpu(env)); 7523 int code; 7524 uint32_t table; 7525 uint32_t desc; 7526 int type; 7527 int ap; 7528 int domain = 0; 7529 int domain_prot; 7530 hwaddr phys_addr; 7531 uint32_t dacr; 7532 7533 /* Pagetable walk. */ 7534 /* Lookup l1 descriptor. */ 7535 if (!get_level1_table_address(env, mmu_idx, &table, address)) { 7536 /* Section translation fault if page walk is disabled by PD0 or PD1 */ 7537 code = 5; 7538 goto do_fault; 7539 } 7540 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), 7541 mmu_idx, fsr, fi); 7542 type = (desc & 3); 7543 domain = (desc >> 5) & 0x0f; 7544 if (regime_el(env, mmu_idx) == 1) { 7545 dacr = env->cp15.dacr_ns; 7546 } else { 7547 dacr = env->cp15.dacr_s; 7548 } 7549 domain_prot = (dacr >> (domain * 2)) & 3; 7550 if (type == 0) { 7551 /* Section translation fault. */ 7552 code = 5; 7553 goto do_fault; 7554 } 7555 if (domain_prot == 0 || domain_prot == 2) { 7556 if (type == 2) 7557 code = 9; /* Section domain fault. */ 7558 else 7559 code = 11; /* Page domain fault. */ 7560 goto do_fault; 7561 } 7562 if (type == 2) { 7563 /* 1Mb section. */ 7564 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); 7565 ap = (desc >> 10) & 3; 7566 code = 13; 7567 *page_size = 1024 * 1024; 7568 } else { 7569 /* Lookup l2 entry. */ 7570 if (type == 1) { 7571 /* Coarse pagetable. */ 7572 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); 7573 } else { 7574 /* Fine pagetable. */ 7575 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc); 7576 } 7577 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), 7578 mmu_idx, fsr, fi); 7579 switch (desc & 3) { 7580 case 0: /* Page translation fault. */ 7581 code = 7; 7582 goto do_fault; 7583 case 1: /* 64k page. */ 7584 phys_addr = (desc & 0xffff0000) | (address & 0xffff); 7585 ap = (desc >> (4 + ((address >> 13) & 6))) & 3; 7586 *page_size = 0x10000; 7587 break; 7588 case 2: /* 4k page. */ 7589 phys_addr = (desc & 0xfffff000) | (address & 0xfff); 7590 ap = (desc >> (4 + ((address >> 9) & 6))) & 3; 7591 *page_size = 0x1000; 7592 break; 7593 case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */ 7594 if (type == 1) { 7595 /* ARMv6/XScale extended small page format */ 7596 if (arm_feature(env, ARM_FEATURE_XSCALE) 7597 || arm_feature(env, ARM_FEATURE_V6)) { 7598 phys_addr = (desc & 0xfffff000) | (address & 0xfff); 7599 *page_size = 0x1000; 7600 } else { 7601 /* UNPREDICTABLE in ARMv5; we choose to take a 7602 * page translation fault. 7603 */ 7604 code = 7; 7605 goto do_fault; 7606 } 7607 } else { 7608 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff); 7609 *page_size = 0x400; 7610 } 7611 ap = (desc >> 4) & 3; 7612 break; 7613 default: 7614 /* Never happens, but compiler isn't smart enough to tell. */ 7615 abort(); 7616 } 7617 code = 15; 7618 } 7619 *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot); 7620 *prot |= *prot ? PAGE_EXEC : 0; 7621 if (!(*prot & (1 << access_type))) { 7622 /* Access permission fault. */ 7623 goto do_fault; 7624 } 7625 *phys_ptr = phys_addr; 7626 return false; 7627 do_fault: 7628 *fsr = code | (domain << 4); 7629 return true; 7630 } 7631 7632 static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, 7633 int access_type, ARMMMUIdx mmu_idx, 7634 hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, 7635 target_ulong *page_size, uint32_t *fsr, 7636 ARMMMUFaultInfo *fi) 7637 { 7638 CPUState *cs = CPU(arm_env_get_cpu(env)); 7639 int code; 7640 uint32_t table; 7641 uint32_t desc; 7642 uint32_t xn; 7643 uint32_t pxn = 0; 7644 int type; 7645 int ap; 7646 int domain = 0; 7647 int domain_prot; 7648 hwaddr phys_addr; 7649 uint32_t dacr; 7650 bool ns; 7651 7652 /* Pagetable walk. */ 7653 /* Lookup l1 descriptor. */ 7654 if (!get_level1_table_address(env, mmu_idx, &table, address)) { 7655 /* Section translation fault if page walk is disabled by PD0 or PD1 */ 7656 code = 5; 7657 goto do_fault; 7658 } 7659 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), 7660 mmu_idx, fsr, fi); 7661 type = (desc & 3); 7662 if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) { 7663 /* Section translation fault, or attempt to use the encoding 7664 * which is Reserved on implementations without PXN. 7665 */ 7666 code = 5; 7667 goto do_fault; 7668 } 7669 if ((type == 1) || !(desc & (1 << 18))) { 7670 /* Page or Section. */ 7671 domain = (desc >> 5) & 0x0f; 7672 } 7673 if (regime_el(env, mmu_idx) == 1) { 7674 dacr = env->cp15.dacr_ns; 7675 } else { 7676 dacr = env->cp15.dacr_s; 7677 } 7678 domain_prot = (dacr >> (domain * 2)) & 3; 7679 if (domain_prot == 0 || domain_prot == 2) { 7680 if (type != 1) { 7681 code = 9; /* Section domain fault. */ 7682 } else { 7683 code = 11; /* Page domain fault. */ 7684 } 7685 goto do_fault; 7686 } 7687 if (type != 1) { 7688 if (desc & (1 << 18)) { 7689 /* Supersection. */ 7690 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff); 7691 phys_addr |= (uint64_t)extract32(desc, 20, 4) << 32; 7692 phys_addr |= (uint64_t)extract32(desc, 5, 4) << 36; 7693 *page_size = 0x1000000; 7694 } else { 7695 /* Section. */ 7696 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); 7697 *page_size = 0x100000; 7698 } 7699 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4); 7700 xn = desc & (1 << 4); 7701 pxn = desc & 1; 7702 code = 13; 7703 ns = extract32(desc, 19, 1); 7704 } else { 7705 if (arm_feature(env, ARM_FEATURE_PXN)) { 7706 pxn = (desc >> 2) & 1; 7707 } 7708 ns = extract32(desc, 3, 1); 7709 /* Lookup l2 entry. */ 7710 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); 7711 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), 7712 mmu_idx, fsr, fi); 7713 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4); 7714 switch (desc & 3) { 7715 case 0: /* Page translation fault. */ 7716 code = 7; 7717 goto do_fault; 7718 case 1: /* 64k page. */ 7719 phys_addr = (desc & 0xffff0000) | (address & 0xffff); 7720 xn = desc & (1 << 15); 7721 *page_size = 0x10000; 7722 break; 7723 case 2: case 3: /* 4k page. */ 7724 phys_addr = (desc & 0xfffff000) | (address & 0xfff); 7725 xn = desc & 1; 7726 *page_size = 0x1000; 7727 break; 7728 default: 7729 /* Never happens, but compiler isn't smart enough to tell. */ 7730 abort(); 7731 } 7732 code = 15; 7733 } 7734 if (domain_prot == 3) { 7735 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 7736 } else { 7737 if (pxn && !regime_is_user(env, mmu_idx)) { 7738 xn = 1; 7739 } 7740 if (xn && access_type == 2) 7741 goto do_fault; 7742 7743 if (arm_feature(env, ARM_FEATURE_V6K) && 7744 (regime_sctlr(env, mmu_idx) & SCTLR_AFE)) { 7745 /* The simplified model uses AP[0] as an access control bit. */ 7746 if ((ap & 1) == 0) { 7747 /* Access flag fault. */ 7748 code = (code == 15) ? 6 : 3; 7749 goto do_fault; 7750 } 7751 *prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1); 7752 } else { 7753 *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot); 7754 } 7755 if (*prot && !xn) { 7756 *prot |= PAGE_EXEC; 7757 } 7758 if (!(*prot & (1 << access_type))) { 7759 /* Access permission fault. */ 7760 goto do_fault; 7761 } 7762 } 7763 if (ns) { 7764 /* The NS bit will (as required by the architecture) have no effect if 7765 * the CPU doesn't support TZ or this is a non-secure translation 7766 * regime, because the attribute will already be non-secure. 7767 */ 7768 attrs->secure = false; 7769 } 7770 *phys_ptr = phys_addr; 7771 return false; 7772 do_fault: 7773 *fsr = code | (domain << 4); 7774 return true; 7775 } 7776 7777 /* Fault type for long-descriptor MMU fault reporting; this corresponds 7778 * to bits [5..2] in the STATUS field in long-format DFSR/IFSR. 7779 */ 7780 typedef enum { 7781 translation_fault = 1, 7782 access_fault = 2, 7783 permission_fault = 3, 7784 } MMUFaultType; 7785 7786 /* 7787 * check_s2_mmu_setup 7788 * @cpu: ARMCPU 7789 * @is_aa64: True if the translation regime is in AArch64 state 7790 * @startlevel: Suggested starting level 7791 * @inputsize: Bitsize of IPAs 7792 * @stride: Page-table stride (See the ARM ARM) 7793 * 7794 * Returns true if the suggested S2 translation parameters are OK and 7795 * false otherwise. 7796 */ 7797 static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, 7798 int inputsize, int stride) 7799 { 7800 const int grainsize = stride + 3; 7801 int startsizecheck; 7802 7803 /* Negative levels are never allowed. */ 7804 if (level < 0) { 7805 return false; 7806 } 7807 7808 startsizecheck = inputsize - ((3 - level) * stride + grainsize); 7809 if (startsizecheck < 1 || startsizecheck > stride + 4) { 7810 return false; 7811 } 7812 7813 if (is_aa64) { 7814 CPUARMState *env = &cpu->env; 7815 unsigned int pamax = arm_pamax(cpu); 7816 7817 switch (stride) { 7818 case 13: /* 64KB Pages. */ 7819 if (level == 0 || (level == 1 && pamax <= 42)) { 7820 return false; 7821 } 7822 break; 7823 case 11: /* 16KB Pages. */ 7824 if (level == 0 || (level == 1 && pamax <= 40)) { 7825 return false; 7826 } 7827 break; 7828 case 9: /* 4KB Pages. */ 7829 if (level == 0 && pamax <= 42) { 7830 return false; 7831 } 7832 break; 7833 default: 7834 g_assert_not_reached(); 7835 } 7836 7837 /* Inputsize checks. */ 7838 if (inputsize > pamax && 7839 (arm_el_is_aa64(env, 1) || inputsize > 40)) { 7840 /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */ 7841 return false; 7842 } 7843 } else { 7844 /* AArch32 only supports 4KB pages. Assert on that. */ 7845 assert(stride == 9); 7846 7847 if (level == 0) { 7848 return false; 7849 } 7850 } 7851 return true; 7852 } 7853 7854 static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, 7855 int access_type, ARMMMUIdx mmu_idx, 7856 hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, 7857 target_ulong *page_size_ptr, uint32_t *fsr, 7858 ARMMMUFaultInfo *fi) 7859 { 7860 ARMCPU *cpu = arm_env_get_cpu(env); 7861 CPUState *cs = CPU(cpu); 7862 /* Read an LPAE long-descriptor translation table. */ 7863 MMUFaultType fault_type = translation_fault; 7864 uint32_t level; 7865 uint32_t epd = 0; 7866 int32_t t0sz, t1sz; 7867 uint32_t tg; 7868 uint64_t ttbr; 7869 int ttbr_select; 7870 hwaddr descaddr, indexmask, indexmask_grainsize; 7871 uint32_t tableattrs; 7872 target_ulong page_size; 7873 uint32_t attrs; 7874 int32_t stride = 9; 7875 int32_t addrsize; 7876 int inputsize; 7877 int32_t tbi = 0; 7878 TCR *tcr = regime_tcr(env, mmu_idx); 7879 int ap, ns, xn, pxn; 7880 uint32_t el = regime_el(env, mmu_idx); 7881 bool ttbr1_valid = true; 7882 uint64_t descaddrmask; 7883 bool aarch64 = arm_el_is_aa64(env, el); 7884 7885 /* TODO: 7886 * This code does not handle the different format TCR for VTCR_EL2. 7887 * This code also does not support shareability levels. 7888 * Attribute and permission bit handling should also be checked when adding 7889 * support for those page table walks. 7890 */ 7891 if (aarch64) { 7892 level = 0; 7893 addrsize = 64; 7894 if (el > 1) { 7895 if (mmu_idx != ARMMMUIdx_S2NS) { 7896 tbi = extract64(tcr->raw_tcr, 20, 1); 7897 } 7898 } else { 7899 if (extract64(address, 55, 1)) { 7900 tbi = extract64(tcr->raw_tcr, 38, 1); 7901 } else { 7902 tbi = extract64(tcr->raw_tcr, 37, 1); 7903 } 7904 } 7905 tbi *= 8; 7906 7907 /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it 7908 * invalid. 7909 */ 7910 if (el > 1) { 7911 ttbr1_valid = false; 7912 } 7913 } else { 7914 level = 1; 7915 addrsize = 32; 7916 /* There is no TTBR1 for EL2 */ 7917 if (el == 2) { 7918 ttbr1_valid = false; 7919 } 7920 } 7921 7922 /* Determine whether this address is in the region controlled by 7923 * TTBR0 or TTBR1 (or if it is in neither region and should fault). 7924 * This is a Non-secure PL0/1 stage 1 translation, so controlled by 7925 * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32: 7926 */ 7927 if (aarch64) { 7928 /* AArch64 translation. */ 7929 t0sz = extract32(tcr->raw_tcr, 0, 6); 7930 t0sz = MIN(t0sz, 39); 7931 t0sz = MAX(t0sz, 16); 7932 } else if (mmu_idx != ARMMMUIdx_S2NS) { 7933 /* AArch32 stage 1 translation. */ 7934 t0sz = extract32(tcr->raw_tcr, 0, 3); 7935 } else { 7936 /* AArch32 stage 2 translation. */ 7937 bool sext = extract32(tcr->raw_tcr, 4, 1); 7938 bool sign = extract32(tcr->raw_tcr, 3, 1); 7939 /* Address size is 40-bit for a stage 2 translation, 7940 * and t0sz can be negative (from -8 to 7), 7941 * so we need to adjust it to use the TTBR selecting logic below. 7942 */ 7943 addrsize = 40; 7944 t0sz = sextract32(tcr->raw_tcr, 0, 4) + 8; 7945 7946 /* If the sign-extend bit is not the same as t0sz[3], the result 7947 * is unpredictable. Flag this as a guest error. */ 7948 if (sign != sext) { 7949 qemu_log_mask(LOG_GUEST_ERROR, 7950 "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n"); 7951 } 7952 } 7953 t1sz = extract32(tcr->raw_tcr, 16, 6); 7954 if (aarch64) { 7955 t1sz = MIN(t1sz, 39); 7956 t1sz = MAX(t1sz, 16); 7957 } 7958 if (t0sz && !extract64(address, addrsize - t0sz, t0sz - tbi)) { 7959 /* there is a ttbr0 region and we are in it (high bits all zero) */ 7960 ttbr_select = 0; 7961 } else if (ttbr1_valid && t1sz && 7962 !extract64(~address, addrsize - t1sz, t1sz - tbi)) { 7963 /* there is a ttbr1 region and we are in it (high bits all one) */ 7964 ttbr_select = 1; 7965 } else if (!t0sz) { 7966 /* ttbr0 region is "everything not in the ttbr1 region" */ 7967 ttbr_select = 0; 7968 } else if (!t1sz && ttbr1_valid) { 7969 /* ttbr1 region is "everything not in the ttbr0 region" */ 7970 ttbr_select = 1; 7971 } else { 7972 /* in the gap between the two regions, this is a Translation fault */ 7973 fault_type = translation_fault; 7974 goto do_fault; 7975 } 7976 7977 /* Note that QEMU ignores shareability and cacheability attributes, 7978 * so we don't need to do anything with the SH, ORGN, IRGN fields 7979 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the 7980 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently 7981 * implement any ASID-like capability so we can ignore it (instead 7982 * we will always flush the TLB any time the ASID is changed). 7983 */ 7984 if (ttbr_select == 0) { 7985 ttbr = regime_ttbr(env, mmu_idx, 0); 7986 if (el < 2) { 7987 epd = extract32(tcr->raw_tcr, 7, 1); 7988 } 7989 inputsize = addrsize - t0sz; 7990 7991 tg = extract32(tcr->raw_tcr, 14, 2); 7992 if (tg == 1) { /* 64KB pages */ 7993 stride = 13; 7994 } 7995 if (tg == 2) { /* 16KB pages */ 7996 stride = 11; 7997 } 7998 } else { 7999 /* We should only be here if TTBR1 is valid */ 8000 assert(ttbr1_valid); 8001 8002 ttbr = regime_ttbr(env, mmu_idx, 1); 8003 epd = extract32(tcr->raw_tcr, 23, 1); 8004 inputsize = addrsize - t1sz; 8005 8006 tg = extract32(tcr->raw_tcr, 30, 2); 8007 if (tg == 3) { /* 64KB pages */ 8008 stride = 13; 8009 } 8010 if (tg == 1) { /* 16KB pages */ 8011 stride = 11; 8012 } 8013 } 8014 8015 /* Here we should have set up all the parameters for the translation: 8016 * inputsize, ttbr, epd, stride, tbi 8017 */ 8018 8019 if (epd) { 8020 /* Translation table walk disabled => Translation fault on TLB miss 8021 * Note: This is always 0 on 64-bit EL2 and EL3. 8022 */ 8023 goto do_fault; 8024 } 8025 8026 if (mmu_idx != ARMMMUIdx_S2NS) { 8027 /* The starting level depends on the virtual address size (which can 8028 * be up to 48 bits) and the translation granule size. It indicates 8029 * the number of strides (stride bits at a time) needed to 8030 * consume the bits of the input address. In the pseudocode this is: 8031 * level = 4 - RoundUp((inputsize - grainsize) / stride) 8032 * where their 'inputsize' is our 'inputsize', 'grainsize' is 8033 * our 'stride + 3' and 'stride' is our 'stride'. 8034 * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying: 8035 * = 4 - (inputsize - stride - 3 + stride - 1) / stride 8036 * = 4 - (inputsize - 4) / stride; 8037 */ 8038 level = 4 - (inputsize - 4) / stride; 8039 } else { 8040 /* For stage 2 translations the starting level is specified by the 8041 * VTCR_EL2.SL0 field (whose interpretation depends on the page size) 8042 */ 8043 uint32_t sl0 = extract32(tcr->raw_tcr, 6, 2); 8044 uint32_t startlevel; 8045 bool ok; 8046 8047 if (!aarch64 || stride == 9) { 8048 /* AArch32 or 4KB pages */ 8049 startlevel = 2 - sl0; 8050 } else { 8051 /* 16KB or 64KB pages */ 8052 startlevel = 3 - sl0; 8053 } 8054 8055 /* Check that the starting level is valid. */ 8056 ok = check_s2_mmu_setup(cpu, aarch64, startlevel, 8057 inputsize, stride); 8058 if (!ok) { 8059 fault_type = translation_fault; 8060 goto do_fault; 8061 } 8062 level = startlevel; 8063 } 8064 8065 indexmask_grainsize = (1ULL << (stride + 3)) - 1; 8066 indexmask = (1ULL << (inputsize - (stride * (4 - level)))) - 1; 8067 8068 /* Now we can extract the actual base address from the TTBR */ 8069 descaddr = extract64(ttbr, 0, 48); 8070 descaddr &= ~indexmask; 8071 8072 /* The address field in the descriptor goes up to bit 39 for ARMv7 8073 * but up to bit 47 for ARMv8, but we use the descaddrmask 8074 * up to bit 39 for AArch32, because we don't need other bits in that case 8075 * to construct next descriptor address (anyway they should be all zeroes). 8076 */ 8077 descaddrmask = ((1ull << (aarch64 ? 48 : 40)) - 1) & 8078 ~indexmask_grainsize; 8079 8080 /* Secure accesses start with the page table in secure memory and 8081 * can be downgraded to non-secure at any step. Non-secure accesses 8082 * remain non-secure. We implement this by just ORing in the NSTable/NS 8083 * bits at each step. 8084 */ 8085 tableattrs = regime_is_secure(env, mmu_idx) ? 0 : (1 << 4); 8086 for (;;) { 8087 uint64_t descriptor; 8088 bool nstable; 8089 8090 descaddr |= (address >> (stride * (4 - level))) & indexmask; 8091 descaddr &= ~7ULL; 8092 nstable = extract32(tableattrs, 4, 1); 8093 descriptor = arm_ldq_ptw(cs, descaddr, !nstable, mmu_idx, fsr, fi); 8094 if (fi->s1ptw) { 8095 goto do_fault; 8096 } 8097 8098 if (!(descriptor & 1) || 8099 (!(descriptor & 2) && (level == 3))) { 8100 /* Invalid, or the Reserved level 3 encoding */ 8101 goto do_fault; 8102 } 8103 descaddr = descriptor & descaddrmask; 8104 8105 if ((descriptor & 2) && (level < 3)) { 8106 /* Table entry. The top five bits are attributes which may 8107 * propagate down through lower levels of the table (and 8108 * which are all arranged so that 0 means "no effect", so 8109 * we can gather them up by ORing in the bits at each level). 8110 */ 8111 tableattrs |= extract64(descriptor, 59, 5); 8112 level++; 8113 indexmask = indexmask_grainsize; 8114 continue; 8115 } 8116 /* Block entry at level 1 or 2, or page entry at level 3. 8117 * These are basically the same thing, although the number 8118 * of bits we pull in from the vaddr varies. 8119 */ 8120 page_size = (1ULL << ((stride * (4 - level)) + 3)); 8121 descaddr |= (address & (page_size - 1)); 8122 /* Extract attributes from the descriptor */ 8123 attrs = extract64(descriptor, 2, 10) 8124 | (extract64(descriptor, 52, 12) << 10); 8125 8126 if (mmu_idx == ARMMMUIdx_S2NS) { 8127 /* Stage 2 table descriptors do not include any attribute fields */ 8128 break; 8129 } 8130 /* Merge in attributes from table descriptors */ 8131 attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */ 8132 attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */ 8133 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1 8134 * means "force PL1 access only", which means forcing AP[1] to 0. 8135 */ 8136 if (extract32(tableattrs, 2, 1)) { 8137 attrs &= ~(1 << 4); 8138 } 8139 attrs |= nstable << 3; /* NS */ 8140 break; 8141 } 8142 /* Here descaddr is the final physical address, and attributes 8143 * are all in attrs. 8144 */ 8145 fault_type = access_fault; 8146 if ((attrs & (1 << 8)) == 0) { 8147 /* Access flag */ 8148 goto do_fault; 8149 } 8150 8151 ap = extract32(attrs, 4, 2); 8152 xn = extract32(attrs, 12, 1); 8153 8154 if (mmu_idx == ARMMMUIdx_S2NS) { 8155 ns = true; 8156 *prot = get_S2prot(env, ap, xn); 8157 } else { 8158 ns = extract32(attrs, 3, 1); 8159 pxn = extract32(attrs, 11, 1); 8160 *prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn); 8161 } 8162 8163 fault_type = permission_fault; 8164 if (!(*prot & (1 << access_type))) { 8165 goto do_fault; 8166 } 8167 8168 if (ns) { 8169 /* The NS bit will (as required by the architecture) have no effect if 8170 * the CPU doesn't support TZ or this is a non-secure translation 8171 * regime, because the attribute will already be non-secure. 8172 */ 8173 txattrs->secure = false; 8174 } 8175 *phys_ptr = descaddr; 8176 *page_size_ptr = page_size; 8177 return false; 8178 8179 do_fault: 8180 /* Long-descriptor format IFSR/DFSR value */ 8181 *fsr = (1 << 9) | (fault_type << 2) | level; 8182 /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */ 8183 fi->stage2 = fi->s1ptw || (mmu_idx == ARMMMUIdx_S2NS); 8184 return true; 8185 } 8186 8187 static inline void get_phys_addr_pmsav7_default(CPUARMState *env, 8188 ARMMMUIdx mmu_idx, 8189 int32_t address, int *prot) 8190 { 8191 if (!arm_feature(env, ARM_FEATURE_M)) { 8192 *prot = PAGE_READ | PAGE_WRITE; 8193 switch (address) { 8194 case 0xF0000000 ... 0xFFFFFFFF: 8195 if (regime_sctlr(env, mmu_idx) & SCTLR_V) { 8196 /* hivecs execing is ok */ 8197 *prot |= PAGE_EXEC; 8198 } 8199 break; 8200 case 0x00000000 ... 0x7FFFFFFF: 8201 *prot |= PAGE_EXEC; 8202 break; 8203 } 8204 } else { 8205 /* Default system address map for M profile cores. 8206 * The architecture specifies which regions are execute-never; 8207 * at the MPU level no other checks are defined. 8208 */ 8209 switch (address) { 8210 case 0x00000000 ... 0x1fffffff: /* ROM */ 8211 case 0x20000000 ... 0x3fffffff: /* SRAM */ 8212 case 0x60000000 ... 0x7fffffff: /* RAM */ 8213 case 0x80000000 ... 0x9fffffff: /* RAM */ 8214 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 8215 break; 8216 case 0x40000000 ... 0x5fffffff: /* Peripheral */ 8217 case 0xa0000000 ... 0xbfffffff: /* Device */ 8218 case 0xc0000000 ... 0xdfffffff: /* Device */ 8219 case 0xe0000000 ... 0xffffffff: /* System */ 8220 *prot = PAGE_READ | PAGE_WRITE; 8221 break; 8222 default: 8223 g_assert_not_reached(); 8224 } 8225 } 8226 } 8227 8228 static bool pmsav7_use_background_region(ARMCPU *cpu, 8229 ARMMMUIdx mmu_idx, bool is_user) 8230 { 8231 /* Return true if we should use the default memory map as a 8232 * "background" region if there are no hits against any MPU regions. 8233 */ 8234 CPUARMState *env = &cpu->env; 8235 8236 if (is_user) { 8237 return false; 8238 } 8239 8240 if (arm_feature(env, ARM_FEATURE_M)) { 8241 return env->v7m.mpu_ctrl & R_V7M_MPU_CTRL_PRIVDEFENA_MASK; 8242 } else { 8243 return regime_sctlr(env, mmu_idx) & SCTLR_BR; 8244 } 8245 } 8246 8247 static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, 8248 int access_type, ARMMMUIdx mmu_idx, 8249 hwaddr *phys_ptr, int *prot, uint32_t *fsr) 8250 { 8251 ARMCPU *cpu = arm_env_get_cpu(env); 8252 int n; 8253 bool is_user = regime_is_user(env, mmu_idx); 8254 8255 *phys_ptr = address; 8256 *prot = 0; 8257 8258 if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */ 8259 get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); 8260 } else { /* MPU enabled */ 8261 for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) { 8262 /* region search */ 8263 uint32_t base = env->pmsav7.drbar[n]; 8264 uint32_t rsize = extract32(env->pmsav7.drsr[n], 1, 5); 8265 uint32_t rmask; 8266 bool srdis = false; 8267 8268 if (!(env->pmsav7.drsr[n] & 0x1)) { 8269 continue; 8270 } 8271 8272 if (!rsize) { 8273 qemu_log_mask(LOG_GUEST_ERROR, 8274 "DRSR[%d]: Rsize field cannot be 0\n", n); 8275 continue; 8276 } 8277 rsize++; 8278 rmask = (1ull << rsize) - 1; 8279 8280 if (base & rmask) { 8281 qemu_log_mask(LOG_GUEST_ERROR, 8282 "DRBAR[%d]: 0x%" PRIx32 " misaligned " 8283 "to DRSR region size, mask = 0x%" PRIx32 "\n", 8284 n, base, rmask); 8285 continue; 8286 } 8287 8288 if (address < base || address > base + rmask) { 8289 continue; 8290 } 8291 8292 /* Region matched */ 8293 8294 if (rsize >= 8) { /* no subregions for regions < 256 bytes */ 8295 int i, snd; 8296 uint32_t srdis_mask; 8297 8298 rsize -= 3; /* sub region size (power of 2) */ 8299 snd = ((address - base) >> rsize) & 0x7; 8300 srdis = extract32(env->pmsav7.drsr[n], snd + 8, 1); 8301 8302 srdis_mask = srdis ? 0x3 : 0x0; 8303 for (i = 2; i <= 8 && rsize < TARGET_PAGE_BITS; i *= 2) { 8304 /* This will check in groups of 2, 4 and then 8, whether 8305 * the subregion bits are consistent. rsize is incremented 8306 * back up to give the region size, considering consistent 8307 * adjacent subregions as one region. Stop testing if rsize 8308 * is already big enough for an entire QEMU page. 8309 */ 8310 int snd_rounded = snd & ~(i - 1); 8311 uint32_t srdis_multi = extract32(env->pmsav7.drsr[n], 8312 snd_rounded + 8, i); 8313 if (srdis_mask ^ srdis_multi) { 8314 break; 8315 } 8316 srdis_mask = (srdis_mask << i) | srdis_mask; 8317 rsize++; 8318 } 8319 } 8320 if (rsize < TARGET_PAGE_BITS) { 8321 qemu_log_mask(LOG_UNIMP, 8322 "DRSR[%d]: No support for MPU (sub)region " 8323 "alignment of %" PRIu32 " bits. Minimum is %d\n", 8324 n, rsize, TARGET_PAGE_BITS); 8325 continue; 8326 } 8327 if (srdis) { 8328 continue; 8329 } 8330 break; 8331 } 8332 8333 if (n == -1) { /* no hits */ 8334 if (!pmsav7_use_background_region(cpu, mmu_idx, is_user)) { 8335 /* background fault */ 8336 *fsr = 0; 8337 return true; 8338 } 8339 get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); 8340 } else { /* a MPU hit! */ 8341 uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3); 8342 8343 if (is_user) { /* User mode AP bit decoding */ 8344 switch (ap) { 8345 case 0: 8346 case 1: 8347 case 5: 8348 break; /* no access */ 8349 case 3: 8350 *prot |= PAGE_WRITE; 8351 /* fall through */ 8352 case 2: 8353 case 6: 8354 *prot |= PAGE_READ | PAGE_EXEC; 8355 break; 8356 default: 8357 qemu_log_mask(LOG_GUEST_ERROR, 8358 "DRACR[%d]: Bad value for AP bits: 0x%" 8359 PRIx32 "\n", n, ap); 8360 } 8361 } else { /* Priv. mode AP bits decoding */ 8362 switch (ap) { 8363 case 0: 8364 break; /* no access */ 8365 case 1: 8366 case 2: 8367 case 3: 8368 *prot |= PAGE_WRITE; 8369 /* fall through */ 8370 case 5: 8371 case 6: 8372 *prot |= PAGE_READ | PAGE_EXEC; 8373 break; 8374 default: 8375 qemu_log_mask(LOG_GUEST_ERROR, 8376 "DRACR[%d]: Bad value for AP bits: 0x%" 8377 PRIx32 "\n", n, ap); 8378 } 8379 } 8380 8381 /* execute never */ 8382 if (env->pmsav7.dracr[n] & (1 << 12)) { 8383 *prot &= ~PAGE_EXEC; 8384 } 8385 } 8386 } 8387 8388 *fsr = 0x00d; /* Permission fault */ 8389 return !(*prot & (1 << access_type)); 8390 } 8391 8392 static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, 8393 int access_type, ARMMMUIdx mmu_idx, 8394 hwaddr *phys_ptr, int *prot, uint32_t *fsr) 8395 { 8396 int n; 8397 uint32_t mask; 8398 uint32_t base; 8399 bool is_user = regime_is_user(env, mmu_idx); 8400 8401 *phys_ptr = address; 8402 for (n = 7; n >= 0; n--) { 8403 base = env->cp15.c6_region[n]; 8404 if ((base & 1) == 0) { 8405 continue; 8406 } 8407 mask = 1 << ((base >> 1) & 0x1f); 8408 /* Keep this shift separate from the above to avoid an 8409 (undefined) << 32. */ 8410 mask = (mask << 1) - 1; 8411 if (((base ^ address) & ~mask) == 0) { 8412 break; 8413 } 8414 } 8415 if (n < 0) { 8416 *fsr = 2; 8417 return true; 8418 } 8419 8420 if (access_type == 2) { 8421 mask = env->cp15.pmsav5_insn_ap; 8422 } else { 8423 mask = env->cp15.pmsav5_data_ap; 8424 } 8425 mask = (mask >> (n * 4)) & 0xf; 8426 switch (mask) { 8427 case 0: 8428 *fsr = 1; 8429 return true; 8430 case 1: 8431 if (is_user) { 8432 *fsr = 1; 8433 return true; 8434 } 8435 *prot = PAGE_READ | PAGE_WRITE; 8436 break; 8437 case 2: 8438 *prot = PAGE_READ; 8439 if (!is_user) { 8440 *prot |= PAGE_WRITE; 8441 } 8442 break; 8443 case 3: 8444 *prot = PAGE_READ | PAGE_WRITE; 8445 break; 8446 case 5: 8447 if (is_user) { 8448 *fsr = 1; 8449 return true; 8450 } 8451 *prot = PAGE_READ; 8452 break; 8453 case 6: 8454 *prot = PAGE_READ; 8455 break; 8456 default: 8457 /* Bad permission. */ 8458 *fsr = 1; 8459 return true; 8460 } 8461 *prot |= PAGE_EXEC; 8462 return false; 8463 } 8464 8465 /* get_phys_addr - get the physical address for this virtual address 8466 * 8467 * Find the physical address corresponding to the given virtual address, 8468 * by doing a translation table walk on MMU based systems or using the 8469 * MPU state on MPU based systems. 8470 * 8471 * Returns false if the translation was successful. Otherwise, phys_ptr, attrs, 8472 * prot and page_size may not be filled in, and the populated fsr value provides 8473 * information on why the translation aborted, in the format of a 8474 * DFSR/IFSR fault register, with the following caveats: 8475 * * we honour the short vs long DFSR format differences. 8476 * * the WnR bit is never set (the caller must do this). 8477 * * for PSMAv5 based systems we don't bother to return a full FSR format 8478 * value. 8479 * 8480 * @env: CPUARMState 8481 * @address: virtual address to get physical address for 8482 * @access_type: 0 for read, 1 for write, 2 for execute 8483 * @mmu_idx: MMU index indicating required translation regime 8484 * @phys_ptr: set to the physical address corresponding to the virtual address 8485 * @attrs: set to the memory transaction attributes to use 8486 * @prot: set to the permissions for the page containing phys_ptr 8487 * @page_size: set to the size of the page containing phys_ptr 8488 * @fsr: set to the DFSR/IFSR value on failure 8489 */ 8490 static bool get_phys_addr(CPUARMState *env, target_ulong address, 8491 int access_type, ARMMMUIdx mmu_idx, 8492 hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, 8493 target_ulong *page_size, uint32_t *fsr, 8494 ARMMMUFaultInfo *fi) 8495 { 8496 if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { 8497 /* Call ourselves recursively to do the stage 1 and then stage 2 8498 * translations. 8499 */ 8500 if (arm_feature(env, ARM_FEATURE_EL2)) { 8501 hwaddr ipa; 8502 int s2_prot; 8503 int ret; 8504 8505 ret = get_phys_addr(env, address, access_type, 8506 stage_1_mmu_idx(mmu_idx), &ipa, attrs, 8507 prot, page_size, fsr, fi); 8508 8509 /* If S1 fails or S2 is disabled, return early. */ 8510 if (ret || regime_translation_disabled(env, ARMMMUIdx_S2NS)) { 8511 *phys_ptr = ipa; 8512 return ret; 8513 } 8514 8515 /* S1 is done. Now do S2 translation. */ 8516 ret = get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_S2NS, 8517 phys_ptr, attrs, &s2_prot, 8518 page_size, fsr, fi); 8519 fi->s2addr = ipa; 8520 /* Combine the S1 and S2 perms. */ 8521 *prot &= s2_prot; 8522 return ret; 8523 } else { 8524 /* 8525 * For non-EL2 CPUs a stage1+stage2 translation is just stage 1. 8526 */ 8527 mmu_idx = stage_1_mmu_idx(mmu_idx); 8528 } 8529 } 8530 8531 /* The page table entries may downgrade secure to non-secure, but 8532 * cannot upgrade an non-secure translation regime's attributes 8533 * to secure. 8534 */ 8535 attrs->secure = regime_is_secure(env, mmu_idx); 8536 attrs->user = regime_is_user(env, mmu_idx); 8537 8538 /* Fast Context Switch Extension. This doesn't exist at all in v8. 8539 * In v7 and earlier it affects all stage 1 translations. 8540 */ 8541 if (address < 0x02000000 && mmu_idx != ARMMMUIdx_S2NS 8542 && !arm_feature(env, ARM_FEATURE_V8)) { 8543 if (regime_el(env, mmu_idx) == 3) { 8544 address += env->cp15.fcseidr_s; 8545 } else { 8546 address += env->cp15.fcseidr_ns; 8547 } 8548 } 8549 8550 /* pmsav7 has special handling for when MPU is disabled so call it before 8551 * the common MMU/MPU disabled check below. 8552 */ 8553 if (arm_feature(env, ARM_FEATURE_PMSA) && 8554 arm_feature(env, ARM_FEATURE_V7)) { 8555 bool ret; 8556 *page_size = TARGET_PAGE_SIZE; 8557 ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx, 8558 phys_ptr, prot, fsr); 8559 qemu_log_mask(CPU_LOG_MMU, "PMSAv7 MPU lookup for %s at 0x%08" PRIx32 8560 " mmu_idx %u -> %s (prot %c%c%c)\n", 8561 access_type == 1 ? "reading" : 8562 (access_type == 2 ? "writing" : "execute"), 8563 (uint32_t)address, mmu_idx, 8564 ret ? "Miss" : "Hit", 8565 *prot & PAGE_READ ? 'r' : '-', 8566 *prot & PAGE_WRITE ? 'w' : '-', 8567 *prot & PAGE_EXEC ? 'x' : '-'); 8568 8569 return ret; 8570 } 8571 8572 if (regime_translation_disabled(env, mmu_idx)) { 8573 /* MMU/MPU disabled. */ 8574 *phys_ptr = address; 8575 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 8576 *page_size = TARGET_PAGE_SIZE; 8577 return 0; 8578 } 8579 8580 if (arm_feature(env, ARM_FEATURE_PMSA)) { 8581 /* Pre-v7 MPU */ 8582 *page_size = TARGET_PAGE_SIZE; 8583 return get_phys_addr_pmsav5(env, address, access_type, mmu_idx, 8584 phys_ptr, prot, fsr); 8585 } 8586 8587 if (regime_using_lpae_format(env, mmu_idx)) { 8588 return get_phys_addr_lpae(env, address, access_type, mmu_idx, phys_ptr, 8589 attrs, prot, page_size, fsr, fi); 8590 } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { 8591 return get_phys_addr_v6(env, address, access_type, mmu_idx, phys_ptr, 8592 attrs, prot, page_size, fsr, fi); 8593 } else { 8594 return get_phys_addr_v5(env, address, access_type, mmu_idx, phys_ptr, 8595 prot, page_size, fsr, fi); 8596 } 8597 } 8598 8599 /* Walk the page table and (if the mapping exists) add the page 8600 * to the TLB. Return false on success, or true on failure. Populate 8601 * fsr with ARM DFSR/IFSR fault register format value on failure. 8602 */ 8603 bool arm_tlb_fill(CPUState *cs, vaddr address, 8604 int access_type, int mmu_idx, uint32_t *fsr, 8605 ARMMMUFaultInfo *fi) 8606 { 8607 ARMCPU *cpu = ARM_CPU(cs); 8608 CPUARMState *env = &cpu->env; 8609 hwaddr phys_addr; 8610 target_ulong page_size; 8611 int prot; 8612 int ret; 8613 MemTxAttrs attrs = {}; 8614 8615 ret = get_phys_addr(env, address, access_type, 8616 core_to_arm_mmu_idx(env, mmu_idx), &phys_addr, 8617 &attrs, &prot, &page_size, fsr, fi); 8618 if (!ret) { 8619 /* Map a single [sub]page. */ 8620 phys_addr &= TARGET_PAGE_MASK; 8621 address &= TARGET_PAGE_MASK; 8622 tlb_set_page_with_attrs(cs, address, phys_addr, attrs, 8623 prot, mmu_idx, page_size); 8624 return 0; 8625 } 8626 8627 return ret; 8628 } 8629 8630 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, 8631 MemTxAttrs *attrs) 8632 { 8633 ARMCPU *cpu = ARM_CPU(cs); 8634 CPUARMState *env = &cpu->env; 8635 hwaddr phys_addr; 8636 target_ulong page_size; 8637 int prot; 8638 bool ret; 8639 uint32_t fsr; 8640 ARMMMUFaultInfo fi = {}; 8641 ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false)); 8642 8643 *attrs = (MemTxAttrs) {}; 8644 8645 ret = get_phys_addr(env, addr, 0, mmu_idx, &phys_addr, 8646 attrs, &prot, &page_size, &fsr, &fi); 8647 8648 if (ret) { 8649 return -1; 8650 } 8651 return phys_addr; 8652 } 8653 8654 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) 8655 { 8656 uint32_t mask; 8657 unsigned el = arm_current_el(env); 8658 8659 /* First handle registers which unprivileged can read */ 8660 8661 switch (reg) { 8662 case 0 ... 7: /* xPSR sub-fields */ 8663 mask = 0; 8664 if ((reg & 1) && el) { 8665 mask |= 0x000001ff; /* IPSR (unpriv. reads as zero) */ 8666 } 8667 if (!(reg & 4)) { 8668 mask |= 0xf8000000; /* APSR */ 8669 } 8670 /* EPSR reads as zero */ 8671 return xpsr_read(env) & mask; 8672 break; 8673 case 20: /* CONTROL */ 8674 return env->v7m.control; 8675 } 8676 8677 if (el == 0) { 8678 return 0; /* unprivileged reads others as zero */ 8679 } 8680 8681 switch (reg) { 8682 case 8: /* MSP */ 8683 return (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) ? 8684 env->v7m.other_sp : env->regs[13]; 8685 case 9: /* PSP */ 8686 return (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) ? 8687 env->regs[13] : env->v7m.other_sp; 8688 case 16: /* PRIMASK */ 8689 return (env->daif & PSTATE_I) != 0; 8690 case 17: /* BASEPRI */ 8691 case 18: /* BASEPRI_MAX */ 8692 return env->v7m.basepri; 8693 case 19: /* FAULTMASK */ 8694 return (env->daif & PSTATE_F) != 0; 8695 default: 8696 qemu_log_mask(LOG_GUEST_ERROR, "Attempt to read unknown special" 8697 " register %d\n", reg); 8698 return 0; 8699 } 8700 } 8701 8702 void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) 8703 { 8704 /* We're passed bits [11..0] of the instruction; extract 8705 * SYSm and the mask bits. 8706 * Invalid combinations of SYSm and mask are UNPREDICTABLE; 8707 * we choose to treat them as if the mask bits were valid. 8708 * NB that the pseudocode 'mask' variable is bits [11..10], 8709 * whereas ours is [11..8]. 8710 */ 8711 uint32_t mask = extract32(maskreg, 8, 4); 8712 uint32_t reg = extract32(maskreg, 0, 8); 8713 8714 if (arm_current_el(env) == 0 && reg > 7) { 8715 /* only xPSR sub-fields may be written by unprivileged */ 8716 return; 8717 } 8718 8719 switch (reg) { 8720 case 0 ... 7: /* xPSR sub-fields */ 8721 /* only APSR is actually writable */ 8722 if (!(reg & 4)) { 8723 uint32_t apsrmask = 0; 8724 8725 if (mask & 8) { 8726 apsrmask |= 0xf8000000; /* APSR NZCVQ */ 8727 } 8728 if ((mask & 4) && arm_feature(env, ARM_FEATURE_THUMB_DSP)) { 8729 apsrmask |= 0x000f0000; /* APSR GE[3:0] */ 8730 } 8731 xpsr_write(env, val, apsrmask); 8732 } 8733 break; 8734 case 8: /* MSP */ 8735 if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) { 8736 env->v7m.other_sp = val; 8737 } else { 8738 env->regs[13] = val; 8739 } 8740 break; 8741 case 9: /* PSP */ 8742 if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) { 8743 env->regs[13] = val; 8744 } else { 8745 env->v7m.other_sp = val; 8746 } 8747 break; 8748 case 16: /* PRIMASK */ 8749 if (val & 1) { 8750 env->daif |= PSTATE_I; 8751 } else { 8752 env->daif &= ~PSTATE_I; 8753 } 8754 break; 8755 case 17: /* BASEPRI */ 8756 env->v7m.basepri = val & 0xff; 8757 break; 8758 case 18: /* BASEPRI_MAX */ 8759 val &= 0xff; 8760 if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0)) 8761 env->v7m.basepri = val; 8762 break; 8763 case 19: /* FAULTMASK */ 8764 if (val & 1) { 8765 env->daif |= PSTATE_F; 8766 } else { 8767 env->daif &= ~PSTATE_F; 8768 } 8769 break; 8770 case 20: /* CONTROL */ 8771 switch_v7m_sp(env, (val & R_V7M_CONTROL_SPSEL_MASK) != 0); 8772 env->v7m.control = val & (R_V7M_CONTROL_SPSEL_MASK | 8773 R_V7M_CONTROL_NPRIV_MASK); 8774 break; 8775 default: 8776 qemu_log_mask(LOG_GUEST_ERROR, "Attempt to write unknown special" 8777 " register %d\n", reg); 8778 return; 8779 } 8780 } 8781 8782 #endif 8783 8784 void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in) 8785 { 8786 /* Implement DC ZVA, which zeroes a fixed-length block of memory. 8787 * Note that we do not implement the (architecturally mandated) 8788 * alignment fault for attempts to use this on Device memory 8789 * (which matches the usual QEMU behaviour of not implementing either 8790 * alignment faults or any memory attribute handling). 8791 */ 8792 8793 ARMCPU *cpu = arm_env_get_cpu(env); 8794 uint64_t blocklen = 4 << cpu->dcz_blocksize; 8795 uint64_t vaddr = vaddr_in & ~(blocklen - 1); 8796 8797 #ifndef CONFIG_USER_ONLY 8798 { 8799 /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than 8800 * the block size so we might have to do more than one TLB lookup. 8801 * We know that in fact for any v8 CPU the page size is at least 4K 8802 * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only 8803 * 1K as an artefact of legacy v5 subpage support being present in the 8804 * same QEMU executable. 8805 */ 8806 int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE); 8807 void *hostaddr[maxidx]; 8808 int try, i; 8809 unsigned mmu_idx = cpu_mmu_index(env, false); 8810 TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx); 8811 8812 for (try = 0; try < 2; try++) { 8813 8814 for (i = 0; i < maxidx; i++) { 8815 hostaddr[i] = tlb_vaddr_to_host(env, 8816 vaddr + TARGET_PAGE_SIZE * i, 8817 1, mmu_idx); 8818 if (!hostaddr[i]) { 8819 break; 8820 } 8821 } 8822 if (i == maxidx) { 8823 /* If it's all in the TLB it's fair game for just writing to; 8824 * we know we don't need to update dirty status, etc. 8825 */ 8826 for (i = 0; i < maxidx - 1; i++) { 8827 memset(hostaddr[i], 0, TARGET_PAGE_SIZE); 8828 } 8829 memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE)); 8830 return; 8831 } 8832 /* OK, try a store and see if we can populate the tlb. This 8833 * might cause an exception if the memory isn't writable, 8834 * in which case we will longjmp out of here. We must for 8835 * this purpose use the actual register value passed to us 8836 * so that we get the fault address right. 8837 */ 8838 helper_ret_stb_mmu(env, vaddr_in, 0, oi, GETPC()); 8839 /* Now we can populate the other TLB entries, if any */ 8840 for (i = 0; i < maxidx; i++) { 8841 uint64_t va = vaddr + TARGET_PAGE_SIZE * i; 8842 if (va != (vaddr_in & TARGET_PAGE_MASK)) { 8843 helper_ret_stb_mmu(env, va, 0, oi, GETPC()); 8844 } 8845 } 8846 } 8847 8848 /* Slow path (probably attempt to do this to an I/O device or 8849 * similar, or clearing of a block of code we have translations 8850 * cached for). Just do a series of byte writes as the architecture 8851 * demands. It's not worth trying to use a cpu_physical_memory_map(), 8852 * memset(), unmap() sequence here because: 8853 * + we'd need to account for the blocksize being larger than a page 8854 * + the direct-RAM access case is almost always going to be dealt 8855 * with in the fastpath code above, so there's no speed benefit 8856 * + we would have to deal with the map returning NULL because the 8857 * bounce buffer was in use 8858 */ 8859 for (i = 0; i < blocklen; i++) { 8860 helper_ret_stb_mmu(env, vaddr + i, 0, oi, GETPC()); 8861 } 8862 } 8863 #else 8864 memset(g2h(vaddr), 0, blocklen); 8865 #endif 8866 } 8867 8868 /* Note that signed overflow is undefined in C. The following routines are 8869 careful to use unsigned types where modulo arithmetic is required. 8870 Failure to do so _will_ break on newer gcc. */ 8871 8872 /* Signed saturating arithmetic. */ 8873 8874 /* Perform 16-bit signed saturating addition. */ 8875 static inline uint16_t add16_sat(uint16_t a, uint16_t b) 8876 { 8877 uint16_t res; 8878 8879 res = a + b; 8880 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) { 8881 if (a & 0x8000) 8882 res = 0x8000; 8883 else 8884 res = 0x7fff; 8885 } 8886 return res; 8887 } 8888 8889 /* Perform 8-bit signed saturating addition. */ 8890 static inline uint8_t add8_sat(uint8_t a, uint8_t b) 8891 { 8892 uint8_t res; 8893 8894 res = a + b; 8895 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) { 8896 if (a & 0x80) 8897 res = 0x80; 8898 else 8899 res = 0x7f; 8900 } 8901 return res; 8902 } 8903 8904 /* Perform 16-bit signed saturating subtraction. */ 8905 static inline uint16_t sub16_sat(uint16_t a, uint16_t b) 8906 { 8907 uint16_t res; 8908 8909 res = a - b; 8910 if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) { 8911 if (a & 0x8000) 8912 res = 0x8000; 8913 else 8914 res = 0x7fff; 8915 } 8916 return res; 8917 } 8918 8919 /* Perform 8-bit signed saturating subtraction. */ 8920 static inline uint8_t sub8_sat(uint8_t a, uint8_t b) 8921 { 8922 uint8_t res; 8923 8924 res = a - b; 8925 if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) { 8926 if (a & 0x80) 8927 res = 0x80; 8928 else 8929 res = 0x7f; 8930 } 8931 return res; 8932 } 8933 8934 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16); 8935 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16); 8936 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8); 8937 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8); 8938 #define PFX q 8939 8940 #include "op_addsub.h" 8941 8942 /* Unsigned saturating arithmetic. */ 8943 static inline uint16_t add16_usat(uint16_t a, uint16_t b) 8944 { 8945 uint16_t res; 8946 res = a + b; 8947 if (res < a) 8948 res = 0xffff; 8949 return res; 8950 } 8951 8952 static inline uint16_t sub16_usat(uint16_t a, uint16_t b) 8953 { 8954 if (a > b) 8955 return a - b; 8956 else 8957 return 0; 8958 } 8959 8960 static inline uint8_t add8_usat(uint8_t a, uint8_t b) 8961 { 8962 uint8_t res; 8963 res = a + b; 8964 if (res < a) 8965 res = 0xff; 8966 return res; 8967 } 8968 8969 static inline uint8_t sub8_usat(uint8_t a, uint8_t b) 8970 { 8971 if (a > b) 8972 return a - b; 8973 else 8974 return 0; 8975 } 8976 8977 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16); 8978 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16); 8979 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8); 8980 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8); 8981 #define PFX uq 8982 8983 #include "op_addsub.h" 8984 8985 /* Signed modulo arithmetic. */ 8986 #define SARITH16(a, b, n, op) do { \ 8987 int32_t sum; \ 8988 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \ 8989 RESULT(sum, n, 16); \ 8990 if (sum >= 0) \ 8991 ge |= 3 << (n * 2); \ 8992 } while(0) 8993 8994 #define SARITH8(a, b, n, op) do { \ 8995 int32_t sum; \ 8996 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \ 8997 RESULT(sum, n, 8); \ 8998 if (sum >= 0) \ 8999 ge |= 1 << n; \ 9000 } while(0) 9001 9002 9003 #define ADD16(a, b, n) SARITH16(a, b, n, +) 9004 #define SUB16(a, b, n) SARITH16(a, b, n, -) 9005 #define ADD8(a, b, n) SARITH8(a, b, n, +) 9006 #define SUB8(a, b, n) SARITH8(a, b, n, -) 9007 #define PFX s 9008 #define ARITH_GE 9009 9010 #include "op_addsub.h" 9011 9012 /* Unsigned modulo arithmetic. */ 9013 #define ADD16(a, b, n) do { \ 9014 uint32_t sum; \ 9015 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \ 9016 RESULT(sum, n, 16); \ 9017 if ((sum >> 16) == 1) \ 9018 ge |= 3 << (n * 2); \ 9019 } while(0) 9020 9021 #define ADD8(a, b, n) do { \ 9022 uint32_t sum; \ 9023 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \ 9024 RESULT(sum, n, 8); \ 9025 if ((sum >> 8) == 1) \ 9026 ge |= 1 << n; \ 9027 } while(0) 9028 9029 #define SUB16(a, b, n) do { \ 9030 uint32_t sum; \ 9031 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \ 9032 RESULT(sum, n, 16); \ 9033 if ((sum >> 16) == 0) \ 9034 ge |= 3 << (n * 2); \ 9035 } while(0) 9036 9037 #define SUB8(a, b, n) do { \ 9038 uint32_t sum; \ 9039 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \ 9040 RESULT(sum, n, 8); \ 9041 if ((sum >> 8) == 0) \ 9042 ge |= 1 << n; \ 9043 } while(0) 9044 9045 #define PFX u 9046 #define ARITH_GE 9047 9048 #include "op_addsub.h" 9049 9050 /* Halved signed arithmetic. */ 9051 #define ADD16(a, b, n) \ 9052 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16) 9053 #define SUB16(a, b, n) \ 9054 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16) 9055 #define ADD8(a, b, n) \ 9056 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8) 9057 #define SUB8(a, b, n) \ 9058 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8) 9059 #define PFX sh 9060 9061 #include "op_addsub.h" 9062 9063 /* Halved unsigned arithmetic. */ 9064 #define ADD16(a, b, n) \ 9065 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16) 9066 #define SUB16(a, b, n) \ 9067 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16) 9068 #define ADD8(a, b, n) \ 9069 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8) 9070 #define SUB8(a, b, n) \ 9071 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8) 9072 #define PFX uh 9073 9074 #include "op_addsub.h" 9075 9076 static inline uint8_t do_usad(uint8_t a, uint8_t b) 9077 { 9078 if (a > b) 9079 return a - b; 9080 else 9081 return b - a; 9082 } 9083 9084 /* Unsigned sum of absolute byte differences. */ 9085 uint32_t HELPER(usad8)(uint32_t a, uint32_t b) 9086 { 9087 uint32_t sum; 9088 sum = do_usad(a, b); 9089 sum += do_usad(a >> 8, b >> 8); 9090 sum += do_usad(a >> 16, b >>16); 9091 sum += do_usad(a >> 24, b >> 24); 9092 return sum; 9093 } 9094 9095 /* For ARMv6 SEL instruction. */ 9096 uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b) 9097 { 9098 uint32_t mask; 9099 9100 mask = 0; 9101 if (flags & 1) 9102 mask |= 0xff; 9103 if (flags & 2) 9104 mask |= 0xff00; 9105 if (flags & 4) 9106 mask |= 0xff0000; 9107 if (flags & 8) 9108 mask |= 0xff000000; 9109 return (a & mask) | (b & ~mask); 9110 } 9111 9112 /* VFP support. We follow the convention used for VFP instructions: 9113 Single precision routines have a "s" suffix, double precision a 9114 "d" suffix. */ 9115 9116 /* Convert host exception flags to vfp form. */ 9117 static inline int vfp_exceptbits_from_host(int host_bits) 9118 { 9119 int target_bits = 0; 9120 9121 if (host_bits & float_flag_invalid) 9122 target_bits |= 1; 9123 if (host_bits & float_flag_divbyzero) 9124 target_bits |= 2; 9125 if (host_bits & float_flag_overflow) 9126 target_bits |= 4; 9127 if (host_bits & (float_flag_underflow | float_flag_output_denormal)) 9128 target_bits |= 8; 9129 if (host_bits & float_flag_inexact) 9130 target_bits |= 0x10; 9131 if (host_bits & float_flag_input_denormal) 9132 target_bits |= 0x80; 9133 return target_bits; 9134 } 9135 9136 uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env) 9137 { 9138 int i; 9139 uint32_t fpscr; 9140 9141 fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff) 9142 | (env->vfp.vec_len << 16) 9143 | (env->vfp.vec_stride << 20); 9144 i = get_float_exception_flags(&env->vfp.fp_status); 9145 i |= get_float_exception_flags(&env->vfp.standard_fp_status); 9146 fpscr |= vfp_exceptbits_from_host(i); 9147 return fpscr; 9148 } 9149 9150 uint32_t vfp_get_fpscr(CPUARMState *env) 9151 { 9152 return HELPER(vfp_get_fpscr)(env); 9153 } 9154 9155 /* Convert vfp exception flags to target form. */ 9156 static inline int vfp_exceptbits_to_host(int target_bits) 9157 { 9158 int host_bits = 0; 9159 9160 if (target_bits & 1) 9161 host_bits |= float_flag_invalid; 9162 if (target_bits & 2) 9163 host_bits |= float_flag_divbyzero; 9164 if (target_bits & 4) 9165 host_bits |= float_flag_overflow; 9166 if (target_bits & 8) 9167 host_bits |= float_flag_underflow; 9168 if (target_bits & 0x10) 9169 host_bits |= float_flag_inexact; 9170 if (target_bits & 0x80) 9171 host_bits |= float_flag_input_denormal; 9172 return host_bits; 9173 } 9174 9175 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) 9176 { 9177 int i; 9178 uint32_t changed; 9179 9180 changed = env->vfp.xregs[ARM_VFP_FPSCR]; 9181 env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff); 9182 env->vfp.vec_len = (val >> 16) & 7; 9183 env->vfp.vec_stride = (val >> 20) & 3; 9184 9185 changed ^= val; 9186 if (changed & (3 << 22)) { 9187 i = (val >> 22) & 3; 9188 switch (i) { 9189 case FPROUNDING_TIEEVEN: 9190 i = float_round_nearest_even; 9191 break; 9192 case FPROUNDING_POSINF: 9193 i = float_round_up; 9194 break; 9195 case FPROUNDING_NEGINF: 9196 i = float_round_down; 9197 break; 9198 case FPROUNDING_ZERO: 9199 i = float_round_to_zero; 9200 break; 9201 } 9202 set_float_rounding_mode(i, &env->vfp.fp_status); 9203 } 9204 if (changed & (1 << 24)) { 9205 set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status); 9206 set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status); 9207 } 9208 if (changed & (1 << 25)) 9209 set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status); 9210 9211 i = vfp_exceptbits_to_host(val); 9212 set_float_exception_flags(i, &env->vfp.fp_status); 9213 set_float_exception_flags(0, &env->vfp.standard_fp_status); 9214 } 9215 9216 void vfp_set_fpscr(CPUARMState *env, uint32_t val) 9217 { 9218 HELPER(vfp_set_fpscr)(env, val); 9219 } 9220 9221 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p)) 9222 9223 #define VFP_BINOP(name) \ 9224 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \ 9225 { \ 9226 float_status *fpst = fpstp; \ 9227 return float32_ ## name(a, b, fpst); \ 9228 } \ 9229 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \ 9230 { \ 9231 float_status *fpst = fpstp; \ 9232 return float64_ ## name(a, b, fpst); \ 9233 } 9234 VFP_BINOP(add) 9235 VFP_BINOP(sub) 9236 VFP_BINOP(mul) 9237 VFP_BINOP(div) 9238 VFP_BINOP(min) 9239 VFP_BINOP(max) 9240 VFP_BINOP(minnum) 9241 VFP_BINOP(maxnum) 9242 #undef VFP_BINOP 9243 9244 float32 VFP_HELPER(neg, s)(float32 a) 9245 { 9246 return float32_chs(a); 9247 } 9248 9249 float64 VFP_HELPER(neg, d)(float64 a) 9250 { 9251 return float64_chs(a); 9252 } 9253 9254 float32 VFP_HELPER(abs, s)(float32 a) 9255 { 9256 return float32_abs(a); 9257 } 9258 9259 float64 VFP_HELPER(abs, d)(float64 a) 9260 { 9261 return float64_abs(a); 9262 } 9263 9264 float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env) 9265 { 9266 return float32_sqrt(a, &env->vfp.fp_status); 9267 } 9268 9269 float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env) 9270 { 9271 return float64_sqrt(a, &env->vfp.fp_status); 9272 } 9273 9274 /* XXX: check quiet/signaling case */ 9275 #define DO_VFP_cmp(p, type) \ 9276 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \ 9277 { \ 9278 uint32_t flags; \ 9279 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \ 9280 case 0: flags = 0x6; break; \ 9281 case -1: flags = 0x8; break; \ 9282 case 1: flags = 0x2; break; \ 9283 default: case 2: flags = 0x3; break; \ 9284 } \ 9285 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \ 9286 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \ 9287 } \ 9288 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \ 9289 { \ 9290 uint32_t flags; \ 9291 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \ 9292 case 0: flags = 0x6; break; \ 9293 case -1: flags = 0x8; break; \ 9294 case 1: flags = 0x2; break; \ 9295 default: case 2: flags = 0x3; break; \ 9296 } \ 9297 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \ 9298 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \ 9299 } 9300 DO_VFP_cmp(s, float32) 9301 DO_VFP_cmp(d, float64) 9302 #undef DO_VFP_cmp 9303 9304 /* Integer to float and float to integer conversions */ 9305 9306 #define CONV_ITOF(name, fsz, sign) \ 9307 float##fsz HELPER(name)(uint32_t x, void *fpstp) \ 9308 { \ 9309 float_status *fpst = fpstp; \ 9310 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \ 9311 } 9312 9313 #define CONV_FTOI(name, fsz, sign, round) \ 9314 uint32_t HELPER(name)(float##fsz x, void *fpstp) \ 9315 { \ 9316 float_status *fpst = fpstp; \ 9317 if (float##fsz##_is_any_nan(x)) { \ 9318 float_raise(float_flag_invalid, fpst); \ 9319 return 0; \ 9320 } \ 9321 return float##fsz##_to_##sign##int32##round(x, fpst); \ 9322 } 9323 9324 #define FLOAT_CONVS(name, p, fsz, sign) \ 9325 CONV_ITOF(vfp_##name##to##p, fsz, sign) \ 9326 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \ 9327 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero) 9328 9329 FLOAT_CONVS(si, s, 32, ) 9330 FLOAT_CONVS(si, d, 64, ) 9331 FLOAT_CONVS(ui, s, 32, u) 9332 FLOAT_CONVS(ui, d, 64, u) 9333 9334 #undef CONV_ITOF 9335 #undef CONV_FTOI 9336 #undef FLOAT_CONVS 9337 9338 /* floating point conversion */ 9339 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env) 9340 { 9341 float64 r = float32_to_float64(x, &env->vfp.fp_status); 9342 /* ARM requires that S<->D conversion of any kind of NaN generates 9343 * a quiet NaN by forcing the most significant frac bit to 1. 9344 */ 9345 return float64_maybe_silence_nan(r, &env->vfp.fp_status); 9346 } 9347 9348 float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env) 9349 { 9350 float32 r = float64_to_float32(x, &env->vfp.fp_status); 9351 /* ARM requires that S<->D conversion of any kind of NaN generates 9352 * a quiet NaN by forcing the most significant frac bit to 1. 9353 */ 9354 return float32_maybe_silence_nan(r, &env->vfp.fp_status); 9355 } 9356 9357 /* VFP3 fixed point conversion. */ 9358 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \ 9359 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \ 9360 void *fpstp) \ 9361 { \ 9362 float_status *fpst = fpstp; \ 9363 float##fsz tmp; \ 9364 tmp = itype##_to_##float##fsz(x, fpst); \ 9365 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \ 9366 } 9367 9368 /* Notice that we want only input-denormal exception flags from the 9369 * scalbn operation: the other possible flags (overflow+inexact if 9370 * we overflow to infinity, output-denormal) aren't correct for the 9371 * complete scale-and-convert operation. 9372 */ 9373 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \ 9374 uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \ 9375 uint32_t shift, \ 9376 void *fpstp) \ 9377 { \ 9378 float_status *fpst = fpstp; \ 9379 int old_exc_flags = get_float_exception_flags(fpst); \ 9380 float##fsz tmp; \ 9381 if (float##fsz##_is_any_nan(x)) { \ 9382 float_raise(float_flag_invalid, fpst); \ 9383 return 0; \ 9384 } \ 9385 tmp = float##fsz##_scalbn(x, shift, fpst); \ 9386 old_exc_flags |= get_float_exception_flags(fpst) \ 9387 & float_flag_input_denormal; \ 9388 set_float_exception_flags(old_exc_flags, fpst); \ 9389 return float##fsz##_to_##itype##round(tmp, fpst); \ 9390 } 9391 9392 #define VFP_CONV_FIX(name, p, fsz, isz, itype) \ 9393 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \ 9394 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \ 9395 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, ) 9396 9397 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype) \ 9398 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \ 9399 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, ) 9400 9401 VFP_CONV_FIX(sh, d, 64, 64, int16) 9402 VFP_CONV_FIX(sl, d, 64, 64, int32) 9403 VFP_CONV_FIX_A64(sq, d, 64, 64, int64) 9404 VFP_CONV_FIX(uh, d, 64, 64, uint16) 9405 VFP_CONV_FIX(ul, d, 64, 64, uint32) 9406 VFP_CONV_FIX_A64(uq, d, 64, 64, uint64) 9407 VFP_CONV_FIX(sh, s, 32, 32, int16) 9408 VFP_CONV_FIX(sl, s, 32, 32, int32) 9409 VFP_CONV_FIX_A64(sq, s, 32, 64, int64) 9410 VFP_CONV_FIX(uh, s, 32, 32, uint16) 9411 VFP_CONV_FIX(ul, s, 32, 32, uint32) 9412 VFP_CONV_FIX_A64(uq, s, 32, 64, uint64) 9413 #undef VFP_CONV_FIX 9414 #undef VFP_CONV_FIX_FLOAT 9415 #undef VFP_CONV_FLOAT_FIX_ROUND 9416 9417 /* Set the current fp rounding mode and return the old one. 9418 * The argument is a softfloat float_round_ value. 9419 */ 9420 uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env) 9421 { 9422 float_status *fp_status = &env->vfp.fp_status; 9423 9424 uint32_t prev_rmode = get_float_rounding_mode(fp_status); 9425 set_float_rounding_mode(rmode, fp_status); 9426 9427 return prev_rmode; 9428 } 9429 9430 /* Set the current fp rounding mode in the standard fp status and return 9431 * the old one. This is for NEON instructions that need to change the 9432 * rounding mode but wish to use the standard FPSCR values for everything 9433 * else. Always set the rounding mode back to the correct value after 9434 * modifying it. 9435 * The argument is a softfloat float_round_ value. 9436 */ 9437 uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env) 9438 { 9439 float_status *fp_status = &env->vfp.standard_fp_status; 9440 9441 uint32_t prev_rmode = get_float_rounding_mode(fp_status); 9442 set_float_rounding_mode(rmode, fp_status); 9443 9444 return prev_rmode; 9445 } 9446 9447 /* Half precision conversions. */ 9448 static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s) 9449 { 9450 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; 9451 float32 r = float16_to_float32(make_float16(a), ieee, s); 9452 if (ieee) { 9453 return float32_maybe_silence_nan(r, s); 9454 } 9455 return r; 9456 } 9457 9458 static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s) 9459 { 9460 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; 9461 float16 r = float32_to_float16(a, ieee, s); 9462 if (ieee) { 9463 r = float16_maybe_silence_nan(r, s); 9464 } 9465 return float16_val(r); 9466 } 9467 9468 float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env) 9469 { 9470 return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status); 9471 } 9472 9473 uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env) 9474 { 9475 return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status); 9476 } 9477 9478 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env) 9479 { 9480 return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status); 9481 } 9482 9483 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env) 9484 { 9485 return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status); 9486 } 9487 9488 float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env) 9489 { 9490 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; 9491 float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status); 9492 if (ieee) { 9493 return float64_maybe_silence_nan(r, &env->vfp.fp_status); 9494 } 9495 return r; 9496 } 9497 9498 uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env) 9499 { 9500 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; 9501 float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status); 9502 if (ieee) { 9503 r = float16_maybe_silence_nan(r, &env->vfp.fp_status); 9504 } 9505 return float16_val(r); 9506 } 9507 9508 #define float32_two make_float32(0x40000000) 9509 #define float32_three make_float32(0x40400000) 9510 #define float32_one_point_five make_float32(0x3fc00000) 9511 9512 float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env) 9513 { 9514 float_status *s = &env->vfp.standard_fp_status; 9515 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) || 9516 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) { 9517 if (!(float32_is_zero(a) || float32_is_zero(b))) { 9518 float_raise(float_flag_input_denormal, s); 9519 } 9520 return float32_two; 9521 } 9522 return float32_sub(float32_two, float32_mul(a, b, s), s); 9523 } 9524 9525 float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env) 9526 { 9527 float_status *s = &env->vfp.standard_fp_status; 9528 float32 product; 9529 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) || 9530 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) { 9531 if (!(float32_is_zero(a) || float32_is_zero(b))) { 9532 float_raise(float_flag_input_denormal, s); 9533 } 9534 return float32_one_point_five; 9535 } 9536 product = float32_mul(a, b, s); 9537 return float32_div(float32_sub(float32_three, product, s), float32_two, s); 9538 } 9539 9540 /* NEON helpers. */ 9541 9542 /* Constants 256 and 512 are used in some helpers; we avoid relying on 9543 * int->float conversions at run-time. */ 9544 #define float64_256 make_float64(0x4070000000000000LL) 9545 #define float64_512 make_float64(0x4080000000000000LL) 9546 #define float32_maxnorm make_float32(0x7f7fffff) 9547 #define float64_maxnorm make_float64(0x7fefffffffffffffLL) 9548 9549 /* Reciprocal functions 9550 * 9551 * The algorithm that must be used to calculate the estimate 9552 * is specified by the ARM ARM, see FPRecipEstimate() 9553 */ 9554 9555 static float64 recip_estimate(float64 a, float_status *real_fp_status) 9556 { 9557 /* These calculations mustn't set any fp exception flags, 9558 * so we use a local copy of the fp_status. 9559 */ 9560 float_status dummy_status = *real_fp_status; 9561 float_status *s = &dummy_status; 9562 /* q = (int)(a * 512.0) */ 9563 float64 q = float64_mul(float64_512, a, s); 9564 int64_t q_int = float64_to_int64_round_to_zero(q, s); 9565 9566 /* r = 1.0 / (((double)q + 0.5) / 512.0) */ 9567 q = int64_to_float64(q_int, s); 9568 q = float64_add(q, float64_half, s); 9569 q = float64_div(q, float64_512, s); 9570 q = float64_div(float64_one, q, s); 9571 9572 /* s = (int)(256.0 * r + 0.5) */ 9573 q = float64_mul(q, float64_256, s); 9574 q = float64_add(q, float64_half, s); 9575 q_int = float64_to_int64_round_to_zero(q, s); 9576 9577 /* return (double)s / 256.0 */ 9578 return float64_div(int64_to_float64(q_int, s), float64_256, s); 9579 } 9580 9581 /* Common wrapper to call recip_estimate */ 9582 static float64 call_recip_estimate(float64 num, int off, float_status *fpst) 9583 { 9584 uint64_t val64 = float64_val(num); 9585 uint64_t frac = extract64(val64, 0, 52); 9586 int64_t exp = extract64(val64, 52, 11); 9587 uint64_t sbit; 9588 float64 scaled, estimate; 9589 9590 /* Generate the scaled number for the estimate function */ 9591 if (exp == 0) { 9592 if (extract64(frac, 51, 1) == 0) { 9593 exp = -1; 9594 frac = extract64(frac, 0, 50) << 2; 9595 } else { 9596 frac = extract64(frac, 0, 51) << 1; 9597 } 9598 } 9599 9600 /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */ 9601 scaled = make_float64((0x3feULL << 52) 9602 | extract64(frac, 44, 8) << 44); 9603 9604 estimate = recip_estimate(scaled, fpst); 9605 9606 /* Build new result */ 9607 val64 = float64_val(estimate); 9608 sbit = 0x8000000000000000ULL & val64; 9609 exp = off - exp; 9610 frac = extract64(val64, 0, 52); 9611 9612 if (exp == 0) { 9613 frac = 1ULL << 51 | extract64(frac, 1, 51); 9614 } else if (exp == -1) { 9615 frac = 1ULL << 50 | extract64(frac, 2, 50); 9616 exp = 0; 9617 } 9618 9619 return make_float64(sbit | (exp << 52) | frac); 9620 } 9621 9622 static bool round_to_inf(float_status *fpst, bool sign_bit) 9623 { 9624 switch (fpst->float_rounding_mode) { 9625 case float_round_nearest_even: /* Round to Nearest */ 9626 return true; 9627 case float_round_up: /* Round to +Inf */ 9628 return !sign_bit; 9629 case float_round_down: /* Round to -Inf */ 9630 return sign_bit; 9631 case float_round_to_zero: /* Round to Zero */ 9632 return false; 9633 } 9634 9635 g_assert_not_reached(); 9636 } 9637 9638 float32 HELPER(recpe_f32)(float32 input, void *fpstp) 9639 { 9640 float_status *fpst = fpstp; 9641 float32 f32 = float32_squash_input_denormal(input, fpst); 9642 uint32_t f32_val = float32_val(f32); 9643 uint32_t f32_sbit = 0x80000000ULL & f32_val; 9644 int32_t f32_exp = extract32(f32_val, 23, 8); 9645 uint32_t f32_frac = extract32(f32_val, 0, 23); 9646 float64 f64, r64; 9647 uint64_t r64_val; 9648 int64_t r64_exp; 9649 uint64_t r64_frac; 9650 9651 if (float32_is_any_nan(f32)) { 9652 float32 nan = f32; 9653 if (float32_is_signaling_nan(f32, fpst)) { 9654 float_raise(float_flag_invalid, fpst); 9655 nan = float32_maybe_silence_nan(f32, fpst); 9656 } 9657 if (fpst->default_nan_mode) { 9658 nan = float32_default_nan(fpst); 9659 } 9660 return nan; 9661 } else if (float32_is_infinity(f32)) { 9662 return float32_set_sign(float32_zero, float32_is_neg(f32)); 9663 } else if (float32_is_zero(f32)) { 9664 float_raise(float_flag_divbyzero, fpst); 9665 return float32_set_sign(float32_infinity, float32_is_neg(f32)); 9666 } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) { 9667 /* Abs(value) < 2.0^-128 */ 9668 float_raise(float_flag_overflow | float_flag_inexact, fpst); 9669 if (round_to_inf(fpst, f32_sbit)) { 9670 return float32_set_sign(float32_infinity, float32_is_neg(f32)); 9671 } else { 9672 return float32_set_sign(float32_maxnorm, float32_is_neg(f32)); 9673 } 9674 } else if (f32_exp >= 253 && fpst->flush_to_zero) { 9675 float_raise(float_flag_underflow, fpst); 9676 return float32_set_sign(float32_zero, float32_is_neg(f32)); 9677 } 9678 9679 9680 f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29); 9681 r64 = call_recip_estimate(f64, 253, fpst); 9682 r64_val = float64_val(r64); 9683 r64_exp = extract64(r64_val, 52, 11); 9684 r64_frac = extract64(r64_val, 0, 52); 9685 9686 /* result = sign : result_exp<7:0> : fraction<51:29>; */ 9687 return make_float32(f32_sbit | 9688 (r64_exp & 0xff) << 23 | 9689 extract64(r64_frac, 29, 24)); 9690 } 9691 9692 float64 HELPER(recpe_f64)(float64 input, void *fpstp) 9693 { 9694 float_status *fpst = fpstp; 9695 float64 f64 = float64_squash_input_denormal(input, fpst); 9696 uint64_t f64_val = float64_val(f64); 9697 uint64_t f64_sbit = 0x8000000000000000ULL & f64_val; 9698 int64_t f64_exp = extract64(f64_val, 52, 11); 9699 float64 r64; 9700 uint64_t r64_val; 9701 int64_t r64_exp; 9702 uint64_t r64_frac; 9703 9704 /* Deal with any special cases */ 9705 if (float64_is_any_nan(f64)) { 9706 float64 nan = f64; 9707 if (float64_is_signaling_nan(f64, fpst)) { 9708 float_raise(float_flag_invalid, fpst); 9709 nan = float64_maybe_silence_nan(f64, fpst); 9710 } 9711 if (fpst->default_nan_mode) { 9712 nan = float64_default_nan(fpst); 9713 } 9714 return nan; 9715 } else if (float64_is_infinity(f64)) { 9716 return float64_set_sign(float64_zero, float64_is_neg(f64)); 9717 } else if (float64_is_zero(f64)) { 9718 float_raise(float_flag_divbyzero, fpst); 9719 return float64_set_sign(float64_infinity, float64_is_neg(f64)); 9720 } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) { 9721 /* Abs(value) < 2.0^-1024 */ 9722 float_raise(float_flag_overflow | float_flag_inexact, fpst); 9723 if (round_to_inf(fpst, f64_sbit)) { 9724 return float64_set_sign(float64_infinity, float64_is_neg(f64)); 9725 } else { 9726 return float64_set_sign(float64_maxnorm, float64_is_neg(f64)); 9727 } 9728 } else if (f64_exp >= 2045 && fpst->flush_to_zero) { 9729 float_raise(float_flag_underflow, fpst); 9730 return float64_set_sign(float64_zero, float64_is_neg(f64)); 9731 } 9732 9733 r64 = call_recip_estimate(f64, 2045, fpst); 9734 r64_val = float64_val(r64); 9735 r64_exp = extract64(r64_val, 52, 11); 9736 r64_frac = extract64(r64_val, 0, 52); 9737 9738 /* result = sign : result_exp<10:0> : fraction<51:0> */ 9739 return make_float64(f64_sbit | 9740 ((r64_exp & 0x7ff) << 52) | 9741 r64_frac); 9742 } 9743 9744 /* The algorithm that must be used to calculate the estimate 9745 * is specified by the ARM ARM. 9746 */ 9747 static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status) 9748 { 9749 /* These calculations mustn't set any fp exception flags, 9750 * so we use a local copy of the fp_status. 9751 */ 9752 float_status dummy_status = *real_fp_status; 9753 float_status *s = &dummy_status; 9754 float64 q; 9755 int64_t q_int; 9756 9757 if (float64_lt(a, float64_half, s)) { 9758 /* range 0.25 <= a < 0.5 */ 9759 9760 /* a in units of 1/512 rounded down */ 9761 /* q0 = (int)(a * 512.0); */ 9762 q = float64_mul(float64_512, a, s); 9763 q_int = float64_to_int64_round_to_zero(q, s); 9764 9765 /* reciprocal root r */ 9766 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */ 9767 q = int64_to_float64(q_int, s); 9768 q = float64_add(q, float64_half, s); 9769 q = float64_div(q, float64_512, s); 9770 q = float64_sqrt(q, s); 9771 q = float64_div(float64_one, q, s); 9772 } else { 9773 /* range 0.5 <= a < 1.0 */ 9774 9775 /* a in units of 1/256 rounded down */ 9776 /* q1 = (int)(a * 256.0); */ 9777 q = float64_mul(float64_256, a, s); 9778 int64_t q_int = float64_to_int64_round_to_zero(q, s); 9779 9780 /* reciprocal root r */ 9781 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */ 9782 q = int64_to_float64(q_int, s); 9783 q = float64_add(q, float64_half, s); 9784 q = float64_div(q, float64_256, s); 9785 q = float64_sqrt(q, s); 9786 q = float64_div(float64_one, q, s); 9787 } 9788 /* r in units of 1/256 rounded to nearest */ 9789 /* s = (int)(256.0 * r + 0.5); */ 9790 9791 q = float64_mul(q, float64_256,s ); 9792 q = float64_add(q, float64_half, s); 9793 q_int = float64_to_int64_round_to_zero(q, s); 9794 9795 /* return (double)s / 256.0;*/ 9796 return float64_div(int64_to_float64(q_int, s), float64_256, s); 9797 } 9798 9799 float32 HELPER(rsqrte_f32)(float32 input, void *fpstp) 9800 { 9801 float_status *s = fpstp; 9802 float32 f32 = float32_squash_input_denormal(input, s); 9803 uint32_t val = float32_val(f32); 9804 uint32_t f32_sbit = 0x80000000 & val; 9805 int32_t f32_exp = extract32(val, 23, 8); 9806 uint32_t f32_frac = extract32(val, 0, 23); 9807 uint64_t f64_frac; 9808 uint64_t val64; 9809 int result_exp; 9810 float64 f64; 9811 9812 if (float32_is_any_nan(f32)) { 9813 float32 nan = f32; 9814 if (float32_is_signaling_nan(f32, s)) { 9815 float_raise(float_flag_invalid, s); 9816 nan = float32_maybe_silence_nan(f32, s); 9817 } 9818 if (s->default_nan_mode) { 9819 nan = float32_default_nan(s); 9820 } 9821 return nan; 9822 } else if (float32_is_zero(f32)) { 9823 float_raise(float_flag_divbyzero, s); 9824 return float32_set_sign(float32_infinity, float32_is_neg(f32)); 9825 } else if (float32_is_neg(f32)) { 9826 float_raise(float_flag_invalid, s); 9827 return float32_default_nan(s); 9828 } else if (float32_is_infinity(f32)) { 9829 return float32_zero; 9830 } 9831 9832 /* Scale and normalize to a double-precision value between 0.25 and 1.0, 9833 * preserving the parity of the exponent. */ 9834 9835 f64_frac = ((uint64_t) f32_frac) << 29; 9836 if (f32_exp == 0) { 9837 while (extract64(f64_frac, 51, 1) == 0) { 9838 f64_frac = f64_frac << 1; 9839 f32_exp = f32_exp-1; 9840 } 9841 f64_frac = extract64(f64_frac, 0, 51) << 1; 9842 } 9843 9844 if (extract64(f32_exp, 0, 1) == 0) { 9845 f64 = make_float64(((uint64_t) f32_sbit) << 32 9846 | (0x3feULL << 52) 9847 | f64_frac); 9848 } else { 9849 f64 = make_float64(((uint64_t) f32_sbit) << 32 9850 | (0x3fdULL << 52) 9851 | f64_frac); 9852 } 9853 9854 result_exp = (380 - f32_exp) / 2; 9855 9856 f64 = recip_sqrt_estimate(f64, s); 9857 9858 val64 = float64_val(f64); 9859 9860 val = ((result_exp & 0xff) << 23) 9861 | ((val64 >> 29) & 0x7fffff); 9862 return make_float32(val); 9863 } 9864 9865 float64 HELPER(rsqrte_f64)(float64 input, void *fpstp) 9866 { 9867 float_status *s = fpstp; 9868 float64 f64 = float64_squash_input_denormal(input, s); 9869 uint64_t val = float64_val(f64); 9870 uint64_t f64_sbit = 0x8000000000000000ULL & val; 9871 int64_t f64_exp = extract64(val, 52, 11); 9872 uint64_t f64_frac = extract64(val, 0, 52); 9873 int64_t result_exp; 9874 uint64_t result_frac; 9875 9876 if (float64_is_any_nan(f64)) { 9877 float64 nan = f64; 9878 if (float64_is_signaling_nan(f64, s)) { 9879 float_raise(float_flag_invalid, s); 9880 nan = float64_maybe_silence_nan(f64, s); 9881 } 9882 if (s->default_nan_mode) { 9883 nan = float64_default_nan(s); 9884 } 9885 return nan; 9886 } else if (float64_is_zero(f64)) { 9887 float_raise(float_flag_divbyzero, s); 9888 return float64_set_sign(float64_infinity, float64_is_neg(f64)); 9889 } else if (float64_is_neg(f64)) { 9890 float_raise(float_flag_invalid, s); 9891 return float64_default_nan(s); 9892 } else if (float64_is_infinity(f64)) { 9893 return float64_zero; 9894 } 9895 9896 /* Scale and normalize to a double-precision value between 0.25 and 1.0, 9897 * preserving the parity of the exponent. */ 9898 9899 if (f64_exp == 0) { 9900 while (extract64(f64_frac, 51, 1) == 0) { 9901 f64_frac = f64_frac << 1; 9902 f64_exp = f64_exp - 1; 9903 } 9904 f64_frac = extract64(f64_frac, 0, 51) << 1; 9905 } 9906 9907 if (extract64(f64_exp, 0, 1) == 0) { 9908 f64 = make_float64(f64_sbit 9909 | (0x3feULL << 52) 9910 | f64_frac); 9911 } else { 9912 f64 = make_float64(f64_sbit 9913 | (0x3fdULL << 52) 9914 | f64_frac); 9915 } 9916 9917 result_exp = (3068 - f64_exp) / 2; 9918 9919 f64 = recip_sqrt_estimate(f64, s); 9920 9921 result_frac = extract64(float64_val(f64), 0, 52); 9922 9923 return make_float64(f64_sbit | 9924 ((result_exp & 0x7ff) << 52) | 9925 result_frac); 9926 } 9927 9928 uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp) 9929 { 9930 float_status *s = fpstp; 9931 float64 f64; 9932 9933 if ((a & 0x80000000) == 0) { 9934 return 0xffffffff; 9935 } 9936 9937 f64 = make_float64((0x3feULL << 52) 9938 | ((int64_t)(a & 0x7fffffff) << 21)); 9939 9940 f64 = recip_estimate(f64, s); 9941 9942 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff); 9943 } 9944 9945 uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp) 9946 { 9947 float_status *fpst = fpstp; 9948 float64 f64; 9949 9950 if ((a & 0xc0000000) == 0) { 9951 return 0xffffffff; 9952 } 9953 9954 if (a & 0x80000000) { 9955 f64 = make_float64((0x3feULL << 52) 9956 | ((uint64_t)(a & 0x7fffffff) << 21)); 9957 } else { /* bits 31-30 == '01' */ 9958 f64 = make_float64((0x3fdULL << 52) 9959 | ((uint64_t)(a & 0x3fffffff) << 22)); 9960 } 9961 9962 f64 = recip_sqrt_estimate(f64, fpst); 9963 9964 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff); 9965 } 9966 9967 /* VFPv4 fused multiply-accumulate */ 9968 float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp) 9969 { 9970 float_status *fpst = fpstp; 9971 return float32_muladd(a, b, c, 0, fpst); 9972 } 9973 9974 float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp) 9975 { 9976 float_status *fpst = fpstp; 9977 return float64_muladd(a, b, c, 0, fpst); 9978 } 9979 9980 /* ARMv8 round to integral */ 9981 float32 HELPER(rints_exact)(float32 x, void *fp_status) 9982 { 9983 return float32_round_to_int(x, fp_status); 9984 } 9985 9986 float64 HELPER(rintd_exact)(float64 x, void *fp_status) 9987 { 9988 return float64_round_to_int(x, fp_status); 9989 } 9990 9991 float32 HELPER(rints)(float32 x, void *fp_status) 9992 { 9993 int old_flags = get_float_exception_flags(fp_status), new_flags; 9994 float32 ret; 9995 9996 ret = float32_round_to_int(x, fp_status); 9997 9998 /* Suppress any inexact exceptions the conversion produced */ 9999 if (!(old_flags & float_flag_inexact)) { 10000 new_flags = get_float_exception_flags(fp_status); 10001 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); 10002 } 10003 10004 return ret; 10005 } 10006 10007 float64 HELPER(rintd)(float64 x, void *fp_status) 10008 { 10009 int old_flags = get_float_exception_flags(fp_status), new_flags; 10010 float64 ret; 10011 10012 ret = float64_round_to_int(x, fp_status); 10013 10014 new_flags = get_float_exception_flags(fp_status); 10015 10016 /* Suppress any inexact exceptions the conversion produced */ 10017 if (!(old_flags & float_flag_inexact)) { 10018 new_flags = get_float_exception_flags(fp_status); 10019 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); 10020 } 10021 10022 return ret; 10023 } 10024 10025 /* Convert ARM rounding mode to softfloat */ 10026 int arm_rmode_to_sf(int rmode) 10027 { 10028 switch (rmode) { 10029 case FPROUNDING_TIEAWAY: 10030 rmode = float_round_ties_away; 10031 break; 10032 case FPROUNDING_ODD: 10033 /* FIXME: add support for TIEAWAY and ODD */ 10034 qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n", 10035 rmode); 10036 case FPROUNDING_TIEEVEN: 10037 default: 10038 rmode = float_round_nearest_even; 10039 break; 10040 case FPROUNDING_POSINF: 10041 rmode = float_round_up; 10042 break; 10043 case FPROUNDING_NEGINF: 10044 rmode = float_round_down; 10045 break; 10046 case FPROUNDING_ZERO: 10047 rmode = float_round_to_zero; 10048 break; 10049 } 10050 return rmode; 10051 } 10052 10053 /* CRC helpers. 10054 * The upper bytes of val (above the number specified by 'bytes') must have 10055 * been zeroed out by the caller. 10056 */ 10057 uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes) 10058 { 10059 uint8_t buf[4]; 10060 10061 stl_le_p(buf, val); 10062 10063 /* zlib crc32 converts the accumulator and output to one's complement. */ 10064 return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff; 10065 } 10066 10067 uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes) 10068 { 10069 uint8_t buf[4]; 10070 10071 stl_le_p(buf, val); 10072 10073 /* Linux crc32c converts the output to one's complement. */ 10074 return crc32c(acc, buf, bytes) ^ 0xffffffff; 10075 } 10076