1 #include "qemu/osdep.h" 2 #include "trace.h" 3 #include "cpu.h" 4 #include "internals.h" 5 #include "exec/gdbstub.h" 6 #include "exec/helper-proto.h" 7 #include "qemu/host-utils.h" 8 #include "sysemu/arch_init.h" 9 #include "sysemu/sysemu.h" 10 #include "qemu/bitops.h" 11 #include "qemu/crc32c.h" 12 #include "exec/exec-all.h" 13 #include "exec/cpu_ldst.h" 14 #include "arm_ldst.h" 15 #include <zlib.h> /* For crc32 */ 16 #include "exec/semihost.h" 17 #include "sysemu/kvm.h" 18 19 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ 20 21 #ifndef CONFIG_USER_ONLY 22 static bool get_phys_addr(CPUARMState *env, target_ulong address, 23 MMUAccessType access_type, ARMMMUIdx mmu_idx, 24 hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, 25 target_ulong *page_size, uint32_t *fsr, 26 ARMMMUFaultInfo *fi); 27 28 static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, 29 MMUAccessType access_type, ARMMMUIdx mmu_idx, 30 hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, 31 target_ulong *page_size_ptr, uint32_t *fsr, 32 ARMMMUFaultInfo *fi); 33 34 /* Definitions for the PMCCNTR and PMCR registers */ 35 #define PMCRD 0x8 36 #define PMCRC 0x4 37 #define PMCRE 0x1 38 #endif 39 40 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) 41 { 42 int nregs; 43 44 /* VFP data registers are always little-endian. */ 45 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; 46 if (reg < nregs) { 47 stfq_le_p(buf, env->vfp.regs[reg]); 48 return 8; 49 } 50 if (arm_feature(env, ARM_FEATURE_NEON)) { 51 /* Aliases for Q regs. */ 52 nregs += 16; 53 if (reg < nregs) { 54 stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]); 55 stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]); 56 return 16; 57 } 58 } 59 switch (reg - nregs) { 60 case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4; 61 case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4; 62 case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4; 63 } 64 return 0; 65 } 66 67 static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) 68 { 69 int nregs; 70 71 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; 72 if (reg < nregs) { 73 env->vfp.regs[reg] = ldfq_le_p(buf); 74 return 8; 75 } 76 if (arm_feature(env, ARM_FEATURE_NEON)) { 77 nregs += 16; 78 if (reg < nregs) { 79 env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf); 80 env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8); 81 return 16; 82 } 83 } 84 switch (reg - nregs) { 85 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4; 86 case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4; 87 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4; 88 } 89 return 0; 90 } 91 92 static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) 93 { 94 switch (reg) { 95 case 0 ... 31: 96 /* 128 bit FP register */ 97 stfq_le_p(buf, env->vfp.regs[reg * 2]); 98 stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]); 99 return 16; 100 case 32: 101 /* FPSR */ 102 stl_p(buf, vfp_get_fpsr(env)); 103 return 4; 104 case 33: 105 /* FPCR */ 106 stl_p(buf, vfp_get_fpcr(env)); 107 return 4; 108 default: 109 return 0; 110 } 111 } 112 113 static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) 114 { 115 switch (reg) { 116 case 0 ... 31: 117 /* 128 bit FP register */ 118 env->vfp.regs[reg * 2] = ldfq_le_p(buf); 119 env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8); 120 return 16; 121 case 32: 122 /* FPSR */ 123 vfp_set_fpsr(env, ldl_p(buf)); 124 return 4; 125 case 33: 126 /* FPCR */ 127 vfp_set_fpcr(env, ldl_p(buf)); 128 return 4; 129 default: 130 return 0; 131 } 132 } 133 134 static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri) 135 { 136 assert(ri->fieldoffset); 137 if (cpreg_field_is_64bit(ri)) { 138 return CPREG_FIELD64(env, ri); 139 } else { 140 return CPREG_FIELD32(env, ri); 141 } 142 } 143 144 static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, 145 uint64_t value) 146 { 147 assert(ri->fieldoffset); 148 if (cpreg_field_is_64bit(ri)) { 149 CPREG_FIELD64(env, ri) = value; 150 } else { 151 CPREG_FIELD32(env, ri) = value; 152 } 153 } 154 155 static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri) 156 { 157 return (char *)env + ri->fieldoffset; 158 } 159 160 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri) 161 { 162 /* Raw read of a coprocessor register (as needed for migration, etc). */ 163 if (ri->type & ARM_CP_CONST) { 164 return ri->resetvalue; 165 } else if (ri->raw_readfn) { 166 return ri->raw_readfn(env, ri); 167 } else if (ri->readfn) { 168 return ri->readfn(env, ri); 169 } else { 170 return raw_read(env, ri); 171 } 172 } 173 174 static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri, 175 uint64_t v) 176 { 177 /* Raw write of a coprocessor register (as needed for migration, etc). 178 * Note that constant registers are treated as write-ignored; the 179 * caller should check for success by whether a readback gives the 180 * value written. 181 */ 182 if (ri->type & ARM_CP_CONST) { 183 return; 184 } else if (ri->raw_writefn) { 185 ri->raw_writefn(env, ri, v); 186 } else if (ri->writefn) { 187 ri->writefn(env, ri, v); 188 } else { 189 raw_write(env, ri, v); 190 } 191 } 192 193 static bool raw_accessors_invalid(const ARMCPRegInfo *ri) 194 { 195 /* Return true if the regdef would cause an assertion if you called 196 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a 197 * program bug for it not to have the NO_RAW flag). 198 * NB that returning false here doesn't necessarily mean that calling 199 * read/write_raw_cp_reg() is safe, because we can't distinguish "has 200 * read/write access functions which are safe for raw use" from "has 201 * read/write access functions which have side effects but has forgotten 202 * to provide raw access functions". 203 * The tests here line up with the conditions in read/write_raw_cp_reg() 204 * and assertions in raw_read()/raw_write(). 205 */ 206 if ((ri->type & ARM_CP_CONST) || 207 ri->fieldoffset || 208 ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) { 209 return false; 210 } 211 return true; 212 } 213 214 bool write_cpustate_to_list(ARMCPU *cpu) 215 { 216 /* Write the coprocessor state from cpu->env to the (index,value) list. */ 217 int i; 218 bool ok = true; 219 220 for (i = 0; i < cpu->cpreg_array_len; i++) { 221 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); 222 const ARMCPRegInfo *ri; 223 224 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); 225 if (!ri) { 226 ok = false; 227 continue; 228 } 229 if (ri->type & ARM_CP_NO_RAW) { 230 continue; 231 } 232 cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri); 233 } 234 return ok; 235 } 236 237 bool write_list_to_cpustate(ARMCPU *cpu) 238 { 239 int i; 240 bool ok = true; 241 242 for (i = 0; i < cpu->cpreg_array_len; i++) { 243 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); 244 uint64_t v = cpu->cpreg_values[i]; 245 const ARMCPRegInfo *ri; 246 247 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); 248 if (!ri) { 249 ok = false; 250 continue; 251 } 252 if (ri->type & ARM_CP_NO_RAW) { 253 continue; 254 } 255 /* Write value and confirm it reads back as written 256 * (to catch read-only registers and partially read-only 257 * registers where the incoming migration value doesn't match) 258 */ 259 write_raw_cp_reg(&cpu->env, ri, v); 260 if (read_raw_cp_reg(&cpu->env, ri) != v) { 261 ok = false; 262 } 263 } 264 return ok; 265 } 266 267 static void add_cpreg_to_list(gpointer key, gpointer opaque) 268 { 269 ARMCPU *cpu = opaque; 270 uint64_t regidx; 271 const ARMCPRegInfo *ri; 272 273 regidx = *(uint32_t *)key; 274 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); 275 276 if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { 277 cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx); 278 /* The value array need not be initialized at this point */ 279 cpu->cpreg_array_len++; 280 } 281 } 282 283 static void count_cpreg(gpointer key, gpointer opaque) 284 { 285 ARMCPU *cpu = opaque; 286 uint64_t regidx; 287 const ARMCPRegInfo *ri; 288 289 regidx = *(uint32_t *)key; 290 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); 291 292 if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { 293 cpu->cpreg_array_len++; 294 } 295 } 296 297 static gint cpreg_key_compare(gconstpointer a, gconstpointer b) 298 { 299 uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a); 300 uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b); 301 302 if (aidx > bidx) { 303 return 1; 304 } 305 if (aidx < bidx) { 306 return -1; 307 } 308 return 0; 309 } 310 311 void init_cpreg_list(ARMCPU *cpu) 312 { 313 /* Initialise the cpreg_tuples[] array based on the cp_regs hash. 314 * Note that we require cpreg_tuples[] to be sorted by key ID. 315 */ 316 GList *keys; 317 int arraylen; 318 319 keys = g_hash_table_get_keys(cpu->cp_regs); 320 keys = g_list_sort(keys, cpreg_key_compare); 321 322 cpu->cpreg_array_len = 0; 323 324 g_list_foreach(keys, count_cpreg, cpu); 325 326 arraylen = cpu->cpreg_array_len; 327 cpu->cpreg_indexes = g_new(uint64_t, arraylen); 328 cpu->cpreg_values = g_new(uint64_t, arraylen); 329 cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen); 330 cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen); 331 cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len; 332 cpu->cpreg_array_len = 0; 333 334 g_list_foreach(keys, add_cpreg_to_list, cpu); 335 336 assert(cpu->cpreg_array_len == arraylen); 337 338 g_list_free(keys); 339 } 340 341 /* 342 * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but 343 * they are accessible when EL3 is using AArch64 regardless of EL3.NS. 344 * 345 * access_el3_aa32ns: Used to check AArch32 register views. 346 * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views. 347 */ 348 static CPAccessResult access_el3_aa32ns(CPUARMState *env, 349 const ARMCPRegInfo *ri, 350 bool isread) 351 { 352 bool secure = arm_is_secure_below_el3(env); 353 354 assert(!arm_el_is_aa64(env, 3)); 355 if (secure) { 356 return CP_ACCESS_TRAP_UNCATEGORIZED; 357 } 358 return CP_ACCESS_OK; 359 } 360 361 static CPAccessResult access_el3_aa32ns_aa64any(CPUARMState *env, 362 const ARMCPRegInfo *ri, 363 bool isread) 364 { 365 if (!arm_el_is_aa64(env, 3)) { 366 return access_el3_aa32ns(env, ri, isread); 367 } 368 return CP_ACCESS_OK; 369 } 370 371 /* Some secure-only AArch32 registers trap to EL3 if used from 372 * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts). 373 * Note that an access from Secure EL1 can only happen if EL3 is AArch64. 374 * We assume that the .access field is set to PL1_RW. 375 */ 376 static CPAccessResult access_trap_aa32s_el1(CPUARMState *env, 377 const ARMCPRegInfo *ri, 378 bool isread) 379 { 380 if (arm_current_el(env) == 3) { 381 return CP_ACCESS_OK; 382 } 383 if (arm_is_secure_below_el3(env)) { 384 return CP_ACCESS_TRAP_EL3; 385 } 386 /* This will be EL1 NS and EL2 NS, which just UNDEF */ 387 return CP_ACCESS_TRAP_UNCATEGORIZED; 388 } 389 390 /* Check for traps to "powerdown debug" registers, which are controlled 391 * by MDCR.TDOSA 392 */ 393 static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *ri, 394 bool isread) 395 { 396 int el = arm_current_el(env); 397 398 if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDOSA) 399 && !arm_is_secure_below_el3(env)) { 400 return CP_ACCESS_TRAP_EL2; 401 } 402 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDOSA)) { 403 return CP_ACCESS_TRAP_EL3; 404 } 405 return CP_ACCESS_OK; 406 } 407 408 /* Check for traps to "debug ROM" registers, which are controlled 409 * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3. 410 */ 411 static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri, 412 bool isread) 413 { 414 int el = arm_current_el(env); 415 416 if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDRA) 417 && !arm_is_secure_below_el3(env)) { 418 return CP_ACCESS_TRAP_EL2; 419 } 420 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { 421 return CP_ACCESS_TRAP_EL3; 422 } 423 return CP_ACCESS_OK; 424 } 425 426 /* Check for traps to general debug registers, which are controlled 427 * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3. 428 */ 429 static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri, 430 bool isread) 431 { 432 int el = arm_current_el(env); 433 434 if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDA) 435 && !arm_is_secure_below_el3(env)) { 436 return CP_ACCESS_TRAP_EL2; 437 } 438 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { 439 return CP_ACCESS_TRAP_EL3; 440 } 441 return CP_ACCESS_OK; 442 } 443 444 /* Check for traps to performance monitor registers, which are controlled 445 * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3. 446 */ 447 static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri, 448 bool isread) 449 { 450 int el = arm_current_el(env); 451 452 if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM) 453 && !arm_is_secure_below_el3(env)) { 454 return CP_ACCESS_TRAP_EL2; 455 } 456 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { 457 return CP_ACCESS_TRAP_EL3; 458 } 459 return CP_ACCESS_OK; 460 } 461 462 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) 463 { 464 ARMCPU *cpu = arm_env_get_cpu(env); 465 466 raw_write(env, ri, value); 467 tlb_flush(CPU(cpu)); /* Flush TLB as domain not tracked in TLB */ 468 } 469 470 static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) 471 { 472 ARMCPU *cpu = arm_env_get_cpu(env); 473 474 if (raw_read(env, ri) != value) { 475 /* Unlike real hardware the qemu TLB uses virtual addresses, 476 * not modified virtual addresses, so this causes a TLB flush. 477 */ 478 tlb_flush(CPU(cpu)); 479 raw_write(env, ri, value); 480 } 481 } 482 483 static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, 484 uint64_t value) 485 { 486 ARMCPU *cpu = arm_env_get_cpu(env); 487 488 if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_PMSA) 489 && !extended_addresses_enabled(env)) { 490 /* For VMSA (when not using the LPAE long descriptor page table 491 * format) this register includes the ASID, so do a TLB flush. 492 * For PMSA it is purely a process ID and no action is needed. 493 */ 494 tlb_flush(CPU(cpu)); 495 } 496 raw_write(env, ri, value); 497 } 498 499 static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri, 500 uint64_t value) 501 { 502 /* Invalidate all (TLBIALL) */ 503 ARMCPU *cpu = arm_env_get_cpu(env); 504 505 tlb_flush(CPU(cpu)); 506 } 507 508 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, 509 uint64_t value) 510 { 511 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ 512 ARMCPU *cpu = arm_env_get_cpu(env); 513 514 tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); 515 } 516 517 static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, 518 uint64_t value) 519 { 520 /* Invalidate by ASID (TLBIASID) */ 521 ARMCPU *cpu = arm_env_get_cpu(env); 522 523 tlb_flush(CPU(cpu)); 524 } 525 526 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, 527 uint64_t value) 528 { 529 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ 530 ARMCPU *cpu = arm_env_get_cpu(env); 531 532 tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); 533 } 534 535 /* IS variants of TLB operations must affect all cores */ 536 static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri, 537 uint64_t value) 538 { 539 CPUState *cs = ENV_GET_CPU(env); 540 541 tlb_flush_all_cpus_synced(cs); 542 } 543 544 static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri, 545 uint64_t value) 546 { 547 CPUState *cs = ENV_GET_CPU(env); 548 549 tlb_flush_all_cpus_synced(cs); 550 } 551 552 static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri, 553 uint64_t value) 554 { 555 CPUState *cs = ENV_GET_CPU(env); 556 557 tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK); 558 } 559 560 static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri, 561 uint64_t value) 562 { 563 CPUState *cs = ENV_GET_CPU(env); 564 565 tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK); 566 } 567 568 static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri, 569 uint64_t value) 570 { 571 CPUState *cs = ENV_GET_CPU(env); 572 573 tlb_flush_by_mmuidx(cs, 574 ARMMMUIdxBit_S12NSE1 | 575 ARMMMUIdxBit_S12NSE0 | 576 ARMMMUIdxBit_S2NS); 577 } 578 579 static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri, 580 uint64_t value) 581 { 582 CPUState *cs = ENV_GET_CPU(env); 583 584 tlb_flush_by_mmuidx_all_cpus_synced(cs, 585 ARMMMUIdxBit_S12NSE1 | 586 ARMMMUIdxBit_S12NSE0 | 587 ARMMMUIdxBit_S2NS); 588 } 589 590 static void tlbiipas2_write(CPUARMState *env, const ARMCPRegInfo *ri, 591 uint64_t value) 592 { 593 /* Invalidate by IPA. This has to invalidate any structures that 594 * contain only stage 2 translation information, but does not need 595 * to apply to structures that contain combined stage 1 and stage 2 596 * translation information. 597 * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero. 598 */ 599 CPUState *cs = ENV_GET_CPU(env); 600 uint64_t pageaddr; 601 602 if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { 603 return; 604 } 605 606 pageaddr = sextract64(value << 12, 0, 40); 607 608 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S2NS); 609 } 610 611 static void tlbiipas2_is_write(CPUARMState *env, const ARMCPRegInfo *ri, 612 uint64_t value) 613 { 614 CPUState *cs = ENV_GET_CPU(env); 615 uint64_t pageaddr; 616 617 if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { 618 return; 619 } 620 621 pageaddr = sextract64(value << 12, 0, 40); 622 623 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, 624 ARMMMUIdxBit_S2NS); 625 } 626 627 static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, 628 uint64_t value) 629 { 630 CPUState *cs = ENV_GET_CPU(env); 631 632 tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2); 633 } 634 635 static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, 636 uint64_t value) 637 { 638 CPUState *cs = ENV_GET_CPU(env); 639 640 tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2); 641 } 642 643 static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, 644 uint64_t value) 645 { 646 CPUState *cs = ENV_GET_CPU(env); 647 uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12); 648 649 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E2); 650 } 651 652 static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, 653 uint64_t value) 654 { 655 CPUState *cs = ENV_GET_CPU(env); 656 uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12); 657 658 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, 659 ARMMMUIdxBit_S1E2); 660 } 661 662 static const ARMCPRegInfo cp_reginfo[] = { 663 /* Define the secure and non-secure FCSE identifier CP registers 664 * separately because there is no secure bank in V8 (no _EL3). This allows 665 * the secure register to be properly reset and migrated. There is also no 666 * v8 EL1 version of the register so the non-secure instance stands alone. 667 */ 668 { .name = "FCSEIDR(NS)", 669 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0, 670 .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS, 671 .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_ns), 672 .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, }, 673 { .name = "FCSEIDR(S)", 674 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0, 675 .access = PL1_RW, .secure = ARM_CP_SECSTATE_S, 676 .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s), 677 .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, }, 678 /* Define the secure and non-secure context identifier CP registers 679 * separately because there is no secure bank in V8 (no _EL3). This allows 680 * the secure register to be properly reset and migrated. In the 681 * non-secure case, the 32-bit register will have reset and migration 682 * disabled during registration as it is handled by the 64-bit instance. 683 */ 684 { .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH, 685 .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, 686 .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS, 687 .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]), 688 .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, 689 { .name = "CONTEXTIDR(S)", .state = ARM_CP_STATE_AA32, 690 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, 691 .access = PL1_RW, .secure = ARM_CP_SECSTATE_S, 692 .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s), 693 .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, 694 REGINFO_SENTINEL 695 }; 696 697 static const ARMCPRegInfo not_v8_cp_reginfo[] = { 698 /* NB: Some of these registers exist in v8 but with more precise 699 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]). 700 */ 701 /* MMU Domain access control / MPU write buffer control */ 702 { .name = "DACR", 703 .cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY, 704 .access = PL1_RW, .resetvalue = 0, 705 .writefn = dacr_write, .raw_writefn = raw_write, 706 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s), 707 offsetoflow32(CPUARMState, cp15.dacr_ns) } }, 708 /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs. 709 * For v6 and v5, these mappings are overly broad. 710 */ 711 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 0, 712 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, 713 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 1, 714 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, 715 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 4, 716 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, 717 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 8, 718 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, 719 /* Cache maintenance ops; some of this space may be overridden later. */ 720 { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, 721 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, 722 .type = ARM_CP_NOP | ARM_CP_OVERRIDE }, 723 REGINFO_SENTINEL 724 }; 725 726 static const ARMCPRegInfo not_v6_cp_reginfo[] = { 727 /* Not all pre-v6 cores implemented this WFI, so this is slightly 728 * over-broad. 729 */ 730 { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2, 731 .access = PL1_W, .type = ARM_CP_WFI }, 732 REGINFO_SENTINEL 733 }; 734 735 static const ARMCPRegInfo not_v7_cp_reginfo[] = { 736 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which 737 * is UNPREDICTABLE; we choose to NOP as most implementations do). 738 */ 739 { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, 740 .access = PL1_W, .type = ARM_CP_WFI }, 741 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice 742 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and 743 * OMAPCP will override this space. 744 */ 745 { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0, 746 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data), 747 .resetvalue = 0 }, 748 { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1, 749 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn), 750 .resetvalue = 0 }, 751 /* v6 doesn't have the cache ID registers but Linux reads them anyway */ 752 { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY, 753 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, 754 .resetvalue = 0 }, 755 /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR; 756 * implementing it as RAZ means the "debug architecture version" bits 757 * will read as a reserved value, which should cause Linux to not try 758 * to use the debug hardware. 759 */ 760 { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, 761 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 762 /* MMU TLB control. Note that the wildcarding means we cover not just 763 * the unified TLB ops but also the dside/iside/inner-shareable variants. 764 */ 765 { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY, 766 .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write, 767 .type = ARM_CP_NO_RAW }, 768 { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY, 769 .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write, 770 .type = ARM_CP_NO_RAW }, 771 { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY, 772 .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write, 773 .type = ARM_CP_NO_RAW }, 774 { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY, 775 .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write, 776 .type = ARM_CP_NO_RAW }, 777 { .name = "PRRR", .cp = 15, .crn = 10, .crm = 2, 778 .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP }, 779 { .name = "NMRR", .cp = 15, .crn = 10, .crm = 2, 780 .opc1 = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_NOP }, 781 REGINFO_SENTINEL 782 }; 783 784 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, 785 uint64_t value) 786 { 787 uint32_t mask = 0; 788 789 /* In ARMv8 most bits of CPACR_EL1 are RES0. */ 790 if (!arm_feature(env, ARM_FEATURE_V8)) { 791 /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI. 792 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP. 793 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell. 794 */ 795 if (arm_feature(env, ARM_FEATURE_VFP)) { 796 /* VFP coprocessor: cp10 & cp11 [23:20] */ 797 mask |= (1 << 31) | (1 << 30) | (0xf << 20); 798 799 if (!arm_feature(env, ARM_FEATURE_NEON)) { 800 /* ASEDIS [31] bit is RAO/WI */ 801 value |= (1 << 31); 802 } 803 804 /* VFPv3 and upwards with NEON implement 32 double precision 805 * registers (D0-D31). 806 */ 807 if (!arm_feature(env, ARM_FEATURE_NEON) || 808 !arm_feature(env, ARM_FEATURE_VFP3)) { 809 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */ 810 value |= (1 << 30); 811 } 812 } 813 value &= mask; 814 } 815 env->cp15.cpacr_el1 = value; 816 } 817 818 static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri, 819 bool isread) 820 { 821 if (arm_feature(env, ARM_FEATURE_V8)) { 822 /* Check if CPACR accesses are to be trapped to EL2 */ 823 if (arm_current_el(env) == 1 && 824 (env->cp15.cptr_el[2] & CPTR_TCPAC) && !arm_is_secure(env)) { 825 return CP_ACCESS_TRAP_EL2; 826 /* Check if CPACR accesses are to be trapped to EL3 */ 827 } else if (arm_current_el(env) < 3 && 828 (env->cp15.cptr_el[3] & CPTR_TCPAC)) { 829 return CP_ACCESS_TRAP_EL3; 830 } 831 } 832 833 return CP_ACCESS_OK; 834 } 835 836 static CPAccessResult cptr_access(CPUARMState *env, const ARMCPRegInfo *ri, 837 bool isread) 838 { 839 /* Check if CPTR accesses are set to trap to EL3 */ 840 if (arm_current_el(env) == 2 && (env->cp15.cptr_el[3] & CPTR_TCPAC)) { 841 return CP_ACCESS_TRAP_EL3; 842 } 843 844 return CP_ACCESS_OK; 845 } 846 847 static const ARMCPRegInfo v6_cp_reginfo[] = { 848 /* prefetch by MVA in v6, NOP in v7 */ 849 { .name = "MVA_prefetch", 850 .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1, 851 .access = PL1_W, .type = ARM_CP_NOP }, 852 /* We need to break the TB after ISB to execute self-modifying code 853 * correctly and also to take any pending interrupts immediately. 854 * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag. 855 */ 856 { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4, 857 .access = PL0_W, .type = ARM_CP_NO_RAW, .writefn = arm_cp_write_ignore }, 858 { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4, 859 .access = PL0_W, .type = ARM_CP_NOP }, 860 { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5, 861 .access = PL0_W, .type = ARM_CP_NOP }, 862 { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2, 863 .access = PL1_RW, 864 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s), 865 offsetof(CPUARMState, cp15.ifar_ns) }, 866 .resetvalue = 0, }, 867 /* Watchpoint Fault Address Register : should actually only be present 868 * for 1136, 1176, 11MPCore. 869 */ 870 { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, 871 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, }, 872 { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, 873 .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access, 874 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1), 875 .resetvalue = 0, .writefn = cpacr_write }, 876 REGINFO_SENTINEL 877 }; 878 879 static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri, 880 bool isread) 881 { 882 /* Performance monitor registers user accessibility is controlled 883 * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable 884 * trapping to EL2 or EL3 for other accesses. 885 */ 886 int el = arm_current_el(env); 887 888 if (el == 0 && !(env->cp15.c9_pmuserenr & 1)) { 889 return CP_ACCESS_TRAP; 890 } 891 if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM) 892 && !arm_is_secure_below_el3(env)) { 893 return CP_ACCESS_TRAP_EL2; 894 } 895 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { 896 return CP_ACCESS_TRAP_EL3; 897 } 898 899 return CP_ACCESS_OK; 900 } 901 902 static CPAccessResult pmreg_access_xevcntr(CPUARMState *env, 903 const ARMCPRegInfo *ri, 904 bool isread) 905 { 906 /* ER: event counter read trap control */ 907 if (arm_feature(env, ARM_FEATURE_V8) 908 && arm_current_el(env) == 0 909 && (env->cp15.c9_pmuserenr & (1 << 3)) != 0 910 && isread) { 911 return CP_ACCESS_OK; 912 } 913 914 return pmreg_access(env, ri, isread); 915 } 916 917 static CPAccessResult pmreg_access_swinc(CPUARMState *env, 918 const ARMCPRegInfo *ri, 919 bool isread) 920 { 921 /* SW: software increment write trap control */ 922 if (arm_feature(env, ARM_FEATURE_V8) 923 && arm_current_el(env) == 0 924 && (env->cp15.c9_pmuserenr & (1 << 1)) != 0 925 && !isread) { 926 return CP_ACCESS_OK; 927 } 928 929 return pmreg_access(env, ri, isread); 930 } 931 932 #ifndef CONFIG_USER_ONLY 933 934 static CPAccessResult pmreg_access_selr(CPUARMState *env, 935 const ARMCPRegInfo *ri, 936 bool isread) 937 { 938 /* ER: event counter read trap control */ 939 if (arm_feature(env, ARM_FEATURE_V8) 940 && arm_current_el(env) == 0 941 && (env->cp15.c9_pmuserenr & (1 << 3)) != 0) { 942 return CP_ACCESS_OK; 943 } 944 945 return pmreg_access(env, ri, isread); 946 } 947 948 static CPAccessResult pmreg_access_ccntr(CPUARMState *env, 949 const ARMCPRegInfo *ri, 950 bool isread) 951 { 952 /* CR: cycle counter read trap control */ 953 if (arm_feature(env, ARM_FEATURE_V8) 954 && arm_current_el(env) == 0 955 && (env->cp15.c9_pmuserenr & (1 << 2)) != 0 956 && isread) { 957 return CP_ACCESS_OK; 958 } 959 960 return pmreg_access(env, ri, isread); 961 } 962 963 static inline bool arm_ccnt_enabled(CPUARMState *env) 964 { 965 /* This does not support checking PMCCFILTR_EL0 register */ 966 967 if (!(env->cp15.c9_pmcr & PMCRE)) { 968 return false; 969 } 970 971 return true; 972 } 973 974 void pmccntr_sync(CPUARMState *env) 975 { 976 uint64_t temp_ticks; 977 978 temp_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 979 ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); 980 981 if (env->cp15.c9_pmcr & PMCRD) { 982 /* Increment once every 64 processor clock cycles */ 983 temp_ticks /= 64; 984 } 985 986 if (arm_ccnt_enabled(env)) { 987 env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt; 988 } 989 } 990 991 static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, 992 uint64_t value) 993 { 994 pmccntr_sync(env); 995 996 if (value & PMCRC) { 997 /* The counter has been reset */ 998 env->cp15.c15_ccnt = 0; 999 } 1000 1001 /* only the DP, X, D and E bits are writable */ 1002 env->cp15.c9_pmcr &= ~0x39; 1003 env->cp15.c9_pmcr |= (value & 0x39); 1004 1005 pmccntr_sync(env); 1006 } 1007 1008 static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) 1009 { 1010 uint64_t total_ticks; 1011 1012 if (!arm_ccnt_enabled(env)) { 1013 /* Counter is disabled, do not change value */ 1014 return env->cp15.c15_ccnt; 1015 } 1016 1017 total_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 1018 ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); 1019 1020 if (env->cp15.c9_pmcr & PMCRD) { 1021 /* Increment once every 64 processor clock cycles */ 1022 total_ticks /= 64; 1023 } 1024 return total_ticks - env->cp15.c15_ccnt; 1025 } 1026 1027 static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1028 uint64_t value) 1029 { 1030 /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and 1031 * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the 1032 * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are 1033 * accessed. 1034 */ 1035 env->cp15.c9_pmselr = value & 0x1f; 1036 } 1037 1038 static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1039 uint64_t value) 1040 { 1041 uint64_t total_ticks; 1042 1043 if (!arm_ccnt_enabled(env)) { 1044 /* Counter is disabled, set the absolute value */ 1045 env->cp15.c15_ccnt = value; 1046 return; 1047 } 1048 1049 total_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 1050 ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); 1051 1052 if (env->cp15.c9_pmcr & PMCRD) { 1053 /* Increment once every 64 processor clock cycles */ 1054 total_ticks /= 64; 1055 } 1056 env->cp15.c15_ccnt = total_ticks - value; 1057 } 1058 1059 static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri, 1060 uint64_t value) 1061 { 1062 uint64_t cur_val = pmccntr_read(env, NULL); 1063 1064 pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value)); 1065 } 1066 1067 #else /* CONFIG_USER_ONLY */ 1068 1069 void pmccntr_sync(CPUARMState *env) 1070 { 1071 } 1072 1073 #endif 1074 1075 static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1076 uint64_t value) 1077 { 1078 pmccntr_sync(env); 1079 env->cp15.pmccfiltr_el0 = value & 0x7E000000; 1080 pmccntr_sync(env); 1081 } 1082 1083 static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, 1084 uint64_t value) 1085 { 1086 value &= (1 << 31); 1087 env->cp15.c9_pmcnten |= value; 1088 } 1089 1090 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1091 uint64_t value) 1092 { 1093 value &= (1 << 31); 1094 env->cp15.c9_pmcnten &= ~value; 1095 } 1096 1097 static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1098 uint64_t value) 1099 { 1100 env->cp15.c9_pmovsr &= ~value; 1101 } 1102 1103 static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, 1104 uint64_t value) 1105 { 1106 /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when 1107 * PMSELR value is equal to or greater than the number of implemented 1108 * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI. 1109 */ 1110 if (env->cp15.c9_pmselr == 0x1f) { 1111 pmccfiltr_write(env, ri, value); 1112 } 1113 } 1114 1115 static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri) 1116 { 1117 /* We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER 1118 * are CONSTRAINED UNPREDICTABLE. See comments in pmxevtyper_write(). 1119 */ 1120 if (env->cp15.c9_pmselr == 0x1f) { 1121 return env->cp15.pmccfiltr_el0; 1122 } else { 1123 return 0; 1124 } 1125 } 1126 1127 static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1128 uint64_t value) 1129 { 1130 if (arm_feature(env, ARM_FEATURE_V8)) { 1131 env->cp15.c9_pmuserenr = value & 0xf; 1132 } else { 1133 env->cp15.c9_pmuserenr = value & 1; 1134 } 1135 } 1136 1137 static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri, 1138 uint64_t value) 1139 { 1140 /* We have no event counters so only the C bit can be changed */ 1141 value &= (1 << 31); 1142 env->cp15.c9_pminten |= value; 1143 } 1144 1145 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1146 uint64_t value) 1147 { 1148 value &= (1 << 31); 1149 env->cp15.c9_pminten &= ~value; 1150 } 1151 1152 static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, 1153 uint64_t value) 1154 { 1155 /* Note that even though the AArch64 view of this register has bits 1156 * [10:0] all RES0 we can only mask the bottom 5, to comply with the 1157 * architectural requirements for bits which are RES0 only in some 1158 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7 1159 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.) 1160 */ 1161 raw_write(env, ri, value & ~0x1FULL); 1162 } 1163 1164 static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) 1165 { 1166 /* We only mask off bits that are RES0 both for AArch64 and AArch32. 1167 * For bits that vary between AArch32/64, code needs to check the 1168 * current execution mode before directly using the feature bit. 1169 */ 1170 uint32_t valid_mask = SCR_AARCH64_MASK | SCR_AARCH32_MASK; 1171 1172 if (!arm_feature(env, ARM_FEATURE_EL2)) { 1173 valid_mask &= ~SCR_HCE; 1174 1175 /* On ARMv7, SMD (or SCD as it is called in v7) is only 1176 * supported if EL2 exists. The bit is UNK/SBZP when 1177 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero 1178 * when EL2 is unavailable. 1179 * On ARMv8, this bit is always available. 1180 */ 1181 if (arm_feature(env, ARM_FEATURE_V7) && 1182 !arm_feature(env, ARM_FEATURE_V8)) { 1183 valid_mask &= ~SCR_SMD; 1184 } 1185 } 1186 1187 /* Clear all-context RES0 bits. */ 1188 value &= valid_mask; 1189 raw_write(env, ri, value); 1190 } 1191 1192 static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) 1193 { 1194 ARMCPU *cpu = arm_env_get_cpu(env); 1195 1196 /* Acquire the CSSELR index from the bank corresponding to the CCSIDR 1197 * bank 1198 */ 1199 uint32_t index = A32_BANKED_REG_GET(env, csselr, 1200 ri->secure & ARM_CP_SECSTATE_S); 1201 1202 return cpu->ccsidr[index]; 1203 } 1204 1205 static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1206 uint64_t value) 1207 { 1208 raw_write(env, ri, value & 0xf); 1209 } 1210 1211 static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) 1212 { 1213 CPUState *cs = ENV_GET_CPU(env); 1214 uint64_t ret = 0; 1215 1216 if (cs->interrupt_request & CPU_INTERRUPT_HARD) { 1217 ret |= CPSR_I; 1218 } 1219 if (cs->interrupt_request & CPU_INTERRUPT_FIQ) { 1220 ret |= CPSR_F; 1221 } 1222 /* External aborts are not possible in QEMU so A bit is always clear */ 1223 return ret; 1224 } 1225 1226 static const ARMCPRegInfo v7_cp_reginfo[] = { 1227 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */ 1228 { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, 1229 .access = PL1_W, .type = ARM_CP_NOP }, 1230 /* Performance monitors are implementation defined in v7, 1231 * but with an ARM recommended set of registers, which we 1232 * follow (although we don't actually implement any counters) 1233 * 1234 * Performance registers fall into three categories: 1235 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR) 1236 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR) 1237 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others) 1238 * For the cases controlled by PMUSERENR we must set .access to PL0_RW 1239 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn. 1240 */ 1241 { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1, 1242 .access = PL0_RW, .type = ARM_CP_ALIAS, 1243 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten), 1244 .writefn = pmcntenset_write, 1245 .accessfn = pmreg_access, 1246 .raw_writefn = raw_write }, 1247 { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64, 1248 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1, 1249 .access = PL0_RW, .accessfn = pmreg_access, 1250 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0, 1251 .writefn = pmcntenset_write, .raw_writefn = raw_write }, 1252 { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2, 1253 .access = PL0_RW, 1254 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten), 1255 .accessfn = pmreg_access, 1256 .writefn = pmcntenclr_write, 1257 .type = ARM_CP_ALIAS }, 1258 { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64, 1259 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2, 1260 .access = PL0_RW, .accessfn = pmreg_access, 1261 .type = ARM_CP_ALIAS, 1262 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), 1263 .writefn = pmcntenclr_write }, 1264 { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3, 1265 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), 1266 .accessfn = pmreg_access, 1267 .writefn = pmovsr_write, 1268 .raw_writefn = raw_write }, 1269 { .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64, 1270 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 3, 1271 .access = PL0_RW, .accessfn = pmreg_access, 1272 .type = ARM_CP_ALIAS, 1273 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), 1274 .writefn = pmovsr_write, 1275 .raw_writefn = raw_write }, 1276 /* Unimplemented so WI. */ 1277 { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4, 1278 .access = PL0_W, .accessfn = pmreg_access_swinc, .type = ARM_CP_NOP }, 1279 #ifndef CONFIG_USER_ONLY 1280 { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5, 1281 .access = PL0_RW, .type = ARM_CP_ALIAS, 1282 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr), 1283 .accessfn = pmreg_access_selr, .writefn = pmselr_write, 1284 .raw_writefn = raw_write}, 1285 { .name = "PMSELR_EL0", .state = ARM_CP_STATE_AA64, 1286 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 5, 1287 .access = PL0_RW, .accessfn = pmreg_access_selr, 1288 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmselr), 1289 .writefn = pmselr_write, .raw_writefn = raw_write, }, 1290 { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0, 1291 .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO, 1292 .readfn = pmccntr_read, .writefn = pmccntr_write32, 1293 .accessfn = pmreg_access_ccntr }, 1294 { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64, 1295 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0, 1296 .access = PL0_RW, .accessfn = pmreg_access_ccntr, 1297 .type = ARM_CP_IO, 1298 .readfn = pmccntr_read, .writefn = pmccntr_write, }, 1299 #endif 1300 { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64, 1301 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7, 1302 .writefn = pmccfiltr_write, 1303 .access = PL0_RW, .accessfn = pmreg_access, 1304 .type = ARM_CP_IO, 1305 .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0), 1306 .resetvalue = 0, }, 1307 { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1, 1308 .access = PL0_RW, .type = ARM_CP_NO_RAW, .accessfn = pmreg_access, 1309 .writefn = pmxevtyper_write, .readfn = pmxevtyper_read }, 1310 { .name = "PMXEVTYPER_EL0", .state = ARM_CP_STATE_AA64, 1311 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 1, 1312 .access = PL0_RW, .type = ARM_CP_NO_RAW, .accessfn = pmreg_access, 1313 .writefn = pmxevtyper_write, .readfn = pmxevtyper_read }, 1314 /* Unimplemented, RAZ/WI. */ 1315 { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2, 1316 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0, 1317 .accessfn = pmreg_access_xevcntr }, 1318 { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0, 1319 .access = PL0_R | PL1_RW, .accessfn = access_tpm, 1320 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr), 1321 .resetvalue = 0, 1322 .writefn = pmuserenr_write, .raw_writefn = raw_write }, 1323 { .name = "PMUSERENR_EL0", .state = ARM_CP_STATE_AA64, 1324 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 0, 1325 .access = PL0_R | PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS, 1326 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr), 1327 .resetvalue = 0, 1328 .writefn = pmuserenr_write, .raw_writefn = raw_write }, 1329 { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1, 1330 .access = PL1_RW, .accessfn = access_tpm, 1331 .type = ARM_CP_ALIAS, 1332 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pminten), 1333 .resetvalue = 0, 1334 .writefn = pmintenset_write, .raw_writefn = raw_write }, 1335 { .name = "PMINTENSET_EL1", .state = ARM_CP_STATE_AA64, 1336 .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 1, 1337 .access = PL1_RW, .accessfn = access_tpm, 1338 .type = ARM_CP_IO, 1339 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), 1340 .writefn = pmintenset_write, .raw_writefn = raw_write, 1341 .resetvalue = 0x0 }, 1342 { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2, 1343 .access = PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS, 1344 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), 1345 .writefn = pmintenclr_write, }, 1346 { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64, 1347 .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2, 1348 .access = PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS, 1349 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), 1350 .writefn = pmintenclr_write }, 1351 { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, 1352 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, 1353 .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_RAW }, 1354 { .name = "CSSELR", .state = ARM_CP_STATE_BOTH, 1355 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0, 1356 .access = PL1_RW, .writefn = csselr_write, .resetvalue = 0, 1357 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s), 1358 offsetof(CPUARMState, cp15.csselr_ns) } }, 1359 /* Auxiliary ID register: this actually has an IMPDEF value but for now 1360 * just RAZ for all cores: 1361 */ 1362 { .name = "AIDR", .state = ARM_CP_STATE_BOTH, 1363 .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7, 1364 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 1365 /* Auxiliary fault status registers: these also are IMPDEF, and we 1366 * choose to RAZ/WI for all cores. 1367 */ 1368 { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH, 1369 .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0, 1370 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1371 { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH, 1372 .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1, 1373 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1374 /* MAIR can just read-as-written because we don't implement caches 1375 * and so don't need to care about memory attributes. 1376 */ 1377 { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64, 1378 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, 1379 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]), 1380 .resetvalue = 0 }, 1381 { .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64, 1382 .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0, 1383 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]), 1384 .resetvalue = 0 }, 1385 /* For non-long-descriptor page tables these are PRRR and NMRR; 1386 * regardless they still act as reads-as-written for QEMU. 1387 */ 1388 /* MAIR0/1 are defined separately from their 64-bit counterpart which 1389 * allows them to assign the correct fieldoffset based on the endianness 1390 * handled in the field definitions. 1391 */ 1392 { .name = "MAIR0", .state = ARM_CP_STATE_AA32, 1393 .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW, 1394 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair0_s), 1395 offsetof(CPUARMState, cp15.mair0_ns) }, 1396 .resetfn = arm_cp_reset_ignore }, 1397 { .name = "MAIR1", .state = ARM_CP_STATE_AA32, 1398 .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW, 1399 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair1_s), 1400 offsetof(CPUARMState, cp15.mair1_ns) }, 1401 .resetfn = arm_cp_reset_ignore }, 1402 { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH, 1403 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0, 1404 .type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read }, 1405 /* 32 bit ITLB invalidates */ 1406 { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0, 1407 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write }, 1408 { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1, 1409 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, 1410 { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2, 1411 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write }, 1412 /* 32 bit DTLB invalidates */ 1413 { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0, 1414 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write }, 1415 { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1, 1416 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, 1417 { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2, 1418 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write }, 1419 /* 32 bit TLB invalidates */ 1420 { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, 1421 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write }, 1422 { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, 1423 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, 1424 { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, 1425 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write }, 1426 { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, 1427 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write }, 1428 REGINFO_SENTINEL 1429 }; 1430 1431 static const ARMCPRegInfo v7mp_cp_reginfo[] = { 1432 /* 32 bit TLB invalidates, Inner Shareable */ 1433 { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, 1434 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_is_write }, 1435 { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, 1436 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write }, 1437 { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, 1438 .type = ARM_CP_NO_RAW, .access = PL1_W, 1439 .writefn = tlbiasid_is_write }, 1440 { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, 1441 .type = ARM_CP_NO_RAW, .access = PL1_W, 1442 .writefn = tlbimvaa_is_write }, 1443 REGINFO_SENTINEL 1444 }; 1445 1446 static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1447 uint64_t value) 1448 { 1449 value &= 1; 1450 env->teecr = value; 1451 } 1452 1453 static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri, 1454 bool isread) 1455 { 1456 if (arm_current_el(env) == 0 && (env->teecr & 1)) { 1457 return CP_ACCESS_TRAP; 1458 } 1459 return CP_ACCESS_OK; 1460 } 1461 1462 static const ARMCPRegInfo t2ee_cp_reginfo[] = { 1463 { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0, 1464 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr), 1465 .resetvalue = 0, 1466 .writefn = teecr_write }, 1467 { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0, 1468 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr), 1469 .accessfn = teehbr_access, .resetvalue = 0 }, 1470 REGINFO_SENTINEL 1471 }; 1472 1473 static const ARMCPRegInfo v6k_cp_reginfo[] = { 1474 { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64, 1475 .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0, 1476 .access = PL0_RW, 1477 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 }, 1478 { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2, 1479 .access = PL0_RW, 1480 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s), 1481 offsetoflow32(CPUARMState, cp15.tpidrurw_ns) }, 1482 .resetfn = arm_cp_reset_ignore }, 1483 { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64, 1484 .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0, 1485 .access = PL0_R|PL1_W, 1486 .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]), 1487 .resetvalue = 0}, 1488 { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3, 1489 .access = PL0_R|PL1_W, 1490 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s), 1491 offsetoflow32(CPUARMState, cp15.tpidruro_ns) }, 1492 .resetfn = arm_cp_reset_ignore }, 1493 { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64, 1494 .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0, 1495 .access = PL1_RW, 1496 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 }, 1497 { .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4, 1498 .access = PL1_RW, 1499 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s), 1500 offsetoflow32(CPUARMState, cp15.tpidrprw_ns) }, 1501 .resetvalue = 0 }, 1502 REGINFO_SENTINEL 1503 }; 1504 1505 #ifndef CONFIG_USER_ONLY 1506 1507 static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri, 1508 bool isread) 1509 { 1510 /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero. 1511 * Writable only at the highest implemented exception level. 1512 */ 1513 int el = arm_current_el(env); 1514 1515 switch (el) { 1516 case 0: 1517 if (!extract32(env->cp15.c14_cntkctl, 0, 2)) { 1518 return CP_ACCESS_TRAP; 1519 } 1520 break; 1521 case 1: 1522 if (!isread && ri->state == ARM_CP_STATE_AA32 && 1523 arm_is_secure_below_el3(env)) { 1524 /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */ 1525 return CP_ACCESS_TRAP_UNCATEGORIZED; 1526 } 1527 break; 1528 case 2: 1529 case 3: 1530 break; 1531 } 1532 1533 if (!isread && el < arm_highest_el(env)) { 1534 return CP_ACCESS_TRAP_UNCATEGORIZED; 1535 } 1536 1537 return CP_ACCESS_OK; 1538 } 1539 1540 static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx, 1541 bool isread) 1542 { 1543 unsigned int cur_el = arm_current_el(env); 1544 bool secure = arm_is_secure(env); 1545 1546 /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */ 1547 if (cur_el == 0 && 1548 !extract32(env->cp15.c14_cntkctl, timeridx, 1)) { 1549 return CP_ACCESS_TRAP; 1550 } 1551 1552 if (arm_feature(env, ARM_FEATURE_EL2) && 1553 timeridx == GTIMER_PHYS && !secure && cur_el < 2 && 1554 !extract32(env->cp15.cnthctl_el2, 0, 1)) { 1555 return CP_ACCESS_TRAP_EL2; 1556 } 1557 return CP_ACCESS_OK; 1558 } 1559 1560 static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx, 1561 bool isread) 1562 { 1563 unsigned int cur_el = arm_current_el(env); 1564 bool secure = arm_is_secure(env); 1565 1566 /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if 1567 * EL0[PV]TEN is zero. 1568 */ 1569 if (cur_el == 0 && 1570 !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) { 1571 return CP_ACCESS_TRAP; 1572 } 1573 1574 if (arm_feature(env, ARM_FEATURE_EL2) && 1575 timeridx == GTIMER_PHYS && !secure && cur_el < 2 && 1576 !extract32(env->cp15.cnthctl_el2, 1, 1)) { 1577 return CP_ACCESS_TRAP_EL2; 1578 } 1579 return CP_ACCESS_OK; 1580 } 1581 1582 static CPAccessResult gt_pct_access(CPUARMState *env, 1583 const ARMCPRegInfo *ri, 1584 bool isread) 1585 { 1586 return gt_counter_access(env, GTIMER_PHYS, isread); 1587 } 1588 1589 static CPAccessResult gt_vct_access(CPUARMState *env, 1590 const ARMCPRegInfo *ri, 1591 bool isread) 1592 { 1593 return gt_counter_access(env, GTIMER_VIRT, isread); 1594 } 1595 1596 static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri, 1597 bool isread) 1598 { 1599 return gt_timer_access(env, GTIMER_PHYS, isread); 1600 } 1601 1602 static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri, 1603 bool isread) 1604 { 1605 return gt_timer_access(env, GTIMER_VIRT, isread); 1606 } 1607 1608 static CPAccessResult gt_stimer_access(CPUARMState *env, 1609 const ARMCPRegInfo *ri, 1610 bool isread) 1611 { 1612 /* The AArch64 register view of the secure physical timer is 1613 * always accessible from EL3, and configurably accessible from 1614 * Secure EL1. 1615 */ 1616 switch (arm_current_el(env)) { 1617 case 1: 1618 if (!arm_is_secure(env)) { 1619 return CP_ACCESS_TRAP; 1620 } 1621 if (!(env->cp15.scr_el3 & SCR_ST)) { 1622 return CP_ACCESS_TRAP_EL3; 1623 } 1624 return CP_ACCESS_OK; 1625 case 0: 1626 case 2: 1627 return CP_ACCESS_TRAP; 1628 case 3: 1629 return CP_ACCESS_OK; 1630 default: 1631 g_assert_not_reached(); 1632 } 1633 } 1634 1635 static uint64_t gt_get_countervalue(CPUARMState *env) 1636 { 1637 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE; 1638 } 1639 1640 static void gt_recalc_timer(ARMCPU *cpu, int timeridx) 1641 { 1642 ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx]; 1643 1644 if (gt->ctl & 1) { 1645 /* Timer enabled: calculate and set current ISTATUS, irq, and 1646 * reset timer to when ISTATUS next has to change 1647 */ 1648 uint64_t offset = timeridx == GTIMER_VIRT ? 1649 cpu->env.cp15.cntvoff_el2 : 0; 1650 uint64_t count = gt_get_countervalue(&cpu->env); 1651 /* Note that this must be unsigned 64 bit arithmetic: */ 1652 int istatus = count - offset >= gt->cval; 1653 uint64_t nexttick; 1654 int irqstate; 1655 1656 gt->ctl = deposit32(gt->ctl, 2, 1, istatus); 1657 1658 irqstate = (istatus && !(gt->ctl & 2)); 1659 qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate); 1660 1661 if (istatus) { 1662 /* Next transition is when count rolls back over to zero */ 1663 nexttick = UINT64_MAX; 1664 } else { 1665 /* Next transition is when we hit cval */ 1666 nexttick = gt->cval + offset; 1667 } 1668 /* Note that the desired next expiry time might be beyond the 1669 * signed-64-bit range of a QEMUTimer -- in this case we just 1670 * set the timer for as far in the future as possible. When the 1671 * timer expires we will reset the timer for any remaining period. 1672 */ 1673 if (nexttick > INT64_MAX / GTIMER_SCALE) { 1674 nexttick = INT64_MAX / GTIMER_SCALE; 1675 } 1676 timer_mod(cpu->gt_timer[timeridx], nexttick); 1677 trace_arm_gt_recalc(timeridx, irqstate, nexttick); 1678 } else { 1679 /* Timer disabled: ISTATUS and timer output always clear */ 1680 gt->ctl &= ~4; 1681 qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0); 1682 timer_del(cpu->gt_timer[timeridx]); 1683 trace_arm_gt_recalc_disabled(timeridx); 1684 } 1685 } 1686 1687 static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri, 1688 int timeridx) 1689 { 1690 ARMCPU *cpu = arm_env_get_cpu(env); 1691 1692 timer_del(cpu->gt_timer[timeridx]); 1693 } 1694 1695 static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) 1696 { 1697 return gt_get_countervalue(env); 1698 } 1699 1700 static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) 1701 { 1702 return gt_get_countervalue(env) - env->cp15.cntvoff_el2; 1703 } 1704 1705 static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1706 int timeridx, 1707 uint64_t value) 1708 { 1709 trace_arm_gt_cval_write(timeridx, value); 1710 env->cp15.c14_timer[timeridx].cval = value; 1711 gt_recalc_timer(arm_env_get_cpu(env), timeridx); 1712 } 1713 1714 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri, 1715 int timeridx) 1716 { 1717 uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0; 1718 1719 return (uint32_t)(env->cp15.c14_timer[timeridx].cval - 1720 (gt_get_countervalue(env) - offset)); 1721 } 1722 1723 static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1724 int timeridx, 1725 uint64_t value) 1726 { 1727 uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0; 1728 1729 trace_arm_gt_tval_write(timeridx, value); 1730 env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset + 1731 sextract64(value, 0, 32); 1732 gt_recalc_timer(arm_env_get_cpu(env), timeridx); 1733 } 1734 1735 static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, 1736 int timeridx, 1737 uint64_t value) 1738 { 1739 ARMCPU *cpu = arm_env_get_cpu(env); 1740 uint32_t oldval = env->cp15.c14_timer[timeridx].ctl; 1741 1742 trace_arm_gt_ctl_write(timeridx, value); 1743 env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value); 1744 if ((oldval ^ value) & 1) { 1745 /* Enable toggled */ 1746 gt_recalc_timer(cpu, timeridx); 1747 } else if ((oldval ^ value) & 2) { 1748 /* IMASK toggled: don't need to recalculate, 1749 * just set the interrupt line based on ISTATUS 1750 */ 1751 int irqstate = (oldval & 4) && !(value & 2); 1752 1753 trace_arm_gt_imask_toggle(timeridx, irqstate); 1754 qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate); 1755 } 1756 } 1757 1758 static void gt_phys_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) 1759 { 1760 gt_timer_reset(env, ri, GTIMER_PHYS); 1761 } 1762 1763 static void gt_phys_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1764 uint64_t value) 1765 { 1766 gt_cval_write(env, ri, GTIMER_PHYS, value); 1767 } 1768 1769 static uint64_t gt_phys_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) 1770 { 1771 return gt_tval_read(env, ri, GTIMER_PHYS); 1772 } 1773 1774 static void gt_phys_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1775 uint64_t value) 1776 { 1777 gt_tval_write(env, ri, GTIMER_PHYS, value); 1778 } 1779 1780 static void gt_phys_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, 1781 uint64_t value) 1782 { 1783 gt_ctl_write(env, ri, GTIMER_PHYS, value); 1784 } 1785 1786 static void gt_virt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) 1787 { 1788 gt_timer_reset(env, ri, GTIMER_VIRT); 1789 } 1790 1791 static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1792 uint64_t value) 1793 { 1794 gt_cval_write(env, ri, GTIMER_VIRT, value); 1795 } 1796 1797 static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) 1798 { 1799 return gt_tval_read(env, ri, GTIMER_VIRT); 1800 } 1801 1802 static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1803 uint64_t value) 1804 { 1805 gt_tval_write(env, ri, GTIMER_VIRT, value); 1806 } 1807 1808 static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, 1809 uint64_t value) 1810 { 1811 gt_ctl_write(env, ri, GTIMER_VIRT, value); 1812 } 1813 1814 static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri, 1815 uint64_t value) 1816 { 1817 ARMCPU *cpu = arm_env_get_cpu(env); 1818 1819 trace_arm_gt_cntvoff_write(value); 1820 raw_write(env, ri, value); 1821 gt_recalc_timer(cpu, GTIMER_VIRT); 1822 } 1823 1824 static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) 1825 { 1826 gt_timer_reset(env, ri, GTIMER_HYP); 1827 } 1828 1829 static void gt_hyp_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1830 uint64_t value) 1831 { 1832 gt_cval_write(env, ri, GTIMER_HYP, value); 1833 } 1834 1835 static uint64_t gt_hyp_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) 1836 { 1837 return gt_tval_read(env, ri, GTIMER_HYP); 1838 } 1839 1840 static void gt_hyp_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1841 uint64_t value) 1842 { 1843 gt_tval_write(env, ri, GTIMER_HYP, value); 1844 } 1845 1846 static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, 1847 uint64_t value) 1848 { 1849 gt_ctl_write(env, ri, GTIMER_HYP, value); 1850 } 1851 1852 static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) 1853 { 1854 gt_timer_reset(env, ri, GTIMER_SEC); 1855 } 1856 1857 static void gt_sec_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1858 uint64_t value) 1859 { 1860 gt_cval_write(env, ri, GTIMER_SEC, value); 1861 } 1862 1863 static uint64_t gt_sec_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) 1864 { 1865 return gt_tval_read(env, ri, GTIMER_SEC); 1866 } 1867 1868 static void gt_sec_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1869 uint64_t value) 1870 { 1871 gt_tval_write(env, ri, GTIMER_SEC, value); 1872 } 1873 1874 static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, 1875 uint64_t value) 1876 { 1877 gt_ctl_write(env, ri, GTIMER_SEC, value); 1878 } 1879 1880 void arm_gt_ptimer_cb(void *opaque) 1881 { 1882 ARMCPU *cpu = opaque; 1883 1884 gt_recalc_timer(cpu, GTIMER_PHYS); 1885 } 1886 1887 void arm_gt_vtimer_cb(void *opaque) 1888 { 1889 ARMCPU *cpu = opaque; 1890 1891 gt_recalc_timer(cpu, GTIMER_VIRT); 1892 } 1893 1894 void arm_gt_htimer_cb(void *opaque) 1895 { 1896 ARMCPU *cpu = opaque; 1897 1898 gt_recalc_timer(cpu, GTIMER_HYP); 1899 } 1900 1901 void arm_gt_stimer_cb(void *opaque) 1902 { 1903 ARMCPU *cpu = opaque; 1904 1905 gt_recalc_timer(cpu, GTIMER_SEC); 1906 } 1907 1908 static const ARMCPRegInfo generic_timer_cp_reginfo[] = { 1909 /* Note that CNTFRQ is purely reads-as-written for the benefit 1910 * of software; writing it doesn't actually change the timer frequency. 1911 * Our reset value matches the fixed frequency we implement the timer at. 1912 */ 1913 { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0, 1914 .type = ARM_CP_ALIAS, 1915 .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, 1916 .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq), 1917 }, 1918 { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64, 1919 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0, 1920 .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, 1921 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq), 1922 .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE, 1923 }, 1924 /* overall control: mostly access permissions */ 1925 { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH, 1926 .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0, 1927 .access = PL1_RW, 1928 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl), 1929 .resetvalue = 0, 1930 }, 1931 /* per-timer control */ 1932 { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1, 1933 .secure = ARM_CP_SECSTATE_NS, 1934 .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R, 1935 .accessfn = gt_ptimer_access, 1936 .fieldoffset = offsetoflow32(CPUARMState, 1937 cp15.c14_timer[GTIMER_PHYS].ctl), 1938 .writefn = gt_phys_ctl_write, .raw_writefn = raw_write, 1939 }, 1940 { .name = "CNTP_CTL(S)", 1941 .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1, 1942 .secure = ARM_CP_SECSTATE_S, 1943 .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R, 1944 .accessfn = gt_ptimer_access, 1945 .fieldoffset = offsetoflow32(CPUARMState, 1946 cp15.c14_timer[GTIMER_SEC].ctl), 1947 .writefn = gt_sec_ctl_write, .raw_writefn = raw_write, 1948 }, 1949 { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64, 1950 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1, 1951 .type = ARM_CP_IO, .access = PL1_RW | PL0_R, 1952 .accessfn = gt_ptimer_access, 1953 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl), 1954 .resetvalue = 0, 1955 .writefn = gt_phys_ctl_write, .raw_writefn = raw_write, 1956 }, 1957 { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1, 1958 .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R, 1959 .accessfn = gt_vtimer_access, 1960 .fieldoffset = offsetoflow32(CPUARMState, 1961 cp15.c14_timer[GTIMER_VIRT].ctl), 1962 .writefn = gt_virt_ctl_write, .raw_writefn = raw_write, 1963 }, 1964 { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64, 1965 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1, 1966 .type = ARM_CP_IO, .access = PL1_RW | PL0_R, 1967 .accessfn = gt_vtimer_access, 1968 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl), 1969 .resetvalue = 0, 1970 .writefn = gt_virt_ctl_write, .raw_writefn = raw_write, 1971 }, 1972 /* TimerValue views: a 32 bit downcounting view of the underlying state */ 1973 { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0, 1974 .secure = ARM_CP_SECSTATE_NS, 1975 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R, 1976 .accessfn = gt_ptimer_access, 1977 .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write, 1978 }, 1979 { .name = "CNTP_TVAL(S)", 1980 .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0, 1981 .secure = ARM_CP_SECSTATE_S, 1982 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R, 1983 .accessfn = gt_ptimer_access, 1984 .readfn = gt_sec_tval_read, .writefn = gt_sec_tval_write, 1985 }, 1986 { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64, 1987 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0, 1988 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R, 1989 .accessfn = gt_ptimer_access, .resetfn = gt_phys_timer_reset, 1990 .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write, 1991 }, 1992 { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0, 1993 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R, 1994 .accessfn = gt_vtimer_access, 1995 .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write, 1996 }, 1997 { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64, 1998 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0, 1999 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R, 2000 .accessfn = gt_vtimer_access, .resetfn = gt_virt_timer_reset, 2001 .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write, 2002 }, 2003 /* The counter itself */ 2004 { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0, 2005 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, 2006 .accessfn = gt_pct_access, 2007 .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore, 2008 }, 2009 { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64, 2010 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1, 2011 .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, 2012 .accessfn = gt_pct_access, .readfn = gt_cnt_read, 2013 }, 2014 { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1, 2015 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, 2016 .accessfn = gt_vct_access, 2017 .readfn = gt_virt_cnt_read, .resetfn = arm_cp_reset_ignore, 2018 }, 2019 { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64, 2020 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2, 2021 .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, 2022 .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read, 2023 }, 2024 /* Comparison value, indicating when the timer goes off */ 2025 { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2, 2026 .secure = ARM_CP_SECSTATE_NS, 2027 .access = PL1_RW | PL0_R, 2028 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, 2029 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), 2030 .accessfn = gt_ptimer_access, 2031 .writefn = gt_phys_cval_write, .raw_writefn = raw_write, 2032 }, 2033 { .name = "CNTP_CVAL(S)", .cp = 15, .crm = 14, .opc1 = 2, 2034 .secure = ARM_CP_SECSTATE_S, 2035 .access = PL1_RW | PL0_R, 2036 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, 2037 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval), 2038 .accessfn = gt_ptimer_access, 2039 .writefn = gt_sec_cval_write, .raw_writefn = raw_write, 2040 }, 2041 { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64, 2042 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2, 2043 .access = PL1_RW | PL0_R, 2044 .type = ARM_CP_IO, 2045 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), 2046 .resetvalue = 0, .accessfn = gt_ptimer_access, 2047 .writefn = gt_phys_cval_write, .raw_writefn = raw_write, 2048 }, 2049 { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3, 2050 .access = PL1_RW | PL0_R, 2051 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, 2052 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), 2053 .accessfn = gt_vtimer_access, 2054 .writefn = gt_virt_cval_write, .raw_writefn = raw_write, 2055 }, 2056 { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64, 2057 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2, 2058 .access = PL1_RW | PL0_R, 2059 .type = ARM_CP_IO, 2060 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), 2061 .resetvalue = 0, .accessfn = gt_vtimer_access, 2062 .writefn = gt_virt_cval_write, .raw_writefn = raw_write, 2063 }, 2064 /* Secure timer -- this is actually restricted to only EL3 2065 * and configurably Secure-EL1 via the accessfn. 2066 */ 2067 { .name = "CNTPS_TVAL_EL1", .state = ARM_CP_STATE_AA64, 2068 .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 0, 2069 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW, 2070 .accessfn = gt_stimer_access, 2071 .readfn = gt_sec_tval_read, 2072 .writefn = gt_sec_tval_write, 2073 .resetfn = gt_sec_timer_reset, 2074 }, 2075 { .name = "CNTPS_CTL_EL1", .state = ARM_CP_STATE_AA64, 2076 .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 1, 2077 .type = ARM_CP_IO, .access = PL1_RW, 2078 .accessfn = gt_stimer_access, 2079 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].ctl), 2080 .resetvalue = 0, 2081 .writefn = gt_sec_ctl_write, .raw_writefn = raw_write, 2082 }, 2083 { .name = "CNTPS_CVAL_EL1", .state = ARM_CP_STATE_AA64, 2084 .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 2, 2085 .type = ARM_CP_IO, .access = PL1_RW, 2086 .accessfn = gt_stimer_access, 2087 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval), 2088 .writefn = gt_sec_cval_write, .raw_writefn = raw_write, 2089 }, 2090 REGINFO_SENTINEL 2091 }; 2092 2093 #else 2094 /* In user-mode none of the generic timer registers are accessible, 2095 * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs, 2096 * so instead just don't register any of them. 2097 */ 2098 static const ARMCPRegInfo generic_timer_cp_reginfo[] = { 2099 REGINFO_SENTINEL 2100 }; 2101 2102 #endif 2103 2104 static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) 2105 { 2106 if (arm_feature(env, ARM_FEATURE_LPAE)) { 2107 raw_write(env, ri, value); 2108 } else if (arm_feature(env, ARM_FEATURE_V7)) { 2109 raw_write(env, ri, value & 0xfffff6ff); 2110 } else { 2111 raw_write(env, ri, value & 0xfffff1ff); 2112 } 2113 } 2114 2115 #ifndef CONFIG_USER_ONLY 2116 /* get_phys_addr() isn't present for user-mode-only targets */ 2117 2118 static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri, 2119 bool isread) 2120 { 2121 if (ri->opc2 & 4) { 2122 /* The ATS12NSO* operations must trap to EL3 if executed in 2123 * Secure EL1 (which can only happen if EL3 is AArch64). 2124 * They are simply UNDEF if executed from NS EL1. 2125 * They function normally from EL2 or EL3. 2126 */ 2127 if (arm_current_el(env) == 1) { 2128 if (arm_is_secure_below_el3(env)) { 2129 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3; 2130 } 2131 return CP_ACCESS_TRAP_UNCATEGORIZED; 2132 } 2133 } 2134 return CP_ACCESS_OK; 2135 } 2136 2137 static uint64_t do_ats_write(CPUARMState *env, uint64_t value, 2138 MMUAccessType access_type, ARMMMUIdx mmu_idx) 2139 { 2140 hwaddr phys_addr; 2141 target_ulong page_size; 2142 int prot; 2143 uint32_t fsr; 2144 bool ret; 2145 uint64_t par64; 2146 MemTxAttrs attrs = {}; 2147 ARMMMUFaultInfo fi = {}; 2148 2149 ret = get_phys_addr(env, value, access_type, mmu_idx, 2150 &phys_addr, &attrs, &prot, &page_size, &fsr, &fi); 2151 if (extended_addresses_enabled(env)) { 2152 /* fsr is a DFSR/IFSR value for the long descriptor 2153 * translation table format, but with WnR always clear. 2154 * Convert it to a 64-bit PAR. 2155 */ 2156 par64 = (1 << 11); /* LPAE bit always set */ 2157 if (!ret) { 2158 par64 |= phys_addr & ~0xfffULL; 2159 if (!attrs.secure) { 2160 par64 |= (1 << 9); /* NS */ 2161 } 2162 /* We don't set the ATTR or SH fields in the PAR. */ 2163 } else { 2164 par64 |= 1; /* F */ 2165 par64 |= (fsr & 0x3f) << 1; /* FS */ 2166 /* Note that S2WLK and FSTAGE are always zero, because we don't 2167 * implement virtualization and therefore there can't be a stage 2 2168 * fault. 2169 */ 2170 } 2171 } else { 2172 /* fsr is a DFSR/IFSR value for the short descriptor 2173 * translation table format (with WnR always clear). 2174 * Convert it to a 32-bit PAR. 2175 */ 2176 if (!ret) { 2177 /* We do not set any attribute bits in the PAR */ 2178 if (page_size == (1 << 24) 2179 && arm_feature(env, ARM_FEATURE_V7)) { 2180 par64 = (phys_addr & 0xff000000) | (1 << 1); 2181 } else { 2182 par64 = phys_addr & 0xfffff000; 2183 } 2184 if (!attrs.secure) { 2185 par64 |= (1 << 9); /* NS */ 2186 } 2187 } else { 2188 par64 = ((fsr & (1 << 10)) >> 5) | ((fsr & (1 << 12)) >> 6) | 2189 ((fsr & 0xf) << 1) | 1; 2190 } 2191 } 2192 return par64; 2193 } 2194 2195 static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) 2196 { 2197 MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; 2198 uint64_t par64; 2199 ARMMMUIdx mmu_idx; 2200 int el = arm_current_el(env); 2201 bool secure = arm_is_secure_below_el3(env); 2202 2203 switch (ri->opc2 & 6) { 2204 case 0: 2205 /* stage 1 current state PL1: ATS1CPR, ATS1CPW */ 2206 switch (el) { 2207 case 3: 2208 mmu_idx = ARMMMUIdx_S1E3; 2209 break; 2210 case 2: 2211 mmu_idx = ARMMMUIdx_S1NSE1; 2212 break; 2213 case 1: 2214 mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1; 2215 break; 2216 default: 2217 g_assert_not_reached(); 2218 } 2219 break; 2220 case 2: 2221 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */ 2222 switch (el) { 2223 case 3: 2224 mmu_idx = ARMMMUIdx_S1SE0; 2225 break; 2226 case 2: 2227 mmu_idx = ARMMMUIdx_S1NSE0; 2228 break; 2229 case 1: 2230 mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0; 2231 break; 2232 default: 2233 g_assert_not_reached(); 2234 } 2235 break; 2236 case 4: 2237 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */ 2238 mmu_idx = ARMMMUIdx_S12NSE1; 2239 break; 2240 case 6: 2241 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */ 2242 mmu_idx = ARMMMUIdx_S12NSE0; 2243 break; 2244 default: 2245 g_assert_not_reached(); 2246 } 2247 2248 par64 = do_ats_write(env, value, access_type, mmu_idx); 2249 2250 A32_BANKED_CURRENT_REG_SET(env, par, par64); 2251 } 2252 2253 static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri, 2254 uint64_t value) 2255 { 2256 MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; 2257 uint64_t par64; 2258 2259 par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S2NS); 2260 2261 A32_BANKED_CURRENT_REG_SET(env, par, par64); 2262 } 2263 2264 static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri, 2265 bool isread) 2266 { 2267 if (arm_current_el(env) == 3 && !(env->cp15.scr_el3 & SCR_NS)) { 2268 return CP_ACCESS_TRAP; 2269 } 2270 return CP_ACCESS_OK; 2271 } 2272 2273 static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, 2274 uint64_t value) 2275 { 2276 MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; 2277 ARMMMUIdx mmu_idx; 2278 int secure = arm_is_secure_below_el3(env); 2279 2280 switch (ri->opc2 & 6) { 2281 case 0: 2282 switch (ri->opc1) { 2283 case 0: /* AT S1E1R, AT S1E1W */ 2284 mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1; 2285 break; 2286 case 4: /* AT S1E2R, AT S1E2W */ 2287 mmu_idx = ARMMMUIdx_S1E2; 2288 break; 2289 case 6: /* AT S1E3R, AT S1E3W */ 2290 mmu_idx = ARMMMUIdx_S1E3; 2291 break; 2292 default: 2293 g_assert_not_reached(); 2294 } 2295 break; 2296 case 2: /* AT S1E0R, AT S1E0W */ 2297 mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0; 2298 break; 2299 case 4: /* AT S12E1R, AT S12E1W */ 2300 mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S12NSE1; 2301 break; 2302 case 6: /* AT S12E0R, AT S12E0W */ 2303 mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S12NSE0; 2304 break; 2305 default: 2306 g_assert_not_reached(); 2307 } 2308 2309 env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx); 2310 } 2311 #endif 2312 2313 static const ARMCPRegInfo vapa_cp_reginfo[] = { 2314 { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0, 2315 .access = PL1_RW, .resetvalue = 0, 2316 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s), 2317 offsetoflow32(CPUARMState, cp15.par_ns) }, 2318 .writefn = par_write }, 2319 #ifndef CONFIG_USER_ONLY 2320 /* This underdecoding is safe because the reginfo is NO_RAW. */ 2321 { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY, 2322 .access = PL1_W, .accessfn = ats_access, 2323 .writefn = ats_write, .type = ARM_CP_NO_RAW }, 2324 #endif 2325 REGINFO_SENTINEL 2326 }; 2327 2328 /* Return basic MPU access permission bits. */ 2329 static uint32_t simple_mpu_ap_bits(uint32_t val) 2330 { 2331 uint32_t ret; 2332 uint32_t mask; 2333 int i; 2334 ret = 0; 2335 mask = 3; 2336 for (i = 0; i < 16; i += 2) { 2337 ret |= (val >> i) & mask; 2338 mask <<= 2; 2339 } 2340 return ret; 2341 } 2342 2343 /* Pad basic MPU access permission bits to extended format. */ 2344 static uint32_t extended_mpu_ap_bits(uint32_t val) 2345 { 2346 uint32_t ret; 2347 uint32_t mask; 2348 int i; 2349 ret = 0; 2350 mask = 3; 2351 for (i = 0; i < 16; i += 2) { 2352 ret |= (val & mask) << i; 2353 mask <<= 2; 2354 } 2355 return ret; 2356 } 2357 2358 static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, 2359 uint64_t value) 2360 { 2361 env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value); 2362 } 2363 2364 static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) 2365 { 2366 return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap); 2367 } 2368 2369 static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, 2370 uint64_t value) 2371 { 2372 env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value); 2373 } 2374 2375 static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) 2376 { 2377 return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap); 2378 } 2379 2380 static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri) 2381 { 2382 uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri); 2383 2384 if (!u32p) { 2385 return 0; 2386 } 2387 2388 u32p += env->pmsav7.rnr[M_REG_NS]; 2389 return *u32p; 2390 } 2391 2392 static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri, 2393 uint64_t value) 2394 { 2395 ARMCPU *cpu = arm_env_get_cpu(env); 2396 uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri); 2397 2398 if (!u32p) { 2399 return; 2400 } 2401 2402 u32p += env->pmsav7.rnr[M_REG_NS]; 2403 tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ 2404 *u32p = value; 2405 } 2406 2407 static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri, 2408 uint64_t value) 2409 { 2410 ARMCPU *cpu = arm_env_get_cpu(env); 2411 uint32_t nrgs = cpu->pmsav7_dregion; 2412 2413 if (value >= nrgs) { 2414 qemu_log_mask(LOG_GUEST_ERROR, 2415 "PMSAv7 RGNR write >= # supported regions, %" PRIu32 2416 " > %" PRIu32 "\n", (uint32_t)value, nrgs); 2417 return; 2418 } 2419 2420 raw_write(env, ri, value); 2421 } 2422 2423 static const ARMCPRegInfo pmsav7_cp_reginfo[] = { 2424 /* Reset for all these registers is handled in arm_cpu_reset(), 2425 * because the PMSAv7 is also used by M-profile CPUs, which do 2426 * not register cpregs but still need the state to be reset. 2427 */ 2428 { .name = "DRBAR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 0, 2429 .access = PL1_RW, .type = ARM_CP_NO_RAW, 2430 .fieldoffset = offsetof(CPUARMState, pmsav7.drbar), 2431 .readfn = pmsav7_read, .writefn = pmsav7_write, 2432 .resetfn = arm_cp_reset_ignore }, 2433 { .name = "DRSR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 2, 2434 .access = PL1_RW, .type = ARM_CP_NO_RAW, 2435 .fieldoffset = offsetof(CPUARMState, pmsav7.drsr), 2436 .readfn = pmsav7_read, .writefn = pmsav7_write, 2437 .resetfn = arm_cp_reset_ignore }, 2438 { .name = "DRACR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 4, 2439 .access = PL1_RW, .type = ARM_CP_NO_RAW, 2440 .fieldoffset = offsetof(CPUARMState, pmsav7.dracr), 2441 .readfn = pmsav7_read, .writefn = pmsav7_write, 2442 .resetfn = arm_cp_reset_ignore }, 2443 { .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0, 2444 .access = PL1_RW, 2445 .fieldoffset = offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]), 2446 .writefn = pmsav7_rgnr_write, 2447 .resetfn = arm_cp_reset_ignore }, 2448 REGINFO_SENTINEL 2449 }; 2450 2451 static const ARMCPRegInfo pmsav5_cp_reginfo[] = { 2452 { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, 2453 .access = PL1_RW, .type = ARM_CP_ALIAS, 2454 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap), 2455 .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, }, 2456 { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, 2457 .access = PL1_RW, .type = ARM_CP_ALIAS, 2458 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap), 2459 .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, }, 2460 { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2, 2461 .access = PL1_RW, 2462 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap), 2463 .resetvalue = 0, }, 2464 { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3, 2465 .access = PL1_RW, 2466 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap), 2467 .resetvalue = 0, }, 2468 { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, 2469 .access = PL1_RW, 2470 .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, }, 2471 { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1, 2472 .access = PL1_RW, 2473 .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, }, 2474 /* Protection region base and size registers */ 2475 { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, 2476 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, 2477 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) }, 2478 { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0, 2479 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, 2480 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) }, 2481 { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0, 2482 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, 2483 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) }, 2484 { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0, 2485 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, 2486 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) }, 2487 { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0, 2488 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, 2489 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) }, 2490 { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0, 2491 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, 2492 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) }, 2493 { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0, 2494 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, 2495 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) }, 2496 { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0, 2497 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, 2498 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) }, 2499 REGINFO_SENTINEL 2500 }; 2501 2502 static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, 2503 uint64_t value) 2504 { 2505 TCR *tcr = raw_ptr(env, ri); 2506 int maskshift = extract32(value, 0, 3); 2507 2508 if (!arm_feature(env, ARM_FEATURE_V8)) { 2509 if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) { 2510 /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when 2511 * using Long-desciptor translation table format */ 2512 value &= ~((7 << 19) | (3 << 14) | (0xf << 3)); 2513 } else if (arm_feature(env, ARM_FEATURE_EL3)) { 2514 /* In an implementation that includes the Security Extensions 2515 * TTBCR has additional fields PD0 [4] and PD1 [5] for 2516 * Short-descriptor translation table format. 2517 */ 2518 value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N; 2519 } else { 2520 value &= TTBCR_N; 2521 } 2522 } 2523 2524 /* Update the masks corresponding to the TCR bank being written 2525 * Note that we always calculate mask and base_mask, but 2526 * they are only used for short-descriptor tables (ie if EAE is 0); 2527 * for long-descriptor tables the TCR fields are used differently 2528 * and the mask and base_mask values are meaningless. 2529 */ 2530 tcr->raw_tcr = value; 2531 tcr->mask = ~(((uint32_t)0xffffffffu) >> maskshift); 2532 tcr->base_mask = ~((uint32_t)0x3fffu >> maskshift); 2533 } 2534 2535 static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, 2536 uint64_t value) 2537 { 2538 ARMCPU *cpu = arm_env_get_cpu(env); 2539 2540 if (arm_feature(env, ARM_FEATURE_LPAE)) { 2541 /* With LPAE the TTBCR could result in a change of ASID 2542 * via the TTBCR.A1 bit, so do a TLB flush. 2543 */ 2544 tlb_flush(CPU(cpu)); 2545 } 2546 vmsa_ttbcr_raw_write(env, ri, value); 2547 } 2548 2549 static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri) 2550 { 2551 TCR *tcr = raw_ptr(env, ri); 2552 2553 /* Reset both the TCR as well as the masks corresponding to the bank of 2554 * the TCR being reset. 2555 */ 2556 tcr->raw_tcr = 0; 2557 tcr->mask = 0; 2558 tcr->base_mask = 0xffffc000u; 2559 } 2560 2561 static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, 2562 uint64_t value) 2563 { 2564 ARMCPU *cpu = arm_env_get_cpu(env); 2565 TCR *tcr = raw_ptr(env, ri); 2566 2567 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */ 2568 tlb_flush(CPU(cpu)); 2569 tcr->raw_tcr = value; 2570 } 2571 2572 static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, 2573 uint64_t value) 2574 { 2575 /* 64 bit accesses to the TTBRs can change the ASID and so we 2576 * must flush the TLB. 2577 */ 2578 if (cpreg_field_is_64bit(ri)) { 2579 ARMCPU *cpu = arm_env_get_cpu(env); 2580 2581 tlb_flush(CPU(cpu)); 2582 } 2583 raw_write(env, ri, value); 2584 } 2585 2586 static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, 2587 uint64_t value) 2588 { 2589 ARMCPU *cpu = arm_env_get_cpu(env); 2590 CPUState *cs = CPU(cpu); 2591 2592 /* Accesses to VTTBR may change the VMID so we must flush the TLB. */ 2593 if (raw_read(env, ri) != value) { 2594 tlb_flush_by_mmuidx(cs, 2595 ARMMMUIdxBit_S12NSE1 | 2596 ARMMMUIdxBit_S12NSE0 | 2597 ARMMMUIdxBit_S2NS); 2598 raw_write(env, ri, value); 2599 } 2600 } 2601 2602 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = { 2603 { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, 2604 .access = PL1_RW, .type = ARM_CP_ALIAS, 2605 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s), 2606 offsetoflow32(CPUARMState, cp15.dfsr_ns) }, }, 2607 { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, 2608 .access = PL1_RW, .resetvalue = 0, 2609 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s), 2610 offsetoflow32(CPUARMState, cp15.ifsr_ns) } }, 2611 { .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0, 2612 .access = PL1_RW, .resetvalue = 0, 2613 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s), 2614 offsetof(CPUARMState, cp15.dfar_ns) } }, 2615 { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64, 2616 .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, 2617 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]), 2618 .resetvalue = 0, }, 2619 REGINFO_SENTINEL 2620 }; 2621 2622 static const ARMCPRegInfo vmsa_cp_reginfo[] = { 2623 { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64, 2624 .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0, 2625 .access = PL1_RW, 2626 .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, }, 2627 { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH, 2628 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0, 2629 .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0, 2630 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), 2631 offsetof(CPUARMState, cp15.ttbr0_ns) } }, 2632 { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH, 2633 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1, 2634 .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0, 2635 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), 2636 offsetof(CPUARMState, cp15.ttbr1_ns) } }, 2637 { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64, 2638 .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, 2639 .access = PL1_RW, .writefn = vmsa_tcr_el1_write, 2640 .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write, 2641 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) }, 2642 { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, 2643 .access = PL1_RW, .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write, 2644 .raw_writefn = vmsa_ttbcr_raw_write, 2645 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]), 2646 offsetoflow32(CPUARMState, cp15.tcr_el[1])} }, 2647 REGINFO_SENTINEL 2648 }; 2649 2650 static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri, 2651 uint64_t value) 2652 { 2653 env->cp15.c15_ticonfig = value & 0xe7; 2654 /* The OS_TYPE bit in this register changes the reported CPUID! */ 2655 env->cp15.c0_cpuid = (value & (1 << 5)) ? 2656 ARM_CPUID_TI915T : ARM_CPUID_TI925T; 2657 } 2658 2659 static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri, 2660 uint64_t value) 2661 { 2662 env->cp15.c15_threadid = value & 0xffff; 2663 } 2664 2665 static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri, 2666 uint64_t value) 2667 { 2668 /* Wait-for-interrupt (deprecated) */ 2669 cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT); 2670 } 2671 2672 static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri, 2673 uint64_t value) 2674 { 2675 /* On OMAP there are registers indicating the max/min index of dcache lines 2676 * containing a dirty line; cache flush operations have to reset these. 2677 */ 2678 env->cp15.c15_i_max = 0x000; 2679 env->cp15.c15_i_min = 0xff0; 2680 } 2681 2682 static const ARMCPRegInfo omap_cp_reginfo[] = { 2683 { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY, 2684 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE, 2685 .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]), 2686 .resetvalue = 0, }, 2687 { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, 2688 .access = PL1_RW, .type = ARM_CP_NOP }, 2689 { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, 2690 .access = PL1_RW, 2691 .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0, 2692 .writefn = omap_ticonfig_write }, 2693 { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0, 2694 .access = PL1_RW, 2695 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, }, 2696 { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0, 2697 .access = PL1_RW, .resetvalue = 0xff0, 2698 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) }, 2699 { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0, 2700 .access = PL1_RW, 2701 .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0, 2702 .writefn = omap_threadid_write }, 2703 { .name = "TI925T_STATUS", .cp = 15, .crn = 15, 2704 .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW, 2705 .type = ARM_CP_NO_RAW, 2706 .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, }, 2707 /* TODO: Peripheral port remap register: 2708 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller 2709 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff), 2710 * when MMU is off. 2711 */ 2712 { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, 2713 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, 2714 .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW, 2715 .writefn = omap_cachemaint_write }, 2716 { .name = "C9", .cp = 15, .crn = 9, 2717 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, 2718 .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 }, 2719 REGINFO_SENTINEL 2720 }; 2721 2722 static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri, 2723 uint64_t value) 2724 { 2725 env->cp15.c15_cpar = value & 0x3fff; 2726 } 2727 2728 static const ARMCPRegInfo xscale_cp_reginfo[] = { 2729 { .name = "XSCALE_CPAR", 2730 .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW, 2731 .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0, 2732 .writefn = xscale_cpar_write, }, 2733 { .name = "XSCALE_AUXCR", 2734 .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW, 2735 .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr), 2736 .resetvalue = 0, }, 2737 /* XScale specific cache-lockdown: since we have no cache we NOP these 2738 * and hope the guest does not really rely on cache behaviour. 2739 */ 2740 { .name = "XSCALE_LOCK_ICACHE_LINE", 2741 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, 2742 .access = PL1_W, .type = ARM_CP_NOP }, 2743 { .name = "XSCALE_UNLOCK_ICACHE", 2744 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, 2745 .access = PL1_W, .type = ARM_CP_NOP }, 2746 { .name = "XSCALE_DCACHE_LOCK", 2747 .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0, 2748 .access = PL1_RW, .type = ARM_CP_NOP }, 2749 { .name = "XSCALE_UNLOCK_DCACHE", 2750 .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1, 2751 .access = PL1_W, .type = ARM_CP_NOP }, 2752 REGINFO_SENTINEL 2753 }; 2754 2755 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = { 2756 /* RAZ/WI the whole crn=15 space, when we don't have a more specific 2757 * implementation of this implementation-defined space. 2758 * Ideally this should eventually disappear in favour of actually 2759 * implementing the correct behaviour for all cores. 2760 */ 2761 { .name = "C15_IMPDEF", .cp = 15, .crn = 15, 2762 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, 2763 .access = PL1_RW, 2764 .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE, 2765 .resetvalue = 0 }, 2766 REGINFO_SENTINEL 2767 }; 2768 2769 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = { 2770 /* Cache status: RAZ because we have no cache so it's always clean */ 2771 { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6, 2772 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, 2773 .resetvalue = 0 }, 2774 REGINFO_SENTINEL 2775 }; 2776 2777 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = { 2778 /* We never have a a block transfer operation in progress */ 2779 { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4, 2780 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, 2781 .resetvalue = 0 }, 2782 /* The cache ops themselves: these all NOP for QEMU */ 2783 { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0, 2784 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, 2785 { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0, 2786 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, 2787 { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0, 2788 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, 2789 { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1, 2790 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, 2791 { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2, 2792 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, 2793 { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0, 2794 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, 2795 REGINFO_SENTINEL 2796 }; 2797 2798 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = { 2799 /* The cache test-and-clean instructions always return (1 << 30) 2800 * to indicate that there are no dirty cache lines. 2801 */ 2802 { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3, 2803 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, 2804 .resetvalue = (1 << 30) }, 2805 { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3, 2806 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, 2807 .resetvalue = (1 << 30) }, 2808 REGINFO_SENTINEL 2809 }; 2810 2811 static const ARMCPRegInfo strongarm_cp_reginfo[] = { 2812 /* Ignore ReadBuffer accesses */ 2813 { .name = "C9_READBUFFER", .cp = 15, .crn = 9, 2814 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, 2815 .access = PL1_RW, .resetvalue = 0, 2816 .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW }, 2817 REGINFO_SENTINEL 2818 }; 2819 2820 static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri) 2821 { 2822 ARMCPU *cpu = arm_env_get_cpu(env); 2823 unsigned int cur_el = arm_current_el(env); 2824 bool secure = arm_is_secure(env); 2825 2826 if (arm_feature(&cpu->env, ARM_FEATURE_EL2) && !secure && cur_el == 1) { 2827 return env->cp15.vpidr_el2; 2828 } 2829 return raw_read(env, ri); 2830 } 2831 2832 static uint64_t mpidr_read_val(CPUARMState *env) 2833 { 2834 ARMCPU *cpu = ARM_CPU(arm_env_get_cpu(env)); 2835 uint64_t mpidr = cpu->mp_affinity; 2836 2837 if (arm_feature(env, ARM_FEATURE_V7MP)) { 2838 mpidr |= (1U << 31); 2839 /* Cores which are uniprocessor (non-coherent) 2840 * but still implement the MP extensions set 2841 * bit 30. (For instance, Cortex-R5). 2842 */ 2843 if (cpu->mp_is_up) { 2844 mpidr |= (1u << 30); 2845 } 2846 } 2847 return mpidr; 2848 } 2849 2850 static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri) 2851 { 2852 unsigned int cur_el = arm_current_el(env); 2853 bool secure = arm_is_secure(env); 2854 2855 if (arm_feature(env, ARM_FEATURE_EL2) && !secure && cur_el == 1) { 2856 return env->cp15.vmpidr_el2; 2857 } 2858 return mpidr_read_val(env); 2859 } 2860 2861 static const ARMCPRegInfo mpidr_cp_reginfo[] = { 2862 { .name = "MPIDR", .state = ARM_CP_STATE_BOTH, 2863 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5, 2864 .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW }, 2865 REGINFO_SENTINEL 2866 }; 2867 2868 static const ARMCPRegInfo lpae_cp_reginfo[] = { 2869 /* NOP AMAIR0/1 */ 2870 { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH, 2871 .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0, 2872 .access = PL1_RW, .type = ARM_CP_CONST, 2873 .resetvalue = 0 }, 2874 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */ 2875 { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1, 2876 .access = PL1_RW, .type = ARM_CP_CONST, 2877 .resetvalue = 0 }, 2878 { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0, 2879 .access = PL1_RW, .type = ARM_CP_64BIT, .resetvalue = 0, 2880 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.par_s), 2881 offsetof(CPUARMState, cp15.par_ns)} }, 2882 { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0, 2883 .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, 2884 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), 2885 offsetof(CPUARMState, cp15.ttbr0_ns) }, 2886 .writefn = vmsa_ttbr_write, }, 2887 { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1, 2888 .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, 2889 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), 2890 offsetof(CPUARMState, cp15.ttbr1_ns) }, 2891 .writefn = vmsa_ttbr_write, }, 2892 REGINFO_SENTINEL 2893 }; 2894 2895 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri) 2896 { 2897 return vfp_get_fpcr(env); 2898 } 2899 2900 static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri, 2901 uint64_t value) 2902 { 2903 vfp_set_fpcr(env, value); 2904 } 2905 2906 static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri) 2907 { 2908 return vfp_get_fpsr(env); 2909 } 2910 2911 static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri, 2912 uint64_t value) 2913 { 2914 vfp_set_fpsr(env, value); 2915 } 2916 2917 static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri, 2918 bool isread) 2919 { 2920 if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) { 2921 return CP_ACCESS_TRAP; 2922 } 2923 return CP_ACCESS_OK; 2924 } 2925 2926 static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri, 2927 uint64_t value) 2928 { 2929 env->daif = value & PSTATE_DAIF; 2930 } 2931 2932 static CPAccessResult aa64_cacheop_access(CPUARMState *env, 2933 const ARMCPRegInfo *ri, 2934 bool isread) 2935 { 2936 /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless 2937 * SCTLR_EL1.UCI is set. 2938 */ 2939 if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCI)) { 2940 return CP_ACCESS_TRAP; 2941 } 2942 return CP_ACCESS_OK; 2943 } 2944 2945 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions 2946 * Page D4-1736 (DDI0487A.b) 2947 */ 2948 2949 static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri, 2950 uint64_t value) 2951 { 2952 CPUState *cs = ENV_GET_CPU(env); 2953 2954 if (arm_is_secure_below_el3(env)) { 2955 tlb_flush_by_mmuidx(cs, 2956 ARMMMUIdxBit_S1SE1 | 2957 ARMMMUIdxBit_S1SE0); 2958 } else { 2959 tlb_flush_by_mmuidx(cs, 2960 ARMMMUIdxBit_S12NSE1 | 2961 ARMMMUIdxBit_S12NSE0); 2962 } 2963 } 2964 2965 static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, 2966 uint64_t value) 2967 { 2968 CPUState *cs = ENV_GET_CPU(env); 2969 bool sec = arm_is_secure_below_el3(env); 2970 2971 if (sec) { 2972 tlb_flush_by_mmuidx_all_cpus_synced(cs, 2973 ARMMMUIdxBit_S1SE1 | 2974 ARMMMUIdxBit_S1SE0); 2975 } else { 2976 tlb_flush_by_mmuidx_all_cpus_synced(cs, 2977 ARMMMUIdxBit_S12NSE1 | 2978 ARMMMUIdxBit_S12NSE0); 2979 } 2980 } 2981 2982 static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, 2983 uint64_t value) 2984 { 2985 /* Note that the 'ALL' scope must invalidate both stage 1 and 2986 * stage 2 translations, whereas most other scopes only invalidate 2987 * stage 1 translations. 2988 */ 2989 ARMCPU *cpu = arm_env_get_cpu(env); 2990 CPUState *cs = CPU(cpu); 2991 2992 if (arm_is_secure_below_el3(env)) { 2993 tlb_flush_by_mmuidx(cs, 2994 ARMMMUIdxBit_S1SE1 | 2995 ARMMMUIdxBit_S1SE0); 2996 } else { 2997 if (arm_feature(env, ARM_FEATURE_EL2)) { 2998 tlb_flush_by_mmuidx(cs, 2999 ARMMMUIdxBit_S12NSE1 | 3000 ARMMMUIdxBit_S12NSE0 | 3001 ARMMMUIdxBit_S2NS); 3002 } else { 3003 tlb_flush_by_mmuidx(cs, 3004 ARMMMUIdxBit_S12NSE1 | 3005 ARMMMUIdxBit_S12NSE0); 3006 } 3007 } 3008 } 3009 3010 static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri, 3011 uint64_t value) 3012 { 3013 ARMCPU *cpu = arm_env_get_cpu(env); 3014 CPUState *cs = CPU(cpu); 3015 3016 tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2); 3017 } 3018 3019 static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri, 3020 uint64_t value) 3021 { 3022 ARMCPU *cpu = arm_env_get_cpu(env); 3023 CPUState *cs = CPU(cpu); 3024 3025 tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E3); 3026 } 3027 3028 static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, 3029 uint64_t value) 3030 { 3031 /* Note that the 'ALL' scope must invalidate both stage 1 and 3032 * stage 2 translations, whereas most other scopes only invalidate 3033 * stage 1 translations. 3034 */ 3035 CPUState *cs = ENV_GET_CPU(env); 3036 bool sec = arm_is_secure_below_el3(env); 3037 bool has_el2 = arm_feature(env, ARM_FEATURE_EL2); 3038 3039 if (sec) { 3040 tlb_flush_by_mmuidx_all_cpus_synced(cs, 3041 ARMMMUIdxBit_S1SE1 | 3042 ARMMMUIdxBit_S1SE0); 3043 } else if (has_el2) { 3044 tlb_flush_by_mmuidx_all_cpus_synced(cs, 3045 ARMMMUIdxBit_S12NSE1 | 3046 ARMMMUIdxBit_S12NSE0 | 3047 ARMMMUIdxBit_S2NS); 3048 } else { 3049 tlb_flush_by_mmuidx_all_cpus_synced(cs, 3050 ARMMMUIdxBit_S12NSE1 | 3051 ARMMMUIdxBit_S12NSE0); 3052 } 3053 } 3054 3055 static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri, 3056 uint64_t value) 3057 { 3058 CPUState *cs = ENV_GET_CPU(env); 3059 3060 tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2); 3061 } 3062 3063 static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri, 3064 uint64_t value) 3065 { 3066 CPUState *cs = ENV_GET_CPU(env); 3067 3068 tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E3); 3069 } 3070 3071 static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri, 3072 uint64_t value) 3073 { 3074 /* Invalidate by VA, EL1&0 (AArch64 version). 3075 * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1, 3076 * since we don't support flush-for-specific-ASID-only or 3077 * flush-last-level-only. 3078 */ 3079 ARMCPU *cpu = arm_env_get_cpu(env); 3080 CPUState *cs = CPU(cpu); 3081 uint64_t pageaddr = sextract64(value << 12, 0, 56); 3082 3083 if (arm_is_secure_below_el3(env)) { 3084 tlb_flush_page_by_mmuidx(cs, pageaddr, 3085 ARMMMUIdxBit_S1SE1 | 3086 ARMMMUIdxBit_S1SE0); 3087 } else { 3088 tlb_flush_page_by_mmuidx(cs, pageaddr, 3089 ARMMMUIdxBit_S12NSE1 | 3090 ARMMMUIdxBit_S12NSE0); 3091 } 3092 } 3093 3094 static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri, 3095 uint64_t value) 3096 { 3097 /* Invalidate by VA, EL2 3098 * Currently handles both VAE2 and VALE2, since we don't support 3099 * flush-last-level-only. 3100 */ 3101 ARMCPU *cpu = arm_env_get_cpu(env); 3102 CPUState *cs = CPU(cpu); 3103 uint64_t pageaddr = sextract64(value << 12, 0, 56); 3104 3105 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E2); 3106 } 3107 3108 static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri, 3109 uint64_t value) 3110 { 3111 /* Invalidate by VA, EL3 3112 * Currently handles both VAE3 and VALE3, since we don't support 3113 * flush-last-level-only. 3114 */ 3115 ARMCPU *cpu = arm_env_get_cpu(env); 3116 CPUState *cs = CPU(cpu); 3117 uint64_t pageaddr = sextract64(value << 12, 0, 56); 3118 3119 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E3); 3120 } 3121 3122 static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri, 3123 uint64_t value) 3124 { 3125 ARMCPU *cpu = arm_env_get_cpu(env); 3126 CPUState *cs = CPU(cpu); 3127 bool sec = arm_is_secure_below_el3(env); 3128 uint64_t pageaddr = sextract64(value << 12, 0, 56); 3129 3130 if (sec) { 3131 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, 3132 ARMMMUIdxBit_S1SE1 | 3133 ARMMMUIdxBit_S1SE0); 3134 } else { 3135 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, 3136 ARMMMUIdxBit_S12NSE1 | 3137 ARMMMUIdxBit_S12NSE0); 3138 } 3139 } 3140 3141 static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri, 3142 uint64_t value) 3143 { 3144 CPUState *cs = ENV_GET_CPU(env); 3145 uint64_t pageaddr = sextract64(value << 12, 0, 56); 3146 3147 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, 3148 ARMMMUIdxBit_S1E2); 3149 } 3150 3151 static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri, 3152 uint64_t value) 3153 { 3154 CPUState *cs = ENV_GET_CPU(env); 3155 uint64_t pageaddr = sextract64(value << 12, 0, 56); 3156 3157 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, 3158 ARMMMUIdxBit_S1E3); 3159 } 3160 3161 static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri, 3162 uint64_t value) 3163 { 3164 /* Invalidate by IPA. This has to invalidate any structures that 3165 * contain only stage 2 translation information, but does not need 3166 * to apply to structures that contain combined stage 1 and stage 2 3167 * translation information. 3168 * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero. 3169 */ 3170 ARMCPU *cpu = arm_env_get_cpu(env); 3171 CPUState *cs = CPU(cpu); 3172 uint64_t pageaddr; 3173 3174 if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { 3175 return; 3176 } 3177 3178 pageaddr = sextract64(value << 12, 0, 48); 3179 3180 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S2NS); 3181 } 3182 3183 static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri, 3184 uint64_t value) 3185 { 3186 CPUState *cs = ENV_GET_CPU(env); 3187 uint64_t pageaddr; 3188 3189 if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { 3190 return; 3191 } 3192 3193 pageaddr = sextract64(value << 12, 0, 48); 3194 3195 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, 3196 ARMMMUIdxBit_S2NS); 3197 } 3198 3199 static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri, 3200 bool isread) 3201 { 3202 /* We don't implement EL2, so the only control on DC ZVA is the 3203 * bit in the SCTLR which can prohibit access for EL0. 3204 */ 3205 if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_DZE)) { 3206 return CP_ACCESS_TRAP; 3207 } 3208 return CP_ACCESS_OK; 3209 } 3210 3211 static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri) 3212 { 3213 ARMCPU *cpu = arm_env_get_cpu(env); 3214 int dzp_bit = 1 << 4; 3215 3216 /* DZP indicates whether DC ZVA access is allowed */ 3217 if (aa64_zva_access(env, NULL, false) == CP_ACCESS_OK) { 3218 dzp_bit = 0; 3219 } 3220 return cpu->dcz_blocksize | dzp_bit; 3221 } 3222 3223 static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri, 3224 bool isread) 3225 { 3226 if (!(env->pstate & PSTATE_SP)) { 3227 /* Access to SP_EL0 is undefined if it's being used as 3228 * the stack pointer. 3229 */ 3230 return CP_ACCESS_TRAP_UNCATEGORIZED; 3231 } 3232 return CP_ACCESS_OK; 3233 } 3234 3235 static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri) 3236 { 3237 return env->pstate & PSTATE_SP; 3238 } 3239 3240 static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) 3241 { 3242 update_spsel(env, val); 3243 } 3244 3245 static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, 3246 uint64_t value) 3247 { 3248 ARMCPU *cpu = arm_env_get_cpu(env); 3249 3250 if (raw_read(env, ri) == value) { 3251 /* Skip the TLB flush if nothing actually changed; Linux likes 3252 * to do a lot of pointless SCTLR writes. 3253 */ 3254 return; 3255 } 3256 3257 if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) { 3258 /* M bit is RAZ/WI for PMSA with no MPU implemented */ 3259 value &= ~SCTLR_M; 3260 } 3261 3262 raw_write(env, ri, value); 3263 /* ??? Lots of these bits are not implemented. */ 3264 /* This may enable/disable the MMU, so do a TLB flush. */ 3265 tlb_flush(CPU(cpu)); 3266 } 3267 3268 static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri, 3269 bool isread) 3270 { 3271 if ((env->cp15.cptr_el[2] & CPTR_TFP) && arm_current_el(env) == 2) { 3272 return CP_ACCESS_TRAP_FP_EL2; 3273 } 3274 if (env->cp15.cptr_el[3] & CPTR_TFP) { 3275 return CP_ACCESS_TRAP_FP_EL3; 3276 } 3277 return CP_ACCESS_OK; 3278 } 3279 3280 static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri, 3281 uint64_t value) 3282 { 3283 env->cp15.mdcr_el3 = value & SDCR_VALID_MASK; 3284 } 3285 3286 static const ARMCPRegInfo v8_cp_reginfo[] = { 3287 /* Minimal set of EL0-visible registers. This will need to be expanded 3288 * significantly for system emulation of AArch64 CPUs. 3289 */ 3290 { .name = "NZCV", .state = ARM_CP_STATE_AA64, 3291 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2, 3292 .access = PL0_RW, .type = ARM_CP_NZCV }, 3293 { .name = "DAIF", .state = ARM_CP_STATE_AA64, 3294 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2, 3295 .type = ARM_CP_NO_RAW, 3296 .access = PL0_RW, .accessfn = aa64_daif_access, 3297 .fieldoffset = offsetof(CPUARMState, daif), 3298 .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore }, 3299 { .name = "FPCR", .state = ARM_CP_STATE_AA64, 3300 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4, 3301 .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write }, 3302 { .name = "FPSR", .state = ARM_CP_STATE_AA64, 3303 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4, 3304 .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write }, 3305 { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64, 3306 .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0, 3307 .access = PL0_R, .type = ARM_CP_NO_RAW, 3308 .readfn = aa64_dczid_read }, 3309 { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64, 3310 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1, 3311 .access = PL0_W, .type = ARM_CP_DC_ZVA, 3312 #ifndef CONFIG_USER_ONLY 3313 /* Avoid overhead of an access check that always passes in user-mode */ 3314 .accessfn = aa64_zva_access, 3315 #endif 3316 }, 3317 { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64, 3318 .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2, 3319 .access = PL1_R, .type = ARM_CP_CURRENTEL }, 3320 /* Cache ops: all NOPs since we don't emulate caches */ 3321 { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64, 3322 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, 3323 .access = PL1_W, .type = ARM_CP_NOP }, 3324 { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64, 3325 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, 3326 .access = PL1_W, .type = ARM_CP_NOP }, 3327 { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64, 3328 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1, 3329 .access = PL0_W, .type = ARM_CP_NOP, 3330 .accessfn = aa64_cacheop_access }, 3331 { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64, 3332 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, 3333 .access = PL1_W, .type = ARM_CP_NOP }, 3334 { .name = "DC_ISW", .state = ARM_CP_STATE_AA64, 3335 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, 3336 .access = PL1_W, .type = ARM_CP_NOP }, 3337 { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64, 3338 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1, 3339 .access = PL0_W, .type = ARM_CP_NOP, 3340 .accessfn = aa64_cacheop_access }, 3341 { .name = "DC_CSW", .state = ARM_CP_STATE_AA64, 3342 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, 3343 .access = PL1_W, .type = ARM_CP_NOP }, 3344 { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64, 3345 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1, 3346 .access = PL0_W, .type = ARM_CP_NOP, 3347 .accessfn = aa64_cacheop_access }, 3348 { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64, 3349 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1, 3350 .access = PL0_W, .type = ARM_CP_NOP, 3351 .accessfn = aa64_cacheop_access }, 3352 { .name = "DC_CISW", .state = ARM_CP_STATE_AA64, 3353 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, 3354 .access = PL1_W, .type = ARM_CP_NOP }, 3355 /* TLBI operations */ 3356 { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64, 3357 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, 3358 .access = PL1_W, .type = ARM_CP_NO_RAW, 3359 .writefn = tlbi_aa64_vmalle1is_write }, 3360 { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64, 3361 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, 3362 .access = PL1_W, .type = ARM_CP_NO_RAW, 3363 .writefn = tlbi_aa64_vae1is_write }, 3364 { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64, 3365 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, 3366 .access = PL1_W, .type = ARM_CP_NO_RAW, 3367 .writefn = tlbi_aa64_vmalle1is_write }, 3368 { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64, 3369 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, 3370 .access = PL1_W, .type = ARM_CP_NO_RAW, 3371 .writefn = tlbi_aa64_vae1is_write }, 3372 { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64, 3373 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, 3374 .access = PL1_W, .type = ARM_CP_NO_RAW, 3375 .writefn = tlbi_aa64_vae1is_write }, 3376 { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64, 3377 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, 3378 .access = PL1_W, .type = ARM_CP_NO_RAW, 3379 .writefn = tlbi_aa64_vae1is_write }, 3380 { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64, 3381 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, 3382 .access = PL1_W, .type = ARM_CP_NO_RAW, 3383 .writefn = tlbi_aa64_vmalle1_write }, 3384 { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64, 3385 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, 3386 .access = PL1_W, .type = ARM_CP_NO_RAW, 3387 .writefn = tlbi_aa64_vae1_write }, 3388 { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64, 3389 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, 3390 .access = PL1_W, .type = ARM_CP_NO_RAW, 3391 .writefn = tlbi_aa64_vmalle1_write }, 3392 { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64, 3393 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, 3394 .access = PL1_W, .type = ARM_CP_NO_RAW, 3395 .writefn = tlbi_aa64_vae1_write }, 3396 { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64, 3397 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, 3398 .access = PL1_W, .type = ARM_CP_NO_RAW, 3399 .writefn = tlbi_aa64_vae1_write }, 3400 { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64, 3401 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, 3402 .access = PL1_W, .type = ARM_CP_NO_RAW, 3403 .writefn = tlbi_aa64_vae1_write }, 3404 { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64, 3405 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1, 3406 .access = PL2_W, .type = ARM_CP_NO_RAW, 3407 .writefn = tlbi_aa64_ipas2e1is_write }, 3408 { .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64, 3409 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5, 3410 .access = PL2_W, .type = ARM_CP_NO_RAW, 3411 .writefn = tlbi_aa64_ipas2e1is_write }, 3412 { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64, 3413 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4, 3414 .access = PL2_W, .type = ARM_CP_NO_RAW, 3415 .writefn = tlbi_aa64_alle1is_write }, 3416 { .name = "TLBI_VMALLS12E1IS", .state = ARM_CP_STATE_AA64, 3417 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 6, 3418 .access = PL2_W, .type = ARM_CP_NO_RAW, 3419 .writefn = tlbi_aa64_alle1is_write }, 3420 { .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64, 3421 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1, 3422 .access = PL2_W, .type = ARM_CP_NO_RAW, 3423 .writefn = tlbi_aa64_ipas2e1_write }, 3424 { .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64, 3425 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5, 3426 .access = PL2_W, .type = ARM_CP_NO_RAW, 3427 .writefn = tlbi_aa64_ipas2e1_write }, 3428 { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64, 3429 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4, 3430 .access = PL2_W, .type = ARM_CP_NO_RAW, 3431 .writefn = tlbi_aa64_alle1_write }, 3432 { .name = "TLBI_VMALLS12E1", .state = ARM_CP_STATE_AA64, 3433 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6, 3434 .access = PL2_W, .type = ARM_CP_NO_RAW, 3435 .writefn = tlbi_aa64_alle1is_write }, 3436 #ifndef CONFIG_USER_ONLY 3437 /* 64 bit address translation operations */ 3438 { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64, 3439 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0, 3440 .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3441 { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64, 3442 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1, 3443 .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3444 { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64, 3445 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2, 3446 .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3447 { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64, 3448 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3, 3449 .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3450 { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64, 3451 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4, 3452 .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3453 { .name = "AT_S12E1W", .state = ARM_CP_STATE_AA64, 3454 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 5, 3455 .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3456 { .name = "AT_S12E0R", .state = ARM_CP_STATE_AA64, 3457 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 6, 3458 .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3459 { .name = "AT_S12E0W", .state = ARM_CP_STATE_AA64, 3460 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 7, 3461 .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3462 /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */ 3463 { .name = "AT_S1E3R", .state = ARM_CP_STATE_AA64, 3464 .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 0, 3465 .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3466 { .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64, 3467 .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1, 3468 .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3469 { .name = "PAR_EL1", .state = ARM_CP_STATE_AA64, 3470 .type = ARM_CP_ALIAS, 3471 .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0, 3472 .access = PL1_RW, .resetvalue = 0, 3473 .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]), 3474 .writefn = par_write }, 3475 #endif 3476 /* TLB invalidate last level of translation table walk */ 3477 { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, 3478 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write }, 3479 { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, 3480 .type = ARM_CP_NO_RAW, .access = PL1_W, 3481 .writefn = tlbimvaa_is_write }, 3482 { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, 3483 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, 3484 { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, 3485 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write }, 3486 { .name = "TLBIMVALH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5, 3487 .type = ARM_CP_NO_RAW, .access = PL2_W, 3488 .writefn = tlbimva_hyp_write }, 3489 { .name = "TLBIMVALHIS", 3490 .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5, 3491 .type = ARM_CP_NO_RAW, .access = PL2_W, 3492 .writefn = tlbimva_hyp_is_write }, 3493 { .name = "TLBIIPAS2", 3494 .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1, 3495 .type = ARM_CP_NO_RAW, .access = PL2_W, 3496 .writefn = tlbiipas2_write }, 3497 { .name = "TLBIIPAS2IS", 3498 .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1, 3499 .type = ARM_CP_NO_RAW, .access = PL2_W, 3500 .writefn = tlbiipas2_is_write }, 3501 { .name = "TLBIIPAS2L", 3502 .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5, 3503 .type = ARM_CP_NO_RAW, .access = PL2_W, 3504 .writefn = tlbiipas2_write }, 3505 { .name = "TLBIIPAS2LIS", 3506 .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5, 3507 .type = ARM_CP_NO_RAW, .access = PL2_W, 3508 .writefn = tlbiipas2_is_write }, 3509 /* 32 bit cache operations */ 3510 { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, 3511 .type = ARM_CP_NOP, .access = PL1_W }, 3512 { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6, 3513 .type = ARM_CP_NOP, .access = PL1_W }, 3514 { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, 3515 .type = ARM_CP_NOP, .access = PL1_W }, 3516 { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1, 3517 .type = ARM_CP_NOP, .access = PL1_W }, 3518 { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6, 3519 .type = ARM_CP_NOP, .access = PL1_W }, 3520 { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7, 3521 .type = ARM_CP_NOP, .access = PL1_W }, 3522 { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, 3523 .type = ARM_CP_NOP, .access = PL1_W }, 3524 { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, 3525 .type = ARM_CP_NOP, .access = PL1_W }, 3526 { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1, 3527 .type = ARM_CP_NOP, .access = PL1_W }, 3528 { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, 3529 .type = ARM_CP_NOP, .access = PL1_W }, 3530 { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1, 3531 .type = ARM_CP_NOP, .access = PL1_W }, 3532 { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1, 3533 .type = ARM_CP_NOP, .access = PL1_W }, 3534 { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, 3535 .type = ARM_CP_NOP, .access = PL1_W }, 3536 /* MMU Domain access control / MPU write buffer control */ 3537 { .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0, 3538 .access = PL1_RW, .resetvalue = 0, 3539 .writefn = dacr_write, .raw_writefn = raw_write, 3540 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s), 3541 offsetoflow32(CPUARMState, cp15.dacr_ns) } }, 3542 { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64, 3543 .type = ARM_CP_ALIAS, 3544 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1, 3545 .access = PL1_RW, 3546 .fieldoffset = offsetof(CPUARMState, elr_el[1]) }, 3547 { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64, 3548 .type = ARM_CP_ALIAS, 3549 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0, 3550 .access = PL1_RW, 3551 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_SVC]) }, 3552 /* We rely on the access checks not allowing the guest to write to the 3553 * state field when SPSel indicates that it's being used as the stack 3554 * pointer. 3555 */ 3556 { .name = "SP_EL0", .state = ARM_CP_STATE_AA64, 3557 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0, 3558 .access = PL1_RW, .accessfn = sp_el0_access, 3559 .type = ARM_CP_ALIAS, 3560 .fieldoffset = offsetof(CPUARMState, sp_el[0]) }, 3561 { .name = "SP_EL1", .state = ARM_CP_STATE_AA64, 3562 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0, 3563 .access = PL2_RW, .type = ARM_CP_ALIAS, 3564 .fieldoffset = offsetof(CPUARMState, sp_el[1]) }, 3565 { .name = "SPSel", .state = ARM_CP_STATE_AA64, 3566 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0, 3567 .type = ARM_CP_NO_RAW, 3568 .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write }, 3569 { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64, 3570 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0, 3571 .type = ARM_CP_ALIAS, 3572 .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]), 3573 .access = PL2_RW, .accessfn = fpexc32_access }, 3574 { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64, 3575 .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0, 3576 .access = PL2_RW, .resetvalue = 0, 3577 .writefn = dacr_write, .raw_writefn = raw_write, 3578 .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) }, 3579 { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64, 3580 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1, 3581 .access = PL2_RW, .resetvalue = 0, 3582 .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) }, 3583 { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64, 3584 .type = ARM_CP_ALIAS, 3585 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 0, 3586 .access = PL2_RW, 3587 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_IRQ]) }, 3588 { .name = "SPSR_ABT", .state = ARM_CP_STATE_AA64, 3589 .type = ARM_CP_ALIAS, 3590 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 1, 3591 .access = PL2_RW, 3592 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_ABT]) }, 3593 { .name = "SPSR_UND", .state = ARM_CP_STATE_AA64, 3594 .type = ARM_CP_ALIAS, 3595 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 2, 3596 .access = PL2_RW, 3597 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_UND]) }, 3598 { .name = "SPSR_FIQ", .state = ARM_CP_STATE_AA64, 3599 .type = ARM_CP_ALIAS, 3600 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 3, 3601 .access = PL2_RW, 3602 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) }, 3603 { .name = "MDCR_EL3", .state = ARM_CP_STATE_AA64, 3604 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1, 3605 .resetvalue = 0, 3606 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) }, 3607 { .name = "SDCR", .type = ARM_CP_ALIAS, 3608 .cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1, 3609 .access = PL1_RW, .accessfn = access_trap_aa32s_el1, 3610 .writefn = sdcr_write, 3611 .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) }, 3612 REGINFO_SENTINEL 3613 }; 3614 3615 /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */ 3616 static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { 3617 { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64, 3618 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, 3619 .access = PL2_RW, 3620 .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, 3621 { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64, 3622 .type = ARM_CP_NO_RAW, 3623 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, 3624 .access = PL2_RW, 3625 .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, 3626 { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH, 3627 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, 3628 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3629 { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH, 3630 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0, 3631 .access = PL2_RW, .type = ARM_CP_CONST, 3632 .resetvalue = 0 }, 3633 { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, 3634 .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, 3635 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3636 { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH, 3637 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0, 3638 .access = PL2_RW, .type = ARM_CP_CONST, 3639 .resetvalue = 0 }, 3640 { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, 3641 .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, 3642 .access = PL2_RW, .type = ARM_CP_CONST, 3643 .resetvalue = 0 }, 3644 { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH, 3645 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0, 3646 .access = PL2_RW, .type = ARM_CP_CONST, 3647 .resetvalue = 0 }, 3648 { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH, 3649 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1, 3650 .access = PL2_RW, .type = ARM_CP_CONST, 3651 .resetvalue = 0 }, 3652 { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, 3653 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, 3654 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3655 { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH, 3656 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, 3657 .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, 3658 .type = ARM_CP_CONST, .resetvalue = 0 }, 3659 { .name = "VTTBR", .state = ARM_CP_STATE_AA32, 3660 .cp = 15, .opc1 = 6, .crm = 2, 3661 .access = PL2_RW, .accessfn = access_el3_aa32ns, 3662 .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 3663 { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64, 3664 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0, 3665 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3666 { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH, 3667 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, 3668 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3669 { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH, 3670 .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2, 3671 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3672 { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64, 3673 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, 3674 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3675 { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2, 3676 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, 3677 .resetvalue = 0 }, 3678 { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH, 3679 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0, 3680 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3681 { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64, 3682 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3, 3683 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3684 { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14, 3685 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, 3686 .resetvalue = 0 }, 3687 { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64, 3688 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2, 3689 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3690 { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14, 3691 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, 3692 .resetvalue = 0 }, 3693 { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH, 3694 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0, 3695 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3696 { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, 3697 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, 3698 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3699 { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, 3700 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1, 3701 .access = PL2_RW, .accessfn = access_tda, 3702 .type = ARM_CP_CONST, .resetvalue = 0 }, 3703 { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH, 3704 .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, 3705 .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, 3706 .type = ARM_CP_CONST, .resetvalue = 0 }, 3707 { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH, 3708 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3, 3709 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3710 REGINFO_SENTINEL 3711 }; 3712 3713 static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) 3714 { 3715 ARMCPU *cpu = arm_env_get_cpu(env); 3716 uint64_t valid_mask = HCR_MASK; 3717 3718 if (arm_feature(env, ARM_FEATURE_EL3)) { 3719 valid_mask &= ~HCR_HCD; 3720 } else if (cpu->psci_conduit != QEMU_PSCI_CONDUIT_SMC) { 3721 /* Architecturally HCR.TSC is RES0 if EL3 is not implemented. 3722 * However, if we're using the SMC PSCI conduit then QEMU is 3723 * effectively acting like EL3 firmware and so the guest at 3724 * EL2 should retain the ability to prevent EL1 from being 3725 * able to make SMC calls into the ersatz firmware, so in 3726 * that case HCR.TSC should be read/write. 3727 */ 3728 valid_mask &= ~HCR_TSC; 3729 } 3730 3731 /* Clear RES0 bits. */ 3732 value &= valid_mask; 3733 3734 /* These bits change the MMU setup: 3735 * HCR_VM enables stage 2 translation 3736 * HCR_PTW forbids certain page-table setups 3737 * HCR_DC Disables stage1 and enables stage2 translation 3738 */ 3739 if ((raw_read(env, ri) ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) { 3740 tlb_flush(CPU(cpu)); 3741 } 3742 raw_write(env, ri, value); 3743 } 3744 3745 static const ARMCPRegInfo el2_cp_reginfo[] = { 3746 { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64, 3747 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, 3748 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), 3749 .writefn = hcr_write }, 3750 { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64, 3751 .type = ARM_CP_ALIAS, 3752 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1, 3753 .access = PL2_RW, 3754 .fieldoffset = offsetof(CPUARMState, elr_el[2]) }, 3755 { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64, 3756 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, 3757 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) }, 3758 { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64, 3759 .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, 3760 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) }, 3761 { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64, 3762 .type = ARM_CP_ALIAS, 3763 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0, 3764 .access = PL2_RW, 3765 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_HYP]) }, 3766 { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64, 3767 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, 3768 .access = PL2_RW, .writefn = vbar_write, 3769 .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]), 3770 .resetvalue = 0 }, 3771 { .name = "SP_EL2", .state = ARM_CP_STATE_AA64, 3772 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0, 3773 .access = PL3_RW, .type = ARM_CP_ALIAS, 3774 .fieldoffset = offsetof(CPUARMState, sp_el[2]) }, 3775 { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH, 3776 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, 3777 .access = PL2_RW, .accessfn = cptr_access, .resetvalue = 0, 3778 .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[2]) }, 3779 { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH, 3780 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0, 3781 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[2]), 3782 .resetvalue = 0 }, 3783 { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, 3784 .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, 3785 .access = PL2_RW, .type = ARM_CP_ALIAS, 3786 .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el[2]) }, 3787 { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH, 3788 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0, 3789 .access = PL2_RW, .type = ARM_CP_CONST, 3790 .resetvalue = 0 }, 3791 /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */ 3792 { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, 3793 .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, 3794 .access = PL2_RW, .type = ARM_CP_CONST, 3795 .resetvalue = 0 }, 3796 { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH, 3797 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0, 3798 .access = PL2_RW, .type = ARM_CP_CONST, 3799 .resetvalue = 0 }, 3800 { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH, 3801 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1, 3802 .access = PL2_RW, .type = ARM_CP_CONST, 3803 .resetvalue = 0 }, 3804 { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, 3805 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, 3806 .access = PL2_RW, 3807 /* no .writefn needed as this can't cause an ASID change; 3808 * no .raw_writefn or .resetfn needed as we never use mask/base_mask 3809 */ 3810 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) }, 3811 { .name = "VTCR", .state = ARM_CP_STATE_AA32, 3812 .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, 3813 .type = ARM_CP_ALIAS, 3814 .access = PL2_RW, .accessfn = access_el3_aa32ns, 3815 .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) }, 3816 { .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64, 3817 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, 3818 .access = PL2_RW, 3819 /* no .writefn needed as this can't cause an ASID change; 3820 * no .raw_writefn or .resetfn needed as we never use mask/base_mask 3821 */ 3822 .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) }, 3823 { .name = "VTTBR", .state = ARM_CP_STATE_AA32, 3824 .cp = 15, .opc1 = 6, .crm = 2, 3825 .type = ARM_CP_64BIT | ARM_CP_ALIAS, 3826 .access = PL2_RW, .accessfn = access_el3_aa32ns, 3827 .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2), 3828 .writefn = vttbr_write }, 3829 { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64, 3830 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0, 3831 .access = PL2_RW, .writefn = vttbr_write, 3832 .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2) }, 3833 { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH, 3834 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, 3835 .access = PL2_RW, .raw_writefn = raw_write, .writefn = sctlr_write, 3836 .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[2]) }, 3837 { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH, 3838 .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2, 3839 .access = PL2_RW, .resetvalue = 0, 3840 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) }, 3841 { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64, 3842 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, 3843 .access = PL2_RW, .resetvalue = 0, 3844 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) }, 3845 { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2, 3846 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, 3847 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) }, 3848 { .name = "TLBIALLNSNH", 3849 .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4, 3850 .type = ARM_CP_NO_RAW, .access = PL2_W, 3851 .writefn = tlbiall_nsnh_write }, 3852 { .name = "TLBIALLNSNHIS", 3853 .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4, 3854 .type = ARM_CP_NO_RAW, .access = PL2_W, 3855 .writefn = tlbiall_nsnh_is_write }, 3856 { .name = "TLBIALLH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0, 3857 .type = ARM_CP_NO_RAW, .access = PL2_W, 3858 .writefn = tlbiall_hyp_write }, 3859 { .name = "TLBIALLHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0, 3860 .type = ARM_CP_NO_RAW, .access = PL2_W, 3861 .writefn = tlbiall_hyp_is_write }, 3862 { .name = "TLBIMVAH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1, 3863 .type = ARM_CP_NO_RAW, .access = PL2_W, 3864 .writefn = tlbimva_hyp_write }, 3865 { .name = "TLBIMVAHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1, 3866 .type = ARM_CP_NO_RAW, .access = PL2_W, 3867 .writefn = tlbimva_hyp_is_write }, 3868 { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64, 3869 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0, 3870 .type = ARM_CP_NO_RAW, .access = PL2_W, 3871 .writefn = tlbi_aa64_alle2_write }, 3872 { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64, 3873 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1, 3874 .type = ARM_CP_NO_RAW, .access = PL2_W, 3875 .writefn = tlbi_aa64_vae2_write }, 3876 { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64, 3877 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5, 3878 .access = PL2_W, .type = ARM_CP_NO_RAW, 3879 .writefn = tlbi_aa64_vae2_write }, 3880 { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64, 3881 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0, 3882 .access = PL2_W, .type = ARM_CP_NO_RAW, 3883 .writefn = tlbi_aa64_alle2is_write }, 3884 { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64, 3885 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1, 3886 .type = ARM_CP_NO_RAW, .access = PL2_W, 3887 .writefn = tlbi_aa64_vae2is_write }, 3888 { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64, 3889 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5, 3890 .access = PL2_W, .type = ARM_CP_NO_RAW, 3891 .writefn = tlbi_aa64_vae2is_write }, 3892 #ifndef CONFIG_USER_ONLY 3893 /* Unlike the other EL2-related AT operations, these must 3894 * UNDEF from EL3 if EL2 is not implemented, which is why we 3895 * define them here rather than with the rest of the AT ops. 3896 */ 3897 { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64, 3898 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, 3899 .access = PL2_W, .accessfn = at_s1e2_access, 3900 .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3901 { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64, 3902 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, 3903 .access = PL2_W, .accessfn = at_s1e2_access, 3904 .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3905 /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE 3906 * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3 3907 * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose 3908 * to behave as if SCR.NS was 1. 3909 */ 3910 { .name = "ATS1HR", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, 3911 .access = PL2_W, 3912 .writefn = ats1h_write, .type = ARM_CP_NO_RAW }, 3913 { .name = "ATS1HW", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, 3914 .access = PL2_W, 3915 .writefn = ats1h_write, .type = ARM_CP_NO_RAW }, 3916 { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH, 3917 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0, 3918 /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the 3919 * reset values as IMPDEF. We choose to reset to 3 to comply with 3920 * both ARMv7 and ARMv8. 3921 */ 3922 .access = PL2_RW, .resetvalue = 3, 3923 .fieldoffset = offsetof(CPUARMState, cp15.cnthctl_el2) }, 3924 { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64, 3925 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3, 3926 .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0, 3927 .writefn = gt_cntvoff_write, 3928 .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) }, 3929 { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14, 3930 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS | ARM_CP_IO, 3931 .writefn = gt_cntvoff_write, 3932 .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) }, 3933 { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64, 3934 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2, 3935 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval), 3936 .type = ARM_CP_IO, .access = PL2_RW, 3937 .writefn = gt_hyp_cval_write, .raw_writefn = raw_write }, 3938 { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14, 3939 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval), 3940 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_IO, 3941 .writefn = gt_hyp_cval_write, .raw_writefn = raw_write }, 3942 { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH, 3943 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0, 3944 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW, 3945 .resetfn = gt_hyp_timer_reset, 3946 .readfn = gt_hyp_tval_read, .writefn = gt_hyp_tval_write }, 3947 { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, 3948 .type = ARM_CP_IO, 3949 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, 3950 .access = PL2_RW, 3951 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].ctl), 3952 .resetvalue = 0, 3953 .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write }, 3954 #endif 3955 /* The only field of MDCR_EL2 that has a defined architectural reset value 3956 * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but we 3957 * don't impelment any PMU event counters, so using zero as a reset 3958 * value for MDCR_EL2 is okay 3959 */ 3960 { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, 3961 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1, 3962 .access = PL2_RW, .resetvalue = 0, 3963 .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), }, 3964 { .name = "HPFAR", .state = ARM_CP_STATE_AA32, 3965 .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, 3966 .access = PL2_RW, .accessfn = access_el3_aa32ns, 3967 .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, 3968 { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64, 3969 .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, 3970 .access = PL2_RW, 3971 .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, 3972 { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH, 3973 .cp = 15, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3, 3974 .access = PL2_RW, 3975 .fieldoffset = offsetof(CPUARMState, cp15.hstr_el2) }, 3976 REGINFO_SENTINEL 3977 }; 3978 3979 static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri, 3980 bool isread) 3981 { 3982 /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2. 3983 * At Secure EL1 it traps to EL3. 3984 */ 3985 if (arm_current_el(env) == 3) { 3986 return CP_ACCESS_OK; 3987 } 3988 if (arm_is_secure_below_el3(env)) { 3989 return CP_ACCESS_TRAP_EL3; 3990 } 3991 /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */ 3992 if (isread) { 3993 return CP_ACCESS_OK; 3994 } 3995 return CP_ACCESS_TRAP_UNCATEGORIZED; 3996 } 3997 3998 static const ARMCPRegInfo el3_cp_reginfo[] = { 3999 { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64, 4000 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0, 4001 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), 4002 .resetvalue = 0, .writefn = scr_write }, 4003 { .name = "SCR", .type = ARM_CP_ALIAS, 4004 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0, 4005 .access = PL1_RW, .accessfn = access_trap_aa32s_el1, 4006 .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3), 4007 .writefn = scr_write }, 4008 { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64, 4009 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1, 4010 .access = PL3_RW, .resetvalue = 0, 4011 .fieldoffset = offsetof(CPUARMState, cp15.sder) }, 4012 { .name = "SDER", 4013 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1, 4014 .access = PL3_RW, .resetvalue = 0, 4015 .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) }, 4016 { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, 4017 .access = PL1_RW, .accessfn = access_trap_aa32s_el1, 4018 .writefn = vbar_write, .resetvalue = 0, 4019 .fieldoffset = offsetof(CPUARMState, cp15.mvbar) }, 4020 { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64, 4021 .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0, 4022 .access = PL3_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0, 4023 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) }, 4024 { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64, 4025 .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2, 4026 .access = PL3_RW, 4027 /* no .writefn needed as this can't cause an ASID change; 4028 * we must provide a .raw_writefn and .resetfn because we handle 4029 * reset and migration for the AArch32 TTBCR(S), which might be 4030 * using mask and base_mask. 4031 */ 4032 .resetfn = vmsa_ttbcr_reset, .raw_writefn = vmsa_ttbcr_raw_write, 4033 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) }, 4034 { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64, 4035 .type = ARM_CP_ALIAS, 4036 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1, 4037 .access = PL3_RW, 4038 .fieldoffset = offsetof(CPUARMState, elr_el[3]) }, 4039 { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64, 4040 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0, 4041 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) }, 4042 { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64, 4043 .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0, 4044 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) }, 4045 { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64, 4046 .type = ARM_CP_ALIAS, 4047 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0, 4048 .access = PL3_RW, 4049 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_MON]) }, 4050 { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64, 4051 .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0, 4052 .access = PL3_RW, .writefn = vbar_write, 4053 .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]), 4054 .resetvalue = 0 }, 4055 { .name = "CPTR_EL3", .state = ARM_CP_STATE_AA64, 4056 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 2, 4057 .access = PL3_RW, .accessfn = cptr_access, .resetvalue = 0, 4058 .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[3]) }, 4059 { .name = "TPIDR_EL3", .state = ARM_CP_STATE_AA64, 4060 .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 2, 4061 .access = PL3_RW, .resetvalue = 0, 4062 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[3]) }, 4063 { .name = "AMAIR_EL3", .state = ARM_CP_STATE_AA64, 4064 .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0, 4065 .access = PL3_RW, .type = ARM_CP_CONST, 4066 .resetvalue = 0 }, 4067 { .name = "AFSR0_EL3", .state = ARM_CP_STATE_BOTH, 4068 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 0, 4069 .access = PL3_RW, .type = ARM_CP_CONST, 4070 .resetvalue = 0 }, 4071 { .name = "AFSR1_EL3", .state = ARM_CP_STATE_BOTH, 4072 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 1, 4073 .access = PL3_RW, .type = ARM_CP_CONST, 4074 .resetvalue = 0 }, 4075 { .name = "TLBI_ALLE3IS", .state = ARM_CP_STATE_AA64, 4076 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 0, 4077 .access = PL3_W, .type = ARM_CP_NO_RAW, 4078 .writefn = tlbi_aa64_alle3is_write }, 4079 { .name = "TLBI_VAE3IS", .state = ARM_CP_STATE_AA64, 4080 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 1, 4081 .access = PL3_W, .type = ARM_CP_NO_RAW, 4082 .writefn = tlbi_aa64_vae3is_write }, 4083 { .name = "TLBI_VALE3IS", .state = ARM_CP_STATE_AA64, 4084 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 5, 4085 .access = PL3_W, .type = ARM_CP_NO_RAW, 4086 .writefn = tlbi_aa64_vae3is_write }, 4087 { .name = "TLBI_ALLE3", .state = ARM_CP_STATE_AA64, 4088 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 0, 4089 .access = PL3_W, .type = ARM_CP_NO_RAW, 4090 .writefn = tlbi_aa64_alle3_write }, 4091 { .name = "TLBI_VAE3", .state = ARM_CP_STATE_AA64, 4092 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 1, 4093 .access = PL3_W, .type = ARM_CP_NO_RAW, 4094 .writefn = tlbi_aa64_vae3_write }, 4095 { .name = "TLBI_VALE3", .state = ARM_CP_STATE_AA64, 4096 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5, 4097 .access = PL3_W, .type = ARM_CP_NO_RAW, 4098 .writefn = tlbi_aa64_vae3_write }, 4099 REGINFO_SENTINEL 4100 }; 4101 4102 static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri, 4103 bool isread) 4104 { 4105 /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64, 4106 * but the AArch32 CTR has its own reginfo struct) 4107 */ 4108 if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCT)) { 4109 return CP_ACCESS_TRAP; 4110 } 4111 return CP_ACCESS_OK; 4112 } 4113 4114 static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri, 4115 uint64_t value) 4116 { 4117 /* Writes to OSLAR_EL1 may update the OS lock status, which can be 4118 * read via a bit in OSLSR_EL1. 4119 */ 4120 int oslock; 4121 4122 if (ri->state == ARM_CP_STATE_AA32) { 4123 oslock = (value == 0xC5ACCE55); 4124 } else { 4125 oslock = value & 1; 4126 } 4127 4128 env->cp15.oslsr_el1 = deposit32(env->cp15.oslsr_el1, 1, 1, oslock); 4129 } 4130 4131 static const ARMCPRegInfo debug_cp_reginfo[] = { 4132 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped 4133 * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1; 4134 * unlike DBGDRAR it is never accessible from EL0. 4135 * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64 4136 * accessor. 4137 */ 4138 { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0, 4139 .access = PL0_R, .accessfn = access_tdra, 4140 .type = ARM_CP_CONST, .resetvalue = 0 }, 4141 { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64, 4142 .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, 4143 .access = PL1_R, .accessfn = access_tdra, 4144 .type = ARM_CP_CONST, .resetvalue = 0 }, 4145 { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, 4146 .access = PL0_R, .accessfn = access_tdra, 4147 .type = ARM_CP_CONST, .resetvalue = 0 }, 4148 /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */ 4149 { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH, 4150 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, 4151 .access = PL1_RW, .accessfn = access_tda, 4152 .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), 4153 .resetvalue = 0 }, 4154 /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1. 4155 * We don't implement the configurable EL0 access. 4156 */ 4157 { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH, 4158 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, 4159 .type = ARM_CP_ALIAS, 4160 .access = PL1_R, .accessfn = access_tda, 4161 .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), }, 4162 { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH, 4163 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4, 4164 .access = PL1_W, .type = ARM_CP_NO_RAW, 4165 .accessfn = access_tdosa, 4166 .writefn = oslar_write }, 4167 { .name = "OSLSR_EL1", .state = ARM_CP_STATE_BOTH, 4168 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 4, 4169 .access = PL1_R, .resetvalue = 10, 4170 .accessfn = access_tdosa, 4171 .fieldoffset = offsetof(CPUARMState, cp15.oslsr_el1) }, 4172 /* Dummy OSDLR_EL1: 32-bit Linux will read this */ 4173 { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH, 4174 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4, 4175 .access = PL1_RW, .accessfn = access_tdosa, 4176 .type = ARM_CP_NOP }, 4177 /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't 4178 * implement vector catch debug events yet. 4179 */ 4180 { .name = "DBGVCR", 4181 .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, 4182 .access = PL1_RW, .accessfn = access_tda, 4183 .type = ARM_CP_NOP }, 4184 /* Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor 4185 * to save and restore a 32-bit guest's DBGVCR) 4186 */ 4187 { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64, 4188 .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0, 4189 .access = PL2_RW, .accessfn = access_tda, 4190 .type = ARM_CP_NOP }, 4191 /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications 4192 * Channel but Linux may try to access this register. The 32-bit 4193 * alias is DBGDCCINT. 4194 */ 4195 { .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH, 4196 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, 4197 .access = PL1_RW, .accessfn = access_tda, 4198 .type = ARM_CP_NOP }, 4199 REGINFO_SENTINEL 4200 }; 4201 4202 static const ARMCPRegInfo debug_lpae_cp_reginfo[] = { 4203 /* 64 bit access versions of the (dummy) debug registers */ 4204 { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0, 4205 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, 4206 { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0, 4207 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, 4208 REGINFO_SENTINEL 4209 }; 4210 4211 void hw_watchpoint_update(ARMCPU *cpu, int n) 4212 { 4213 CPUARMState *env = &cpu->env; 4214 vaddr len = 0; 4215 vaddr wvr = env->cp15.dbgwvr[n]; 4216 uint64_t wcr = env->cp15.dbgwcr[n]; 4217 int mask; 4218 int flags = BP_CPU | BP_STOP_BEFORE_ACCESS; 4219 4220 if (env->cpu_watchpoint[n]) { 4221 cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]); 4222 env->cpu_watchpoint[n] = NULL; 4223 } 4224 4225 if (!extract64(wcr, 0, 1)) { 4226 /* E bit clear : watchpoint disabled */ 4227 return; 4228 } 4229 4230 switch (extract64(wcr, 3, 2)) { 4231 case 0: 4232 /* LSC 00 is reserved and must behave as if the wp is disabled */ 4233 return; 4234 case 1: 4235 flags |= BP_MEM_READ; 4236 break; 4237 case 2: 4238 flags |= BP_MEM_WRITE; 4239 break; 4240 case 3: 4241 flags |= BP_MEM_ACCESS; 4242 break; 4243 } 4244 4245 /* Attempts to use both MASK and BAS fields simultaneously are 4246 * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case, 4247 * thus generating a watchpoint for every byte in the masked region. 4248 */ 4249 mask = extract64(wcr, 24, 4); 4250 if (mask == 1 || mask == 2) { 4251 /* Reserved values of MASK; we must act as if the mask value was 4252 * some non-reserved value, or as if the watchpoint were disabled. 4253 * We choose the latter. 4254 */ 4255 return; 4256 } else if (mask) { 4257 /* Watchpoint covers an aligned area up to 2GB in size */ 4258 len = 1ULL << mask; 4259 /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE 4260 * whether the watchpoint fires when the unmasked bits match; we opt 4261 * to generate the exceptions. 4262 */ 4263 wvr &= ~(len - 1); 4264 } else { 4265 /* Watchpoint covers bytes defined by the byte address select bits */ 4266 int bas = extract64(wcr, 5, 8); 4267 int basstart; 4268 4269 if (bas == 0) { 4270 /* This must act as if the watchpoint is disabled */ 4271 return; 4272 } 4273 4274 if (extract64(wvr, 2, 1)) { 4275 /* Deprecated case of an only 4-aligned address. BAS[7:4] are 4276 * ignored, and BAS[3:0] define which bytes to watch. 4277 */ 4278 bas &= 0xf; 4279 } 4280 /* The BAS bits are supposed to be programmed to indicate a contiguous 4281 * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether 4282 * we fire for each byte in the word/doubleword addressed by the WVR. 4283 * We choose to ignore any non-zero bits after the first range of 1s. 4284 */ 4285 basstart = ctz32(bas); 4286 len = cto32(bas >> basstart); 4287 wvr += basstart; 4288 } 4289 4290 cpu_watchpoint_insert(CPU(cpu), wvr, len, flags, 4291 &env->cpu_watchpoint[n]); 4292 } 4293 4294 void hw_watchpoint_update_all(ARMCPU *cpu) 4295 { 4296 int i; 4297 CPUARMState *env = &cpu->env; 4298 4299 /* Completely clear out existing QEMU watchpoints and our array, to 4300 * avoid possible stale entries following migration load. 4301 */ 4302 cpu_watchpoint_remove_all(CPU(cpu), BP_CPU); 4303 memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint)); 4304 4305 for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) { 4306 hw_watchpoint_update(cpu, i); 4307 } 4308 } 4309 4310 static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri, 4311 uint64_t value) 4312 { 4313 ARMCPU *cpu = arm_env_get_cpu(env); 4314 int i = ri->crm; 4315 4316 /* Bits [63:49] are hardwired to the value of bit [48]; that is, the 4317 * register reads and behaves as if values written are sign extended. 4318 * Bits [1:0] are RES0. 4319 */ 4320 value = sextract64(value, 0, 49) & ~3ULL; 4321 4322 raw_write(env, ri, value); 4323 hw_watchpoint_update(cpu, i); 4324 } 4325 4326 static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri, 4327 uint64_t value) 4328 { 4329 ARMCPU *cpu = arm_env_get_cpu(env); 4330 int i = ri->crm; 4331 4332 raw_write(env, ri, value); 4333 hw_watchpoint_update(cpu, i); 4334 } 4335 4336 void hw_breakpoint_update(ARMCPU *cpu, int n) 4337 { 4338 CPUARMState *env = &cpu->env; 4339 uint64_t bvr = env->cp15.dbgbvr[n]; 4340 uint64_t bcr = env->cp15.dbgbcr[n]; 4341 vaddr addr; 4342 int bt; 4343 int flags = BP_CPU; 4344 4345 if (env->cpu_breakpoint[n]) { 4346 cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]); 4347 env->cpu_breakpoint[n] = NULL; 4348 } 4349 4350 if (!extract64(bcr, 0, 1)) { 4351 /* E bit clear : watchpoint disabled */ 4352 return; 4353 } 4354 4355 bt = extract64(bcr, 20, 4); 4356 4357 switch (bt) { 4358 case 4: /* unlinked address mismatch (reserved if AArch64) */ 4359 case 5: /* linked address mismatch (reserved if AArch64) */ 4360 qemu_log_mask(LOG_UNIMP, 4361 "arm: address mismatch breakpoint types not implemented"); 4362 return; 4363 case 0: /* unlinked address match */ 4364 case 1: /* linked address match */ 4365 { 4366 /* Bits [63:49] are hardwired to the value of bit [48]; that is, 4367 * we behave as if the register was sign extended. Bits [1:0] are 4368 * RES0. The BAS field is used to allow setting breakpoints on 16 4369 * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether 4370 * a bp will fire if the addresses covered by the bp and the addresses 4371 * covered by the insn overlap but the insn doesn't start at the 4372 * start of the bp address range. We choose to require the insn and 4373 * the bp to have the same address. The constraints on writing to 4374 * BAS enforced in dbgbcr_write mean we have only four cases: 4375 * 0b0000 => no breakpoint 4376 * 0b0011 => breakpoint on addr 4377 * 0b1100 => breakpoint on addr + 2 4378 * 0b1111 => breakpoint on addr 4379 * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c). 4380 */ 4381 int bas = extract64(bcr, 5, 4); 4382 addr = sextract64(bvr, 0, 49) & ~3ULL; 4383 if (bas == 0) { 4384 return; 4385 } 4386 if (bas == 0xc) { 4387 addr += 2; 4388 } 4389 break; 4390 } 4391 case 2: /* unlinked context ID match */ 4392 case 8: /* unlinked VMID match (reserved if no EL2) */ 4393 case 10: /* unlinked context ID and VMID match (reserved if no EL2) */ 4394 qemu_log_mask(LOG_UNIMP, 4395 "arm: unlinked context breakpoint types not implemented"); 4396 return; 4397 case 9: /* linked VMID match (reserved if no EL2) */ 4398 case 11: /* linked context ID and VMID match (reserved if no EL2) */ 4399 case 3: /* linked context ID match */ 4400 default: 4401 /* We must generate no events for Linked context matches (unless 4402 * they are linked to by some other bp/wp, which is handled in 4403 * updates for the linking bp/wp). We choose to also generate no events 4404 * for reserved values. 4405 */ 4406 return; 4407 } 4408 4409 cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]); 4410 } 4411 4412 void hw_breakpoint_update_all(ARMCPU *cpu) 4413 { 4414 int i; 4415 CPUARMState *env = &cpu->env; 4416 4417 /* Completely clear out existing QEMU breakpoints and our array, to 4418 * avoid possible stale entries following migration load. 4419 */ 4420 cpu_breakpoint_remove_all(CPU(cpu), BP_CPU); 4421 memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint)); 4422 4423 for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) { 4424 hw_breakpoint_update(cpu, i); 4425 } 4426 } 4427 4428 static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri, 4429 uint64_t value) 4430 { 4431 ARMCPU *cpu = arm_env_get_cpu(env); 4432 int i = ri->crm; 4433 4434 raw_write(env, ri, value); 4435 hw_breakpoint_update(cpu, i); 4436 } 4437 4438 static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, 4439 uint64_t value) 4440 { 4441 ARMCPU *cpu = arm_env_get_cpu(env); 4442 int i = ri->crm; 4443 4444 /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only 4445 * copy of BAS[0]. 4446 */ 4447 value = deposit64(value, 6, 1, extract64(value, 5, 1)); 4448 value = deposit64(value, 8, 1, extract64(value, 7, 1)); 4449 4450 raw_write(env, ri, value); 4451 hw_breakpoint_update(cpu, i); 4452 } 4453 4454 static void define_debug_regs(ARMCPU *cpu) 4455 { 4456 /* Define v7 and v8 architectural debug registers. 4457 * These are just dummy implementations for now. 4458 */ 4459 int i; 4460 int wrps, brps, ctx_cmps; 4461 ARMCPRegInfo dbgdidr = { 4462 .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, 4463 .access = PL0_R, .accessfn = access_tda, 4464 .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr, 4465 }; 4466 4467 /* Note that all these register fields hold "number of Xs minus 1". */ 4468 brps = extract32(cpu->dbgdidr, 24, 4); 4469 wrps = extract32(cpu->dbgdidr, 28, 4); 4470 ctx_cmps = extract32(cpu->dbgdidr, 20, 4); 4471 4472 assert(ctx_cmps <= brps); 4473 4474 /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties 4475 * of the debug registers such as number of breakpoints; 4476 * check that if they both exist then they agree. 4477 */ 4478 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 4479 assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps); 4480 assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps); 4481 assert(extract32(cpu->id_aa64dfr0, 28, 4) == ctx_cmps); 4482 } 4483 4484 define_one_arm_cp_reg(cpu, &dbgdidr); 4485 define_arm_cp_regs(cpu, debug_cp_reginfo); 4486 4487 if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) { 4488 define_arm_cp_regs(cpu, debug_lpae_cp_reginfo); 4489 } 4490 4491 for (i = 0; i < brps + 1; i++) { 4492 ARMCPRegInfo dbgregs[] = { 4493 { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH, 4494 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4, 4495 .access = PL1_RW, .accessfn = access_tda, 4496 .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]), 4497 .writefn = dbgbvr_write, .raw_writefn = raw_write 4498 }, 4499 { .name = "DBGBCR", .state = ARM_CP_STATE_BOTH, 4500 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5, 4501 .access = PL1_RW, .accessfn = access_tda, 4502 .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]), 4503 .writefn = dbgbcr_write, .raw_writefn = raw_write 4504 }, 4505 REGINFO_SENTINEL 4506 }; 4507 define_arm_cp_regs(cpu, dbgregs); 4508 } 4509 4510 for (i = 0; i < wrps + 1; i++) { 4511 ARMCPRegInfo dbgregs[] = { 4512 { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH, 4513 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6, 4514 .access = PL1_RW, .accessfn = access_tda, 4515 .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]), 4516 .writefn = dbgwvr_write, .raw_writefn = raw_write 4517 }, 4518 { .name = "DBGWCR", .state = ARM_CP_STATE_BOTH, 4519 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7, 4520 .access = PL1_RW, .accessfn = access_tda, 4521 .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]), 4522 .writefn = dbgwcr_write, .raw_writefn = raw_write 4523 }, 4524 REGINFO_SENTINEL 4525 }; 4526 define_arm_cp_regs(cpu, dbgregs); 4527 } 4528 } 4529 4530 void register_cp_regs_for_features(ARMCPU *cpu) 4531 { 4532 /* Register all the coprocessor registers based on feature bits */ 4533 CPUARMState *env = &cpu->env; 4534 if (arm_feature(env, ARM_FEATURE_M)) { 4535 /* M profile has no coprocessor registers */ 4536 return; 4537 } 4538 4539 define_arm_cp_regs(cpu, cp_reginfo); 4540 if (!arm_feature(env, ARM_FEATURE_V8)) { 4541 /* Must go early as it is full of wildcards that may be 4542 * overridden by later definitions. 4543 */ 4544 define_arm_cp_regs(cpu, not_v8_cp_reginfo); 4545 } 4546 4547 if (arm_feature(env, ARM_FEATURE_V6)) { 4548 /* The ID registers all have impdef reset values */ 4549 ARMCPRegInfo v6_idregs[] = { 4550 { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH, 4551 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, 4552 .access = PL1_R, .type = ARM_CP_CONST, 4553 .resetvalue = cpu->id_pfr0 }, 4554 { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH, 4555 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1, 4556 .access = PL1_R, .type = ARM_CP_CONST, 4557 .resetvalue = cpu->id_pfr1 }, 4558 { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH, 4559 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2, 4560 .access = PL1_R, .type = ARM_CP_CONST, 4561 .resetvalue = cpu->id_dfr0 }, 4562 { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH, 4563 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3, 4564 .access = PL1_R, .type = ARM_CP_CONST, 4565 .resetvalue = cpu->id_afr0 }, 4566 { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH, 4567 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4, 4568 .access = PL1_R, .type = ARM_CP_CONST, 4569 .resetvalue = cpu->id_mmfr0 }, 4570 { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH, 4571 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5, 4572 .access = PL1_R, .type = ARM_CP_CONST, 4573 .resetvalue = cpu->id_mmfr1 }, 4574 { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH, 4575 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6, 4576 .access = PL1_R, .type = ARM_CP_CONST, 4577 .resetvalue = cpu->id_mmfr2 }, 4578 { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH, 4579 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7, 4580 .access = PL1_R, .type = ARM_CP_CONST, 4581 .resetvalue = cpu->id_mmfr3 }, 4582 { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH, 4583 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, 4584 .access = PL1_R, .type = ARM_CP_CONST, 4585 .resetvalue = cpu->id_isar0 }, 4586 { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH, 4587 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1, 4588 .access = PL1_R, .type = ARM_CP_CONST, 4589 .resetvalue = cpu->id_isar1 }, 4590 { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH, 4591 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, 4592 .access = PL1_R, .type = ARM_CP_CONST, 4593 .resetvalue = cpu->id_isar2 }, 4594 { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH, 4595 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3, 4596 .access = PL1_R, .type = ARM_CP_CONST, 4597 .resetvalue = cpu->id_isar3 }, 4598 { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH, 4599 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4, 4600 .access = PL1_R, .type = ARM_CP_CONST, 4601 .resetvalue = cpu->id_isar4 }, 4602 { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH, 4603 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5, 4604 .access = PL1_R, .type = ARM_CP_CONST, 4605 .resetvalue = cpu->id_isar5 }, 4606 { .name = "ID_MMFR4", .state = ARM_CP_STATE_BOTH, 4607 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6, 4608 .access = PL1_R, .type = ARM_CP_CONST, 4609 .resetvalue = cpu->id_mmfr4 }, 4610 /* 7 is as yet unallocated and must RAZ */ 4611 { .name = "ID_ISAR7_RESERVED", .state = ARM_CP_STATE_BOTH, 4612 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7, 4613 .access = PL1_R, .type = ARM_CP_CONST, 4614 .resetvalue = 0 }, 4615 REGINFO_SENTINEL 4616 }; 4617 define_arm_cp_regs(cpu, v6_idregs); 4618 define_arm_cp_regs(cpu, v6_cp_reginfo); 4619 } else { 4620 define_arm_cp_regs(cpu, not_v6_cp_reginfo); 4621 } 4622 if (arm_feature(env, ARM_FEATURE_V6K)) { 4623 define_arm_cp_regs(cpu, v6k_cp_reginfo); 4624 } 4625 if (arm_feature(env, ARM_FEATURE_V7MP) && 4626 !arm_feature(env, ARM_FEATURE_PMSA)) { 4627 define_arm_cp_regs(cpu, v7mp_cp_reginfo); 4628 } 4629 if (arm_feature(env, ARM_FEATURE_V7)) { 4630 /* v7 performance monitor control register: same implementor 4631 * field as main ID register, and we implement only the cycle 4632 * count register. 4633 */ 4634 #ifndef CONFIG_USER_ONLY 4635 ARMCPRegInfo pmcr = { 4636 .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0, 4637 .access = PL0_RW, 4638 .type = ARM_CP_IO | ARM_CP_ALIAS, 4639 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr), 4640 .accessfn = pmreg_access, .writefn = pmcr_write, 4641 .raw_writefn = raw_write, 4642 }; 4643 ARMCPRegInfo pmcr64 = { 4644 .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64, 4645 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0, 4646 .access = PL0_RW, .accessfn = pmreg_access, 4647 .type = ARM_CP_IO, 4648 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr), 4649 .resetvalue = cpu->midr & 0xff000000, 4650 .writefn = pmcr_write, .raw_writefn = raw_write, 4651 }; 4652 define_one_arm_cp_reg(cpu, &pmcr); 4653 define_one_arm_cp_reg(cpu, &pmcr64); 4654 #endif 4655 ARMCPRegInfo clidr = { 4656 .name = "CLIDR", .state = ARM_CP_STATE_BOTH, 4657 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1, 4658 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr 4659 }; 4660 define_one_arm_cp_reg(cpu, &clidr); 4661 define_arm_cp_regs(cpu, v7_cp_reginfo); 4662 define_debug_regs(cpu); 4663 } else { 4664 define_arm_cp_regs(cpu, not_v7_cp_reginfo); 4665 } 4666 if (arm_feature(env, ARM_FEATURE_V8)) { 4667 /* AArch64 ID registers, which all have impdef reset values. 4668 * Note that within the ID register ranges the unused slots 4669 * must all RAZ, not UNDEF; future architecture versions may 4670 * define new registers here. 4671 */ 4672 ARMCPRegInfo v8_idregs[] = { 4673 { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64, 4674 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0, 4675 .access = PL1_R, .type = ARM_CP_CONST, 4676 .resetvalue = cpu->id_aa64pfr0 }, 4677 { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64, 4678 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1, 4679 .access = PL1_R, .type = ARM_CP_CONST, 4680 .resetvalue = cpu->id_aa64pfr1}, 4681 { .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4682 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2, 4683 .access = PL1_R, .type = ARM_CP_CONST, 4684 .resetvalue = 0 }, 4685 { .name = "ID_AA64PFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4686 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3, 4687 .access = PL1_R, .type = ARM_CP_CONST, 4688 .resetvalue = 0 }, 4689 { .name = "ID_AA64PFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4690 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4, 4691 .access = PL1_R, .type = ARM_CP_CONST, 4692 .resetvalue = 0 }, 4693 { .name = "ID_AA64PFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4694 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5, 4695 .access = PL1_R, .type = ARM_CP_CONST, 4696 .resetvalue = 0 }, 4697 { .name = "ID_AA64PFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4698 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6, 4699 .access = PL1_R, .type = ARM_CP_CONST, 4700 .resetvalue = 0 }, 4701 { .name = "ID_AA64PFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4702 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 7, 4703 .access = PL1_R, .type = ARM_CP_CONST, 4704 .resetvalue = 0 }, 4705 { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64, 4706 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0, 4707 .access = PL1_R, .type = ARM_CP_CONST, 4708 .resetvalue = cpu->id_aa64dfr0 }, 4709 { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64, 4710 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1, 4711 .access = PL1_R, .type = ARM_CP_CONST, 4712 .resetvalue = cpu->id_aa64dfr1 }, 4713 { .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4714 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2, 4715 .access = PL1_R, .type = ARM_CP_CONST, 4716 .resetvalue = 0 }, 4717 { .name = "ID_AA64DFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4718 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 3, 4719 .access = PL1_R, .type = ARM_CP_CONST, 4720 .resetvalue = 0 }, 4721 { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64, 4722 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4, 4723 .access = PL1_R, .type = ARM_CP_CONST, 4724 .resetvalue = cpu->id_aa64afr0 }, 4725 { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64, 4726 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5, 4727 .access = PL1_R, .type = ARM_CP_CONST, 4728 .resetvalue = cpu->id_aa64afr1 }, 4729 { .name = "ID_AA64AFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4730 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 6, 4731 .access = PL1_R, .type = ARM_CP_CONST, 4732 .resetvalue = 0 }, 4733 { .name = "ID_AA64AFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4734 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 7, 4735 .access = PL1_R, .type = ARM_CP_CONST, 4736 .resetvalue = 0 }, 4737 { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64, 4738 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0, 4739 .access = PL1_R, .type = ARM_CP_CONST, 4740 .resetvalue = cpu->id_aa64isar0 }, 4741 { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64, 4742 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1, 4743 .access = PL1_R, .type = ARM_CP_CONST, 4744 .resetvalue = cpu->id_aa64isar1 }, 4745 { .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4746 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2, 4747 .access = PL1_R, .type = ARM_CP_CONST, 4748 .resetvalue = 0 }, 4749 { .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4750 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3, 4751 .access = PL1_R, .type = ARM_CP_CONST, 4752 .resetvalue = 0 }, 4753 { .name = "ID_AA64ISAR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4754 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 4, 4755 .access = PL1_R, .type = ARM_CP_CONST, 4756 .resetvalue = 0 }, 4757 { .name = "ID_AA64ISAR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4758 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 5, 4759 .access = PL1_R, .type = ARM_CP_CONST, 4760 .resetvalue = 0 }, 4761 { .name = "ID_AA64ISAR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4762 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 6, 4763 .access = PL1_R, .type = ARM_CP_CONST, 4764 .resetvalue = 0 }, 4765 { .name = "ID_AA64ISAR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4766 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 7, 4767 .access = PL1_R, .type = ARM_CP_CONST, 4768 .resetvalue = 0 }, 4769 { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64, 4770 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, 4771 .access = PL1_R, .type = ARM_CP_CONST, 4772 .resetvalue = cpu->id_aa64mmfr0 }, 4773 { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64, 4774 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1, 4775 .access = PL1_R, .type = ARM_CP_CONST, 4776 .resetvalue = cpu->id_aa64mmfr1 }, 4777 { .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4778 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2, 4779 .access = PL1_R, .type = ARM_CP_CONST, 4780 .resetvalue = 0 }, 4781 { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4782 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3, 4783 .access = PL1_R, .type = ARM_CP_CONST, 4784 .resetvalue = 0 }, 4785 { .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4786 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4, 4787 .access = PL1_R, .type = ARM_CP_CONST, 4788 .resetvalue = 0 }, 4789 { .name = "ID_AA64MMFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4790 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5, 4791 .access = PL1_R, .type = ARM_CP_CONST, 4792 .resetvalue = 0 }, 4793 { .name = "ID_AA64MMFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4794 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 6, 4795 .access = PL1_R, .type = ARM_CP_CONST, 4796 .resetvalue = 0 }, 4797 { .name = "ID_AA64MMFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4798 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 7, 4799 .access = PL1_R, .type = ARM_CP_CONST, 4800 .resetvalue = 0 }, 4801 { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64, 4802 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0, 4803 .access = PL1_R, .type = ARM_CP_CONST, 4804 .resetvalue = cpu->mvfr0 }, 4805 { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64, 4806 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1, 4807 .access = PL1_R, .type = ARM_CP_CONST, 4808 .resetvalue = cpu->mvfr1 }, 4809 { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64, 4810 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2, 4811 .access = PL1_R, .type = ARM_CP_CONST, 4812 .resetvalue = cpu->mvfr2 }, 4813 { .name = "MVFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4814 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3, 4815 .access = PL1_R, .type = ARM_CP_CONST, 4816 .resetvalue = 0 }, 4817 { .name = "MVFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4818 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4, 4819 .access = PL1_R, .type = ARM_CP_CONST, 4820 .resetvalue = 0 }, 4821 { .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4822 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5, 4823 .access = PL1_R, .type = ARM_CP_CONST, 4824 .resetvalue = 0 }, 4825 { .name = "MVFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4826 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6, 4827 .access = PL1_R, .type = ARM_CP_CONST, 4828 .resetvalue = 0 }, 4829 { .name = "MVFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4830 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7, 4831 .access = PL1_R, .type = ARM_CP_CONST, 4832 .resetvalue = 0 }, 4833 { .name = "PMCEID0", .state = ARM_CP_STATE_AA32, 4834 .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6, 4835 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, 4836 .resetvalue = cpu->pmceid0 }, 4837 { .name = "PMCEID0_EL0", .state = ARM_CP_STATE_AA64, 4838 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 6, 4839 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, 4840 .resetvalue = cpu->pmceid0 }, 4841 { .name = "PMCEID1", .state = ARM_CP_STATE_AA32, 4842 .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 7, 4843 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, 4844 .resetvalue = cpu->pmceid1 }, 4845 { .name = "PMCEID1_EL0", .state = ARM_CP_STATE_AA64, 4846 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7, 4847 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, 4848 .resetvalue = cpu->pmceid1 }, 4849 REGINFO_SENTINEL 4850 }; 4851 /* RVBAR_EL1 is only implemented if EL1 is the highest EL */ 4852 if (!arm_feature(env, ARM_FEATURE_EL3) && 4853 !arm_feature(env, ARM_FEATURE_EL2)) { 4854 ARMCPRegInfo rvbar = { 4855 .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64, 4856 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, 4857 .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar 4858 }; 4859 define_one_arm_cp_reg(cpu, &rvbar); 4860 } 4861 define_arm_cp_regs(cpu, v8_idregs); 4862 define_arm_cp_regs(cpu, v8_cp_reginfo); 4863 } 4864 if (arm_feature(env, ARM_FEATURE_EL2)) { 4865 uint64_t vmpidr_def = mpidr_read_val(env); 4866 ARMCPRegInfo vpidr_regs[] = { 4867 { .name = "VPIDR", .state = ARM_CP_STATE_AA32, 4868 .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, 4869 .access = PL2_RW, .accessfn = access_el3_aa32ns, 4870 .resetvalue = cpu->midr, 4871 .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, 4872 { .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64, 4873 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, 4874 .access = PL2_RW, .resetvalue = cpu->midr, 4875 .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, 4876 { .name = "VMPIDR", .state = ARM_CP_STATE_AA32, 4877 .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, 4878 .access = PL2_RW, .accessfn = access_el3_aa32ns, 4879 .resetvalue = vmpidr_def, 4880 .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) }, 4881 { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64, 4882 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, 4883 .access = PL2_RW, 4884 .resetvalue = vmpidr_def, 4885 .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) }, 4886 REGINFO_SENTINEL 4887 }; 4888 define_arm_cp_regs(cpu, vpidr_regs); 4889 define_arm_cp_regs(cpu, el2_cp_reginfo); 4890 /* RVBAR_EL2 is only implemented if EL2 is the highest EL */ 4891 if (!arm_feature(env, ARM_FEATURE_EL3)) { 4892 ARMCPRegInfo rvbar = { 4893 .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64, 4894 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1, 4895 .type = ARM_CP_CONST, .access = PL2_R, .resetvalue = cpu->rvbar 4896 }; 4897 define_one_arm_cp_reg(cpu, &rvbar); 4898 } 4899 } else { 4900 /* If EL2 is missing but higher ELs are enabled, we need to 4901 * register the no_el2 reginfos. 4902 */ 4903 if (arm_feature(env, ARM_FEATURE_EL3)) { 4904 /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value 4905 * of MIDR_EL1 and MPIDR_EL1. 4906 */ 4907 ARMCPRegInfo vpidr_regs[] = { 4908 { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH, 4909 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, 4910 .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, 4911 .type = ARM_CP_CONST, .resetvalue = cpu->midr, 4912 .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, 4913 { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH, 4914 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, 4915 .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, 4916 .type = ARM_CP_NO_RAW, 4917 .writefn = arm_cp_write_ignore, .readfn = mpidr_read }, 4918 REGINFO_SENTINEL 4919 }; 4920 define_arm_cp_regs(cpu, vpidr_regs); 4921 define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo); 4922 } 4923 } 4924 if (arm_feature(env, ARM_FEATURE_EL3)) { 4925 define_arm_cp_regs(cpu, el3_cp_reginfo); 4926 ARMCPRegInfo el3_regs[] = { 4927 { .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64, 4928 .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1, 4929 .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar }, 4930 { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64, 4931 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0, 4932 .access = PL3_RW, 4933 .raw_writefn = raw_write, .writefn = sctlr_write, 4934 .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]), 4935 .resetvalue = cpu->reset_sctlr }, 4936 REGINFO_SENTINEL 4937 }; 4938 4939 define_arm_cp_regs(cpu, el3_regs); 4940 } 4941 /* The behaviour of NSACR is sufficiently various that we don't 4942 * try to describe it in a single reginfo: 4943 * if EL3 is 64 bit, then trap to EL3 from S EL1, 4944 * reads as constant 0xc00 from NS EL1 and NS EL2 4945 * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2 4946 * if v7 without EL3, register doesn't exist 4947 * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2 4948 */ 4949 if (arm_feature(env, ARM_FEATURE_EL3)) { 4950 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 4951 ARMCPRegInfo nsacr = { 4952 .name = "NSACR", .type = ARM_CP_CONST, 4953 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, 4954 .access = PL1_RW, .accessfn = nsacr_access, 4955 .resetvalue = 0xc00 4956 }; 4957 define_one_arm_cp_reg(cpu, &nsacr); 4958 } else { 4959 ARMCPRegInfo nsacr = { 4960 .name = "NSACR", 4961 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, 4962 .access = PL3_RW | PL1_R, 4963 .resetvalue = 0, 4964 .fieldoffset = offsetof(CPUARMState, cp15.nsacr) 4965 }; 4966 define_one_arm_cp_reg(cpu, &nsacr); 4967 } 4968 } else { 4969 if (arm_feature(env, ARM_FEATURE_V8)) { 4970 ARMCPRegInfo nsacr = { 4971 .name = "NSACR", .type = ARM_CP_CONST, 4972 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, 4973 .access = PL1_R, 4974 .resetvalue = 0xc00 4975 }; 4976 define_one_arm_cp_reg(cpu, &nsacr); 4977 } 4978 } 4979 4980 if (arm_feature(env, ARM_FEATURE_PMSA)) { 4981 if (arm_feature(env, ARM_FEATURE_V6)) { 4982 /* PMSAv6 not implemented */ 4983 assert(arm_feature(env, ARM_FEATURE_V7)); 4984 define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); 4985 define_arm_cp_regs(cpu, pmsav7_cp_reginfo); 4986 } else { 4987 define_arm_cp_regs(cpu, pmsav5_cp_reginfo); 4988 } 4989 } else { 4990 define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); 4991 define_arm_cp_regs(cpu, vmsa_cp_reginfo); 4992 } 4993 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { 4994 define_arm_cp_regs(cpu, t2ee_cp_reginfo); 4995 } 4996 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { 4997 define_arm_cp_regs(cpu, generic_timer_cp_reginfo); 4998 } 4999 if (arm_feature(env, ARM_FEATURE_VAPA)) { 5000 define_arm_cp_regs(cpu, vapa_cp_reginfo); 5001 } 5002 if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) { 5003 define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo); 5004 } 5005 if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) { 5006 define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo); 5007 } 5008 if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) { 5009 define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo); 5010 } 5011 if (arm_feature(env, ARM_FEATURE_OMAPCP)) { 5012 define_arm_cp_regs(cpu, omap_cp_reginfo); 5013 } 5014 if (arm_feature(env, ARM_FEATURE_STRONGARM)) { 5015 define_arm_cp_regs(cpu, strongarm_cp_reginfo); 5016 } 5017 if (arm_feature(env, ARM_FEATURE_XSCALE)) { 5018 define_arm_cp_regs(cpu, xscale_cp_reginfo); 5019 } 5020 if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) { 5021 define_arm_cp_regs(cpu, dummy_c15_cp_reginfo); 5022 } 5023 if (arm_feature(env, ARM_FEATURE_LPAE)) { 5024 define_arm_cp_regs(cpu, lpae_cp_reginfo); 5025 } 5026 /* Slightly awkwardly, the OMAP and StrongARM cores need all of 5027 * cp15 crn=0 to be writes-ignored, whereas for other cores they should 5028 * be read-only (ie write causes UNDEF exception). 5029 */ 5030 { 5031 ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = { 5032 /* Pre-v8 MIDR space. 5033 * Note that the MIDR isn't a simple constant register because 5034 * of the TI925 behaviour where writes to another register can 5035 * cause the MIDR value to change. 5036 * 5037 * Unimplemented registers in the c15 0 0 0 space default to 5038 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR 5039 * and friends override accordingly. 5040 */ 5041 { .name = "MIDR", 5042 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY, 5043 .access = PL1_R, .resetvalue = cpu->midr, 5044 .writefn = arm_cp_write_ignore, .raw_writefn = raw_write, 5045 .readfn = midr_read, 5046 .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), 5047 .type = ARM_CP_OVERRIDE }, 5048 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */ 5049 { .name = "DUMMY", 5050 .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY, 5051 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 5052 { .name = "DUMMY", 5053 .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY, 5054 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 5055 { .name = "DUMMY", 5056 .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY, 5057 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 5058 { .name = "DUMMY", 5059 .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY, 5060 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 5061 { .name = "DUMMY", 5062 .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY, 5063 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 5064 REGINFO_SENTINEL 5065 }; 5066 ARMCPRegInfo id_v8_midr_cp_reginfo[] = { 5067 { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH, 5068 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0, 5069 .access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr, 5070 .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), 5071 .readfn = midr_read }, 5072 /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */ 5073 { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST, 5074 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4, 5075 .access = PL1_R, .resetvalue = cpu->midr }, 5076 { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST, 5077 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7, 5078 .access = PL1_R, .resetvalue = cpu->midr }, 5079 { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH, 5080 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6, 5081 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->revidr }, 5082 REGINFO_SENTINEL 5083 }; 5084 ARMCPRegInfo id_cp_reginfo[] = { 5085 /* These are common to v8 and pre-v8 */ 5086 { .name = "CTR", 5087 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1, 5088 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, 5089 { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64, 5090 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0, 5091 .access = PL0_R, .accessfn = ctr_el0_access, 5092 .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, 5093 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */ 5094 { .name = "TCMTR", 5095 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2, 5096 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 5097 REGINFO_SENTINEL 5098 }; 5099 /* TLBTR is specific to VMSA */ 5100 ARMCPRegInfo id_tlbtr_reginfo = { 5101 .name = "TLBTR", 5102 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3, 5103 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0, 5104 }; 5105 /* MPUIR is specific to PMSA V6+ */ 5106 ARMCPRegInfo id_mpuir_reginfo = { 5107 .name = "MPUIR", 5108 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4, 5109 .access = PL1_R, .type = ARM_CP_CONST, 5110 .resetvalue = cpu->pmsav7_dregion << 8 5111 }; 5112 ARMCPRegInfo crn0_wi_reginfo = { 5113 .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY, 5114 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W, 5115 .type = ARM_CP_NOP | ARM_CP_OVERRIDE 5116 }; 5117 if (arm_feature(env, ARM_FEATURE_OMAPCP) || 5118 arm_feature(env, ARM_FEATURE_STRONGARM)) { 5119 ARMCPRegInfo *r; 5120 /* Register the blanket "writes ignored" value first to cover the 5121 * whole space. Then update the specific ID registers to allow write 5122 * access, so that they ignore writes rather than causing them to 5123 * UNDEF. 5124 */ 5125 define_one_arm_cp_reg(cpu, &crn0_wi_reginfo); 5126 for (r = id_pre_v8_midr_cp_reginfo; 5127 r->type != ARM_CP_SENTINEL; r++) { 5128 r->access = PL1_RW; 5129 } 5130 for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) { 5131 r->access = PL1_RW; 5132 } 5133 id_tlbtr_reginfo.access = PL1_RW; 5134 id_tlbtr_reginfo.access = PL1_RW; 5135 } 5136 if (arm_feature(env, ARM_FEATURE_V8)) { 5137 define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo); 5138 } else { 5139 define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo); 5140 } 5141 define_arm_cp_regs(cpu, id_cp_reginfo); 5142 if (!arm_feature(env, ARM_FEATURE_PMSA)) { 5143 define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo); 5144 } else if (arm_feature(env, ARM_FEATURE_V7)) { 5145 define_one_arm_cp_reg(cpu, &id_mpuir_reginfo); 5146 } 5147 } 5148 5149 if (arm_feature(env, ARM_FEATURE_MPIDR)) { 5150 define_arm_cp_regs(cpu, mpidr_cp_reginfo); 5151 } 5152 5153 if (arm_feature(env, ARM_FEATURE_AUXCR)) { 5154 ARMCPRegInfo auxcr_reginfo[] = { 5155 { .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH, 5156 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1, 5157 .access = PL1_RW, .type = ARM_CP_CONST, 5158 .resetvalue = cpu->reset_auxcr }, 5159 { .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH, 5160 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1, 5161 .access = PL2_RW, .type = ARM_CP_CONST, 5162 .resetvalue = 0 }, 5163 { .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64, 5164 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1, 5165 .access = PL3_RW, .type = ARM_CP_CONST, 5166 .resetvalue = 0 }, 5167 REGINFO_SENTINEL 5168 }; 5169 define_arm_cp_regs(cpu, auxcr_reginfo); 5170 } 5171 5172 if (arm_feature(env, ARM_FEATURE_CBAR)) { 5173 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 5174 /* 32 bit view is [31:18] 0...0 [43:32]. */ 5175 uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18) 5176 | extract64(cpu->reset_cbar, 32, 12); 5177 ARMCPRegInfo cbar_reginfo[] = { 5178 { .name = "CBAR", 5179 .type = ARM_CP_CONST, 5180 .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0, 5181 .access = PL1_R, .resetvalue = cpu->reset_cbar }, 5182 { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64, 5183 .type = ARM_CP_CONST, 5184 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0, 5185 .access = PL1_R, .resetvalue = cbar32 }, 5186 REGINFO_SENTINEL 5187 }; 5188 /* We don't implement a r/w 64 bit CBAR currently */ 5189 assert(arm_feature(env, ARM_FEATURE_CBAR_RO)); 5190 define_arm_cp_regs(cpu, cbar_reginfo); 5191 } else { 5192 ARMCPRegInfo cbar = { 5193 .name = "CBAR", 5194 .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0, 5195 .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar, 5196 .fieldoffset = offsetof(CPUARMState, 5197 cp15.c15_config_base_address) 5198 }; 5199 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 5200 cbar.access = PL1_R; 5201 cbar.fieldoffset = 0; 5202 cbar.type = ARM_CP_CONST; 5203 } 5204 define_one_arm_cp_reg(cpu, &cbar); 5205 } 5206 } 5207 5208 if (arm_feature(env, ARM_FEATURE_VBAR)) { 5209 ARMCPRegInfo vbar_cp_reginfo[] = { 5210 { .name = "VBAR", .state = ARM_CP_STATE_BOTH, 5211 .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0, 5212 .access = PL1_RW, .writefn = vbar_write, 5213 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s), 5214 offsetof(CPUARMState, cp15.vbar_ns) }, 5215 .resetvalue = 0 }, 5216 REGINFO_SENTINEL 5217 }; 5218 define_arm_cp_regs(cpu, vbar_cp_reginfo); 5219 } 5220 5221 /* Generic registers whose values depend on the implementation */ 5222 { 5223 ARMCPRegInfo sctlr = { 5224 .name = "SCTLR", .state = ARM_CP_STATE_BOTH, 5225 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, 5226 .access = PL1_RW, 5227 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s), 5228 offsetof(CPUARMState, cp15.sctlr_ns) }, 5229 .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr, 5230 .raw_writefn = raw_write, 5231 }; 5232 if (arm_feature(env, ARM_FEATURE_XSCALE)) { 5233 /* Normally we would always end the TB on an SCTLR write, but Linux 5234 * arch/arm/mach-pxa/sleep.S expects two instructions following 5235 * an MMU enable to execute from cache. Imitate this behaviour. 5236 */ 5237 sctlr.type |= ARM_CP_SUPPRESS_TB_END; 5238 } 5239 define_one_arm_cp_reg(cpu, &sctlr); 5240 } 5241 } 5242 5243 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) 5244 { 5245 CPUState *cs = CPU(cpu); 5246 CPUARMState *env = &cpu->env; 5247 5248 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 5249 gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg, 5250 aarch64_fpu_gdb_set_reg, 5251 34, "aarch64-fpu.xml", 0); 5252 } else if (arm_feature(env, ARM_FEATURE_NEON)) { 5253 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 5254 51, "arm-neon.xml", 0); 5255 } else if (arm_feature(env, ARM_FEATURE_VFP3)) { 5256 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 5257 35, "arm-vfp3.xml", 0); 5258 } else if (arm_feature(env, ARM_FEATURE_VFP)) { 5259 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 5260 19, "arm-vfp.xml", 0); 5261 } 5262 } 5263 5264 /* Sort alphabetically by type name, except for "any". */ 5265 static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b) 5266 { 5267 ObjectClass *class_a = (ObjectClass *)a; 5268 ObjectClass *class_b = (ObjectClass *)b; 5269 const char *name_a, *name_b; 5270 5271 name_a = object_class_get_name(class_a); 5272 name_b = object_class_get_name(class_b); 5273 if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) { 5274 return 1; 5275 } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) { 5276 return -1; 5277 } else { 5278 return strcmp(name_a, name_b); 5279 } 5280 } 5281 5282 static void arm_cpu_list_entry(gpointer data, gpointer user_data) 5283 { 5284 ObjectClass *oc = data; 5285 CPUListState *s = user_data; 5286 const char *typename; 5287 char *name; 5288 5289 typename = object_class_get_name(oc); 5290 name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU)); 5291 (*s->cpu_fprintf)(s->file, " %s\n", 5292 name); 5293 g_free(name); 5294 } 5295 5296 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf) 5297 { 5298 CPUListState s = { 5299 .file = f, 5300 .cpu_fprintf = cpu_fprintf, 5301 }; 5302 GSList *list; 5303 5304 list = object_class_get_list(TYPE_ARM_CPU, false); 5305 list = g_slist_sort(list, arm_cpu_list_compare); 5306 (*cpu_fprintf)(f, "Available CPUs:\n"); 5307 g_slist_foreach(list, arm_cpu_list_entry, &s); 5308 g_slist_free(list); 5309 #ifdef CONFIG_KVM 5310 /* The 'host' CPU type is dynamically registered only if KVM is 5311 * enabled, so we have to special-case it here: 5312 */ 5313 (*cpu_fprintf)(f, " host (only available in KVM mode)\n"); 5314 #endif 5315 } 5316 5317 static void arm_cpu_add_definition(gpointer data, gpointer user_data) 5318 { 5319 ObjectClass *oc = data; 5320 CpuDefinitionInfoList **cpu_list = user_data; 5321 CpuDefinitionInfoList *entry; 5322 CpuDefinitionInfo *info; 5323 const char *typename; 5324 5325 typename = object_class_get_name(oc); 5326 info = g_malloc0(sizeof(*info)); 5327 info->name = g_strndup(typename, 5328 strlen(typename) - strlen("-" TYPE_ARM_CPU)); 5329 info->q_typename = g_strdup(typename); 5330 5331 entry = g_malloc0(sizeof(*entry)); 5332 entry->value = info; 5333 entry->next = *cpu_list; 5334 *cpu_list = entry; 5335 } 5336 5337 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp) 5338 { 5339 CpuDefinitionInfoList *cpu_list = NULL; 5340 GSList *list; 5341 5342 list = object_class_get_list(TYPE_ARM_CPU, false); 5343 g_slist_foreach(list, arm_cpu_add_definition, &cpu_list); 5344 g_slist_free(list); 5345 5346 return cpu_list; 5347 } 5348 5349 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, 5350 void *opaque, int state, int secstate, 5351 int crm, int opc1, int opc2) 5352 { 5353 /* Private utility function for define_one_arm_cp_reg_with_opaque(): 5354 * add a single reginfo struct to the hash table. 5355 */ 5356 uint32_t *key = g_new(uint32_t, 1); 5357 ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo)); 5358 int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0; 5359 int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; 5360 5361 /* Reset the secure state to the specific incoming state. This is 5362 * necessary as the register may have been defined with both states. 5363 */ 5364 r2->secure = secstate; 5365 5366 if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { 5367 /* Register is banked (using both entries in array). 5368 * Overwriting fieldoffset as the array is only used to define 5369 * banked registers but later only fieldoffset is used. 5370 */ 5371 r2->fieldoffset = r->bank_fieldoffsets[ns]; 5372 } 5373 5374 if (state == ARM_CP_STATE_AA32) { 5375 if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { 5376 /* If the register is banked then we don't need to migrate or 5377 * reset the 32-bit instance in certain cases: 5378 * 5379 * 1) If the register has both 32-bit and 64-bit instances then we 5380 * can count on the 64-bit instance taking care of the 5381 * non-secure bank. 5382 * 2) If ARMv8 is enabled then we can count on a 64-bit version 5383 * taking care of the secure bank. This requires that separate 5384 * 32 and 64-bit definitions are provided. 5385 */ 5386 if ((r->state == ARM_CP_STATE_BOTH && ns) || 5387 (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) { 5388 r2->type |= ARM_CP_ALIAS; 5389 } 5390 } else if ((secstate != r->secure) && !ns) { 5391 /* The register is not banked so we only want to allow migration of 5392 * the non-secure instance. 5393 */ 5394 r2->type |= ARM_CP_ALIAS; 5395 } 5396 5397 if (r->state == ARM_CP_STATE_BOTH) { 5398 /* We assume it is a cp15 register if the .cp field is left unset. 5399 */ 5400 if (r2->cp == 0) { 5401 r2->cp = 15; 5402 } 5403 5404 #ifdef HOST_WORDS_BIGENDIAN 5405 if (r2->fieldoffset) { 5406 r2->fieldoffset += sizeof(uint32_t); 5407 } 5408 #endif 5409 } 5410 } 5411 if (state == ARM_CP_STATE_AA64) { 5412 /* To allow abbreviation of ARMCPRegInfo 5413 * definitions, we treat cp == 0 as equivalent to 5414 * the value for "standard guest-visible sysreg". 5415 * STATE_BOTH definitions are also always "standard 5416 * sysreg" in their AArch64 view (the .cp value may 5417 * be non-zero for the benefit of the AArch32 view). 5418 */ 5419 if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) { 5420 r2->cp = CP_REG_ARM64_SYSREG_CP; 5421 } 5422 *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm, 5423 r2->opc0, opc1, opc2); 5424 } else { 5425 *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2); 5426 } 5427 if (opaque) { 5428 r2->opaque = opaque; 5429 } 5430 /* reginfo passed to helpers is correct for the actual access, 5431 * and is never ARM_CP_STATE_BOTH: 5432 */ 5433 r2->state = state; 5434 /* Make sure reginfo passed to helpers for wildcarded regs 5435 * has the correct crm/opc1/opc2 for this reg, not CP_ANY: 5436 */ 5437 r2->crm = crm; 5438 r2->opc1 = opc1; 5439 r2->opc2 = opc2; 5440 /* By convention, for wildcarded registers only the first 5441 * entry is used for migration; the others are marked as 5442 * ALIAS so we don't try to transfer the register 5443 * multiple times. Special registers (ie NOP/WFI) are 5444 * never migratable and not even raw-accessible. 5445 */ 5446 if ((r->type & ARM_CP_SPECIAL)) { 5447 r2->type |= ARM_CP_NO_RAW; 5448 } 5449 if (((r->crm == CP_ANY) && crm != 0) || 5450 ((r->opc1 == CP_ANY) && opc1 != 0) || 5451 ((r->opc2 == CP_ANY) && opc2 != 0)) { 5452 r2->type |= ARM_CP_ALIAS; 5453 } 5454 5455 /* Check that raw accesses are either forbidden or handled. Note that 5456 * we can't assert this earlier because the setup of fieldoffset for 5457 * banked registers has to be done first. 5458 */ 5459 if (!(r2->type & ARM_CP_NO_RAW)) { 5460 assert(!raw_accessors_invalid(r2)); 5461 } 5462 5463 /* Overriding of an existing definition must be explicitly 5464 * requested. 5465 */ 5466 if (!(r->type & ARM_CP_OVERRIDE)) { 5467 ARMCPRegInfo *oldreg; 5468 oldreg = g_hash_table_lookup(cpu->cp_regs, key); 5469 if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) { 5470 fprintf(stderr, "Register redefined: cp=%d %d bit " 5471 "crn=%d crm=%d opc1=%d opc2=%d, " 5472 "was %s, now %s\n", r2->cp, 32 + 32 * is64, 5473 r2->crn, r2->crm, r2->opc1, r2->opc2, 5474 oldreg->name, r2->name); 5475 g_assert_not_reached(); 5476 } 5477 } 5478 g_hash_table_insert(cpu->cp_regs, key, r2); 5479 } 5480 5481 5482 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, 5483 const ARMCPRegInfo *r, void *opaque) 5484 { 5485 /* Define implementations of coprocessor registers. 5486 * We store these in a hashtable because typically 5487 * there are less than 150 registers in a space which 5488 * is 16*16*16*8*8 = 262144 in size. 5489 * Wildcarding is supported for the crm, opc1 and opc2 fields. 5490 * If a register is defined twice then the second definition is 5491 * used, so this can be used to define some generic registers and 5492 * then override them with implementation specific variations. 5493 * At least one of the original and the second definition should 5494 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard 5495 * against accidental use. 5496 * 5497 * The state field defines whether the register is to be 5498 * visible in the AArch32 or AArch64 execution state. If the 5499 * state is set to ARM_CP_STATE_BOTH then we synthesise a 5500 * reginfo structure for the AArch32 view, which sees the lower 5501 * 32 bits of the 64 bit register. 5502 * 5503 * Only registers visible in AArch64 may set r->opc0; opc0 cannot 5504 * be wildcarded. AArch64 registers are always considered to be 64 5505 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of 5506 * the register, if any. 5507 */ 5508 int crm, opc1, opc2, state; 5509 int crmmin = (r->crm == CP_ANY) ? 0 : r->crm; 5510 int crmmax = (r->crm == CP_ANY) ? 15 : r->crm; 5511 int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1; 5512 int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1; 5513 int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2; 5514 int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2; 5515 /* 64 bit registers have only CRm and Opc1 fields */ 5516 assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn))); 5517 /* op0 only exists in the AArch64 encodings */ 5518 assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0)); 5519 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */ 5520 assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT)); 5521 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1 5522 * encodes a minimum access level for the register. We roll this 5523 * runtime check into our general permission check code, so check 5524 * here that the reginfo's specified permissions are strict enough 5525 * to encompass the generic architectural permission check. 5526 */ 5527 if (r->state != ARM_CP_STATE_AA32) { 5528 int mask = 0; 5529 switch (r->opc1) { 5530 case 0: case 1: case 2: 5531 /* min_EL EL1 */ 5532 mask = PL1_RW; 5533 break; 5534 case 3: 5535 /* min_EL EL0 */ 5536 mask = PL0_RW; 5537 break; 5538 case 4: 5539 /* min_EL EL2 */ 5540 mask = PL2_RW; 5541 break; 5542 case 5: 5543 /* unallocated encoding, so not possible */ 5544 assert(false); 5545 break; 5546 case 6: 5547 /* min_EL EL3 */ 5548 mask = PL3_RW; 5549 break; 5550 case 7: 5551 /* min_EL EL1, secure mode only (we don't check the latter) */ 5552 mask = PL1_RW; 5553 break; 5554 default: 5555 /* broken reginfo with out-of-range opc1 */ 5556 assert(false); 5557 break; 5558 } 5559 /* assert our permissions are not too lax (stricter is fine) */ 5560 assert((r->access & ~mask) == 0); 5561 } 5562 5563 /* Check that the register definition has enough info to handle 5564 * reads and writes if they are permitted. 5565 */ 5566 if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) { 5567 if (r->access & PL3_R) { 5568 assert((r->fieldoffset || 5569 (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || 5570 r->readfn); 5571 } 5572 if (r->access & PL3_W) { 5573 assert((r->fieldoffset || 5574 (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || 5575 r->writefn); 5576 } 5577 } 5578 /* Bad type field probably means missing sentinel at end of reg list */ 5579 assert(cptype_valid(r->type)); 5580 for (crm = crmmin; crm <= crmmax; crm++) { 5581 for (opc1 = opc1min; opc1 <= opc1max; opc1++) { 5582 for (opc2 = opc2min; opc2 <= opc2max; opc2++) { 5583 for (state = ARM_CP_STATE_AA32; 5584 state <= ARM_CP_STATE_AA64; state++) { 5585 if (r->state != state && r->state != ARM_CP_STATE_BOTH) { 5586 continue; 5587 } 5588 if (state == ARM_CP_STATE_AA32) { 5589 /* Under AArch32 CP registers can be common 5590 * (same for secure and non-secure world) or banked. 5591 */ 5592 switch (r->secure) { 5593 case ARM_CP_SECSTATE_S: 5594 case ARM_CP_SECSTATE_NS: 5595 add_cpreg_to_hashtable(cpu, r, opaque, state, 5596 r->secure, crm, opc1, opc2); 5597 break; 5598 default: 5599 add_cpreg_to_hashtable(cpu, r, opaque, state, 5600 ARM_CP_SECSTATE_S, 5601 crm, opc1, opc2); 5602 add_cpreg_to_hashtable(cpu, r, opaque, state, 5603 ARM_CP_SECSTATE_NS, 5604 crm, opc1, opc2); 5605 break; 5606 } 5607 } else { 5608 /* AArch64 registers get mapped to non-secure instance 5609 * of AArch32 */ 5610 add_cpreg_to_hashtable(cpu, r, opaque, state, 5611 ARM_CP_SECSTATE_NS, 5612 crm, opc1, opc2); 5613 } 5614 } 5615 } 5616 } 5617 } 5618 } 5619 5620 void define_arm_cp_regs_with_opaque(ARMCPU *cpu, 5621 const ARMCPRegInfo *regs, void *opaque) 5622 { 5623 /* Define a whole list of registers */ 5624 const ARMCPRegInfo *r; 5625 for (r = regs; r->type != ARM_CP_SENTINEL; r++) { 5626 define_one_arm_cp_reg_with_opaque(cpu, r, opaque); 5627 } 5628 } 5629 5630 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp) 5631 { 5632 return g_hash_table_lookup(cpregs, &encoded_cp); 5633 } 5634 5635 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, 5636 uint64_t value) 5637 { 5638 /* Helper coprocessor write function for write-ignore registers */ 5639 } 5640 5641 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri) 5642 { 5643 /* Helper coprocessor write function for read-as-zero registers */ 5644 return 0; 5645 } 5646 5647 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque) 5648 { 5649 /* Helper coprocessor reset function for do-nothing-on-reset registers */ 5650 } 5651 5652 static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type) 5653 { 5654 /* Return true if it is not valid for us to switch to 5655 * this CPU mode (ie all the UNPREDICTABLE cases in 5656 * the ARM ARM CPSRWriteByInstr pseudocode). 5657 */ 5658 5659 /* Changes to or from Hyp via MSR and CPS are illegal. */ 5660 if (write_type == CPSRWriteByInstr && 5661 ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_HYP || 5662 mode == ARM_CPU_MODE_HYP)) { 5663 return 1; 5664 } 5665 5666 switch (mode) { 5667 case ARM_CPU_MODE_USR: 5668 return 0; 5669 case ARM_CPU_MODE_SYS: 5670 case ARM_CPU_MODE_SVC: 5671 case ARM_CPU_MODE_ABT: 5672 case ARM_CPU_MODE_UND: 5673 case ARM_CPU_MODE_IRQ: 5674 case ARM_CPU_MODE_FIQ: 5675 /* Note that we don't implement the IMPDEF NSACR.RFR which in v7 5676 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.) 5677 */ 5678 /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR 5679 * and CPS are treated as illegal mode changes. 5680 */ 5681 if (write_type == CPSRWriteByInstr && 5682 (env->cp15.hcr_el2 & HCR_TGE) && 5683 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON && 5684 !arm_is_secure_below_el3(env)) { 5685 return 1; 5686 } 5687 return 0; 5688 case ARM_CPU_MODE_HYP: 5689 return !arm_feature(env, ARM_FEATURE_EL2) 5690 || arm_current_el(env) < 2 || arm_is_secure(env); 5691 case ARM_CPU_MODE_MON: 5692 return arm_current_el(env) < 3; 5693 default: 5694 return 1; 5695 } 5696 } 5697 5698 uint32_t cpsr_read(CPUARMState *env) 5699 { 5700 int ZF; 5701 ZF = (env->ZF == 0); 5702 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) | 5703 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 5704 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25) 5705 | ((env->condexec_bits & 0xfc) << 8) 5706 | (env->GE << 16) | (env->daif & CPSR_AIF); 5707 } 5708 5709 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 5710 CPSRWriteType write_type) 5711 { 5712 uint32_t changed_daif; 5713 5714 if (mask & CPSR_NZCV) { 5715 env->ZF = (~val) & CPSR_Z; 5716 env->NF = val; 5717 env->CF = (val >> 29) & 1; 5718 env->VF = (val << 3) & 0x80000000; 5719 } 5720 if (mask & CPSR_Q) 5721 env->QF = ((val & CPSR_Q) != 0); 5722 if (mask & CPSR_T) 5723 env->thumb = ((val & CPSR_T) != 0); 5724 if (mask & CPSR_IT_0_1) { 5725 env->condexec_bits &= ~3; 5726 env->condexec_bits |= (val >> 25) & 3; 5727 } 5728 if (mask & CPSR_IT_2_7) { 5729 env->condexec_bits &= 3; 5730 env->condexec_bits |= (val >> 8) & 0xfc; 5731 } 5732 if (mask & CPSR_GE) { 5733 env->GE = (val >> 16) & 0xf; 5734 } 5735 5736 /* In a V7 implementation that includes the security extensions but does 5737 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control 5738 * whether non-secure software is allowed to change the CPSR_F and CPSR_A 5739 * bits respectively. 5740 * 5741 * In a V8 implementation, it is permitted for privileged software to 5742 * change the CPSR A/F bits regardless of the SCR.AW/FW bits. 5743 */ 5744 if (write_type != CPSRWriteRaw && !arm_feature(env, ARM_FEATURE_V8) && 5745 arm_feature(env, ARM_FEATURE_EL3) && 5746 !arm_feature(env, ARM_FEATURE_EL2) && 5747 !arm_is_secure(env)) { 5748 5749 changed_daif = (env->daif ^ val) & mask; 5750 5751 if (changed_daif & CPSR_A) { 5752 /* Check to see if we are allowed to change the masking of async 5753 * abort exceptions from a non-secure state. 5754 */ 5755 if (!(env->cp15.scr_el3 & SCR_AW)) { 5756 qemu_log_mask(LOG_GUEST_ERROR, 5757 "Ignoring attempt to switch CPSR_A flag from " 5758 "non-secure world with SCR.AW bit clear\n"); 5759 mask &= ~CPSR_A; 5760 } 5761 } 5762 5763 if (changed_daif & CPSR_F) { 5764 /* Check to see if we are allowed to change the masking of FIQ 5765 * exceptions from a non-secure state. 5766 */ 5767 if (!(env->cp15.scr_el3 & SCR_FW)) { 5768 qemu_log_mask(LOG_GUEST_ERROR, 5769 "Ignoring attempt to switch CPSR_F flag from " 5770 "non-secure world with SCR.FW bit clear\n"); 5771 mask &= ~CPSR_F; 5772 } 5773 5774 /* Check whether non-maskable FIQ (NMFI) support is enabled. 5775 * If this bit is set software is not allowed to mask 5776 * FIQs, but is allowed to set CPSR_F to 0. 5777 */ 5778 if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) && 5779 (val & CPSR_F)) { 5780 qemu_log_mask(LOG_GUEST_ERROR, 5781 "Ignoring attempt to enable CPSR_F flag " 5782 "(non-maskable FIQ [NMFI] support enabled)\n"); 5783 mask &= ~CPSR_F; 5784 } 5785 } 5786 } 5787 5788 env->daif &= ~(CPSR_AIF & mask); 5789 env->daif |= val & CPSR_AIF & mask; 5790 5791 if (write_type != CPSRWriteRaw && 5792 ((env->uncached_cpsr ^ val) & mask & CPSR_M)) { 5793 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR) { 5794 /* Note that we can only get here in USR mode if this is a 5795 * gdb stub write; for this case we follow the architectural 5796 * behaviour for guest writes in USR mode of ignoring an attempt 5797 * to switch mode. (Those are caught by translate.c for writes 5798 * triggered by guest instructions.) 5799 */ 5800 mask &= ~CPSR_M; 5801 } else if (bad_mode_switch(env, val & CPSR_M, write_type)) { 5802 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in 5803 * v7, and has defined behaviour in v8: 5804 * + leave CPSR.M untouched 5805 * + allow changes to the other CPSR fields 5806 * + set PSTATE.IL 5807 * For user changes via the GDB stub, we don't set PSTATE.IL, 5808 * as this would be unnecessarily harsh for a user error. 5809 */ 5810 mask &= ~CPSR_M; 5811 if (write_type != CPSRWriteByGDBStub && 5812 arm_feature(env, ARM_FEATURE_V8)) { 5813 mask |= CPSR_IL; 5814 val |= CPSR_IL; 5815 } 5816 } else { 5817 switch_mode(env, val & CPSR_M); 5818 } 5819 } 5820 mask &= ~CACHED_CPSR_BITS; 5821 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask); 5822 } 5823 5824 /* Sign/zero extend */ 5825 uint32_t HELPER(sxtb16)(uint32_t x) 5826 { 5827 uint32_t res; 5828 res = (uint16_t)(int8_t)x; 5829 res |= (uint32_t)(int8_t)(x >> 16) << 16; 5830 return res; 5831 } 5832 5833 uint32_t HELPER(uxtb16)(uint32_t x) 5834 { 5835 uint32_t res; 5836 res = (uint16_t)(uint8_t)x; 5837 res |= (uint32_t)(uint8_t)(x >> 16) << 16; 5838 return res; 5839 } 5840 5841 int32_t HELPER(sdiv)(int32_t num, int32_t den) 5842 { 5843 if (den == 0) 5844 return 0; 5845 if (num == INT_MIN && den == -1) 5846 return INT_MIN; 5847 return num / den; 5848 } 5849 5850 uint32_t HELPER(udiv)(uint32_t num, uint32_t den) 5851 { 5852 if (den == 0) 5853 return 0; 5854 return num / den; 5855 } 5856 5857 uint32_t HELPER(rbit)(uint32_t x) 5858 { 5859 return revbit32(x); 5860 } 5861 5862 #if defined(CONFIG_USER_ONLY) 5863 5864 /* These should probably raise undefined insn exceptions. */ 5865 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) 5866 { 5867 ARMCPU *cpu = arm_env_get_cpu(env); 5868 5869 cpu_abort(CPU(cpu), "v7m_msr %d\n", reg); 5870 } 5871 5872 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) 5873 { 5874 ARMCPU *cpu = arm_env_get_cpu(env); 5875 5876 cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg); 5877 return 0; 5878 } 5879 5880 void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest) 5881 { 5882 /* translate.c should never generate calls here in user-only mode */ 5883 g_assert_not_reached(); 5884 } 5885 5886 void switch_mode(CPUARMState *env, int mode) 5887 { 5888 ARMCPU *cpu = arm_env_get_cpu(env); 5889 5890 if (mode != ARM_CPU_MODE_USR) { 5891 cpu_abort(CPU(cpu), "Tried to switch out of user mode\n"); 5892 } 5893 } 5894 5895 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 5896 uint32_t cur_el, bool secure) 5897 { 5898 return 1; 5899 } 5900 5901 void aarch64_sync_64_to_32(CPUARMState *env) 5902 { 5903 g_assert_not_reached(); 5904 } 5905 5906 #else 5907 5908 void switch_mode(CPUARMState *env, int mode) 5909 { 5910 int old_mode; 5911 int i; 5912 5913 old_mode = env->uncached_cpsr & CPSR_M; 5914 if (mode == old_mode) 5915 return; 5916 5917 if (old_mode == ARM_CPU_MODE_FIQ) { 5918 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t)); 5919 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t)); 5920 } else if (mode == ARM_CPU_MODE_FIQ) { 5921 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t)); 5922 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t)); 5923 } 5924 5925 i = bank_number(old_mode); 5926 env->banked_r13[i] = env->regs[13]; 5927 env->banked_r14[i] = env->regs[14]; 5928 env->banked_spsr[i] = env->spsr; 5929 5930 i = bank_number(mode); 5931 env->regs[13] = env->banked_r13[i]; 5932 env->regs[14] = env->banked_r14[i]; 5933 env->spsr = env->banked_spsr[i]; 5934 } 5935 5936 /* Physical Interrupt Target EL Lookup Table 5937 * 5938 * [ From ARM ARM section G1.13.4 (Table G1-15) ] 5939 * 5940 * The below multi-dimensional table is used for looking up the target 5941 * exception level given numerous condition criteria. Specifically, the 5942 * target EL is based on SCR and HCR routing controls as well as the 5943 * currently executing EL and secure state. 5944 * 5945 * Dimensions: 5946 * target_el_table[2][2][2][2][2][4] 5947 * | | | | | +--- Current EL 5948 * | | | | +------ Non-secure(0)/Secure(1) 5949 * | | | +--------- HCR mask override 5950 * | | +------------ SCR exec state control 5951 * | +--------------- SCR mask override 5952 * +------------------ 32-bit(0)/64-bit(1) EL3 5953 * 5954 * The table values are as such: 5955 * 0-3 = EL0-EL3 5956 * -1 = Cannot occur 5957 * 5958 * The ARM ARM target EL table includes entries indicating that an "exception 5959 * is not taken". The two cases where this is applicable are: 5960 * 1) An exception is taken from EL3 but the SCR does not have the exception 5961 * routed to EL3. 5962 * 2) An exception is taken from EL2 but the HCR does not have the exception 5963 * routed to EL2. 5964 * In these two cases, the below table contain a target of EL1. This value is 5965 * returned as it is expected that the consumer of the table data will check 5966 * for "target EL >= current EL" to ensure the exception is not taken. 5967 * 5968 * SCR HCR 5969 * 64 EA AMO From 5970 * BIT IRQ IMO Non-secure Secure 5971 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3 5972 */ 5973 static const int8_t target_el_table[2][2][2][2][2][4] = { 5974 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },}, 5975 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},}, 5976 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },}, 5977 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},}, 5978 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },}, 5979 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},}, 5980 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },}, 5981 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},}, 5982 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },}, 5983 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},}, 5984 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, -1, 1 },}, 5985 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},}, 5986 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },}, 5987 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},}, 5988 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },}, 5989 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},},}, 5990 }; 5991 5992 /* 5993 * Determine the target EL for physical exceptions 5994 */ 5995 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 5996 uint32_t cur_el, bool secure) 5997 { 5998 CPUARMState *env = cs->env_ptr; 5999 int rw; 6000 int scr; 6001 int hcr; 6002 int target_el; 6003 /* Is the highest EL AArch64? */ 6004 int is64 = arm_feature(env, ARM_FEATURE_AARCH64); 6005 6006 if (arm_feature(env, ARM_FEATURE_EL3)) { 6007 rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW); 6008 } else { 6009 /* Either EL2 is the highest EL (and so the EL2 register width 6010 * is given by is64); or there is no EL2 or EL3, in which case 6011 * the value of 'rw' does not affect the table lookup anyway. 6012 */ 6013 rw = is64; 6014 } 6015 6016 switch (excp_idx) { 6017 case EXCP_IRQ: 6018 scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ); 6019 hcr = ((env->cp15.hcr_el2 & HCR_IMO) == HCR_IMO); 6020 break; 6021 case EXCP_FIQ: 6022 scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ); 6023 hcr = ((env->cp15.hcr_el2 & HCR_FMO) == HCR_FMO); 6024 break; 6025 default: 6026 scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA); 6027 hcr = ((env->cp15.hcr_el2 & HCR_AMO) == HCR_AMO); 6028 break; 6029 }; 6030 6031 /* If HCR.TGE is set then HCR is treated as being 1 */ 6032 hcr |= ((env->cp15.hcr_el2 & HCR_TGE) == HCR_TGE); 6033 6034 /* Perform a table-lookup for the target EL given the current state */ 6035 target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el]; 6036 6037 assert(target_el > 0); 6038 6039 return target_el; 6040 } 6041 6042 static void v7m_push(CPUARMState *env, uint32_t val) 6043 { 6044 CPUState *cs = CPU(arm_env_get_cpu(env)); 6045 6046 env->regs[13] -= 4; 6047 stl_phys(cs->as, env->regs[13], val); 6048 } 6049 6050 static uint32_t v7m_pop(CPUARMState *env) 6051 { 6052 CPUState *cs = CPU(arm_env_get_cpu(env)); 6053 uint32_t val; 6054 6055 val = ldl_phys(cs->as, env->regs[13]); 6056 env->regs[13] += 4; 6057 return val; 6058 } 6059 6060 /* Return true if we're using the process stack pointer (not the MSP) */ 6061 static bool v7m_using_psp(CPUARMState *env) 6062 { 6063 /* Handler mode always uses the main stack; for thread mode 6064 * the CONTROL.SPSEL bit determines the answer. 6065 * Note that in v7M it is not possible to be in Handler mode with 6066 * CONTROL.SPSEL non-zero, but in v8M it is, so we must check both. 6067 */ 6068 return !arm_v7m_is_handler_mode(env) && 6069 env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK; 6070 } 6071 6072 /* Switch to V7M main or process stack pointer. */ 6073 static void switch_v7m_sp(CPUARMState *env, bool new_spsel) 6074 { 6075 uint32_t tmp; 6076 uint32_t old_control = env->v7m.control[env->v7m.secure]; 6077 bool old_spsel = old_control & R_V7M_CONTROL_SPSEL_MASK; 6078 6079 if (old_spsel != new_spsel) { 6080 tmp = env->v7m.other_sp; 6081 env->v7m.other_sp = env->regs[13]; 6082 env->regs[13] = tmp; 6083 6084 env->v7m.control[env->v7m.secure] = deposit32(old_control, 6085 R_V7M_CONTROL_SPSEL_SHIFT, 6086 R_V7M_CONTROL_SPSEL_LENGTH, new_spsel); 6087 } 6088 } 6089 6090 /* Switch M profile security state between NS and S */ 6091 static void switch_v7m_security_state(CPUARMState *env, bool new_secstate) 6092 { 6093 uint32_t new_ss_msp, new_ss_psp; 6094 6095 if (env->v7m.secure == new_secstate) { 6096 return; 6097 } 6098 6099 /* All the banked state is accessed by looking at env->v7m.secure 6100 * except for the stack pointer; rearrange the SP appropriately. 6101 */ 6102 new_ss_msp = env->v7m.other_ss_msp; 6103 new_ss_psp = env->v7m.other_ss_psp; 6104 6105 if (v7m_using_psp(env)) { 6106 env->v7m.other_ss_psp = env->regs[13]; 6107 env->v7m.other_ss_msp = env->v7m.other_sp; 6108 } else { 6109 env->v7m.other_ss_msp = env->regs[13]; 6110 env->v7m.other_ss_psp = env->v7m.other_sp; 6111 } 6112 6113 env->v7m.secure = new_secstate; 6114 6115 if (v7m_using_psp(env)) { 6116 env->regs[13] = new_ss_psp; 6117 env->v7m.other_sp = new_ss_msp; 6118 } else { 6119 env->regs[13] = new_ss_msp; 6120 env->v7m.other_sp = new_ss_psp; 6121 } 6122 } 6123 6124 void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest) 6125 { 6126 /* Handle v7M BXNS: 6127 * - if the return value is a magic value, do exception return (like BX) 6128 * - otherwise bit 0 of the return value is the target security state 6129 */ 6130 if (dest >= 0xff000000) { 6131 /* This is an exception return magic value; put it where 6132 * do_v7m_exception_exit() expects and raise EXCEPTION_EXIT. 6133 * Note that if we ever add gen_ss_advance() singlestep support to 6134 * M profile this should count as an "instruction execution complete" 6135 * event (compare gen_bx_excret_final_code()). 6136 */ 6137 env->regs[15] = dest & ~1; 6138 env->thumb = dest & 1; 6139 HELPER(exception_internal)(env, EXCP_EXCEPTION_EXIT); 6140 /* notreached */ 6141 } 6142 6143 /* translate.c should have made BXNS UNDEF unless we're secure */ 6144 assert(env->v7m.secure); 6145 6146 switch_v7m_security_state(env, dest & 1); 6147 env->thumb = 1; 6148 env->regs[15] = dest & ~1; 6149 } 6150 6151 static uint32_t arm_v7m_load_vector(ARMCPU *cpu) 6152 { 6153 CPUState *cs = CPU(cpu); 6154 CPUARMState *env = &cpu->env; 6155 MemTxResult result; 6156 hwaddr vec = env->v7m.vecbase[env->v7m.secure] + env->v7m.exception * 4; 6157 uint32_t addr; 6158 6159 addr = address_space_ldl(cs->as, vec, 6160 MEMTXATTRS_UNSPECIFIED, &result); 6161 if (result != MEMTX_OK) { 6162 /* Architecturally this should cause a HardFault setting HSFR.VECTTBL, 6163 * which would then be immediately followed by our failing to load 6164 * the entry vector for that HardFault, which is a Lockup case. 6165 * Since we don't model Lockup, we just report this guest error 6166 * via cpu_abort(). 6167 */ 6168 cpu_abort(cs, "Failed to read from exception vector table " 6169 "entry %08x\n", (unsigned)vec); 6170 } 6171 return addr; 6172 } 6173 6174 static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr) 6175 { 6176 /* Do the "take the exception" parts of exception entry, 6177 * but not the pushing of state to the stack. This is 6178 * similar to the pseudocode ExceptionTaken() function. 6179 */ 6180 CPUARMState *env = &cpu->env; 6181 uint32_t addr; 6182 6183 armv7m_nvic_acknowledge_irq(env->nvic); 6184 switch_v7m_sp(env, 0); 6185 arm_clear_exclusive(env); 6186 /* Clear IT bits */ 6187 env->condexec_bits = 0; 6188 env->regs[14] = lr; 6189 addr = arm_v7m_load_vector(cpu); 6190 env->regs[15] = addr & 0xfffffffe; 6191 env->thumb = addr & 1; 6192 } 6193 6194 static void v7m_push_stack(ARMCPU *cpu) 6195 { 6196 /* Do the "set up stack frame" part of exception entry, 6197 * similar to pseudocode PushStack(). 6198 */ 6199 CPUARMState *env = &cpu->env; 6200 uint32_t xpsr = xpsr_read(env); 6201 6202 /* Align stack pointer if the guest wants that */ 6203 if ((env->regs[13] & 4) && 6204 (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKALIGN_MASK)) { 6205 env->regs[13] -= 4; 6206 xpsr |= XPSR_SPREALIGN; 6207 } 6208 /* Switch to the handler mode. */ 6209 v7m_push(env, xpsr); 6210 v7m_push(env, env->regs[15]); 6211 v7m_push(env, env->regs[14]); 6212 v7m_push(env, env->regs[12]); 6213 v7m_push(env, env->regs[3]); 6214 v7m_push(env, env->regs[2]); 6215 v7m_push(env, env->regs[1]); 6216 v7m_push(env, env->regs[0]); 6217 } 6218 6219 static void do_v7m_exception_exit(ARMCPU *cpu) 6220 { 6221 CPUARMState *env = &cpu->env; 6222 uint32_t excret; 6223 uint32_t xpsr; 6224 bool ufault = false; 6225 bool return_to_sp_process = false; 6226 bool return_to_handler = false; 6227 bool rettobase = false; 6228 bool exc_secure = false; 6229 6230 /* We can only get here from an EXCP_EXCEPTION_EXIT, and 6231 * gen_bx_excret() enforces the architectural rule 6232 * that jumps to magic addresses don't have magic behaviour unless 6233 * we're in Handler mode (compare pseudocode BXWritePC()). 6234 */ 6235 assert(arm_v7m_is_handler_mode(env)); 6236 6237 /* In the spec pseudocode ExceptionReturn() is called directly 6238 * from BXWritePC() and gets the full target PC value including 6239 * bit zero. In QEMU's implementation we treat it as a normal 6240 * jump-to-register (which is then caught later on), and so split 6241 * the target value up between env->regs[15] and env->thumb in 6242 * gen_bx(). Reconstitute it. 6243 */ 6244 excret = env->regs[15]; 6245 if (env->thumb) { 6246 excret |= 1; 6247 } 6248 6249 qemu_log_mask(CPU_LOG_INT, "Exception return: magic PC %" PRIx32 6250 " previous exception %d\n", 6251 excret, env->v7m.exception); 6252 6253 if ((excret & R_V7M_EXCRET_RES1_MASK) != R_V7M_EXCRET_RES1_MASK) { 6254 qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero high bits in exception " 6255 "exit PC value 0x%" PRIx32 " are UNPREDICTABLE\n", 6256 excret); 6257 } 6258 6259 if (env->v7m.exception != ARMV7M_EXCP_NMI) { 6260 /* Auto-clear FAULTMASK on return from other than NMI. 6261 * If the security extension is implemented then this only 6262 * happens if the raw execution priority is >= 0; the 6263 * value of the ES bit in the exception return value indicates 6264 * which security state's faultmask to clear. (v8M ARM ARM R_KBNF.) 6265 */ 6266 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 6267 exc_secure = excret & R_V7M_EXCRET_ES_MASK; 6268 if (armv7m_nvic_raw_execution_priority(env->nvic) >= 0) { 6269 env->v7m.faultmask[exc_secure] = 0; 6270 } 6271 } else { 6272 env->v7m.faultmask[M_REG_NS] = 0; 6273 } 6274 } 6275 6276 switch (armv7m_nvic_complete_irq(env->nvic, env->v7m.exception, 6277 exc_secure)) { 6278 case -1: 6279 /* attempt to exit an exception that isn't active */ 6280 ufault = true; 6281 break; 6282 case 0: 6283 /* still an irq active now */ 6284 break; 6285 case 1: 6286 /* we returned to base exception level, no nesting. 6287 * (In the pseudocode this is written using "NestedActivation != 1" 6288 * where we have 'rettobase == false'.) 6289 */ 6290 rettobase = true; 6291 break; 6292 default: 6293 g_assert_not_reached(); 6294 } 6295 6296 switch (excret & 0xf) { 6297 case 1: /* Return to Handler */ 6298 return_to_handler = true; 6299 break; 6300 case 13: /* Return to Thread using Process stack */ 6301 return_to_sp_process = true; 6302 /* fall through */ 6303 case 9: /* Return to Thread using Main stack */ 6304 if (!rettobase && 6305 !(env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_NONBASETHRDENA_MASK)) { 6306 ufault = true; 6307 } 6308 break; 6309 default: 6310 ufault = true; 6311 } 6312 6313 if (ufault) { 6314 /* Bad exception return: instead of popping the exception 6315 * stack, directly take a usage fault on the current stack. 6316 */ 6317 env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK; 6318 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure); 6319 v7m_exception_taken(cpu, excret); 6320 qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing " 6321 "stackframe: failed exception return integrity check\n"); 6322 return; 6323 } 6324 6325 /* Switch to the target stack. */ 6326 switch_v7m_sp(env, return_to_sp_process); 6327 /* Pop registers. */ 6328 env->regs[0] = v7m_pop(env); 6329 env->regs[1] = v7m_pop(env); 6330 env->regs[2] = v7m_pop(env); 6331 env->regs[3] = v7m_pop(env); 6332 env->regs[12] = v7m_pop(env); 6333 env->regs[14] = v7m_pop(env); 6334 env->regs[15] = v7m_pop(env); 6335 if (env->regs[15] & 1) { 6336 qemu_log_mask(LOG_GUEST_ERROR, 6337 "M profile return from interrupt with misaligned " 6338 "PC is UNPREDICTABLE\n"); 6339 /* Actual hardware seems to ignore the lsbit, and there are several 6340 * RTOSes out there which incorrectly assume the r15 in the stack 6341 * frame should be a Thumb-style "lsbit indicates ARM/Thumb" value. 6342 */ 6343 env->regs[15] &= ~1U; 6344 } 6345 xpsr = v7m_pop(env); 6346 xpsr_write(env, xpsr, ~XPSR_SPREALIGN); 6347 /* Undo stack alignment. */ 6348 if (xpsr & XPSR_SPREALIGN) { 6349 env->regs[13] |= 4; 6350 } 6351 6352 /* The restored xPSR exception field will be zero if we're 6353 * resuming in Thread mode. If that doesn't match what the 6354 * exception return excret specified then this is a UsageFault. 6355 */ 6356 if (return_to_handler != arm_v7m_is_handler_mode(env)) { 6357 /* Take an INVPC UsageFault by pushing the stack again. 6358 * TODO: the v8M version of this code should target the 6359 * background state for this exception. 6360 */ 6361 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, false); 6362 env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK; 6363 v7m_push_stack(cpu); 6364 v7m_exception_taken(cpu, excret); 6365 qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on new stackframe: " 6366 "failed exception return integrity check\n"); 6367 return; 6368 } 6369 6370 /* Otherwise, we have a successful exception exit. */ 6371 arm_clear_exclusive(env); 6372 qemu_log_mask(CPU_LOG_INT, "...successful exception return\n"); 6373 } 6374 6375 static void arm_log_exception(int idx) 6376 { 6377 if (qemu_loglevel_mask(CPU_LOG_INT)) { 6378 const char *exc = NULL; 6379 static const char * const excnames[] = { 6380 [EXCP_UDEF] = "Undefined Instruction", 6381 [EXCP_SWI] = "SVC", 6382 [EXCP_PREFETCH_ABORT] = "Prefetch Abort", 6383 [EXCP_DATA_ABORT] = "Data Abort", 6384 [EXCP_IRQ] = "IRQ", 6385 [EXCP_FIQ] = "FIQ", 6386 [EXCP_BKPT] = "Breakpoint", 6387 [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit", 6388 [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage", 6389 [EXCP_HVC] = "Hypervisor Call", 6390 [EXCP_HYP_TRAP] = "Hypervisor Trap", 6391 [EXCP_SMC] = "Secure Monitor Call", 6392 [EXCP_VIRQ] = "Virtual IRQ", 6393 [EXCP_VFIQ] = "Virtual FIQ", 6394 [EXCP_SEMIHOST] = "Semihosting call", 6395 [EXCP_NOCP] = "v7M NOCP UsageFault", 6396 [EXCP_INVSTATE] = "v7M INVSTATE UsageFault", 6397 }; 6398 6399 if (idx >= 0 && idx < ARRAY_SIZE(excnames)) { 6400 exc = excnames[idx]; 6401 } 6402 if (!exc) { 6403 exc = "unknown"; 6404 } 6405 qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc); 6406 } 6407 } 6408 6409 void arm_v7m_cpu_do_interrupt(CPUState *cs) 6410 { 6411 ARMCPU *cpu = ARM_CPU(cs); 6412 CPUARMState *env = &cpu->env; 6413 uint32_t lr; 6414 6415 arm_log_exception(cs->exception_index); 6416 6417 /* For exceptions we just mark as pending on the NVIC, and let that 6418 handle it. */ 6419 switch (cs->exception_index) { 6420 case EXCP_UDEF: 6421 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure); 6422 env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_UNDEFINSTR_MASK; 6423 break; 6424 case EXCP_NOCP: 6425 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure); 6426 env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_NOCP_MASK; 6427 break; 6428 case EXCP_INVSTATE: 6429 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure); 6430 env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVSTATE_MASK; 6431 break; 6432 case EXCP_SWI: 6433 /* The PC already points to the next instruction. */ 6434 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC, env->v7m.secure); 6435 break; 6436 case EXCP_PREFETCH_ABORT: 6437 case EXCP_DATA_ABORT: 6438 /* Note that for M profile we don't have a guest facing FSR, but 6439 * the env->exception.fsr will be populated by the code that 6440 * raises the fault, in the A profile short-descriptor format. 6441 */ 6442 switch (env->exception.fsr & 0xf) { 6443 case 0x8: /* External Abort */ 6444 switch (cs->exception_index) { 6445 case EXCP_PREFETCH_ABORT: 6446 env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_IBUSERR_MASK; 6447 qemu_log_mask(CPU_LOG_INT, "...with CFSR.IBUSERR\n"); 6448 break; 6449 case EXCP_DATA_ABORT: 6450 env->v7m.cfsr[M_REG_NS] |= 6451 (R_V7M_CFSR_PRECISERR_MASK | R_V7M_CFSR_BFARVALID_MASK); 6452 env->v7m.bfar = env->exception.vaddress; 6453 qemu_log_mask(CPU_LOG_INT, 6454 "...with CFSR.PRECISERR and BFAR 0x%x\n", 6455 env->v7m.bfar); 6456 break; 6457 } 6458 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false); 6459 break; 6460 default: 6461 /* All other FSR values are either MPU faults or "can't happen 6462 * for M profile" cases. 6463 */ 6464 switch (cs->exception_index) { 6465 case EXCP_PREFETCH_ABORT: 6466 env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_IACCVIOL_MASK; 6467 qemu_log_mask(CPU_LOG_INT, "...with CFSR.IACCVIOL\n"); 6468 break; 6469 case EXCP_DATA_ABORT: 6470 env->v7m.cfsr[env->v7m.secure] |= 6471 (R_V7M_CFSR_DACCVIOL_MASK | R_V7M_CFSR_MMARVALID_MASK); 6472 env->v7m.mmfar[env->v7m.secure] = env->exception.vaddress; 6473 qemu_log_mask(CPU_LOG_INT, 6474 "...with CFSR.DACCVIOL and MMFAR 0x%x\n", 6475 env->v7m.mmfar[env->v7m.secure]); 6476 break; 6477 } 6478 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM, 6479 env->v7m.secure); 6480 break; 6481 } 6482 break; 6483 case EXCP_BKPT: 6484 if (semihosting_enabled()) { 6485 int nr; 6486 nr = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env)) & 0xff; 6487 if (nr == 0xab) { 6488 env->regs[15] += 2; 6489 qemu_log_mask(CPU_LOG_INT, 6490 "...handling as semihosting call 0x%x\n", 6491 env->regs[0]); 6492 env->regs[0] = do_arm_semihosting(env); 6493 return; 6494 } 6495 } 6496 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG, false); 6497 break; 6498 case EXCP_IRQ: 6499 break; 6500 case EXCP_EXCEPTION_EXIT: 6501 do_v7m_exception_exit(cpu); 6502 return; 6503 default: 6504 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); 6505 return; /* Never happens. Keep compiler happy. */ 6506 } 6507 6508 lr = R_V7M_EXCRET_RES1_MASK | 6509 R_V7M_EXCRET_S_MASK | 6510 R_V7M_EXCRET_DCRS_MASK | 6511 R_V7M_EXCRET_FTYPE_MASK | 6512 R_V7M_EXCRET_ES_MASK; 6513 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) { 6514 lr |= R_V7M_EXCRET_SPSEL_MASK; 6515 } 6516 if (!arm_v7m_is_handler_mode(env)) { 6517 lr |= R_V7M_EXCRET_MODE_MASK; 6518 } 6519 6520 v7m_push_stack(cpu); 6521 v7m_exception_taken(cpu, lr); 6522 qemu_log_mask(CPU_LOG_INT, "... as %d\n", env->v7m.exception); 6523 } 6524 6525 /* Function used to synchronize QEMU's AArch64 register set with AArch32 6526 * register set. This is necessary when switching between AArch32 and AArch64 6527 * execution state. 6528 */ 6529 void aarch64_sync_32_to_64(CPUARMState *env) 6530 { 6531 int i; 6532 uint32_t mode = env->uncached_cpsr & CPSR_M; 6533 6534 /* We can blanket copy R[0:7] to X[0:7] */ 6535 for (i = 0; i < 8; i++) { 6536 env->xregs[i] = env->regs[i]; 6537 } 6538 6539 /* Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12. 6540 * Otherwise, they come from the banked user regs. 6541 */ 6542 if (mode == ARM_CPU_MODE_FIQ) { 6543 for (i = 8; i < 13; i++) { 6544 env->xregs[i] = env->usr_regs[i - 8]; 6545 } 6546 } else { 6547 for (i = 8; i < 13; i++) { 6548 env->xregs[i] = env->regs[i]; 6549 } 6550 } 6551 6552 /* Registers x13-x23 are the various mode SP and FP registers. Registers 6553 * r13 and r14 are only copied if we are in that mode, otherwise we copy 6554 * from the mode banked register. 6555 */ 6556 if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) { 6557 env->xregs[13] = env->regs[13]; 6558 env->xregs[14] = env->regs[14]; 6559 } else { 6560 env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)]; 6561 /* HYP is an exception in that it is copied from r14 */ 6562 if (mode == ARM_CPU_MODE_HYP) { 6563 env->xregs[14] = env->regs[14]; 6564 } else { 6565 env->xregs[14] = env->banked_r14[bank_number(ARM_CPU_MODE_USR)]; 6566 } 6567 } 6568 6569 if (mode == ARM_CPU_MODE_HYP) { 6570 env->xregs[15] = env->regs[13]; 6571 } else { 6572 env->xregs[15] = env->banked_r13[bank_number(ARM_CPU_MODE_HYP)]; 6573 } 6574 6575 if (mode == ARM_CPU_MODE_IRQ) { 6576 env->xregs[16] = env->regs[14]; 6577 env->xregs[17] = env->regs[13]; 6578 } else { 6579 env->xregs[16] = env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)]; 6580 env->xregs[17] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)]; 6581 } 6582 6583 if (mode == ARM_CPU_MODE_SVC) { 6584 env->xregs[18] = env->regs[14]; 6585 env->xregs[19] = env->regs[13]; 6586 } else { 6587 env->xregs[18] = env->banked_r14[bank_number(ARM_CPU_MODE_SVC)]; 6588 env->xregs[19] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)]; 6589 } 6590 6591 if (mode == ARM_CPU_MODE_ABT) { 6592 env->xregs[20] = env->regs[14]; 6593 env->xregs[21] = env->regs[13]; 6594 } else { 6595 env->xregs[20] = env->banked_r14[bank_number(ARM_CPU_MODE_ABT)]; 6596 env->xregs[21] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)]; 6597 } 6598 6599 if (mode == ARM_CPU_MODE_UND) { 6600 env->xregs[22] = env->regs[14]; 6601 env->xregs[23] = env->regs[13]; 6602 } else { 6603 env->xregs[22] = env->banked_r14[bank_number(ARM_CPU_MODE_UND)]; 6604 env->xregs[23] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)]; 6605 } 6606 6607 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ 6608 * mode, then we can copy from r8-r14. Otherwise, we copy from the 6609 * FIQ bank for r8-r14. 6610 */ 6611 if (mode == ARM_CPU_MODE_FIQ) { 6612 for (i = 24; i < 31; i++) { 6613 env->xregs[i] = env->regs[i - 16]; /* X[24:30] <- R[8:14] */ 6614 } 6615 } else { 6616 for (i = 24; i < 29; i++) { 6617 env->xregs[i] = env->fiq_regs[i - 24]; 6618 } 6619 env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)]; 6620 env->xregs[30] = env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)]; 6621 } 6622 6623 env->pc = env->regs[15]; 6624 } 6625 6626 /* Function used to synchronize QEMU's AArch32 register set with AArch64 6627 * register set. This is necessary when switching between AArch32 and AArch64 6628 * execution state. 6629 */ 6630 void aarch64_sync_64_to_32(CPUARMState *env) 6631 { 6632 int i; 6633 uint32_t mode = env->uncached_cpsr & CPSR_M; 6634 6635 /* We can blanket copy X[0:7] to R[0:7] */ 6636 for (i = 0; i < 8; i++) { 6637 env->regs[i] = env->xregs[i]; 6638 } 6639 6640 /* Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12. 6641 * Otherwise, we copy x8-x12 into the banked user regs. 6642 */ 6643 if (mode == ARM_CPU_MODE_FIQ) { 6644 for (i = 8; i < 13; i++) { 6645 env->usr_regs[i - 8] = env->xregs[i]; 6646 } 6647 } else { 6648 for (i = 8; i < 13; i++) { 6649 env->regs[i] = env->xregs[i]; 6650 } 6651 } 6652 6653 /* Registers r13 & r14 depend on the current mode. 6654 * If we are in a given mode, we copy the corresponding x registers to r13 6655 * and r14. Otherwise, we copy the x register to the banked r13 and r14 6656 * for the mode. 6657 */ 6658 if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) { 6659 env->regs[13] = env->xregs[13]; 6660 env->regs[14] = env->xregs[14]; 6661 } else { 6662 env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13]; 6663 6664 /* HYP is an exception in that it does not have its own banked r14 but 6665 * shares the USR r14 6666 */ 6667 if (mode == ARM_CPU_MODE_HYP) { 6668 env->regs[14] = env->xregs[14]; 6669 } else { 6670 env->banked_r14[bank_number(ARM_CPU_MODE_USR)] = env->xregs[14]; 6671 } 6672 } 6673 6674 if (mode == ARM_CPU_MODE_HYP) { 6675 env->regs[13] = env->xregs[15]; 6676 } else { 6677 env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] = env->xregs[15]; 6678 } 6679 6680 if (mode == ARM_CPU_MODE_IRQ) { 6681 env->regs[14] = env->xregs[16]; 6682 env->regs[13] = env->xregs[17]; 6683 } else { 6684 env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16]; 6685 env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17]; 6686 } 6687 6688 if (mode == ARM_CPU_MODE_SVC) { 6689 env->regs[14] = env->xregs[18]; 6690 env->regs[13] = env->xregs[19]; 6691 } else { 6692 env->banked_r14[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18]; 6693 env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19]; 6694 } 6695 6696 if (mode == ARM_CPU_MODE_ABT) { 6697 env->regs[14] = env->xregs[20]; 6698 env->regs[13] = env->xregs[21]; 6699 } else { 6700 env->banked_r14[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20]; 6701 env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21]; 6702 } 6703 6704 if (mode == ARM_CPU_MODE_UND) { 6705 env->regs[14] = env->xregs[22]; 6706 env->regs[13] = env->xregs[23]; 6707 } else { 6708 env->banked_r14[bank_number(ARM_CPU_MODE_UND)] = env->xregs[22]; 6709 env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23]; 6710 } 6711 6712 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ 6713 * mode, then we can copy to r8-r14. Otherwise, we copy to the 6714 * FIQ bank for r8-r14. 6715 */ 6716 if (mode == ARM_CPU_MODE_FIQ) { 6717 for (i = 24; i < 31; i++) { 6718 env->regs[i - 16] = env->xregs[i]; /* X[24:30] -> R[8:14] */ 6719 } 6720 } else { 6721 for (i = 24; i < 29; i++) { 6722 env->fiq_regs[i - 24] = env->xregs[i]; 6723 } 6724 env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29]; 6725 env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30]; 6726 } 6727 6728 env->regs[15] = env->pc; 6729 } 6730 6731 static void arm_cpu_do_interrupt_aarch32(CPUState *cs) 6732 { 6733 ARMCPU *cpu = ARM_CPU(cs); 6734 CPUARMState *env = &cpu->env; 6735 uint32_t addr; 6736 uint32_t mask; 6737 int new_mode; 6738 uint32_t offset; 6739 uint32_t moe; 6740 6741 /* If this is a debug exception we must update the DBGDSCR.MOE bits */ 6742 switch (env->exception.syndrome >> ARM_EL_EC_SHIFT) { 6743 case EC_BREAKPOINT: 6744 case EC_BREAKPOINT_SAME_EL: 6745 moe = 1; 6746 break; 6747 case EC_WATCHPOINT: 6748 case EC_WATCHPOINT_SAME_EL: 6749 moe = 10; 6750 break; 6751 case EC_AA32_BKPT: 6752 moe = 3; 6753 break; 6754 case EC_VECTORCATCH: 6755 moe = 5; 6756 break; 6757 default: 6758 moe = 0; 6759 break; 6760 } 6761 6762 if (moe) { 6763 env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe); 6764 } 6765 6766 /* TODO: Vectored interrupt controller. */ 6767 switch (cs->exception_index) { 6768 case EXCP_UDEF: 6769 new_mode = ARM_CPU_MODE_UND; 6770 addr = 0x04; 6771 mask = CPSR_I; 6772 if (env->thumb) 6773 offset = 2; 6774 else 6775 offset = 4; 6776 break; 6777 case EXCP_SWI: 6778 new_mode = ARM_CPU_MODE_SVC; 6779 addr = 0x08; 6780 mask = CPSR_I; 6781 /* The PC already points to the next instruction. */ 6782 offset = 0; 6783 break; 6784 case EXCP_BKPT: 6785 env->exception.fsr = 2; 6786 /* Fall through to prefetch abort. */ 6787 case EXCP_PREFETCH_ABORT: 6788 A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr); 6789 A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress); 6790 qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n", 6791 env->exception.fsr, (uint32_t)env->exception.vaddress); 6792 new_mode = ARM_CPU_MODE_ABT; 6793 addr = 0x0c; 6794 mask = CPSR_A | CPSR_I; 6795 offset = 4; 6796 break; 6797 case EXCP_DATA_ABORT: 6798 A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); 6799 A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress); 6800 qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n", 6801 env->exception.fsr, 6802 (uint32_t)env->exception.vaddress); 6803 new_mode = ARM_CPU_MODE_ABT; 6804 addr = 0x10; 6805 mask = CPSR_A | CPSR_I; 6806 offset = 8; 6807 break; 6808 case EXCP_IRQ: 6809 new_mode = ARM_CPU_MODE_IRQ; 6810 addr = 0x18; 6811 /* Disable IRQ and imprecise data aborts. */ 6812 mask = CPSR_A | CPSR_I; 6813 offset = 4; 6814 if (env->cp15.scr_el3 & SCR_IRQ) { 6815 /* IRQ routed to monitor mode */ 6816 new_mode = ARM_CPU_MODE_MON; 6817 mask |= CPSR_F; 6818 } 6819 break; 6820 case EXCP_FIQ: 6821 new_mode = ARM_CPU_MODE_FIQ; 6822 addr = 0x1c; 6823 /* Disable FIQ, IRQ and imprecise data aborts. */ 6824 mask = CPSR_A | CPSR_I | CPSR_F; 6825 if (env->cp15.scr_el3 & SCR_FIQ) { 6826 /* FIQ routed to monitor mode */ 6827 new_mode = ARM_CPU_MODE_MON; 6828 } 6829 offset = 4; 6830 break; 6831 case EXCP_VIRQ: 6832 new_mode = ARM_CPU_MODE_IRQ; 6833 addr = 0x18; 6834 /* Disable IRQ and imprecise data aborts. */ 6835 mask = CPSR_A | CPSR_I; 6836 offset = 4; 6837 break; 6838 case EXCP_VFIQ: 6839 new_mode = ARM_CPU_MODE_FIQ; 6840 addr = 0x1c; 6841 /* Disable FIQ, IRQ and imprecise data aborts. */ 6842 mask = CPSR_A | CPSR_I | CPSR_F; 6843 offset = 4; 6844 break; 6845 case EXCP_SMC: 6846 new_mode = ARM_CPU_MODE_MON; 6847 addr = 0x08; 6848 mask = CPSR_A | CPSR_I | CPSR_F; 6849 offset = 0; 6850 break; 6851 default: 6852 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); 6853 return; /* Never happens. Keep compiler happy. */ 6854 } 6855 6856 if (new_mode == ARM_CPU_MODE_MON) { 6857 addr += env->cp15.mvbar; 6858 } else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 6859 /* High vectors. When enabled, base address cannot be remapped. */ 6860 addr += 0xffff0000; 6861 } else { 6862 /* ARM v7 architectures provide a vector base address register to remap 6863 * the interrupt vector table. 6864 * This register is only followed in non-monitor mode, and is banked. 6865 * Note: only bits 31:5 are valid. 6866 */ 6867 addr += A32_BANKED_CURRENT_REG_GET(env, vbar); 6868 } 6869 6870 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 6871 env->cp15.scr_el3 &= ~SCR_NS; 6872 } 6873 6874 switch_mode (env, new_mode); 6875 /* For exceptions taken to AArch32 we must clear the SS bit in both 6876 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now. 6877 */ 6878 env->uncached_cpsr &= ~PSTATE_SS; 6879 env->spsr = cpsr_read(env); 6880 /* Clear IT bits. */ 6881 env->condexec_bits = 0; 6882 /* Switch to the new mode, and to the correct instruction set. */ 6883 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; 6884 /* Set new mode endianness */ 6885 env->uncached_cpsr &= ~CPSR_E; 6886 if (env->cp15.sctlr_el[arm_current_el(env)] & SCTLR_EE) { 6887 env->uncached_cpsr |= CPSR_E; 6888 } 6889 env->daif |= mask; 6890 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares 6891 * and we should just guard the thumb mode on V4 */ 6892 if (arm_feature(env, ARM_FEATURE_V4T)) { 6893 env->thumb = (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) != 0; 6894 } 6895 env->regs[14] = env->regs[15] + offset; 6896 env->regs[15] = addr; 6897 } 6898 6899 /* Handle exception entry to a target EL which is using AArch64 */ 6900 static void arm_cpu_do_interrupt_aarch64(CPUState *cs) 6901 { 6902 ARMCPU *cpu = ARM_CPU(cs); 6903 CPUARMState *env = &cpu->env; 6904 unsigned int new_el = env->exception.target_el; 6905 target_ulong addr = env->cp15.vbar_el[new_el]; 6906 unsigned int new_mode = aarch64_pstate_mode(new_el, true); 6907 6908 if (arm_current_el(env) < new_el) { 6909 /* Entry vector offset depends on whether the implemented EL 6910 * immediately lower than the target level is using AArch32 or AArch64 6911 */ 6912 bool is_aa64; 6913 6914 switch (new_el) { 6915 case 3: 6916 is_aa64 = (env->cp15.scr_el3 & SCR_RW) != 0; 6917 break; 6918 case 2: 6919 is_aa64 = (env->cp15.hcr_el2 & HCR_RW) != 0; 6920 break; 6921 case 1: 6922 is_aa64 = is_a64(env); 6923 break; 6924 default: 6925 g_assert_not_reached(); 6926 } 6927 6928 if (is_aa64) { 6929 addr += 0x400; 6930 } else { 6931 addr += 0x600; 6932 } 6933 } else if (pstate_read(env) & PSTATE_SP) { 6934 addr += 0x200; 6935 } 6936 6937 switch (cs->exception_index) { 6938 case EXCP_PREFETCH_ABORT: 6939 case EXCP_DATA_ABORT: 6940 env->cp15.far_el[new_el] = env->exception.vaddress; 6941 qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n", 6942 env->cp15.far_el[new_el]); 6943 /* fall through */ 6944 case EXCP_BKPT: 6945 case EXCP_UDEF: 6946 case EXCP_SWI: 6947 case EXCP_HVC: 6948 case EXCP_HYP_TRAP: 6949 case EXCP_SMC: 6950 env->cp15.esr_el[new_el] = env->exception.syndrome; 6951 break; 6952 case EXCP_IRQ: 6953 case EXCP_VIRQ: 6954 addr += 0x80; 6955 break; 6956 case EXCP_FIQ: 6957 case EXCP_VFIQ: 6958 addr += 0x100; 6959 break; 6960 case EXCP_SEMIHOST: 6961 qemu_log_mask(CPU_LOG_INT, 6962 "...handling as semihosting call 0x%" PRIx64 "\n", 6963 env->xregs[0]); 6964 env->xregs[0] = do_arm_semihosting(env); 6965 return; 6966 default: 6967 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); 6968 } 6969 6970 if (is_a64(env)) { 6971 env->banked_spsr[aarch64_banked_spsr_index(new_el)] = pstate_read(env); 6972 aarch64_save_sp(env, arm_current_el(env)); 6973 env->elr_el[new_el] = env->pc; 6974 } else { 6975 env->banked_spsr[aarch64_banked_spsr_index(new_el)] = cpsr_read(env); 6976 env->elr_el[new_el] = env->regs[15]; 6977 6978 aarch64_sync_32_to_64(env); 6979 6980 env->condexec_bits = 0; 6981 } 6982 qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n", 6983 env->elr_el[new_el]); 6984 6985 pstate_write(env, PSTATE_DAIF | new_mode); 6986 env->aarch64 = 1; 6987 aarch64_restore_sp(env, new_el); 6988 6989 env->pc = addr; 6990 6991 qemu_log_mask(CPU_LOG_INT, "...to EL%d PC 0x%" PRIx64 " PSTATE 0x%x\n", 6992 new_el, env->pc, pstate_read(env)); 6993 } 6994 6995 static inline bool check_for_semihosting(CPUState *cs) 6996 { 6997 /* Check whether this exception is a semihosting call; if so 6998 * then handle it and return true; otherwise return false. 6999 */ 7000 ARMCPU *cpu = ARM_CPU(cs); 7001 CPUARMState *env = &cpu->env; 7002 7003 if (is_a64(env)) { 7004 if (cs->exception_index == EXCP_SEMIHOST) { 7005 /* This is always the 64-bit semihosting exception. 7006 * The "is this usermode" and "is semihosting enabled" 7007 * checks have been done at translate time. 7008 */ 7009 qemu_log_mask(CPU_LOG_INT, 7010 "...handling as semihosting call 0x%" PRIx64 "\n", 7011 env->xregs[0]); 7012 env->xregs[0] = do_arm_semihosting(env); 7013 return true; 7014 } 7015 return false; 7016 } else { 7017 uint32_t imm; 7018 7019 /* Only intercept calls from privileged modes, to provide some 7020 * semblance of security. 7021 */ 7022 if (cs->exception_index != EXCP_SEMIHOST && 7023 (!semihosting_enabled() || 7024 ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR))) { 7025 return false; 7026 } 7027 7028 switch (cs->exception_index) { 7029 case EXCP_SEMIHOST: 7030 /* This is always a semihosting call; the "is this usermode" 7031 * and "is semihosting enabled" checks have been done at 7032 * translate time. 7033 */ 7034 break; 7035 case EXCP_SWI: 7036 /* Check for semihosting interrupt. */ 7037 if (env->thumb) { 7038 imm = arm_lduw_code(env, env->regs[15] - 2, arm_sctlr_b(env)) 7039 & 0xff; 7040 if (imm == 0xab) { 7041 break; 7042 } 7043 } else { 7044 imm = arm_ldl_code(env, env->regs[15] - 4, arm_sctlr_b(env)) 7045 & 0xffffff; 7046 if (imm == 0x123456) { 7047 break; 7048 } 7049 } 7050 return false; 7051 case EXCP_BKPT: 7052 /* See if this is a semihosting syscall. */ 7053 if (env->thumb) { 7054 imm = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env)) 7055 & 0xff; 7056 if (imm == 0xab) { 7057 env->regs[15] += 2; 7058 break; 7059 } 7060 } 7061 return false; 7062 default: 7063 return false; 7064 } 7065 7066 qemu_log_mask(CPU_LOG_INT, 7067 "...handling as semihosting call 0x%x\n", 7068 env->regs[0]); 7069 env->regs[0] = do_arm_semihosting(env); 7070 return true; 7071 } 7072 } 7073 7074 /* Handle a CPU exception for A and R profile CPUs. 7075 * Do any appropriate logging, handle PSCI calls, and then hand off 7076 * to the AArch64-entry or AArch32-entry function depending on the 7077 * target exception level's register width. 7078 */ 7079 void arm_cpu_do_interrupt(CPUState *cs) 7080 { 7081 ARMCPU *cpu = ARM_CPU(cs); 7082 CPUARMState *env = &cpu->env; 7083 unsigned int new_el = env->exception.target_el; 7084 7085 assert(!arm_feature(env, ARM_FEATURE_M)); 7086 7087 arm_log_exception(cs->exception_index); 7088 qemu_log_mask(CPU_LOG_INT, "...from EL%d to EL%d\n", arm_current_el(env), 7089 new_el); 7090 if (qemu_loglevel_mask(CPU_LOG_INT) 7091 && !excp_is_internal(cs->exception_index)) { 7092 qemu_log_mask(CPU_LOG_INT, "...with ESR 0x%x/0x%" PRIx32 "\n", 7093 env->exception.syndrome >> ARM_EL_EC_SHIFT, 7094 env->exception.syndrome); 7095 } 7096 7097 if (arm_is_psci_call(cpu, cs->exception_index)) { 7098 arm_handle_psci_call(cpu); 7099 qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n"); 7100 return; 7101 } 7102 7103 /* Semihosting semantics depend on the register width of the 7104 * code that caused the exception, not the target exception level, 7105 * so must be handled here. 7106 */ 7107 if (check_for_semihosting(cs)) { 7108 return; 7109 } 7110 7111 assert(!excp_is_internal(cs->exception_index)); 7112 if (arm_el_is_aa64(env, new_el)) { 7113 arm_cpu_do_interrupt_aarch64(cs); 7114 } else { 7115 arm_cpu_do_interrupt_aarch32(cs); 7116 } 7117 7118 /* Hooks may change global state so BQL should be held, also the 7119 * BQL needs to be held for any modification of 7120 * cs->interrupt_request. 7121 */ 7122 g_assert(qemu_mutex_iothread_locked()); 7123 7124 arm_call_el_change_hook(cpu); 7125 7126 if (!kvm_enabled()) { 7127 cs->interrupt_request |= CPU_INTERRUPT_EXITTB; 7128 } 7129 } 7130 7131 /* Return the exception level which controls this address translation regime */ 7132 static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) 7133 { 7134 switch (mmu_idx) { 7135 case ARMMMUIdx_S2NS: 7136 case ARMMMUIdx_S1E2: 7137 return 2; 7138 case ARMMMUIdx_S1E3: 7139 return 3; 7140 case ARMMMUIdx_S1SE0: 7141 return arm_el_is_aa64(env, 3) ? 1 : 3; 7142 case ARMMMUIdx_S1SE1: 7143 case ARMMMUIdx_S1NSE0: 7144 case ARMMMUIdx_S1NSE1: 7145 case ARMMMUIdx_MPriv: 7146 case ARMMMUIdx_MNegPri: 7147 case ARMMMUIdx_MUser: 7148 case ARMMMUIdx_MSPriv: 7149 case ARMMMUIdx_MSNegPri: 7150 case ARMMMUIdx_MSUser: 7151 return 1; 7152 default: 7153 g_assert_not_reached(); 7154 } 7155 } 7156 7157 /* Return the SCTLR value which controls this address translation regime */ 7158 static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) 7159 { 7160 return env->cp15.sctlr_el[regime_el(env, mmu_idx)]; 7161 } 7162 7163 /* Return true if the specified stage of address translation is disabled */ 7164 static inline bool regime_translation_disabled(CPUARMState *env, 7165 ARMMMUIdx mmu_idx) 7166 { 7167 if (arm_feature(env, ARM_FEATURE_M)) { 7168 switch (env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] & 7169 (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK)) { 7170 case R_V7M_MPU_CTRL_ENABLE_MASK: 7171 /* Enabled, but not for HardFault and NMI */ 7172 return mmu_idx == ARMMMUIdx_MNegPri || 7173 mmu_idx == ARMMMUIdx_MSNegPri; 7174 case R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK: 7175 /* Enabled for all cases */ 7176 return false; 7177 case 0: 7178 default: 7179 /* HFNMIENA set and ENABLE clear is UNPREDICTABLE, but 7180 * we warned about that in armv7m_nvic.c when the guest set it. 7181 */ 7182 return true; 7183 } 7184 } 7185 7186 if (mmu_idx == ARMMMUIdx_S2NS) { 7187 return (env->cp15.hcr_el2 & HCR_VM) == 0; 7188 } 7189 return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0; 7190 } 7191 7192 static inline bool regime_translation_big_endian(CPUARMState *env, 7193 ARMMMUIdx mmu_idx) 7194 { 7195 return (regime_sctlr(env, mmu_idx) & SCTLR_EE) != 0; 7196 } 7197 7198 /* Return the TCR controlling this translation regime */ 7199 static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) 7200 { 7201 if (mmu_idx == ARMMMUIdx_S2NS) { 7202 return &env->cp15.vtcr_el2; 7203 } 7204 return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; 7205 } 7206 7207 /* Convert a possible stage1+2 MMU index into the appropriate 7208 * stage 1 MMU index 7209 */ 7210 static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) 7211 { 7212 if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { 7213 mmu_idx += (ARMMMUIdx_S1NSE0 - ARMMMUIdx_S12NSE0); 7214 } 7215 return mmu_idx; 7216 } 7217 7218 /* Returns TBI0 value for current regime el */ 7219 uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx) 7220 { 7221 TCR *tcr; 7222 uint32_t el; 7223 7224 /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert 7225 * a stage 1+2 mmu index into the appropriate stage 1 mmu index. 7226 */ 7227 mmu_idx = stage_1_mmu_idx(mmu_idx); 7228 7229 tcr = regime_tcr(env, mmu_idx); 7230 el = regime_el(env, mmu_idx); 7231 7232 if (el > 1) { 7233 return extract64(tcr->raw_tcr, 20, 1); 7234 } else { 7235 return extract64(tcr->raw_tcr, 37, 1); 7236 } 7237 } 7238 7239 /* Returns TBI1 value for current regime el */ 7240 uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx) 7241 { 7242 TCR *tcr; 7243 uint32_t el; 7244 7245 /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert 7246 * a stage 1+2 mmu index into the appropriate stage 1 mmu index. 7247 */ 7248 mmu_idx = stage_1_mmu_idx(mmu_idx); 7249 7250 tcr = regime_tcr(env, mmu_idx); 7251 el = regime_el(env, mmu_idx); 7252 7253 if (el > 1) { 7254 return 0; 7255 } else { 7256 return extract64(tcr->raw_tcr, 38, 1); 7257 } 7258 } 7259 7260 /* Return the TTBR associated with this translation regime */ 7261 static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, 7262 int ttbrn) 7263 { 7264 if (mmu_idx == ARMMMUIdx_S2NS) { 7265 return env->cp15.vttbr_el2; 7266 } 7267 if (ttbrn == 0) { 7268 return env->cp15.ttbr0_el[regime_el(env, mmu_idx)]; 7269 } else { 7270 return env->cp15.ttbr1_el[regime_el(env, mmu_idx)]; 7271 } 7272 } 7273 7274 /* Return true if the translation regime is using LPAE format page tables */ 7275 static inline bool regime_using_lpae_format(CPUARMState *env, 7276 ARMMMUIdx mmu_idx) 7277 { 7278 int el = regime_el(env, mmu_idx); 7279 if (el == 2 || arm_el_is_aa64(env, el)) { 7280 return true; 7281 } 7282 if (arm_feature(env, ARM_FEATURE_LPAE) 7283 && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) { 7284 return true; 7285 } 7286 return false; 7287 } 7288 7289 /* Returns true if the stage 1 translation regime is using LPAE format page 7290 * tables. Used when raising alignment exceptions, whose FSR changes depending 7291 * on whether the long or short descriptor format is in use. */ 7292 bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) 7293 { 7294 mmu_idx = stage_1_mmu_idx(mmu_idx); 7295 7296 return regime_using_lpae_format(env, mmu_idx); 7297 } 7298 7299 static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) 7300 { 7301 switch (mmu_idx) { 7302 case ARMMMUIdx_S1SE0: 7303 case ARMMMUIdx_S1NSE0: 7304 case ARMMMUIdx_MUser: 7305 return true; 7306 default: 7307 return false; 7308 case ARMMMUIdx_S12NSE0: 7309 case ARMMMUIdx_S12NSE1: 7310 g_assert_not_reached(); 7311 } 7312 } 7313 7314 /* Translate section/page access permissions to page 7315 * R/W protection flags 7316 * 7317 * @env: CPUARMState 7318 * @mmu_idx: MMU index indicating required translation regime 7319 * @ap: The 3-bit access permissions (AP[2:0]) 7320 * @domain_prot: The 2-bit domain access permissions 7321 */ 7322 static inline int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, 7323 int ap, int domain_prot) 7324 { 7325 bool is_user = regime_is_user(env, mmu_idx); 7326 7327 if (domain_prot == 3) { 7328 return PAGE_READ | PAGE_WRITE; 7329 } 7330 7331 switch (ap) { 7332 case 0: 7333 if (arm_feature(env, ARM_FEATURE_V7)) { 7334 return 0; 7335 } 7336 switch (regime_sctlr(env, mmu_idx) & (SCTLR_S | SCTLR_R)) { 7337 case SCTLR_S: 7338 return is_user ? 0 : PAGE_READ; 7339 case SCTLR_R: 7340 return PAGE_READ; 7341 default: 7342 return 0; 7343 } 7344 case 1: 7345 return is_user ? 0 : PAGE_READ | PAGE_WRITE; 7346 case 2: 7347 if (is_user) { 7348 return PAGE_READ; 7349 } else { 7350 return PAGE_READ | PAGE_WRITE; 7351 } 7352 case 3: 7353 return PAGE_READ | PAGE_WRITE; 7354 case 4: /* Reserved. */ 7355 return 0; 7356 case 5: 7357 return is_user ? 0 : PAGE_READ; 7358 case 6: 7359 return PAGE_READ; 7360 case 7: 7361 if (!arm_feature(env, ARM_FEATURE_V6K)) { 7362 return 0; 7363 } 7364 return PAGE_READ; 7365 default: 7366 g_assert_not_reached(); 7367 } 7368 } 7369 7370 /* Translate section/page access permissions to page 7371 * R/W protection flags. 7372 * 7373 * @ap: The 2-bit simple AP (AP[2:1]) 7374 * @is_user: TRUE if accessing from PL0 7375 */ 7376 static inline int simple_ap_to_rw_prot_is_user(int ap, bool is_user) 7377 { 7378 switch (ap) { 7379 case 0: 7380 return is_user ? 0 : PAGE_READ | PAGE_WRITE; 7381 case 1: 7382 return PAGE_READ | PAGE_WRITE; 7383 case 2: 7384 return is_user ? 0 : PAGE_READ; 7385 case 3: 7386 return PAGE_READ; 7387 default: 7388 g_assert_not_reached(); 7389 } 7390 } 7391 7392 static inline int 7393 simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap) 7394 { 7395 return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx)); 7396 } 7397 7398 /* Translate S2 section/page access permissions to protection flags 7399 * 7400 * @env: CPUARMState 7401 * @s2ap: The 2-bit stage2 access permissions (S2AP) 7402 * @xn: XN (execute-never) bit 7403 */ 7404 static int get_S2prot(CPUARMState *env, int s2ap, int xn) 7405 { 7406 int prot = 0; 7407 7408 if (s2ap & 1) { 7409 prot |= PAGE_READ; 7410 } 7411 if (s2ap & 2) { 7412 prot |= PAGE_WRITE; 7413 } 7414 if (!xn) { 7415 if (arm_el_is_aa64(env, 2) || prot & PAGE_READ) { 7416 prot |= PAGE_EXEC; 7417 } 7418 } 7419 return prot; 7420 } 7421 7422 /* Translate section/page access permissions to protection flags 7423 * 7424 * @env: CPUARMState 7425 * @mmu_idx: MMU index indicating required translation regime 7426 * @is_aa64: TRUE if AArch64 7427 * @ap: The 2-bit simple AP (AP[2:1]) 7428 * @ns: NS (non-secure) bit 7429 * @xn: XN (execute-never) bit 7430 * @pxn: PXN (privileged execute-never) bit 7431 */ 7432 static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, 7433 int ap, int ns, int xn, int pxn) 7434 { 7435 bool is_user = regime_is_user(env, mmu_idx); 7436 int prot_rw, user_rw; 7437 bool have_wxn; 7438 int wxn = 0; 7439 7440 assert(mmu_idx != ARMMMUIdx_S2NS); 7441 7442 user_rw = simple_ap_to_rw_prot_is_user(ap, true); 7443 if (is_user) { 7444 prot_rw = user_rw; 7445 } else { 7446 prot_rw = simple_ap_to_rw_prot_is_user(ap, false); 7447 } 7448 7449 if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) { 7450 return prot_rw; 7451 } 7452 7453 /* TODO have_wxn should be replaced with 7454 * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2) 7455 * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE 7456 * compatible processors have EL2, which is required for [U]WXN. 7457 */ 7458 have_wxn = arm_feature(env, ARM_FEATURE_LPAE); 7459 7460 if (have_wxn) { 7461 wxn = regime_sctlr(env, mmu_idx) & SCTLR_WXN; 7462 } 7463 7464 if (is_aa64) { 7465 switch (regime_el(env, mmu_idx)) { 7466 case 1: 7467 if (!is_user) { 7468 xn = pxn || (user_rw & PAGE_WRITE); 7469 } 7470 break; 7471 case 2: 7472 case 3: 7473 break; 7474 } 7475 } else if (arm_feature(env, ARM_FEATURE_V7)) { 7476 switch (regime_el(env, mmu_idx)) { 7477 case 1: 7478 case 3: 7479 if (is_user) { 7480 xn = xn || !(user_rw & PAGE_READ); 7481 } else { 7482 int uwxn = 0; 7483 if (have_wxn) { 7484 uwxn = regime_sctlr(env, mmu_idx) & SCTLR_UWXN; 7485 } 7486 xn = xn || !(prot_rw & PAGE_READ) || pxn || 7487 (uwxn && (user_rw & PAGE_WRITE)); 7488 } 7489 break; 7490 case 2: 7491 break; 7492 } 7493 } else { 7494 xn = wxn = 0; 7495 } 7496 7497 if (xn || (wxn && (prot_rw & PAGE_WRITE))) { 7498 return prot_rw; 7499 } 7500 return prot_rw | PAGE_EXEC; 7501 } 7502 7503 static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, 7504 uint32_t *table, uint32_t address) 7505 { 7506 /* Note that we can only get here for an AArch32 PL0/PL1 lookup */ 7507 TCR *tcr = regime_tcr(env, mmu_idx); 7508 7509 if (address & tcr->mask) { 7510 if (tcr->raw_tcr & TTBCR_PD1) { 7511 /* Translation table walk disabled for TTBR1 */ 7512 return false; 7513 } 7514 *table = regime_ttbr(env, mmu_idx, 1) & 0xffffc000; 7515 } else { 7516 if (tcr->raw_tcr & TTBCR_PD0) { 7517 /* Translation table walk disabled for TTBR0 */ 7518 return false; 7519 } 7520 *table = regime_ttbr(env, mmu_idx, 0) & tcr->base_mask; 7521 } 7522 *table |= (address >> 18) & 0x3ffc; 7523 return true; 7524 } 7525 7526 /* Translate a S1 pagetable walk through S2 if needed. */ 7527 static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, 7528 hwaddr addr, MemTxAttrs txattrs, 7529 uint32_t *fsr, 7530 ARMMMUFaultInfo *fi) 7531 { 7532 if ((mmu_idx == ARMMMUIdx_S1NSE0 || mmu_idx == ARMMMUIdx_S1NSE1) && 7533 !regime_translation_disabled(env, ARMMMUIdx_S2NS)) { 7534 target_ulong s2size; 7535 hwaddr s2pa; 7536 int s2prot; 7537 int ret; 7538 7539 ret = get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_S2NS, &s2pa, 7540 &txattrs, &s2prot, &s2size, fsr, fi); 7541 if (ret) { 7542 fi->s2addr = addr; 7543 fi->stage2 = true; 7544 fi->s1ptw = true; 7545 return ~0; 7546 } 7547 addr = s2pa; 7548 } 7549 return addr; 7550 } 7551 7552 /* All loads done in the course of a page table walk go through here. 7553 * TODO: rather than ignoring errors from physical memory reads (which 7554 * are external aborts in ARM terminology) we should propagate this 7555 * error out so that we can turn it into a Data Abort if this walk 7556 * was being done for a CPU load/store or an address translation instruction 7557 * (but not if it was for a debug access). 7558 */ 7559 static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure, 7560 ARMMMUIdx mmu_idx, uint32_t *fsr, 7561 ARMMMUFaultInfo *fi) 7562 { 7563 ARMCPU *cpu = ARM_CPU(cs); 7564 CPUARMState *env = &cpu->env; 7565 MemTxAttrs attrs = {}; 7566 AddressSpace *as; 7567 7568 attrs.secure = is_secure; 7569 as = arm_addressspace(cs, attrs); 7570 addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi); 7571 if (fi->s1ptw) { 7572 return 0; 7573 } 7574 if (regime_translation_big_endian(env, mmu_idx)) { 7575 return address_space_ldl_be(as, addr, attrs, NULL); 7576 } else { 7577 return address_space_ldl_le(as, addr, attrs, NULL); 7578 } 7579 } 7580 7581 static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, 7582 ARMMMUIdx mmu_idx, uint32_t *fsr, 7583 ARMMMUFaultInfo *fi) 7584 { 7585 ARMCPU *cpu = ARM_CPU(cs); 7586 CPUARMState *env = &cpu->env; 7587 MemTxAttrs attrs = {}; 7588 AddressSpace *as; 7589 7590 attrs.secure = is_secure; 7591 as = arm_addressspace(cs, attrs); 7592 addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi); 7593 if (fi->s1ptw) { 7594 return 0; 7595 } 7596 if (regime_translation_big_endian(env, mmu_idx)) { 7597 return address_space_ldq_be(as, addr, attrs, NULL); 7598 } else { 7599 return address_space_ldq_le(as, addr, attrs, NULL); 7600 } 7601 } 7602 7603 static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, 7604 MMUAccessType access_type, ARMMMUIdx mmu_idx, 7605 hwaddr *phys_ptr, int *prot, 7606 target_ulong *page_size, uint32_t *fsr, 7607 ARMMMUFaultInfo *fi) 7608 { 7609 CPUState *cs = CPU(arm_env_get_cpu(env)); 7610 int code; 7611 uint32_t table; 7612 uint32_t desc; 7613 int type; 7614 int ap; 7615 int domain = 0; 7616 int domain_prot; 7617 hwaddr phys_addr; 7618 uint32_t dacr; 7619 7620 /* Pagetable walk. */ 7621 /* Lookup l1 descriptor. */ 7622 if (!get_level1_table_address(env, mmu_idx, &table, address)) { 7623 /* Section translation fault if page walk is disabled by PD0 or PD1 */ 7624 code = 5; 7625 goto do_fault; 7626 } 7627 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), 7628 mmu_idx, fsr, fi); 7629 type = (desc & 3); 7630 domain = (desc >> 5) & 0x0f; 7631 if (regime_el(env, mmu_idx) == 1) { 7632 dacr = env->cp15.dacr_ns; 7633 } else { 7634 dacr = env->cp15.dacr_s; 7635 } 7636 domain_prot = (dacr >> (domain * 2)) & 3; 7637 if (type == 0) { 7638 /* Section translation fault. */ 7639 code = 5; 7640 goto do_fault; 7641 } 7642 if (domain_prot == 0 || domain_prot == 2) { 7643 if (type == 2) 7644 code = 9; /* Section domain fault. */ 7645 else 7646 code = 11; /* Page domain fault. */ 7647 goto do_fault; 7648 } 7649 if (type == 2) { 7650 /* 1Mb section. */ 7651 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); 7652 ap = (desc >> 10) & 3; 7653 code = 13; 7654 *page_size = 1024 * 1024; 7655 } else { 7656 /* Lookup l2 entry. */ 7657 if (type == 1) { 7658 /* Coarse pagetable. */ 7659 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); 7660 } else { 7661 /* Fine pagetable. */ 7662 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc); 7663 } 7664 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), 7665 mmu_idx, fsr, fi); 7666 switch (desc & 3) { 7667 case 0: /* Page translation fault. */ 7668 code = 7; 7669 goto do_fault; 7670 case 1: /* 64k page. */ 7671 phys_addr = (desc & 0xffff0000) | (address & 0xffff); 7672 ap = (desc >> (4 + ((address >> 13) & 6))) & 3; 7673 *page_size = 0x10000; 7674 break; 7675 case 2: /* 4k page. */ 7676 phys_addr = (desc & 0xfffff000) | (address & 0xfff); 7677 ap = (desc >> (4 + ((address >> 9) & 6))) & 3; 7678 *page_size = 0x1000; 7679 break; 7680 case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */ 7681 if (type == 1) { 7682 /* ARMv6/XScale extended small page format */ 7683 if (arm_feature(env, ARM_FEATURE_XSCALE) 7684 || arm_feature(env, ARM_FEATURE_V6)) { 7685 phys_addr = (desc & 0xfffff000) | (address & 0xfff); 7686 *page_size = 0x1000; 7687 } else { 7688 /* UNPREDICTABLE in ARMv5; we choose to take a 7689 * page translation fault. 7690 */ 7691 code = 7; 7692 goto do_fault; 7693 } 7694 } else { 7695 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff); 7696 *page_size = 0x400; 7697 } 7698 ap = (desc >> 4) & 3; 7699 break; 7700 default: 7701 /* Never happens, but compiler isn't smart enough to tell. */ 7702 abort(); 7703 } 7704 code = 15; 7705 } 7706 *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot); 7707 *prot |= *prot ? PAGE_EXEC : 0; 7708 if (!(*prot & (1 << access_type))) { 7709 /* Access permission fault. */ 7710 goto do_fault; 7711 } 7712 *phys_ptr = phys_addr; 7713 return false; 7714 do_fault: 7715 *fsr = code | (domain << 4); 7716 return true; 7717 } 7718 7719 static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, 7720 MMUAccessType access_type, ARMMMUIdx mmu_idx, 7721 hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, 7722 target_ulong *page_size, uint32_t *fsr, 7723 ARMMMUFaultInfo *fi) 7724 { 7725 CPUState *cs = CPU(arm_env_get_cpu(env)); 7726 int code; 7727 uint32_t table; 7728 uint32_t desc; 7729 uint32_t xn; 7730 uint32_t pxn = 0; 7731 int type; 7732 int ap; 7733 int domain = 0; 7734 int domain_prot; 7735 hwaddr phys_addr; 7736 uint32_t dacr; 7737 bool ns; 7738 7739 /* Pagetable walk. */ 7740 /* Lookup l1 descriptor. */ 7741 if (!get_level1_table_address(env, mmu_idx, &table, address)) { 7742 /* Section translation fault if page walk is disabled by PD0 or PD1 */ 7743 code = 5; 7744 goto do_fault; 7745 } 7746 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), 7747 mmu_idx, fsr, fi); 7748 type = (desc & 3); 7749 if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) { 7750 /* Section translation fault, or attempt to use the encoding 7751 * which is Reserved on implementations without PXN. 7752 */ 7753 code = 5; 7754 goto do_fault; 7755 } 7756 if ((type == 1) || !(desc & (1 << 18))) { 7757 /* Page or Section. */ 7758 domain = (desc >> 5) & 0x0f; 7759 } 7760 if (regime_el(env, mmu_idx) == 1) { 7761 dacr = env->cp15.dacr_ns; 7762 } else { 7763 dacr = env->cp15.dacr_s; 7764 } 7765 domain_prot = (dacr >> (domain * 2)) & 3; 7766 if (domain_prot == 0 || domain_prot == 2) { 7767 if (type != 1) { 7768 code = 9; /* Section domain fault. */ 7769 } else { 7770 code = 11; /* Page domain fault. */ 7771 } 7772 goto do_fault; 7773 } 7774 if (type != 1) { 7775 if (desc & (1 << 18)) { 7776 /* Supersection. */ 7777 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff); 7778 phys_addr |= (uint64_t)extract32(desc, 20, 4) << 32; 7779 phys_addr |= (uint64_t)extract32(desc, 5, 4) << 36; 7780 *page_size = 0x1000000; 7781 } else { 7782 /* Section. */ 7783 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); 7784 *page_size = 0x100000; 7785 } 7786 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4); 7787 xn = desc & (1 << 4); 7788 pxn = desc & 1; 7789 code = 13; 7790 ns = extract32(desc, 19, 1); 7791 } else { 7792 if (arm_feature(env, ARM_FEATURE_PXN)) { 7793 pxn = (desc >> 2) & 1; 7794 } 7795 ns = extract32(desc, 3, 1); 7796 /* Lookup l2 entry. */ 7797 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); 7798 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), 7799 mmu_idx, fsr, fi); 7800 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4); 7801 switch (desc & 3) { 7802 case 0: /* Page translation fault. */ 7803 code = 7; 7804 goto do_fault; 7805 case 1: /* 64k page. */ 7806 phys_addr = (desc & 0xffff0000) | (address & 0xffff); 7807 xn = desc & (1 << 15); 7808 *page_size = 0x10000; 7809 break; 7810 case 2: case 3: /* 4k page. */ 7811 phys_addr = (desc & 0xfffff000) | (address & 0xfff); 7812 xn = desc & 1; 7813 *page_size = 0x1000; 7814 break; 7815 default: 7816 /* Never happens, but compiler isn't smart enough to tell. */ 7817 abort(); 7818 } 7819 code = 15; 7820 } 7821 if (domain_prot == 3) { 7822 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 7823 } else { 7824 if (pxn && !regime_is_user(env, mmu_idx)) { 7825 xn = 1; 7826 } 7827 if (xn && access_type == MMU_INST_FETCH) 7828 goto do_fault; 7829 7830 if (arm_feature(env, ARM_FEATURE_V6K) && 7831 (regime_sctlr(env, mmu_idx) & SCTLR_AFE)) { 7832 /* The simplified model uses AP[0] as an access control bit. */ 7833 if ((ap & 1) == 0) { 7834 /* Access flag fault. */ 7835 code = (code == 15) ? 6 : 3; 7836 goto do_fault; 7837 } 7838 *prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1); 7839 } else { 7840 *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot); 7841 } 7842 if (*prot && !xn) { 7843 *prot |= PAGE_EXEC; 7844 } 7845 if (!(*prot & (1 << access_type))) { 7846 /* Access permission fault. */ 7847 goto do_fault; 7848 } 7849 } 7850 if (ns) { 7851 /* The NS bit will (as required by the architecture) have no effect if 7852 * the CPU doesn't support TZ or this is a non-secure translation 7853 * regime, because the attribute will already be non-secure. 7854 */ 7855 attrs->secure = false; 7856 } 7857 *phys_ptr = phys_addr; 7858 return false; 7859 do_fault: 7860 *fsr = code | (domain << 4); 7861 return true; 7862 } 7863 7864 /* Fault type for long-descriptor MMU fault reporting; this corresponds 7865 * to bits [5..2] in the STATUS field in long-format DFSR/IFSR. 7866 */ 7867 typedef enum { 7868 translation_fault = 1, 7869 access_fault = 2, 7870 permission_fault = 3, 7871 } MMUFaultType; 7872 7873 /* 7874 * check_s2_mmu_setup 7875 * @cpu: ARMCPU 7876 * @is_aa64: True if the translation regime is in AArch64 state 7877 * @startlevel: Suggested starting level 7878 * @inputsize: Bitsize of IPAs 7879 * @stride: Page-table stride (See the ARM ARM) 7880 * 7881 * Returns true if the suggested S2 translation parameters are OK and 7882 * false otherwise. 7883 */ 7884 static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, 7885 int inputsize, int stride) 7886 { 7887 const int grainsize = stride + 3; 7888 int startsizecheck; 7889 7890 /* Negative levels are never allowed. */ 7891 if (level < 0) { 7892 return false; 7893 } 7894 7895 startsizecheck = inputsize - ((3 - level) * stride + grainsize); 7896 if (startsizecheck < 1 || startsizecheck > stride + 4) { 7897 return false; 7898 } 7899 7900 if (is_aa64) { 7901 CPUARMState *env = &cpu->env; 7902 unsigned int pamax = arm_pamax(cpu); 7903 7904 switch (stride) { 7905 case 13: /* 64KB Pages. */ 7906 if (level == 0 || (level == 1 && pamax <= 42)) { 7907 return false; 7908 } 7909 break; 7910 case 11: /* 16KB Pages. */ 7911 if (level == 0 || (level == 1 && pamax <= 40)) { 7912 return false; 7913 } 7914 break; 7915 case 9: /* 4KB Pages. */ 7916 if (level == 0 && pamax <= 42) { 7917 return false; 7918 } 7919 break; 7920 default: 7921 g_assert_not_reached(); 7922 } 7923 7924 /* Inputsize checks. */ 7925 if (inputsize > pamax && 7926 (arm_el_is_aa64(env, 1) || inputsize > 40)) { 7927 /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */ 7928 return false; 7929 } 7930 } else { 7931 /* AArch32 only supports 4KB pages. Assert on that. */ 7932 assert(stride == 9); 7933 7934 if (level == 0) { 7935 return false; 7936 } 7937 } 7938 return true; 7939 } 7940 7941 static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, 7942 MMUAccessType access_type, ARMMMUIdx mmu_idx, 7943 hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, 7944 target_ulong *page_size_ptr, uint32_t *fsr, 7945 ARMMMUFaultInfo *fi) 7946 { 7947 ARMCPU *cpu = arm_env_get_cpu(env); 7948 CPUState *cs = CPU(cpu); 7949 /* Read an LPAE long-descriptor translation table. */ 7950 MMUFaultType fault_type = translation_fault; 7951 uint32_t level; 7952 uint32_t epd = 0; 7953 int32_t t0sz, t1sz; 7954 uint32_t tg; 7955 uint64_t ttbr; 7956 int ttbr_select; 7957 hwaddr descaddr, indexmask, indexmask_grainsize; 7958 uint32_t tableattrs; 7959 target_ulong page_size; 7960 uint32_t attrs; 7961 int32_t stride = 9; 7962 int32_t addrsize; 7963 int inputsize; 7964 int32_t tbi = 0; 7965 TCR *tcr = regime_tcr(env, mmu_idx); 7966 int ap, ns, xn, pxn; 7967 uint32_t el = regime_el(env, mmu_idx); 7968 bool ttbr1_valid = true; 7969 uint64_t descaddrmask; 7970 bool aarch64 = arm_el_is_aa64(env, el); 7971 7972 /* TODO: 7973 * This code does not handle the different format TCR for VTCR_EL2. 7974 * This code also does not support shareability levels. 7975 * Attribute and permission bit handling should also be checked when adding 7976 * support for those page table walks. 7977 */ 7978 if (aarch64) { 7979 level = 0; 7980 addrsize = 64; 7981 if (el > 1) { 7982 if (mmu_idx != ARMMMUIdx_S2NS) { 7983 tbi = extract64(tcr->raw_tcr, 20, 1); 7984 } 7985 } else { 7986 if (extract64(address, 55, 1)) { 7987 tbi = extract64(tcr->raw_tcr, 38, 1); 7988 } else { 7989 tbi = extract64(tcr->raw_tcr, 37, 1); 7990 } 7991 } 7992 tbi *= 8; 7993 7994 /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it 7995 * invalid. 7996 */ 7997 if (el > 1) { 7998 ttbr1_valid = false; 7999 } 8000 } else { 8001 level = 1; 8002 addrsize = 32; 8003 /* There is no TTBR1 for EL2 */ 8004 if (el == 2) { 8005 ttbr1_valid = false; 8006 } 8007 } 8008 8009 /* Determine whether this address is in the region controlled by 8010 * TTBR0 or TTBR1 (or if it is in neither region and should fault). 8011 * This is a Non-secure PL0/1 stage 1 translation, so controlled by 8012 * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32: 8013 */ 8014 if (aarch64) { 8015 /* AArch64 translation. */ 8016 t0sz = extract32(tcr->raw_tcr, 0, 6); 8017 t0sz = MIN(t0sz, 39); 8018 t0sz = MAX(t0sz, 16); 8019 } else if (mmu_idx != ARMMMUIdx_S2NS) { 8020 /* AArch32 stage 1 translation. */ 8021 t0sz = extract32(tcr->raw_tcr, 0, 3); 8022 } else { 8023 /* AArch32 stage 2 translation. */ 8024 bool sext = extract32(tcr->raw_tcr, 4, 1); 8025 bool sign = extract32(tcr->raw_tcr, 3, 1); 8026 /* Address size is 40-bit for a stage 2 translation, 8027 * and t0sz can be negative (from -8 to 7), 8028 * so we need to adjust it to use the TTBR selecting logic below. 8029 */ 8030 addrsize = 40; 8031 t0sz = sextract32(tcr->raw_tcr, 0, 4) + 8; 8032 8033 /* If the sign-extend bit is not the same as t0sz[3], the result 8034 * is unpredictable. Flag this as a guest error. */ 8035 if (sign != sext) { 8036 qemu_log_mask(LOG_GUEST_ERROR, 8037 "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n"); 8038 } 8039 } 8040 t1sz = extract32(tcr->raw_tcr, 16, 6); 8041 if (aarch64) { 8042 t1sz = MIN(t1sz, 39); 8043 t1sz = MAX(t1sz, 16); 8044 } 8045 if (t0sz && !extract64(address, addrsize - t0sz, t0sz - tbi)) { 8046 /* there is a ttbr0 region and we are in it (high bits all zero) */ 8047 ttbr_select = 0; 8048 } else if (ttbr1_valid && t1sz && 8049 !extract64(~address, addrsize - t1sz, t1sz - tbi)) { 8050 /* there is a ttbr1 region and we are in it (high bits all one) */ 8051 ttbr_select = 1; 8052 } else if (!t0sz) { 8053 /* ttbr0 region is "everything not in the ttbr1 region" */ 8054 ttbr_select = 0; 8055 } else if (!t1sz && ttbr1_valid) { 8056 /* ttbr1 region is "everything not in the ttbr0 region" */ 8057 ttbr_select = 1; 8058 } else { 8059 /* in the gap between the two regions, this is a Translation fault */ 8060 fault_type = translation_fault; 8061 goto do_fault; 8062 } 8063 8064 /* Note that QEMU ignores shareability and cacheability attributes, 8065 * so we don't need to do anything with the SH, ORGN, IRGN fields 8066 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the 8067 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently 8068 * implement any ASID-like capability so we can ignore it (instead 8069 * we will always flush the TLB any time the ASID is changed). 8070 */ 8071 if (ttbr_select == 0) { 8072 ttbr = regime_ttbr(env, mmu_idx, 0); 8073 if (el < 2) { 8074 epd = extract32(tcr->raw_tcr, 7, 1); 8075 } 8076 inputsize = addrsize - t0sz; 8077 8078 tg = extract32(tcr->raw_tcr, 14, 2); 8079 if (tg == 1) { /* 64KB pages */ 8080 stride = 13; 8081 } 8082 if (tg == 2) { /* 16KB pages */ 8083 stride = 11; 8084 } 8085 } else { 8086 /* We should only be here if TTBR1 is valid */ 8087 assert(ttbr1_valid); 8088 8089 ttbr = regime_ttbr(env, mmu_idx, 1); 8090 epd = extract32(tcr->raw_tcr, 23, 1); 8091 inputsize = addrsize - t1sz; 8092 8093 tg = extract32(tcr->raw_tcr, 30, 2); 8094 if (tg == 3) { /* 64KB pages */ 8095 stride = 13; 8096 } 8097 if (tg == 1) { /* 16KB pages */ 8098 stride = 11; 8099 } 8100 } 8101 8102 /* Here we should have set up all the parameters for the translation: 8103 * inputsize, ttbr, epd, stride, tbi 8104 */ 8105 8106 if (epd) { 8107 /* Translation table walk disabled => Translation fault on TLB miss 8108 * Note: This is always 0 on 64-bit EL2 and EL3. 8109 */ 8110 goto do_fault; 8111 } 8112 8113 if (mmu_idx != ARMMMUIdx_S2NS) { 8114 /* The starting level depends on the virtual address size (which can 8115 * be up to 48 bits) and the translation granule size. It indicates 8116 * the number of strides (stride bits at a time) needed to 8117 * consume the bits of the input address. In the pseudocode this is: 8118 * level = 4 - RoundUp((inputsize - grainsize) / stride) 8119 * where their 'inputsize' is our 'inputsize', 'grainsize' is 8120 * our 'stride + 3' and 'stride' is our 'stride'. 8121 * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying: 8122 * = 4 - (inputsize - stride - 3 + stride - 1) / stride 8123 * = 4 - (inputsize - 4) / stride; 8124 */ 8125 level = 4 - (inputsize - 4) / stride; 8126 } else { 8127 /* For stage 2 translations the starting level is specified by the 8128 * VTCR_EL2.SL0 field (whose interpretation depends on the page size) 8129 */ 8130 uint32_t sl0 = extract32(tcr->raw_tcr, 6, 2); 8131 uint32_t startlevel; 8132 bool ok; 8133 8134 if (!aarch64 || stride == 9) { 8135 /* AArch32 or 4KB pages */ 8136 startlevel = 2 - sl0; 8137 } else { 8138 /* 16KB or 64KB pages */ 8139 startlevel = 3 - sl0; 8140 } 8141 8142 /* Check that the starting level is valid. */ 8143 ok = check_s2_mmu_setup(cpu, aarch64, startlevel, 8144 inputsize, stride); 8145 if (!ok) { 8146 fault_type = translation_fault; 8147 goto do_fault; 8148 } 8149 level = startlevel; 8150 } 8151 8152 indexmask_grainsize = (1ULL << (stride + 3)) - 1; 8153 indexmask = (1ULL << (inputsize - (stride * (4 - level)))) - 1; 8154 8155 /* Now we can extract the actual base address from the TTBR */ 8156 descaddr = extract64(ttbr, 0, 48); 8157 descaddr &= ~indexmask; 8158 8159 /* The address field in the descriptor goes up to bit 39 for ARMv7 8160 * but up to bit 47 for ARMv8, but we use the descaddrmask 8161 * up to bit 39 for AArch32, because we don't need other bits in that case 8162 * to construct next descriptor address (anyway they should be all zeroes). 8163 */ 8164 descaddrmask = ((1ull << (aarch64 ? 48 : 40)) - 1) & 8165 ~indexmask_grainsize; 8166 8167 /* Secure accesses start with the page table in secure memory and 8168 * can be downgraded to non-secure at any step. Non-secure accesses 8169 * remain non-secure. We implement this by just ORing in the NSTable/NS 8170 * bits at each step. 8171 */ 8172 tableattrs = regime_is_secure(env, mmu_idx) ? 0 : (1 << 4); 8173 for (;;) { 8174 uint64_t descriptor; 8175 bool nstable; 8176 8177 descaddr |= (address >> (stride * (4 - level))) & indexmask; 8178 descaddr &= ~7ULL; 8179 nstable = extract32(tableattrs, 4, 1); 8180 descriptor = arm_ldq_ptw(cs, descaddr, !nstable, mmu_idx, fsr, fi); 8181 if (fi->s1ptw) { 8182 goto do_fault; 8183 } 8184 8185 if (!(descriptor & 1) || 8186 (!(descriptor & 2) && (level == 3))) { 8187 /* Invalid, or the Reserved level 3 encoding */ 8188 goto do_fault; 8189 } 8190 descaddr = descriptor & descaddrmask; 8191 8192 if ((descriptor & 2) && (level < 3)) { 8193 /* Table entry. The top five bits are attributes which may 8194 * propagate down through lower levels of the table (and 8195 * which are all arranged so that 0 means "no effect", so 8196 * we can gather them up by ORing in the bits at each level). 8197 */ 8198 tableattrs |= extract64(descriptor, 59, 5); 8199 level++; 8200 indexmask = indexmask_grainsize; 8201 continue; 8202 } 8203 /* Block entry at level 1 or 2, or page entry at level 3. 8204 * These are basically the same thing, although the number 8205 * of bits we pull in from the vaddr varies. 8206 */ 8207 page_size = (1ULL << ((stride * (4 - level)) + 3)); 8208 descaddr |= (address & (page_size - 1)); 8209 /* Extract attributes from the descriptor */ 8210 attrs = extract64(descriptor, 2, 10) 8211 | (extract64(descriptor, 52, 12) << 10); 8212 8213 if (mmu_idx == ARMMMUIdx_S2NS) { 8214 /* Stage 2 table descriptors do not include any attribute fields */ 8215 break; 8216 } 8217 /* Merge in attributes from table descriptors */ 8218 attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */ 8219 attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */ 8220 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1 8221 * means "force PL1 access only", which means forcing AP[1] to 0. 8222 */ 8223 if (extract32(tableattrs, 2, 1)) { 8224 attrs &= ~(1 << 4); 8225 } 8226 attrs |= nstable << 3; /* NS */ 8227 break; 8228 } 8229 /* Here descaddr is the final physical address, and attributes 8230 * are all in attrs. 8231 */ 8232 fault_type = access_fault; 8233 if ((attrs & (1 << 8)) == 0) { 8234 /* Access flag */ 8235 goto do_fault; 8236 } 8237 8238 ap = extract32(attrs, 4, 2); 8239 xn = extract32(attrs, 12, 1); 8240 8241 if (mmu_idx == ARMMMUIdx_S2NS) { 8242 ns = true; 8243 *prot = get_S2prot(env, ap, xn); 8244 } else { 8245 ns = extract32(attrs, 3, 1); 8246 pxn = extract32(attrs, 11, 1); 8247 *prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn); 8248 } 8249 8250 fault_type = permission_fault; 8251 if (!(*prot & (1 << access_type))) { 8252 goto do_fault; 8253 } 8254 8255 if (ns) { 8256 /* The NS bit will (as required by the architecture) have no effect if 8257 * the CPU doesn't support TZ or this is a non-secure translation 8258 * regime, because the attribute will already be non-secure. 8259 */ 8260 txattrs->secure = false; 8261 } 8262 *phys_ptr = descaddr; 8263 *page_size_ptr = page_size; 8264 return false; 8265 8266 do_fault: 8267 /* Long-descriptor format IFSR/DFSR value */ 8268 *fsr = (1 << 9) | (fault_type << 2) | level; 8269 /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */ 8270 fi->stage2 = fi->s1ptw || (mmu_idx == ARMMMUIdx_S2NS); 8271 return true; 8272 } 8273 8274 static inline void get_phys_addr_pmsav7_default(CPUARMState *env, 8275 ARMMMUIdx mmu_idx, 8276 int32_t address, int *prot) 8277 { 8278 if (!arm_feature(env, ARM_FEATURE_M)) { 8279 *prot = PAGE_READ | PAGE_WRITE; 8280 switch (address) { 8281 case 0xF0000000 ... 0xFFFFFFFF: 8282 if (regime_sctlr(env, mmu_idx) & SCTLR_V) { 8283 /* hivecs execing is ok */ 8284 *prot |= PAGE_EXEC; 8285 } 8286 break; 8287 case 0x00000000 ... 0x7FFFFFFF: 8288 *prot |= PAGE_EXEC; 8289 break; 8290 } 8291 } else { 8292 /* Default system address map for M profile cores. 8293 * The architecture specifies which regions are execute-never; 8294 * at the MPU level no other checks are defined. 8295 */ 8296 switch (address) { 8297 case 0x00000000 ... 0x1fffffff: /* ROM */ 8298 case 0x20000000 ... 0x3fffffff: /* SRAM */ 8299 case 0x60000000 ... 0x7fffffff: /* RAM */ 8300 case 0x80000000 ... 0x9fffffff: /* RAM */ 8301 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 8302 break; 8303 case 0x40000000 ... 0x5fffffff: /* Peripheral */ 8304 case 0xa0000000 ... 0xbfffffff: /* Device */ 8305 case 0xc0000000 ... 0xdfffffff: /* Device */ 8306 case 0xe0000000 ... 0xffffffff: /* System */ 8307 *prot = PAGE_READ | PAGE_WRITE; 8308 break; 8309 default: 8310 g_assert_not_reached(); 8311 } 8312 } 8313 } 8314 8315 static bool pmsav7_use_background_region(ARMCPU *cpu, 8316 ARMMMUIdx mmu_idx, bool is_user) 8317 { 8318 /* Return true if we should use the default memory map as a 8319 * "background" region if there are no hits against any MPU regions. 8320 */ 8321 CPUARMState *env = &cpu->env; 8322 8323 if (is_user) { 8324 return false; 8325 } 8326 8327 if (arm_feature(env, ARM_FEATURE_M)) { 8328 return env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] 8329 & R_V7M_MPU_CTRL_PRIVDEFENA_MASK; 8330 } else { 8331 return regime_sctlr(env, mmu_idx) & SCTLR_BR; 8332 } 8333 } 8334 8335 static inline bool m_is_ppb_region(CPUARMState *env, uint32_t address) 8336 { 8337 /* True if address is in the M profile PPB region 0xe0000000 - 0xe00fffff */ 8338 return arm_feature(env, ARM_FEATURE_M) && 8339 extract32(address, 20, 12) == 0xe00; 8340 } 8341 8342 static inline bool m_is_system_region(CPUARMState *env, uint32_t address) 8343 { 8344 /* True if address is in the M profile system region 8345 * 0xe0000000 - 0xffffffff 8346 */ 8347 return arm_feature(env, ARM_FEATURE_M) && extract32(address, 29, 3) == 0x7; 8348 } 8349 8350 static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, 8351 MMUAccessType access_type, ARMMMUIdx mmu_idx, 8352 hwaddr *phys_ptr, int *prot, uint32_t *fsr) 8353 { 8354 ARMCPU *cpu = arm_env_get_cpu(env); 8355 int n; 8356 bool is_user = regime_is_user(env, mmu_idx); 8357 8358 *phys_ptr = address; 8359 *prot = 0; 8360 8361 if (regime_translation_disabled(env, mmu_idx) || 8362 m_is_ppb_region(env, address)) { 8363 /* MPU disabled or M profile PPB access: use default memory map. 8364 * The other case which uses the default memory map in the 8365 * v7M ARM ARM pseudocode is exception vector reads from the vector 8366 * table. In QEMU those accesses are done in arm_v7m_load_vector(), 8367 * which always does a direct read using address_space_ldl(), rather 8368 * than going via this function, so we don't need to check that here. 8369 */ 8370 get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); 8371 } else { /* MPU enabled */ 8372 for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) { 8373 /* region search */ 8374 uint32_t base = env->pmsav7.drbar[n]; 8375 uint32_t rsize = extract32(env->pmsav7.drsr[n], 1, 5); 8376 uint32_t rmask; 8377 bool srdis = false; 8378 8379 if (!(env->pmsav7.drsr[n] & 0x1)) { 8380 continue; 8381 } 8382 8383 if (!rsize) { 8384 qemu_log_mask(LOG_GUEST_ERROR, 8385 "DRSR[%d]: Rsize field cannot be 0\n", n); 8386 continue; 8387 } 8388 rsize++; 8389 rmask = (1ull << rsize) - 1; 8390 8391 if (base & rmask) { 8392 qemu_log_mask(LOG_GUEST_ERROR, 8393 "DRBAR[%d]: 0x%" PRIx32 " misaligned " 8394 "to DRSR region size, mask = 0x%" PRIx32 "\n", 8395 n, base, rmask); 8396 continue; 8397 } 8398 8399 if (address < base || address > base + rmask) { 8400 continue; 8401 } 8402 8403 /* Region matched */ 8404 8405 if (rsize >= 8) { /* no subregions for regions < 256 bytes */ 8406 int i, snd; 8407 uint32_t srdis_mask; 8408 8409 rsize -= 3; /* sub region size (power of 2) */ 8410 snd = ((address - base) >> rsize) & 0x7; 8411 srdis = extract32(env->pmsav7.drsr[n], snd + 8, 1); 8412 8413 srdis_mask = srdis ? 0x3 : 0x0; 8414 for (i = 2; i <= 8 && rsize < TARGET_PAGE_BITS; i *= 2) { 8415 /* This will check in groups of 2, 4 and then 8, whether 8416 * the subregion bits are consistent. rsize is incremented 8417 * back up to give the region size, considering consistent 8418 * adjacent subregions as one region. Stop testing if rsize 8419 * is already big enough for an entire QEMU page. 8420 */ 8421 int snd_rounded = snd & ~(i - 1); 8422 uint32_t srdis_multi = extract32(env->pmsav7.drsr[n], 8423 snd_rounded + 8, i); 8424 if (srdis_mask ^ srdis_multi) { 8425 break; 8426 } 8427 srdis_mask = (srdis_mask << i) | srdis_mask; 8428 rsize++; 8429 } 8430 } 8431 if (rsize < TARGET_PAGE_BITS) { 8432 qemu_log_mask(LOG_UNIMP, 8433 "DRSR[%d]: No support for MPU (sub)region " 8434 "alignment of %" PRIu32 " bits. Minimum is %d\n", 8435 n, rsize, TARGET_PAGE_BITS); 8436 continue; 8437 } 8438 if (srdis) { 8439 continue; 8440 } 8441 break; 8442 } 8443 8444 if (n == -1) { /* no hits */ 8445 if (!pmsav7_use_background_region(cpu, mmu_idx, is_user)) { 8446 /* background fault */ 8447 *fsr = 0; 8448 return true; 8449 } 8450 get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); 8451 } else { /* a MPU hit! */ 8452 uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3); 8453 uint32_t xn = extract32(env->pmsav7.dracr[n], 12, 1); 8454 8455 if (m_is_system_region(env, address)) { 8456 /* System space is always execute never */ 8457 xn = 1; 8458 } 8459 8460 if (is_user) { /* User mode AP bit decoding */ 8461 switch (ap) { 8462 case 0: 8463 case 1: 8464 case 5: 8465 break; /* no access */ 8466 case 3: 8467 *prot |= PAGE_WRITE; 8468 /* fall through */ 8469 case 2: 8470 case 6: 8471 *prot |= PAGE_READ | PAGE_EXEC; 8472 break; 8473 default: 8474 qemu_log_mask(LOG_GUEST_ERROR, 8475 "DRACR[%d]: Bad value for AP bits: 0x%" 8476 PRIx32 "\n", n, ap); 8477 } 8478 } else { /* Priv. mode AP bits decoding */ 8479 switch (ap) { 8480 case 0: 8481 break; /* no access */ 8482 case 1: 8483 case 2: 8484 case 3: 8485 *prot |= PAGE_WRITE; 8486 /* fall through */ 8487 case 5: 8488 case 6: 8489 *prot |= PAGE_READ | PAGE_EXEC; 8490 break; 8491 default: 8492 qemu_log_mask(LOG_GUEST_ERROR, 8493 "DRACR[%d]: Bad value for AP bits: 0x%" 8494 PRIx32 "\n", n, ap); 8495 } 8496 } 8497 8498 /* execute never */ 8499 if (xn) { 8500 *prot &= ~PAGE_EXEC; 8501 } 8502 } 8503 } 8504 8505 *fsr = 0x00d; /* Permission fault */ 8506 return !(*prot & (1 << access_type)); 8507 } 8508 8509 static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, 8510 MMUAccessType access_type, ARMMMUIdx mmu_idx, 8511 hwaddr *phys_ptr, int *prot, uint32_t *fsr) 8512 { 8513 ARMCPU *cpu = arm_env_get_cpu(env); 8514 bool is_user = regime_is_user(env, mmu_idx); 8515 uint32_t secure = regime_is_secure(env, mmu_idx); 8516 int n; 8517 int matchregion = -1; 8518 bool hit = false; 8519 8520 *phys_ptr = address; 8521 *prot = 0; 8522 8523 /* Unlike the ARM ARM pseudocode, we don't need to check whether this 8524 * was an exception vector read from the vector table (which is always 8525 * done using the default system address map), because those accesses 8526 * are done in arm_v7m_load_vector(), which always does a direct 8527 * read using address_space_ldl(), rather than going via this function. 8528 */ 8529 if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */ 8530 hit = true; 8531 } else if (m_is_ppb_region(env, address)) { 8532 hit = true; 8533 } else if (pmsav7_use_background_region(cpu, mmu_idx, is_user)) { 8534 hit = true; 8535 } else { 8536 for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) { 8537 /* region search */ 8538 /* Note that the base address is bits [31:5] from the register 8539 * with bits [4:0] all zeroes, but the limit address is bits 8540 * [31:5] from the register with bits [4:0] all ones. 8541 */ 8542 uint32_t base = env->pmsav8.rbar[secure][n] & ~0x1f; 8543 uint32_t limit = env->pmsav8.rlar[secure][n] | 0x1f; 8544 8545 if (!(env->pmsav8.rlar[secure][n] & 0x1)) { 8546 /* Region disabled */ 8547 continue; 8548 } 8549 8550 if (address < base || address > limit) { 8551 continue; 8552 } 8553 8554 if (hit) { 8555 /* Multiple regions match -- always a failure (unlike 8556 * PMSAv7 where highest-numbered-region wins) 8557 */ 8558 *fsr = 0x00d; /* permission fault */ 8559 return true; 8560 } 8561 8562 matchregion = n; 8563 hit = true; 8564 8565 if (base & ~TARGET_PAGE_MASK) { 8566 qemu_log_mask(LOG_UNIMP, 8567 "MPU_RBAR[%d]: No support for MPU region base" 8568 "address of 0x%" PRIx32 ". Minimum alignment is " 8569 "%d\n", 8570 n, base, TARGET_PAGE_BITS); 8571 continue; 8572 } 8573 if ((limit + 1) & ~TARGET_PAGE_MASK) { 8574 qemu_log_mask(LOG_UNIMP, 8575 "MPU_RBAR[%d]: No support for MPU region limit" 8576 "address of 0x%" PRIx32 ". Minimum alignment is " 8577 "%d\n", 8578 n, limit, TARGET_PAGE_BITS); 8579 continue; 8580 } 8581 } 8582 } 8583 8584 if (!hit) { 8585 /* background fault */ 8586 *fsr = 0; 8587 return true; 8588 } 8589 8590 if (matchregion == -1) { 8591 /* hit using the background region */ 8592 get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); 8593 } else { 8594 uint32_t ap = extract32(env->pmsav8.rbar[secure][matchregion], 1, 2); 8595 uint32_t xn = extract32(env->pmsav8.rbar[secure][matchregion], 0, 1); 8596 8597 if (m_is_system_region(env, address)) { 8598 /* System space is always execute never */ 8599 xn = 1; 8600 } 8601 8602 *prot = simple_ap_to_rw_prot(env, mmu_idx, ap); 8603 if (*prot && !xn) { 8604 *prot |= PAGE_EXEC; 8605 } 8606 /* We don't need to look the attribute up in the MAIR0/MAIR1 8607 * registers because that only tells us about cacheability. 8608 */ 8609 } 8610 8611 *fsr = 0x00d; /* Permission fault */ 8612 return !(*prot & (1 << access_type)); 8613 } 8614 8615 static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, 8616 MMUAccessType access_type, ARMMMUIdx mmu_idx, 8617 hwaddr *phys_ptr, int *prot, uint32_t *fsr) 8618 { 8619 int n; 8620 uint32_t mask; 8621 uint32_t base; 8622 bool is_user = regime_is_user(env, mmu_idx); 8623 8624 if (regime_translation_disabled(env, mmu_idx)) { 8625 /* MPU disabled. */ 8626 *phys_ptr = address; 8627 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 8628 return false; 8629 } 8630 8631 *phys_ptr = address; 8632 for (n = 7; n >= 0; n--) { 8633 base = env->cp15.c6_region[n]; 8634 if ((base & 1) == 0) { 8635 continue; 8636 } 8637 mask = 1 << ((base >> 1) & 0x1f); 8638 /* Keep this shift separate from the above to avoid an 8639 (undefined) << 32. */ 8640 mask = (mask << 1) - 1; 8641 if (((base ^ address) & ~mask) == 0) { 8642 break; 8643 } 8644 } 8645 if (n < 0) { 8646 *fsr = 2; 8647 return true; 8648 } 8649 8650 if (access_type == MMU_INST_FETCH) { 8651 mask = env->cp15.pmsav5_insn_ap; 8652 } else { 8653 mask = env->cp15.pmsav5_data_ap; 8654 } 8655 mask = (mask >> (n * 4)) & 0xf; 8656 switch (mask) { 8657 case 0: 8658 *fsr = 1; 8659 return true; 8660 case 1: 8661 if (is_user) { 8662 *fsr = 1; 8663 return true; 8664 } 8665 *prot = PAGE_READ | PAGE_WRITE; 8666 break; 8667 case 2: 8668 *prot = PAGE_READ; 8669 if (!is_user) { 8670 *prot |= PAGE_WRITE; 8671 } 8672 break; 8673 case 3: 8674 *prot = PAGE_READ | PAGE_WRITE; 8675 break; 8676 case 5: 8677 if (is_user) { 8678 *fsr = 1; 8679 return true; 8680 } 8681 *prot = PAGE_READ; 8682 break; 8683 case 6: 8684 *prot = PAGE_READ; 8685 break; 8686 default: 8687 /* Bad permission. */ 8688 *fsr = 1; 8689 return true; 8690 } 8691 *prot |= PAGE_EXEC; 8692 return false; 8693 } 8694 8695 /* get_phys_addr - get the physical address for this virtual address 8696 * 8697 * Find the physical address corresponding to the given virtual address, 8698 * by doing a translation table walk on MMU based systems or using the 8699 * MPU state on MPU based systems. 8700 * 8701 * Returns false if the translation was successful. Otherwise, phys_ptr, attrs, 8702 * prot and page_size may not be filled in, and the populated fsr value provides 8703 * information on why the translation aborted, in the format of a 8704 * DFSR/IFSR fault register, with the following caveats: 8705 * * we honour the short vs long DFSR format differences. 8706 * * the WnR bit is never set (the caller must do this). 8707 * * for PSMAv5 based systems we don't bother to return a full FSR format 8708 * value. 8709 * 8710 * @env: CPUARMState 8711 * @address: virtual address to get physical address for 8712 * @access_type: 0 for read, 1 for write, 2 for execute 8713 * @mmu_idx: MMU index indicating required translation regime 8714 * @phys_ptr: set to the physical address corresponding to the virtual address 8715 * @attrs: set to the memory transaction attributes to use 8716 * @prot: set to the permissions for the page containing phys_ptr 8717 * @page_size: set to the size of the page containing phys_ptr 8718 * @fsr: set to the DFSR/IFSR value on failure 8719 */ 8720 static bool get_phys_addr(CPUARMState *env, target_ulong address, 8721 MMUAccessType access_type, ARMMMUIdx mmu_idx, 8722 hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, 8723 target_ulong *page_size, uint32_t *fsr, 8724 ARMMMUFaultInfo *fi) 8725 { 8726 if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { 8727 /* Call ourselves recursively to do the stage 1 and then stage 2 8728 * translations. 8729 */ 8730 if (arm_feature(env, ARM_FEATURE_EL2)) { 8731 hwaddr ipa; 8732 int s2_prot; 8733 int ret; 8734 8735 ret = get_phys_addr(env, address, access_type, 8736 stage_1_mmu_idx(mmu_idx), &ipa, attrs, 8737 prot, page_size, fsr, fi); 8738 8739 /* If S1 fails or S2 is disabled, return early. */ 8740 if (ret || regime_translation_disabled(env, ARMMMUIdx_S2NS)) { 8741 *phys_ptr = ipa; 8742 return ret; 8743 } 8744 8745 /* S1 is done. Now do S2 translation. */ 8746 ret = get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_S2NS, 8747 phys_ptr, attrs, &s2_prot, 8748 page_size, fsr, fi); 8749 fi->s2addr = ipa; 8750 /* Combine the S1 and S2 perms. */ 8751 *prot &= s2_prot; 8752 return ret; 8753 } else { 8754 /* 8755 * For non-EL2 CPUs a stage1+stage2 translation is just stage 1. 8756 */ 8757 mmu_idx = stage_1_mmu_idx(mmu_idx); 8758 } 8759 } 8760 8761 /* The page table entries may downgrade secure to non-secure, but 8762 * cannot upgrade an non-secure translation regime's attributes 8763 * to secure. 8764 */ 8765 attrs->secure = regime_is_secure(env, mmu_idx); 8766 attrs->user = regime_is_user(env, mmu_idx); 8767 8768 /* Fast Context Switch Extension. This doesn't exist at all in v8. 8769 * In v7 and earlier it affects all stage 1 translations. 8770 */ 8771 if (address < 0x02000000 && mmu_idx != ARMMMUIdx_S2NS 8772 && !arm_feature(env, ARM_FEATURE_V8)) { 8773 if (regime_el(env, mmu_idx) == 3) { 8774 address += env->cp15.fcseidr_s; 8775 } else { 8776 address += env->cp15.fcseidr_ns; 8777 } 8778 } 8779 8780 if (arm_feature(env, ARM_FEATURE_PMSA)) { 8781 bool ret; 8782 *page_size = TARGET_PAGE_SIZE; 8783 8784 if (arm_feature(env, ARM_FEATURE_V8)) { 8785 /* PMSAv8 */ 8786 ret = get_phys_addr_pmsav8(env, address, access_type, mmu_idx, 8787 phys_ptr, prot, fsr); 8788 } else if (arm_feature(env, ARM_FEATURE_V7)) { 8789 /* PMSAv7 */ 8790 ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx, 8791 phys_ptr, prot, fsr); 8792 } else { 8793 /* Pre-v7 MPU */ 8794 ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx, 8795 phys_ptr, prot, fsr); 8796 } 8797 qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32 8798 " mmu_idx %u -> %s (prot %c%c%c)\n", 8799 access_type == MMU_DATA_LOAD ? "reading" : 8800 (access_type == MMU_DATA_STORE ? "writing" : "execute"), 8801 (uint32_t)address, mmu_idx, 8802 ret ? "Miss" : "Hit", 8803 *prot & PAGE_READ ? 'r' : '-', 8804 *prot & PAGE_WRITE ? 'w' : '-', 8805 *prot & PAGE_EXEC ? 'x' : '-'); 8806 8807 return ret; 8808 } 8809 8810 /* Definitely a real MMU, not an MPU */ 8811 8812 if (regime_translation_disabled(env, mmu_idx)) { 8813 /* MMU disabled. */ 8814 *phys_ptr = address; 8815 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 8816 *page_size = TARGET_PAGE_SIZE; 8817 return 0; 8818 } 8819 8820 if (regime_using_lpae_format(env, mmu_idx)) { 8821 return get_phys_addr_lpae(env, address, access_type, mmu_idx, phys_ptr, 8822 attrs, prot, page_size, fsr, fi); 8823 } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { 8824 return get_phys_addr_v6(env, address, access_type, mmu_idx, phys_ptr, 8825 attrs, prot, page_size, fsr, fi); 8826 } else { 8827 return get_phys_addr_v5(env, address, access_type, mmu_idx, phys_ptr, 8828 prot, page_size, fsr, fi); 8829 } 8830 } 8831 8832 /* Walk the page table and (if the mapping exists) add the page 8833 * to the TLB. Return false on success, or true on failure. Populate 8834 * fsr with ARM DFSR/IFSR fault register format value on failure. 8835 */ 8836 bool arm_tlb_fill(CPUState *cs, vaddr address, 8837 MMUAccessType access_type, int mmu_idx, uint32_t *fsr, 8838 ARMMMUFaultInfo *fi) 8839 { 8840 ARMCPU *cpu = ARM_CPU(cs); 8841 CPUARMState *env = &cpu->env; 8842 hwaddr phys_addr; 8843 target_ulong page_size; 8844 int prot; 8845 int ret; 8846 MemTxAttrs attrs = {}; 8847 8848 ret = get_phys_addr(env, address, access_type, 8849 core_to_arm_mmu_idx(env, mmu_idx), &phys_addr, 8850 &attrs, &prot, &page_size, fsr, fi); 8851 if (!ret) { 8852 /* Map a single [sub]page. */ 8853 phys_addr &= TARGET_PAGE_MASK; 8854 address &= TARGET_PAGE_MASK; 8855 tlb_set_page_with_attrs(cs, address, phys_addr, attrs, 8856 prot, mmu_idx, page_size); 8857 return 0; 8858 } 8859 8860 return ret; 8861 } 8862 8863 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, 8864 MemTxAttrs *attrs) 8865 { 8866 ARMCPU *cpu = ARM_CPU(cs); 8867 CPUARMState *env = &cpu->env; 8868 hwaddr phys_addr; 8869 target_ulong page_size; 8870 int prot; 8871 bool ret; 8872 uint32_t fsr; 8873 ARMMMUFaultInfo fi = {}; 8874 ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false)); 8875 8876 *attrs = (MemTxAttrs) {}; 8877 8878 ret = get_phys_addr(env, addr, 0, mmu_idx, &phys_addr, 8879 attrs, &prot, &page_size, &fsr, &fi); 8880 8881 if (ret) { 8882 return -1; 8883 } 8884 return phys_addr; 8885 } 8886 8887 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) 8888 { 8889 uint32_t mask; 8890 unsigned el = arm_current_el(env); 8891 8892 /* First handle registers which unprivileged can read */ 8893 8894 switch (reg) { 8895 case 0 ... 7: /* xPSR sub-fields */ 8896 mask = 0; 8897 if ((reg & 1) && el) { 8898 mask |= XPSR_EXCP; /* IPSR (unpriv. reads as zero) */ 8899 } 8900 if (!(reg & 4)) { 8901 mask |= XPSR_NZCV | XPSR_Q; /* APSR */ 8902 } 8903 /* EPSR reads as zero */ 8904 return xpsr_read(env) & mask; 8905 break; 8906 case 20: /* CONTROL */ 8907 return env->v7m.control[env->v7m.secure]; 8908 case 0x94: /* CONTROL_NS */ 8909 /* We have to handle this here because unprivileged Secure code 8910 * can read the NS CONTROL register. 8911 */ 8912 if (!env->v7m.secure) { 8913 return 0; 8914 } 8915 return env->v7m.control[M_REG_NS]; 8916 } 8917 8918 if (el == 0) { 8919 return 0; /* unprivileged reads others as zero */ 8920 } 8921 8922 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 8923 switch (reg) { 8924 case 0x88: /* MSP_NS */ 8925 if (!env->v7m.secure) { 8926 return 0; 8927 } 8928 return env->v7m.other_ss_msp; 8929 case 0x89: /* PSP_NS */ 8930 if (!env->v7m.secure) { 8931 return 0; 8932 } 8933 return env->v7m.other_ss_psp; 8934 case 0x90: /* PRIMASK_NS */ 8935 if (!env->v7m.secure) { 8936 return 0; 8937 } 8938 return env->v7m.primask[M_REG_NS]; 8939 case 0x91: /* BASEPRI_NS */ 8940 if (!env->v7m.secure) { 8941 return 0; 8942 } 8943 return env->v7m.basepri[M_REG_NS]; 8944 case 0x93: /* FAULTMASK_NS */ 8945 if (!env->v7m.secure) { 8946 return 0; 8947 } 8948 return env->v7m.faultmask[M_REG_NS]; 8949 case 0x98: /* SP_NS */ 8950 { 8951 /* This gives the non-secure SP selected based on whether we're 8952 * currently in handler mode or not, using the NS CONTROL.SPSEL. 8953 */ 8954 bool spsel = env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK; 8955 8956 if (!env->v7m.secure) { 8957 return 0; 8958 } 8959 if (!arm_v7m_is_handler_mode(env) && spsel) { 8960 return env->v7m.other_ss_psp; 8961 } else { 8962 return env->v7m.other_ss_msp; 8963 } 8964 } 8965 default: 8966 break; 8967 } 8968 } 8969 8970 switch (reg) { 8971 case 8: /* MSP */ 8972 return (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) ? 8973 env->v7m.other_sp : env->regs[13]; 8974 case 9: /* PSP */ 8975 return (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) ? 8976 env->regs[13] : env->v7m.other_sp; 8977 case 16: /* PRIMASK */ 8978 return env->v7m.primask[env->v7m.secure]; 8979 case 17: /* BASEPRI */ 8980 case 18: /* BASEPRI_MAX */ 8981 return env->v7m.basepri[env->v7m.secure]; 8982 case 19: /* FAULTMASK */ 8983 return env->v7m.faultmask[env->v7m.secure]; 8984 default: 8985 qemu_log_mask(LOG_GUEST_ERROR, "Attempt to read unknown special" 8986 " register %d\n", reg); 8987 return 0; 8988 } 8989 } 8990 8991 void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) 8992 { 8993 /* We're passed bits [11..0] of the instruction; extract 8994 * SYSm and the mask bits. 8995 * Invalid combinations of SYSm and mask are UNPREDICTABLE; 8996 * we choose to treat them as if the mask bits were valid. 8997 * NB that the pseudocode 'mask' variable is bits [11..10], 8998 * whereas ours is [11..8]. 8999 */ 9000 uint32_t mask = extract32(maskreg, 8, 4); 9001 uint32_t reg = extract32(maskreg, 0, 8); 9002 9003 if (arm_current_el(env) == 0 && reg > 7) { 9004 /* only xPSR sub-fields may be written by unprivileged */ 9005 return; 9006 } 9007 9008 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 9009 switch (reg) { 9010 case 0x88: /* MSP_NS */ 9011 if (!env->v7m.secure) { 9012 return; 9013 } 9014 env->v7m.other_ss_msp = val; 9015 return; 9016 case 0x89: /* PSP_NS */ 9017 if (!env->v7m.secure) { 9018 return; 9019 } 9020 env->v7m.other_ss_psp = val; 9021 return; 9022 case 0x90: /* PRIMASK_NS */ 9023 if (!env->v7m.secure) { 9024 return; 9025 } 9026 env->v7m.primask[M_REG_NS] = val & 1; 9027 return; 9028 case 0x91: /* BASEPRI_NS */ 9029 if (!env->v7m.secure) { 9030 return; 9031 } 9032 env->v7m.basepri[M_REG_NS] = val & 0xff; 9033 return; 9034 case 0x93: /* FAULTMASK_NS */ 9035 if (!env->v7m.secure) { 9036 return; 9037 } 9038 env->v7m.faultmask[M_REG_NS] = val & 1; 9039 return; 9040 case 0x98: /* SP_NS */ 9041 { 9042 /* This gives the non-secure SP selected based on whether we're 9043 * currently in handler mode or not, using the NS CONTROL.SPSEL. 9044 */ 9045 bool spsel = env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK; 9046 9047 if (!env->v7m.secure) { 9048 return; 9049 } 9050 if (!arm_v7m_is_handler_mode(env) && spsel) { 9051 env->v7m.other_ss_psp = val; 9052 } else { 9053 env->v7m.other_ss_msp = val; 9054 } 9055 return; 9056 } 9057 default: 9058 break; 9059 } 9060 } 9061 9062 switch (reg) { 9063 case 0 ... 7: /* xPSR sub-fields */ 9064 /* only APSR is actually writable */ 9065 if (!(reg & 4)) { 9066 uint32_t apsrmask = 0; 9067 9068 if (mask & 8) { 9069 apsrmask |= XPSR_NZCV | XPSR_Q; 9070 } 9071 if ((mask & 4) && arm_feature(env, ARM_FEATURE_THUMB_DSP)) { 9072 apsrmask |= XPSR_GE; 9073 } 9074 xpsr_write(env, val, apsrmask); 9075 } 9076 break; 9077 case 8: /* MSP */ 9078 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) { 9079 env->v7m.other_sp = val; 9080 } else { 9081 env->regs[13] = val; 9082 } 9083 break; 9084 case 9: /* PSP */ 9085 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) { 9086 env->regs[13] = val; 9087 } else { 9088 env->v7m.other_sp = val; 9089 } 9090 break; 9091 case 16: /* PRIMASK */ 9092 env->v7m.primask[env->v7m.secure] = val & 1; 9093 break; 9094 case 17: /* BASEPRI */ 9095 env->v7m.basepri[env->v7m.secure] = val & 0xff; 9096 break; 9097 case 18: /* BASEPRI_MAX */ 9098 val &= 0xff; 9099 if (val != 0 && (val < env->v7m.basepri[env->v7m.secure] 9100 || env->v7m.basepri[env->v7m.secure] == 0)) { 9101 env->v7m.basepri[env->v7m.secure] = val; 9102 } 9103 break; 9104 case 19: /* FAULTMASK */ 9105 env->v7m.faultmask[env->v7m.secure] = val & 1; 9106 break; 9107 case 20: /* CONTROL */ 9108 /* Writing to the SPSEL bit only has an effect if we are in 9109 * thread mode; other bits can be updated by any privileged code. 9110 * switch_v7m_sp() deals with updating the SPSEL bit in 9111 * env->v7m.control, so we only need update the others. 9112 */ 9113 if (!arm_v7m_is_handler_mode(env)) { 9114 switch_v7m_sp(env, (val & R_V7M_CONTROL_SPSEL_MASK) != 0); 9115 } 9116 env->v7m.control[env->v7m.secure] &= ~R_V7M_CONTROL_NPRIV_MASK; 9117 env->v7m.control[env->v7m.secure] |= val & R_V7M_CONTROL_NPRIV_MASK; 9118 break; 9119 default: 9120 qemu_log_mask(LOG_GUEST_ERROR, "Attempt to write unknown special" 9121 " register %d\n", reg); 9122 return; 9123 } 9124 } 9125 9126 #endif 9127 9128 void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in) 9129 { 9130 /* Implement DC ZVA, which zeroes a fixed-length block of memory. 9131 * Note that we do not implement the (architecturally mandated) 9132 * alignment fault for attempts to use this on Device memory 9133 * (which matches the usual QEMU behaviour of not implementing either 9134 * alignment faults or any memory attribute handling). 9135 */ 9136 9137 ARMCPU *cpu = arm_env_get_cpu(env); 9138 uint64_t blocklen = 4 << cpu->dcz_blocksize; 9139 uint64_t vaddr = vaddr_in & ~(blocklen - 1); 9140 9141 #ifndef CONFIG_USER_ONLY 9142 { 9143 /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than 9144 * the block size so we might have to do more than one TLB lookup. 9145 * We know that in fact for any v8 CPU the page size is at least 4K 9146 * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only 9147 * 1K as an artefact of legacy v5 subpage support being present in the 9148 * same QEMU executable. 9149 */ 9150 int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE); 9151 void *hostaddr[maxidx]; 9152 int try, i; 9153 unsigned mmu_idx = cpu_mmu_index(env, false); 9154 TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx); 9155 9156 for (try = 0; try < 2; try++) { 9157 9158 for (i = 0; i < maxidx; i++) { 9159 hostaddr[i] = tlb_vaddr_to_host(env, 9160 vaddr + TARGET_PAGE_SIZE * i, 9161 1, mmu_idx); 9162 if (!hostaddr[i]) { 9163 break; 9164 } 9165 } 9166 if (i == maxidx) { 9167 /* If it's all in the TLB it's fair game for just writing to; 9168 * we know we don't need to update dirty status, etc. 9169 */ 9170 for (i = 0; i < maxidx - 1; i++) { 9171 memset(hostaddr[i], 0, TARGET_PAGE_SIZE); 9172 } 9173 memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE)); 9174 return; 9175 } 9176 /* OK, try a store and see if we can populate the tlb. This 9177 * might cause an exception if the memory isn't writable, 9178 * in which case we will longjmp out of here. We must for 9179 * this purpose use the actual register value passed to us 9180 * so that we get the fault address right. 9181 */ 9182 helper_ret_stb_mmu(env, vaddr_in, 0, oi, GETPC()); 9183 /* Now we can populate the other TLB entries, if any */ 9184 for (i = 0; i < maxidx; i++) { 9185 uint64_t va = vaddr + TARGET_PAGE_SIZE * i; 9186 if (va != (vaddr_in & TARGET_PAGE_MASK)) { 9187 helper_ret_stb_mmu(env, va, 0, oi, GETPC()); 9188 } 9189 } 9190 } 9191 9192 /* Slow path (probably attempt to do this to an I/O device or 9193 * similar, or clearing of a block of code we have translations 9194 * cached for). Just do a series of byte writes as the architecture 9195 * demands. It's not worth trying to use a cpu_physical_memory_map(), 9196 * memset(), unmap() sequence here because: 9197 * + we'd need to account for the blocksize being larger than a page 9198 * + the direct-RAM access case is almost always going to be dealt 9199 * with in the fastpath code above, so there's no speed benefit 9200 * + we would have to deal with the map returning NULL because the 9201 * bounce buffer was in use 9202 */ 9203 for (i = 0; i < blocklen; i++) { 9204 helper_ret_stb_mmu(env, vaddr + i, 0, oi, GETPC()); 9205 } 9206 } 9207 #else 9208 memset(g2h(vaddr), 0, blocklen); 9209 #endif 9210 } 9211 9212 /* Note that signed overflow is undefined in C. The following routines are 9213 careful to use unsigned types where modulo arithmetic is required. 9214 Failure to do so _will_ break on newer gcc. */ 9215 9216 /* Signed saturating arithmetic. */ 9217 9218 /* Perform 16-bit signed saturating addition. */ 9219 static inline uint16_t add16_sat(uint16_t a, uint16_t b) 9220 { 9221 uint16_t res; 9222 9223 res = a + b; 9224 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) { 9225 if (a & 0x8000) 9226 res = 0x8000; 9227 else 9228 res = 0x7fff; 9229 } 9230 return res; 9231 } 9232 9233 /* Perform 8-bit signed saturating addition. */ 9234 static inline uint8_t add8_sat(uint8_t a, uint8_t b) 9235 { 9236 uint8_t res; 9237 9238 res = a + b; 9239 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) { 9240 if (a & 0x80) 9241 res = 0x80; 9242 else 9243 res = 0x7f; 9244 } 9245 return res; 9246 } 9247 9248 /* Perform 16-bit signed saturating subtraction. */ 9249 static inline uint16_t sub16_sat(uint16_t a, uint16_t b) 9250 { 9251 uint16_t res; 9252 9253 res = a - b; 9254 if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) { 9255 if (a & 0x8000) 9256 res = 0x8000; 9257 else 9258 res = 0x7fff; 9259 } 9260 return res; 9261 } 9262 9263 /* Perform 8-bit signed saturating subtraction. */ 9264 static inline uint8_t sub8_sat(uint8_t a, uint8_t b) 9265 { 9266 uint8_t res; 9267 9268 res = a - b; 9269 if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) { 9270 if (a & 0x80) 9271 res = 0x80; 9272 else 9273 res = 0x7f; 9274 } 9275 return res; 9276 } 9277 9278 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16); 9279 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16); 9280 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8); 9281 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8); 9282 #define PFX q 9283 9284 #include "op_addsub.h" 9285 9286 /* Unsigned saturating arithmetic. */ 9287 static inline uint16_t add16_usat(uint16_t a, uint16_t b) 9288 { 9289 uint16_t res; 9290 res = a + b; 9291 if (res < a) 9292 res = 0xffff; 9293 return res; 9294 } 9295 9296 static inline uint16_t sub16_usat(uint16_t a, uint16_t b) 9297 { 9298 if (a > b) 9299 return a - b; 9300 else 9301 return 0; 9302 } 9303 9304 static inline uint8_t add8_usat(uint8_t a, uint8_t b) 9305 { 9306 uint8_t res; 9307 res = a + b; 9308 if (res < a) 9309 res = 0xff; 9310 return res; 9311 } 9312 9313 static inline uint8_t sub8_usat(uint8_t a, uint8_t b) 9314 { 9315 if (a > b) 9316 return a - b; 9317 else 9318 return 0; 9319 } 9320 9321 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16); 9322 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16); 9323 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8); 9324 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8); 9325 #define PFX uq 9326 9327 #include "op_addsub.h" 9328 9329 /* Signed modulo arithmetic. */ 9330 #define SARITH16(a, b, n, op) do { \ 9331 int32_t sum; \ 9332 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \ 9333 RESULT(sum, n, 16); \ 9334 if (sum >= 0) \ 9335 ge |= 3 << (n * 2); \ 9336 } while(0) 9337 9338 #define SARITH8(a, b, n, op) do { \ 9339 int32_t sum; \ 9340 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \ 9341 RESULT(sum, n, 8); \ 9342 if (sum >= 0) \ 9343 ge |= 1 << n; \ 9344 } while(0) 9345 9346 9347 #define ADD16(a, b, n) SARITH16(a, b, n, +) 9348 #define SUB16(a, b, n) SARITH16(a, b, n, -) 9349 #define ADD8(a, b, n) SARITH8(a, b, n, +) 9350 #define SUB8(a, b, n) SARITH8(a, b, n, -) 9351 #define PFX s 9352 #define ARITH_GE 9353 9354 #include "op_addsub.h" 9355 9356 /* Unsigned modulo arithmetic. */ 9357 #define ADD16(a, b, n) do { \ 9358 uint32_t sum; \ 9359 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \ 9360 RESULT(sum, n, 16); \ 9361 if ((sum >> 16) == 1) \ 9362 ge |= 3 << (n * 2); \ 9363 } while(0) 9364 9365 #define ADD8(a, b, n) do { \ 9366 uint32_t sum; \ 9367 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \ 9368 RESULT(sum, n, 8); \ 9369 if ((sum >> 8) == 1) \ 9370 ge |= 1 << n; \ 9371 } while(0) 9372 9373 #define SUB16(a, b, n) do { \ 9374 uint32_t sum; \ 9375 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \ 9376 RESULT(sum, n, 16); \ 9377 if ((sum >> 16) == 0) \ 9378 ge |= 3 << (n * 2); \ 9379 } while(0) 9380 9381 #define SUB8(a, b, n) do { \ 9382 uint32_t sum; \ 9383 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \ 9384 RESULT(sum, n, 8); \ 9385 if ((sum >> 8) == 0) \ 9386 ge |= 1 << n; \ 9387 } while(0) 9388 9389 #define PFX u 9390 #define ARITH_GE 9391 9392 #include "op_addsub.h" 9393 9394 /* Halved signed arithmetic. */ 9395 #define ADD16(a, b, n) \ 9396 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16) 9397 #define SUB16(a, b, n) \ 9398 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16) 9399 #define ADD8(a, b, n) \ 9400 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8) 9401 #define SUB8(a, b, n) \ 9402 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8) 9403 #define PFX sh 9404 9405 #include "op_addsub.h" 9406 9407 /* Halved unsigned arithmetic. */ 9408 #define ADD16(a, b, n) \ 9409 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16) 9410 #define SUB16(a, b, n) \ 9411 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16) 9412 #define ADD8(a, b, n) \ 9413 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8) 9414 #define SUB8(a, b, n) \ 9415 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8) 9416 #define PFX uh 9417 9418 #include "op_addsub.h" 9419 9420 static inline uint8_t do_usad(uint8_t a, uint8_t b) 9421 { 9422 if (a > b) 9423 return a - b; 9424 else 9425 return b - a; 9426 } 9427 9428 /* Unsigned sum of absolute byte differences. */ 9429 uint32_t HELPER(usad8)(uint32_t a, uint32_t b) 9430 { 9431 uint32_t sum; 9432 sum = do_usad(a, b); 9433 sum += do_usad(a >> 8, b >> 8); 9434 sum += do_usad(a >> 16, b >>16); 9435 sum += do_usad(a >> 24, b >> 24); 9436 return sum; 9437 } 9438 9439 /* For ARMv6 SEL instruction. */ 9440 uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b) 9441 { 9442 uint32_t mask; 9443 9444 mask = 0; 9445 if (flags & 1) 9446 mask |= 0xff; 9447 if (flags & 2) 9448 mask |= 0xff00; 9449 if (flags & 4) 9450 mask |= 0xff0000; 9451 if (flags & 8) 9452 mask |= 0xff000000; 9453 return (a & mask) | (b & ~mask); 9454 } 9455 9456 /* VFP support. We follow the convention used for VFP instructions: 9457 Single precision routines have a "s" suffix, double precision a 9458 "d" suffix. */ 9459 9460 /* Convert host exception flags to vfp form. */ 9461 static inline int vfp_exceptbits_from_host(int host_bits) 9462 { 9463 int target_bits = 0; 9464 9465 if (host_bits & float_flag_invalid) 9466 target_bits |= 1; 9467 if (host_bits & float_flag_divbyzero) 9468 target_bits |= 2; 9469 if (host_bits & float_flag_overflow) 9470 target_bits |= 4; 9471 if (host_bits & (float_flag_underflow | float_flag_output_denormal)) 9472 target_bits |= 8; 9473 if (host_bits & float_flag_inexact) 9474 target_bits |= 0x10; 9475 if (host_bits & float_flag_input_denormal) 9476 target_bits |= 0x80; 9477 return target_bits; 9478 } 9479 9480 uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env) 9481 { 9482 int i; 9483 uint32_t fpscr; 9484 9485 fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff) 9486 | (env->vfp.vec_len << 16) 9487 | (env->vfp.vec_stride << 20); 9488 i = get_float_exception_flags(&env->vfp.fp_status); 9489 i |= get_float_exception_flags(&env->vfp.standard_fp_status); 9490 fpscr |= vfp_exceptbits_from_host(i); 9491 return fpscr; 9492 } 9493 9494 uint32_t vfp_get_fpscr(CPUARMState *env) 9495 { 9496 return HELPER(vfp_get_fpscr)(env); 9497 } 9498 9499 /* Convert vfp exception flags to target form. */ 9500 static inline int vfp_exceptbits_to_host(int target_bits) 9501 { 9502 int host_bits = 0; 9503 9504 if (target_bits & 1) 9505 host_bits |= float_flag_invalid; 9506 if (target_bits & 2) 9507 host_bits |= float_flag_divbyzero; 9508 if (target_bits & 4) 9509 host_bits |= float_flag_overflow; 9510 if (target_bits & 8) 9511 host_bits |= float_flag_underflow; 9512 if (target_bits & 0x10) 9513 host_bits |= float_flag_inexact; 9514 if (target_bits & 0x80) 9515 host_bits |= float_flag_input_denormal; 9516 return host_bits; 9517 } 9518 9519 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) 9520 { 9521 int i; 9522 uint32_t changed; 9523 9524 changed = env->vfp.xregs[ARM_VFP_FPSCR]; 9525 env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff); 9526 env->vfp.vec_len = (val >> 16) & 7; 9527 env->vfp.vec_stride = (val >> 20) & 3; 9528 9529 changed ^= val; 9530 if (changed & (3 << 22)) { 9531 i = (val >> 22) & 3; 9532 switch (i) { 9533 case FPROUNDING_TIEEVEN: 9534 i = float_round_nearest_even; 9535 break; 9536 case FPROUNDING_POSINF: 9537 i = float_round_up; 9538 break; 9539 case FPROUNDING_NEGINF: 9540 i = float_round_down; 9541 break; 9542 case FPROUNDING_ZERO: 9543 i = float_round_to_zero; 9544 break; 9545 } 9546 set_float_rounding_mode(i, &env->vfp.fp_status); 9547 } 9548 if (changed & (1 << 24)) { 9549 set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status); 9550 set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status); 9551 } 9552 if (changed & (1 << 25)) 9553 set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status); 9554 9555 i = vfp_exceptbits_to_host(val); 9556 set_float_exception_flags(i, &env->vfp.fp_status); 9557 set_float_exception_flags(0, &env->vfp.standard_fp_status); 9558 } 9559 9560 void vfp_set_fpscr(CPUARMState *env, uint32_t val) 9561 { 9562 HELPER(vfp_set_fpscr)(env, val); 9563 } 9564 9565 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p)) 9566 9567 #define VFP_BINOP(name) \ 9568 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \ 9569 { \ 9570 float_status *fpst = fpstp; \ 9571 return float32_ ## name(a, b, fpst); \ 9572 } \ 9573 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \ 9574 { \ 9575 float_status *fpst = fpstp; \ 9576 return float64_ ## name(a, b, fpst); \ 9577 } 9578 VFP_BINOP(add) 9579 VFP_BINOP(sub) 9580 VFP_BINOP(mul) 9581 VFP_BINOP(div) 9582 VFP_BINOP(min) 9583 VFP_BINOP(max) 9584 VFP_BINOP(minnum) 9585 VFP_BINOP(maxnum) 9586 #undef VFP_BINOP 9587 9588 float32 VFP_HELPER(neg, s)(float32 a) 9589 { 9590 return float32_chs(a); 9591 } 9592 9593 float64 VFP_HELPER(neg, d)(float64 a) 9594 { 9595 return float64_chs(a); 9596 } 9597 9598 float32 VFP_HELPER(abs, s)(float32 a) 9599 { 9600 return float32_abs(a); 9601 } 9602 9603 float64 VFP_HELPER(abs, d)(float64 a) 9604 { 9605 return float64_abs(a); 9606 } 9607 9608 float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env) 9609 { 9610 return float32_sqrt(a, &env->vfp.fp_status); 9611 } 9612 9613 float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env) 9614 { 9615 return float64_sqrt(a, &env->vfp.fp_status); 9616 } 9617 9618 /* XXX: check quiet/signaling case */ 9619 #define DO_VFP_cmp(p, type) \ 9620 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \ 9621 { \ 9622 uint32_t flags; \ 9623 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \ 9624 case 0: flags = 0x6; break; \ 9625 case -1: flags = 0x8; break; \ 9626 case 1: flags = 0x2; break; \ 9627 default: case 2: flags = 0x3; break; \ 9628 } \ 9629 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \ 9630 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \ 9631 } \ 9632 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \ 9633 { \ 9634 uint32_t flags; \ 9635 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \ 9636 case 0: flags = 0x6; break; \ 9637 case -1: flags = 0x8; break; \ 9638 case 1: flags = 0x2; break; \ 9639 default: case 2: flags = 0x3; break; \ 9640 } \ 9641 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \ 9642 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \ 9643 } 9644 DO_VFP_cmp(s, float32) 9645 DO_VFP_cmp(d, float64) 9646 #undef DO_VFP_cmp 9647 9648 /* Integer to float and float to integer conversions */ 9649 9650 #define CONV_ITOF(name, fsz, sign) \ 9651 float##fsz HELPER(name)(uint32_t x, void *fpstp) \ 9652 { \ 9653 float_status *fpst = fpstp; \ 9654 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \ 9655 } 9656 9657 #define CONV_FTOI(name, fsz, sign, round) \ 9658 uint32_t HELPER(name)(float##fsz x, void *fpstp) \ 9659 { \ 9660 float_status *fpst = fpstp; \ 9661 if (float##fsz##_is_any_nan(x)) { \ 9662 float_raise(float_flag_invalid, fpst); \ 9663 return 0; \ 9664 } \ 9665 return float##fsz##_to_##sign##int32##round(x, fpst); \ 9666 } 9667 9668 #define FLOAT_CONVS(name, p, fsz, sign) \ 9669 CONV_ITOF(vfp_##name##to##p, fsz, sign) \ 9670 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \ 9671 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero) 9672 9673 FLOAT_CONVS(si, s, 32, ) 9674 FLOAT_CONVS(si, d, 64, ) 9675 FLOAT_CONVS(ui, s, 32, u) 9676 FLOAT_CONVS(ui, d, 64, u) 9677 9678 #undef CONV_ITOF 9679 #undef CONV_FTOI 9680 #undef FLOAT_CONVS 9681 9682 /* floating point conversion */ 9683 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env) 9684 { 9685 float64 r = float32_to_float64(x, &env->vfp.fp_status); 9686 /* ARM requires that S<->D conversion of any kind of NaN generates 9687 * a quiet NaN by forcing the most significant frac bit to 1. 9688 */ 9689 return float64_maybe_silence_nan(r, &env->vfp.fp_status); 9690 } 9691 9692 float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env) 9693 { 9694 float32 r = float64_to_float32(x, &env->vfp.fp_status); 9695 /* ARM requires that S<->D conversion of any kind of NaN generates 9696 * a quiet NaN by forcing the most significant frac bit to 1. 9697 */ 9698 return float32_maybe_silence_nan(r, &env->vfp.fp_status); 9699 } 9700 9701 /* VFP3 fixed point conversion. */ 9702 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \ 9703 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \ 9704 void *fpstp) \ 9705 { \ 9706 float_status *fpst = fpstp; \ 9707 float##fsz tmp; \ 9708 tmp = itype##_to_##float##fsz(x, fpst); \ 9709 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \ 9710 } 9711 9712 /* Notice that we want only input-denormal exception flags from the 9713 * scalbn operation: the other possible flags (overflow+inexact if 9714 * we overflow to infinity, output-denormal) aren't correct for the 9715 * complete scale-and-convert operation. 9716 */ 9717 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \ 9718 uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \ 9719 uint32_t shift, \ 9720 void *fpstp) \ 9721 { \ 9722 float_status *fpst = fpstp; \ 9723 int old_exc_flags = get_float_exception_flags(fpst); \ 9724 float##fsz tmp; \ 9725 if (float##fsz##_is_any_nan(x)) { \ 9726 float_raise(float_flag_invalid, fpst); \ 9727 return 0; \ 9728 } \ 9729 tmp = float##fsz##_scalbn(x, shift, fpst); \ 9730 old_exc_flags |= get_float_exception_flags(fpst) \ 9731 & float_flag_input_denormal; \ 9732 set_float_exception_flags(old_exc_flags, fpst); \ 9733 return float##fsz##_to_##itype##round(tmp, fpst); \ 9734 } 9735 9736 #define VFP_CONV_FIX(name, p, fsz, isz, itype) \ 9737 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \ 9738 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \ 9739 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, ) 9740 9741 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype) \ 9742 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \ 9743 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, ) 9744 9745 VFP_CONV_FIX(sh, d, 64, 64, int16) 9746 VFP_CONV_FIX(sl, d, 64, 64, int32) 9747 VFP_CONV_FIX_A64(sq, d, 64, 64, int64) 9748 VFP_CONV_FIX(uh, d, 64, 64, uint16) 9749 VFP_CONV_FIX(ul, d, 64, 64, uint32) 9750 VFP_CONV_FIX_A64(uq, d, 64, 64, uint64) 9751 VFP_CONV_FIX(sh, s, 32, 32, int16) 9752 VFP_CONV_FIX(sl, s, 32, 32, int32) 9753 VFP_CONV_FIX_A64(sq, s, 32, 64, int64) 9754 VFP_CONV_FIX(uh, s, 32, 32, uint16) 9755 VFP_CONV_FIX(ul, s, 32, 32, uint32) 9756 VFP_CONV_FIX_A64(uq, s, 32, 64, uint64) 9757 #undef VFP_CONV_FIX 9758 #undef VFP_CONV_FIX_FLOAT 9759 #undef VFP_CONV_FLOAT_FIX_ROUND 9760 9761 /* Set the current fp rounding mode and return the old one. 9762 * The argument is a softfloat float_round_ value. 9763 */ 9764 uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env) 9765 { 9766 float_status *fp_status = &env->vfp.fp_status; 9767 9768 uint32_t prev_rmode = get_float_rounding_mode(fp_status); 9769 set_float_rounding_mode(rmode, fp_status); 9770 9771 return prev_rmode; 9772 } 9773 9774 /* Set the current fp rounding mode in the standard fp status and return 9775 * the old one. This is for NEON instructions that need to change the 9776 * rounding mode but wish to use the standard FPSCR values for everything 9777 * else. Always set the rounding mode back to the correct value after 9778 * modifying it. 9779 * The argument is a softfloat float_round_ value. 9780 */ 9781 uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env) 9782 { 9783 float_status *fp_status = &env->vfp.standard_fp_status; 9784 9785 uint32_t prev_rmode = get_float_rounding_mode(fp_status); 9786 set_float_rounding_mode(rmode, fp_status); 9787 9788 return prev_rmode; 9789 } 9790 9791 /* Half precision conversions. */ 9792 static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s) 9793 { 9794 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; 9795 float32 r = float16_to_float32(make_float16(a), ieee, s); 9796 if (ieee) { 9797 return float32_maybe_silence_nan(r, s); 9798 } 9799 return r; 9800 } 9801 9802 static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s) 9803 { 9804 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; 9805 float16 r = float32_to_float16(a, ieee, s); 9806 if (ieee) { 9807 r = float16_maybe_silence_nan(r, s); 9808 } 9809 return float16_val(r); 9810 } 9811 9812 float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env) 9813 { 9814 return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status); 9815 } 9816 9817 uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env) 9818 { 9819 return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status); 9820 } 9821 9822 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env) 9823 { 9824 return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status); 9825 } 9826 9827 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env) 9828 { 9829 return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status); 9830 } 9831 9832 float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env) 9833 { 9834 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; 9835 float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status); 9836 if (ieee) { 9837 return float64_maybe_silence_nan(r, &env->vfp.fp_status); 9838 } 9839 return r; 9840 } 9841 9842 uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env) 9843 { 9844 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; 9845 float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status); 9846 if (ieee) { 9847 r = float16_maybe_silence_nan(r, &env->vfp.fp_status); 9848 } 9849 return float16_val(r); 9850 } 9851 9852 #define float32_two make_float32(0x40000000) 9853 #define float32_three make_float32(0x40400000) 9854 #define float32_one_point_five make_float32(0x3fc00000) 9855 9856 float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env) 9857 { 9858 float_status *s = &env->vfp.standard_fp_status; 9859 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) || 9860 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) { 9861 if (!(float32_is_zero(a) || float32_is_zero(b))) { 9862 float_raise(float_flag_input_denormal, s); 9863 } 9864 return float32_two; 9865 } 9866 return float32_sub(float32_two, float32_mul(a, b, s), s); 9867 } 9868 9869 float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env) 9870 { 9871 float_status *s = &env->vfp.standard_fp_status; 9872 float32 product; 9873 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) || 9874 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) { 9875 if (!(float32_is_zero(a) || float32_is_zero(b))) { 9876 float_raise(float_flag_input_denormal, s); 9877 } 9878 return float32_one_point_five; 9879 } 9880 product = float32_mul(a, b, s); 9881 return float32_div(float32_sub(float32_three, product, s), float32_two, s); 9882 } 9883 9884 /* NEON helpers. */ 9885 9886 /* Constants 256 and 512 are used in some helpers; we avoid relying on 9887 * int->float conversions at run-time. */ 9888 #define float64_256 make_float64(0x4070000000000000LL) 9889 #define float64_512 make_float64(0x4080000000000000LL) 9890 #define float32_maxnorm make_float32(0x7f7fffff) 9891 #define float64_maxnorm make_float64(0x7fefffffffffffffLL) 9892 9893 /* Reciprocal functions 9894 * 9895 * The algorithm that must be used to calculate the estimate 9896 * is specified by the ARM ARM, see FPRecipEstimate() 9897 */ 9898 9899 static float64 recip_estimate(float64 a, float_status *real_fp_status) 9900 { 9901 /* These calculations mustn't set any fp exception flags, 9902 * so we use a local copy of the fp_status. 9903 */ 9904 float_status dummy_status = *real_fp_status; 9905 float_status *s = &dummy_status; 9906 /* q = (int)(a * 512.0) */ 9907 float64 q = float64_mul(float64_512, a, s); 9908 int64_t q_int = float64_to_int64_round_to_zero(q, s); 9909 9910 /* r = 1.0 / (((double)q + 0.5) / 512.0) */ 9911 q = int64_to_float64(q_int, s); 9912 q = float64_add(q, float64_half, s); 9913 q = float64_div(q, float64_512, s); 9914 q = float64_div(float64_one, q, s); 9915 9916 /* s = (int)(256.0 * r + 0.5) */ 9917 q = float64_mul(q, float64_256, s); 9918 q = float64_add(q, float64_half, s); 9919 q_int = float64_to_int64_round_to_zero(q, s); 9920 9921 /* return (double)s / 256.0 */ 9922 return float64_div(int64_to_float64(q_int, s), float64_256, s); 9923 } 9924 9925 /* Common wrapper to call recip_estimate */ 9926 static float64 call_recip_estimate(float64 num, int off, float_status *fpst) 9927 { 9928 uint64_t val64 = float64_val(num); 9929 uint64_t frac = extract64(val64, 0, 52); 9930 int64_t exp = extract64(val64, 52, 11); 9931 uint64_t sbit; 9932 float64 scaled, estimate; 9933 9934 /* Generate the scaled number for the estimate function */ 9935 if (exp == 0) { 9936 if (extract64(frac, 51, 1) == 0) { 9937 exp = -1; 9938 frac = extract64(frac, 0, 50) << 2; 9939 } else { 9940 frac = extract64(frac, 0, 51) << 1; 9941 } 9942 } 9943 9944 /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */ 9945 scaled = make_float64((0x3feULL << 52) 9946 | extract64(frac, 44, 8) << 44); 9947 9948 estimate = recip_estimate(scaled, fpst); 9949 9950 /* Build new result */ 9951 val64 = float64_val(estimate); 9952 sbit = 0x8000000000000000ULL & val64; 9953 exp = off - exp; 9954 frac = extract64(val64, 0, 52); 9955 9956 if (exp == 0) { 9957 frac = 1ULL << 51 | extract64(frac, 1, 51); 9958 } else if (exp == -1) { 9959 frac = 1ULL << 50 | extract64(frac, 2, 50); 9960 exp = 0; 9961 } 9962 9963 return make_float64(sbit | (exp << 52) | frac); 9964 } 9965 9966 static bool round_to_inf(float_status *fpst, bool sign_bit) 9967 { 9968 switch (fpst->float_rounding_mode) { 9969 case float_round_nearest_even: /* Round to Nearest */ 9970 return true; 9971 case float_round_up: /* Round to +Inf */ 9972 return !sign_bit; 9973 case float_round_down: /* Round to -Inf */ 9974 return sign_bit; 9975 case float_round_to_zero: /* Round to Zero */ 9976 return false; 9977 } 9978 9979 g_assert_not_reached(); 9980 } 9981 9982 float32 HELPER(recpe_f32)(float32 input, void *fpstp) 9983 { 9984 float_status *fpst = fpstp; 9985 float32 f32 = float32_squash_input_denormal(input, fpst); 9986 uint32_t f32_val = float32_val(f32); 9987 uint32_t f32_sbit = 0x80000000ULL & f32_val; 9988 int32_t f32_exp = extract32(f32_val, 23, 8); 9989 uint32_t f32_frac = extract32(f32_val, 0, 23); 9990 float64 f64, r64; 9991 uint64_t r64_val; 9992 int64_t r64_exp; 9993 uint64_t r64_frac; 9994 9995 if (float32_is_any_nan(f32)) { 9996 float32 nan = f32; 9997 if (float32_is_signaling_nan(f32, fpst)) { 9998 float_raise(float_flag_invalid, fpst); 9999 nan = float32_maybe_silence_nan(f32, fpst); 10000 } 10001 if (fpst->default_nan_mode) { 10002 nan = float32_default_nan(fpst); 10003 } 10004 return nan; 10005 } else if (float32_is_infinity(f32)) { 10006 return float32_set_sign(float32_zero, float32_is_neg(f32)); 10007 } else if (float32_is_zero(f32)) { 10008 float_raise(float_flag_divbyzero, fpst); 10009 return float32_set_sign(float32_infinity, float32_is_neg(f32)); 10010 } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) { 10011 /* Abs(value) < 2.0^-128 */ 10012 float_raise(float_flag_overflow | float_flag_inexact, fpst); 10013 if (round_to_inf(fpst, f32_sbit)) { 10014 return float32_set_sign(float32_infinity, float32_is_neg(f32)); 10015 } else { 10016 return float32_set_sign(float32_maxnorm, float32_is_neg(f32)); 10017 } 10018 } else if (f32_exp >= 253 && fpst->flush_to_zero) { 10019 float_raise(float_flag_underflow, fpst); 10020 return float32_set_sign(float32_zero, float32_is_neg(f32)); 10021 } 10022 10023 10024 f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29); 10025 r64 = call_recip_estimate(f64, 253, fpst); 10026 r64_val = float64_val(r64); 10027 r64_exp = extract64(r64_val, 52, 11); 10028 r64_frac = extract64(r64_val, 0, 52); 10029 10030 /* result = sign : result_exp<7:0> : fraction<51:29>; */ 10031 return make_float32(f32_sbit | 10032 (r64_exp & 0xff) << 23 | 10033 extract64(r64_frac, 29, 24)); 10034 } 10035 10036 float64 HELPER(recpe_f64)(float64 input, void *fpstp) 10037 { 10038 float_status *fpst = fpstp; 10039 float64 f64 = float64_squash_input_denormal(input, fpst); 10040 uint64_t f64_val = float64_val(f64); 10041 uint64_t f64_sbit = 0x8000000000000000ULL & f64_val; 10042 int64_t f64_exp = extract64(f64_val, 52, 11); 10043 float64 r64; 10044 uint64_t r64_val; 10045 int64_t r64_exp; 10046 uint64_t r64_frac; 10047 10048 /* Deal with any special cases */ 10049 if (float64_is_any_nan(f64)) { 10050 float64 nan = f64; 10051 if (float64_is_signaling_nan(f64, fpst)) { 10052 float_raise(float_flag_invalid, fpst); 10053 nan = float64_maybe_silence_nan(f64, fpst); 10054 } 10055 if (fpst->default_nan_mode) { 10056 nan = float64_default_nan(fpst); 10057 } 10058 return nan; 10059 } else if (float64_is_infinity(f64)) { 10060 return float64_set_sign(float64_zero, float64_is_neg(f64)); 10061 } else if (float64_is_zero(f64)) { 10062 float_raise(float_flag_divbyzero, fpst); 10063 return float64_set_sign(float64_infinity, float64_is_neg(f64)); 10064 } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) { 10065 /* Abs(value) < 2.0^-1024 */ 10066 float_raise(float_flag_overflow | float_flag_inexact, fpst); 10067 if (round_to_inf(fpst, f64_sbit)) { 10068 return float64_set_sign(float64_infinity, float64_is_neg(f64)); 10069 } else { 10070 return float64_set_sign(float64_maxnorm, float64_is_neg(f64)); 10071 } 10072 } else if (f64_exp >= 2045 && fpst->flush_to_zero) { 10073 float_raise(float_flag_underflow, fpst); 10074 return float64_set_sign(float64_zero, float64_is_neg(f64)); 10075 } 10076 10077 r64 = call_recip_estimate(f64, 2045, fpst); 10078 r64_val = float64_val(r64); 10079 r64_exp = extract64(r64_val, 52, 11); 10080 r64_frac = extract64(r64_val, 0, 52); 10081 10082 /* result = sign : result_exp<10:0> : fraction<51:0> */ 10083 return make_float64(f64_sbit | 10084 ((r64_exp & 0x7ff) << 52) | 10085 r64_frac); 10086 } 10087 10088 /* The algorithm that must be used to calculate the estimate 10089 * is specified by the ARM ARM. 10090 */ 10091 static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status) 10092 { 10093 /* These calculations mustn't set any fp exception flags, 10094 * so we use a local copy of the fp_status. 10095 */ 10096 float_status dummy_status = *real_fp_status; 10097 float_status *s = &dummy_status; 10098 float64 q; 10099 int64_t q_int; 10100 10101 if (float64_lt(a, float64_half, s)) { 10102 /* range 0.25 <= a < 0.5 */ 10103 10104 /* a in units of 1/512 rounded down */ 10105 /* q0 = (int)(a * 512.0); */ 10106 q = float64_mul(float64_512, a, s); 10107 q_int = float64_to_int64_round_to_zero(q, s); 10108 10109 /* reciprocal root r */ 10110 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */ 10111 q = int64_to_float64(q_int, s); 10112 q = float64_add(q, float64_half, s); 10113 q = float64_div(q, float64_512, s); 10114 q = float64_sqrt(q, s); 10115 q = float64_div(float64_one, q, s); 10116 } else { 10117 /* range 0.5 <= a < 1.0 */ 10118 10119 /* a in units of 1/256 rounded down */ 10120 /* q1 = (int)(a * 256.0); */ 10121 q = float64_mul(float64_256, a, s); 10122 int64_t q_int = float64_to_int64_round_to_zero(q, s); 10123 10124 /* reciprocal root r */ 10125 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */ 10126 q = int64_to_float64(q_int, s); 10127 q = float64_add(q, float64_half, s); 10128 q = float64_div(q, float64_256, s); 10129 q = float64_sqrt(q, s); 10130 q = float64_div(float64_one, q, s); 10131 } 10132 /* r in units of 1/256 rounded to nearest */ 10133 /* s = (int)(256.0 * r + 0.5); */ 10134 10135 q = float64_mul(q, float64_256,s ); 10136 q = float64_add(q, float64_half, s); 10137 q_int = float64_to_int64_round_to_zero(q, s); 10138 10139 /* return (double)s / 256.0;*/ 10140 return float64_div(int64_to_float64(q_int, s), float64_256, s); 10141 } 10142 10143 float32 HELPER(rsqrte_f32)(float32 input, void *fpstp) 10144 { 10145 float_status *s = fpstp; 10146 float32 f32 = float32_squash_input_denormal(input, s); 10147 uint32_t val = float32_val(f32); 10148 uint32_t f32_sbit = 0x80000000 & val; 10149 int32_t f32_exp = extract32(val, 23, 8); 10150 uint32_t f32_frac = extract32(val, 0, 23); 10151 uint64_t f64_frac; 10152 uint64_t val64; 10153 int result_exp; 10154 float64 f64; 10155 10156 if (float32_is_any_nan(f32)) { 10157 float32 nan = f32; 10158 if (float32_is_signaling_nan(f32, s)) { 10159 float_raise(float_flag_invalid, s); 10160 nan = float32_maybe_silence_nan(f32, s); 10161 } 10162 if (s->default_nan_mode) { 10163 nan = float32_default_nan(s); 10164 } 10165 return nan; 10166 } else if (float32_is_zero(f32)) { 10167 float_raise(float_flag_divbyzero, s); 10168 return float32_set_sign(float32_infinity, float32_is_neg(f32)); 10169 } else if (float32_is_neg(f32)) { 10170 float_raise(float_flag_invalid, s); 10171 return float32_default_nan(s); 10172 } else if (float32_is_infinity(f32)) { 10173 return float32_zero; 10174 } 10175 10176 /* Scale and normalize to a double-precision value between 0.25 and 1.0, 10177 * preserving the parity of the exponent. */ 10178 10179 f64_frac = ((uint64_t) f32_frac) << 29; 10180 if (f32_exp == 0) { 10181 while (extract64(f64_frac, 51, 1) == 0) { 10182 f64_frac = f64_frac << 1; 10183 f32_exp = f32_exp-1; 10184 } 10185 f64_frac = extract64(f64_frac, 0, 51) << 1; 10186 } 10187 10188 if (extract64(f32_exp, 0, 1) == 0) { 10189 f64 = make_float64(((uint64_t) f32_sbit) << 32 10190 | (0x3feULL << 52) 10191 | f64_frac); 10192 } else { 10193 f64 = make_float64(((uint64_t) f32_sbit) << 32 10194 | (0x3fdULL << 52) 10195 | f64_frac); 10196 } 10197 10198 result_exp = (380 - f32_exp) / 2; 10199 10200 f64 = recip_sqrt_estimate(f64, s); 10201 10202 val64 = float64_val(f64); 10203 10204 val = ((result_exp & 0xff) << 23) 10205 | ((val64 >> 29) & 0x7fffff); 10206 return make_float32(val); 10207 } 10208 10209 float64 HELPER(rsqrte_f64)(float64 input, void *fpstp) 10210 { 10211 float_status *s = fpstp; 10212 float64 f64 = float64_squash_input_denormal(input, s); 10213 uint64_t val = float64_val(f64); 10214 uint64_t f64_sbit = 0x8000000000000000ULL & val; 10215 int64_t f64_exp = extract64(val, 52, 11); 10216 uint64_t f64_frac = extract64(val, 0, 52); 10217 int64_t result_exp; 10218 uint64_t result_frac; 10219 10220 if (float64_is_any_nan(f64)) { 10221 float64 nan = f64; 10222 if (float64_is_signaling_nan(f64, s)) { 10223 float_raise(float_flag_invalid, s); 10224 nan = float64_maybe_silence_nan(f64, s); 10225 } 10226 if (s->default_nan_mode) { 10227 nan = float64_default_nan(s); 10228 } 10229 return nan; 10230 } else if (float64_is_zero(f64)) { 10231 float_raise(float_flag_divbyzero, s); 10232 return float64_set_sign(float64_infinity, float64_is_neg(f64)); 10233 } else if (float64_is_neg(f64)) { 10234 float_raise(float_flag_invalid, s); 10235 return float64_default_nan(s); 10236 } else if (float64_is_infinity(f64)) { 10237 return float64_zero; 10238 } 10239 10240 /* Scale and normalize to a double-precision value between 0.25 and 1.0, 10241 * preserving the parity of the exponent. */ 10242 10243 if (f64_exp == 0) { 10244 while (extract64(f64_frac, 51, 1) == 0) { 10245 f64_frac = f64_frac << 1; 10246 f64_exp = f64_exp - 1; 10247 } 10248 f64_frac = extract64(f64_frac, 0, 51) << 1; 10249 } 10250 10251 if (extract64(f64_exp, 0, 1) == 0) { 10252 f64 = make_float64(f64_sbit 10253 | (0x3feULL << 52) 10254 | f64_frac); 10255 } else { 10256 f64 = make_float64(f64_sbit 10257 | (0x3fdULL << 52) 10258 | f64_frac); 10259 } 10260 10261 result_exp = (3068 - f64_exp) / 2; 10262 10263 f64 = recip_sqrt_estimate(f64, s); 10264 10265 result_frac = extract64(float64_val(f64), 0, 52); 10266 10267 return make_float64(f64_sbit | 10268 ((result_exp & 0x7ff) << 52) | 10269 result_frac); 10270 } 10271 10272 uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp) 10273 { 10274 float_status *s = fpstp; 10275 float64 f64; 10276 10277 if ((a & 0x80000000) == 0) { 10278 return 0xffffffff; 10279 } 10280 10281 f64 = make_float64((0x3feULL << 52) 10282 | ((int64_t)(a & 0x7fffffff) << 21)); 10283 10284 f64 = recip_estimate(f64, s); 10285 10286 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff); 10287 } 10288 10289 uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp) 10290 { 10291 float_status *fpst = fpstp; 10292 float64 f64; 10293 10294 if ((a & 0xc0000000) == 0) { 10295 return 0xffffffff; 10296 } 10297 10298 if (a & 0x80000000) { 10299 f64 = make_float64((0x3feULL << 52) 10300 | ((uint64_t)(a & 0x7fffffff) << 21)); 10301 } else { /* bits 31-30 == '01' */ 10302 f64 = make_float64((0x3fdULL << 52) 10303 | ((uint64_t)(a & 0x3fffffff) << 22)); 10304 } 10305 10306 f64 = recip_sqrt_estimate(f64, fpst); 10307 10308 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff); 10309 } 10310 10311 /* VFPv4 fused multiply-accumulate */ 10312 float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp) 10313 { 10314 float_status *fpst = fpstp; 10315 return float32_muladd(a, b, c, 0, fpst); 10316 } 10317 10318 float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp) 10319 { 10320 float_status *fpst = fpstp; 10321 return float64_muladd(a, b, c, 0, fpst); 10322 } 10323 10324 /* ARMv8 round to integral */ 10325 float32 HELPER(rints_exact)(float32 x, void *fp_status) 10326 { 10327 return float32_round_to_int(x, fp_status); 10328 } 10329 10330 float64 HELPER(rintd_exact)(float64 x, void *fp_status) 10331 { 10332 return float64_round_to_int(x, fp_status); 10333 } 10334 10335 float32 HELPER(rints)(float32 x, void *fp_status) 10336 { 10337 int old_flags = get_float_exception_flags(fp_status), new_flags; 10338 float32 ret; 10339 10340 ret = float32_round_to_int(x, fp_status); 10341 10342 /* Suppress any inexact exceptions the conversion produced */ 10343 if (!(old_flags & float_flag_inexact)) { 10344 new_flags = get_float_exception_flags(fp_status); 10345 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); 10346 } 10347 10348 return ret; 10349 } 10350 10351 float64 HELPER(rintd)(float64 x, void *fp_status) 10352 { 10353 int old_flags = get_float_exception_flags(fp_status), new_flags; 10354 float64 ret; 10355 10356 ret = float64_round_to_int(x, fp_status); 10357 10358 new_flags = get_float_exception_flags(fp_status); 10359 10360 /* Suppress any inexact exceptions the conversion produced */ 10361 if (!(old_flags & float_flag_inexact)) { 10362 new_flags = get_float_exception_flags(fp_status); 10363 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); 10364 } 10365 10366 return ret; 10367 } 10368 10369 /* Convert ARM rounding mode to softfloat */ 10370 int arm_rmode_to_sf(int rmode) 10371 { 10372 switch (rmode) { 10373 case FPROUNDING_TIEAWAY: 10374 rmode = float_round_ties_away; 10375 break; 10376 case FPROUNDING_ODD: 10377 /* FIXME: add support for TIEAWAY and ODD */ 10378 qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n", 10379 rmode); 10380 case FPROUNDING_TIEEVEN: 10381 default: 10382 rmode = float_round_nearest_even; 10383 break; 10384 case FPROUNDING_POSINF: 10385 rmode = float_round_up; 10386 break; 10387 case FPROUNDING_NEGINF: 10388 rmode = float_round_down; 10389 break; 10390 case FPROUNDING_ZERO: 10391 rmode = float_round_to_zero; 10392 break; 10393 } 10394 return rmode; 10395 } 10396 10397 /* CRC helpers. 10398 * The upper bytes of val (above the number specified by 'bytes') must have 10399 * been zeroed out by the caller. 10400 */ 10401 uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes) 10402 { 10403 uint8_t buf[4]; 10404 10405 stl_le_p(buf, val); 10406 10407 /* zlib crc32 converts the accumulator and output to one's complement. */ 10408 return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff; 10409 } 10410 10411 uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes) 10412 { 10413 uint8_t buf[4]; 10414 10415 stl_le_p(buf, val); 10416 10417 /* Linux crc32c converts the output to one's complement. */ 10418 return crc32c(acc, buf, bytes) ^ 0xffffffff; 10419 } 10420