1 #include "qemu/osdep.h" 2 #include "trace.h" 3 #include "cpu.h" 4 #include "internals.h" 5 #include "exec/gdbstub.h" 6 #include "exec/helper-proto.h" 7 #include "qemu/host-utils.h" 8 #include "sysemu/arch_init.h" 9 #include "sysemu/sysemu.h" 10 #include "qemu/bitops.h" 11 #include "qemu/crc32c.h" 12 #include "exec/exec-all.h" 13 #include "exec/cpu_ldst.h" 14 #include "arm_ldst.h" 15 #include <zlib.h> /* For crc32 */ 16 #include "exec/semihost.h" 17 #include "sysemu/kvm.h" 18 19 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ 20 21 #ifndef CONFIG_USER_ONLY 22 static bool get_phys_addr(CPUARMState *env, target_ulong address, 23 int access_type, ARMMMUIdx mmu_idx, 24 hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, 25 target_ulong *page_size, uint32_t *fsr, 26 ARMMMUFaultInfo *fi); 27 28 static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, 29 int access_type, ARMMMUIdx mmu_idx, 30 hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, 31 target_ulong *page_size_ptr, uint32_t *fsr, 32 ARMMMUFaultInfo *fi); 33 34 /* Definitions for the PMCCNTR and PMCR registers */ 35 #define PMCRD 0x8 36 #define PMCRC 0x4 37 #define PMCRE 0x1 38 #endif 39 40 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) 41 { 42 int nregs; 43 44 /* VFP data registers are always little-endian. */ 45 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; 46 if (reg < nregs) { 47 stfq_le_p(buf, env->vfp.regs[reg]); 48 return 8; 49 } 50 if (arm_feature(env, ARM_FEATURE_NEON)) { 51 /* Aliases for Q regs. */ 52 nregs += 16; 53 if (reg < nregs) { 54 stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]); 55 stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]); 56 return 16; 57 } 58 } 59 switch (reg - nregs) { 60 case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4; 61 case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4; 62 case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4; 63 } 64 return 0; 65 } 66 67 static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) 68 { 69 int nregs; 70 71 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; 72 if (reg < nregs) { 73 env->vfp.regs[reg] = ldfq_le_p(buf); 74 return 8; 75 } 76 if (arm_feature(env, ARM_FEATURE_NEON)) { 77 nregs += 16; 78 if (reg < nregs) { 79 env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf); 80 env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8); 81 return 16; 82 } 83 } 84 switch (reg - nregs) { 85 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4; 86 case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4; 87 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4; 88 } 89 return 0; 90 } 91 92 static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) 93 { 94 switch (reg) { 95 case 0 ... 31: 96 /* 128 bit FP register */ 97 stfq_le_p(buf, env->vfp.regs[reg * 2]); 98 stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]); 99 return 16; 100 case 32: 101 /* FPSR */ 102 stl_p(buf, vfp_get_fpsr(env)); 103 return 4; 104 case 33: 105 /* FPCR */ 106 stl_p(buf, vfp_get_fpcr(env)); 107 return 4; 108 default: 109 return 0; 110 } 111 } 112 113 static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) 114 { 115 switch (reg) { 116 case 0 ... 31: 117 /* 128 bit FP register */ 118 env->vfp.regs[reg * 2] = ldfq_le_p(buf); 119 env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8); 120 return 16; 121 case 32: 122 /* FPSR */ 123 vfp_set_fpsr(env, ldl_p(buf)); 124 return 4; 125 case 33: 126 /* FPCR */ 127 vfp_set_fpcr(env, ldl_p(buf)); 128 return 4; 129 default: 130 return 0; 131 } 132 } 133 134 static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri) 135 { 136 assert(ri->fieldoffset); 137 if (cpreg_field_is_64bit(ri)) { 138 return CPREG_FIELD64(env, ri); 139 } else { 140 return CPREG_FIELD32(env, ri); 141 } 142 } 143 144 static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, 145 uint64_t value) 146 { 147 assert(ri->fieldoffset); 148 if (cpreg_field_is_64bit(ri)) { 149 CPREG_FIELD64(env, ri) = value; 150 } else { 151 CPREG_FIELD32(env, ri) = value; 152 } 153 } 154 155 static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri) 156 { 157 return (char *)env + ri->fieldoffset; 158 } 159 160 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri) 161 { 162 /* Raw read of a coprocessor register (as needed for migration, etc). */ 163 if (ri->type & ARM_CP_CONST) { 164 return ri->resetvalue; 165 } else if (ri->raw_readfn) { 166 return ri->raw_readfn(env, ri); 167 } else if (ri->readfn) { 168 return ri->readfn(env, ri); 169 } else { 170 return raw_read(env, ri); 171 } 172 } 173 174 static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri, 175 uint64_t v) 176 { 177 /* Raw write of a coprocessor register (as needed for migration, etc). 178 * Note that constant registers are treated as write-ignored; the 179 * caller should check for success by whether a readback gives the 180 * value written. 181 */ 182 if (ri->type & ARM_CP_CONST) { 183 return; 184 } else if (ri->raw_writefn) { 185 ri->raw_writefn(env, ri, v); 186 } else if (ri->writefn) { 187 ri->writefn(env, ri, v); 188 } else { 189 raw_write(env, ri, v); 190 } 191 } 192 193 static bool raw_accessors_invalid(const ARMCPRegInfo *ri) 194 { 195 /* Return true if the regdef would cause an assertion if you called 196 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a 197 * program bug for it not to have the NO_RAW flag). 198 * NB that returning false here doesn't necessarily mean that calling 199 * read/write_raw_cp_reg() is safe, because we can't distinguish "has 200 * read/write access functions which are safe for raw use" from "has 201 * read/write access functions which have side effects but has forgotten 202 * to provide raw access functions". 203 * The tests here line up with the conditions in read/write_raw_cp_reg() 204 * and assertions in raw_read()/raw_write(). 205 */ 206 if ((ri->type & ARM_CP_CONST) || 207 ri->fieldoffset || 208 ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) { 209 return false; 210 } 211 return true; 212 } 213 214 bool write_cpustate_to_list(ARMCPU *cpu) 215 { 216 /* Write the coprocessor state from cpu->env to the (index,value) list. */ 217 int i; 218 bool ok = true; 219 220 for (i = 0; i < cpu->cpreg_array_len; i++) { 221 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); 222 const ARMCPRegInfo *ri; 223 224 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); 225 if (!ri) { 226 ok = false; 227 continue; 228 } 229 if (ri->type & ARM_CP_NO_RAW) { 230 continue; 231 } 232 cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri); 233 } 234 return ok; 235 } 236 237 bool write_list_to_cpustate(ARMCPU *cpu) 238 { 239 int i; 240 bool ok = true; 241 242 for (i = 0; i < cpu->cpreg_array_len; i++) { 243 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); 244 uint64_t v = cpu->cpreg_values[i]; 245 const ARMCPRegInfo *ri; 246 247 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); 248 if (!ri) { 249 ok = false; 250 continue; 251 } 252 if (ri->type & ARM_CP_NO_RAW) { 253 continue; 254 } 255 /* Write value and confirm it reads back as written 256 * (to catch read-only registers and partially read-only 257 * registers where the incoming migration value doesn't match) 258 */ 259 write_raw_cp_reg(&cpu->env, ri, v); 260 if (read_raw_cp_reg(&cpu->env, ri) != v) { 261 ok = false; 262 } 263 } 264 return ok; 265 } 266 267 static void add_cpreg_to_list(gpointer key, gpointer opaque) 268 { 269 ARMCPU *cpu = opaque; 270 uint64_t regidx; 271 const ARMCPRegInfo *ri; 272 273 regidx = *(uint32_t *)key; 274 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); 275 276 if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { 277 cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx); 278 /* The value array need not be initialized at this point */ 279 cpu->cpreg_array_len++; 280 } 281 } 282 283 static void count_cpreg(gpointer key, gpointer opaque) 284 { 285 ARMCPU *cpu = opaque; 286 uint64_t regidx; 287 const ARMCPRegInfo *ri; 288 289 regidx = *(uint32_t *)key; 290 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); 291 292 if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { 293 cpu->cpreg_array_len++; 294 } 295 } 296 297 static gint cpreg_key_compare(gconstpointer a, gconstpointer b) 298 { 299 uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a); 300 uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b); 301 302 if (aidx > bidx) { 303 return 1; 304 } 305 if (aidx < bidx) { 306 return -1; 307 } 308 return 0; 309 } 310 311 void init_cpreg_list(ARMCPU *cpu) 312 { 313 /* Initialise the cpreg_tuples[] array based on the cp_regs hash. 314 * Note that we require cpreg_tuples[] to be sorted by key ID. 315 */ 316 GList *keys; 317 int arraylen; 318 319 keys = g_hash_table_get_keys(cpu->cp_regs); 320 keys = g_list_sort(keys, cpreg_key_compare); 321 322 cpu->cpreg_array_len = 0; 323 324 g_list_foreach(keys, count_cpreg, cpu); 325 326 arraylen = cpu->cpreg_array_len; 327 cpu->cpreg_indexes = g_new(uint64_t, arraylen); 328 cpu->cpreg_values = g_new(uint64_t, arraylen); 329 cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen); 330 cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen); 331 cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len; 332 cpu->cpreg_array_len = 0; 333 334 g_list_foreach(keys, add_cpreg_to_list, cpu); 335 336 assert(cpu->cpreg_array_len == arraylen); 337 338 g_list_free(keys); 339 } 340 341 /* 342 * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but 343 * they are accessible when EL3 is using AArch64 regardless of EL3.NS. 344 * 345 * access_el3_aa32ns: Used to check AArch32 register views. 346 * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views. 347 */ 348 static CPAccessResult access_el3_aa32ns(CPUARMState *env, 349 const ARMCPRegInfo *ri, 350 bool isread) 351 { 352 bool secure = arm_is_secure_below_el3(env); 353 354 assert(!arm_el_is_aa64(env, 3)); 355 if (secure) { 356 return CP_ACCESS_TRAP_UNCATEGORIZED; 357 } 358 return CP_ACCESS_OK; 359 } 360 361 static CPAccessResult access_el3_aa32ns_aa64any(CPUARMState *env, 362 const ARMCPRegInfo *ri, 363 bool isread) 364 { 365 if (!arm_el_is_aa64(env, 3)) { 366 return access_el3_aa32ns(env, ri, isread); 367 } 368 return CP_ACCESS_OK; 369 } 370 371 /* Some secure-only AArch32 registers trap to EL3 if used from 372 * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts). 373 * Note that an access from Secure EL1 can only happen if EL3 is AArch64. 374 * We assume that the .access field is set to PL1_RW. 375 */ 376 static CPAccessResult access_trap_aa32s_el1(CPUARMState *env, 377 const ARMCPRegInfo *ri, 378 bool isread) 379 { 380 if (arm_current_el(env) == 3) { 381 return CP_ACCESS_OK; 382 } 383 if (arm_is_secure_below_el3(env)) { 384 return CP_ACCESS_TRAP_EL3; 385 } 386 /* This will be EL1 NS and EL2 NS, which just UNDEF */ 387 return CP_ACCESS_TRAP_UNCATEGORIZED; 388 } 389 390 /* Check for traps to "powerdown debug" registers, which are controlled 391 * by MDCR.TDOSA 392 */ 393 static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *ri, 394 bool isread) 395 { 396 int el = arm_current_el(env); 397 398 if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDOSA) 399 && !arm_is_secure_below_el3(env)) { 400 return CP_ACCESS_TRAP_EL2; 401 } 402 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDOSA)) { 403 return CP_ACCESS_TRAP_EL3; 404 } 405 return CP_ACCESS_OK; 406 } 407 408 /* Check for traps to "debug ROM" registers, which are controlled 409 * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3. 410 */ 411 static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri, 412 bool isread) 413 { 414 int el = arm_current_el(env); 415 416 if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDRA) 417 && !arm_is_secure_below_el3(env)) { 418 return CP_ACCESS_TRAP_EL2; 419 } 420 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { 421 return CP_ACCESS_TRAP_EL3; 422 } 423 return CP_ACCESS_OK; 424 } 425 426 /* Check for traps to general debug registers, which are controlled 427 * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3. 428 */ 429 static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri, 430 bool isread) 431 { 432 int el = arm_current_el(env); 433 434 if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDA) 435 && !arm_is_secure_below_el3(env)) { 436 return CP_ACCESS_TRAP_EL2; 437 } 438 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { 439 return CP_ACCESS_TRAP_EL3; 440 } 441 return CP_ACCESS_OK; 442 } 443 444 /* Check for traps to performance monitor registers, which are controlled 445 * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3. 446 */ 447 static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri, 448 bool isread) 449 { 450 int el = arm_current_el(env); 451 452 if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM) 453 && !arm_is_secure_below_el3(env)) { 454 return CP_ACCESS_TRAP_EL2; 455 } 456 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { 457 return CP_ACCESS_TRAP_EL3; 458 } 459 return CP_ACCESS_OK; 460 } 461 462 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) 463 { 464 ARMCPU *cpu = arm_env_get_cpu(env); 465 466 raw_write(env, ri, value); 467 tlb_flush(CPU(cpu)); /* Flush TLB as domain not tracked in TLB */ 468 } 469 470 static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) 471 { 472 ARMCPU *cpu = arm_env_get_cpu(env); 473 474 if (raw_read(env, ri) != value) { 475 /* Unlike real hardware the qemu TLB uses virtual addresses, 476 * not modified virtual addresses, so this causes a TLB flush. 477 */ 478 tlb_flush(CPU(cpu)); 479 raw_write(env, ri, value); 480 } 481 } 482 483 static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, 484 uint64_t value) 485 { 486 ARMCPU *cpu = arm_env_get_cpu(env); 487 488 if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_MPU) 489 && !extended_addresses_enabled(env)) { 490 /* For VMSA (when not using the LPAE long descriptor page table 491 * format) this register includes the ASID, so do a TLB flush. 492 * For PMSA it is purely a process ID and no action is needed. 493 */ 494 tlb_flush(CPU(cpu)); 495 } 496 raw_write(env, ri, value); 497 } 498 499 static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri, 500 uint64_t value) 501 { 502 /* Invalidate all (TLBIALL) */ 503 ARMCPU *cpu = arm_env_get_cpu(env); 504 505 tlb_flush(CPU(cpu)); 506 } 507 508 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, 509 uint64_t value) 510 { 511 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ 512 ARMCPU *cpu = arm_env_get_cpu(env); 513 514 tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); 515 } 516 517 static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, 518 uint64_t value) 519 { 520 /* Invalidate by ASID (TLBIASID) */ 521 ARMCPU *cpu = arm_env_get_cpu(env); 522 523 tlb_flush(CPU(cpu)); 524 } 525 526 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, 527 uint64_t value) 528 { 529 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ 530 ARMCPU *cpu = arm_env_get_cpu(env); 531 532 tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); 533 } 534 535 /* IS variants of TLB operations must affect all cores */ 536 static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri, 537 uint64_t value) 538 { 539 CPUState *cs = ENV_GET_CPU(env); 540 541 tlb_flush_all_cpus_synced(cs); 542 } 543 544 static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri, 545 uint64_t value) 546 { 547 CPUState *cs = ENV_GET_CPU(env); 548 549 tlb_flush_all_cpus_synced(cs); 550 } 551 552 static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri, 553 uint64_t value) 554 { 555 CPUState *cs = ENV_GET_CPU(env); 556 557 tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK); 558 } 559 560 static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri, 561 uint64_t value) 562 { 563 CPUState *cs = ENV_GET_CPU(env); 564 565 tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK); 566 } 567 568 static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri, 569 uint64_t value) 570 { 571 CPUState *cs = ENV_GET_CPU(env); 572 573 tlb_flush_by_mmuidx(cs, 574 (1 << ARMMMUIdx_S12NSE1) | 575 (1 << ARMMMUIdx_S12NSE0) | 576 (1 << ARMMMUIdx_S2NS)); 577 } 578 579 static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri, 580 uint64_t value) 581 { 582 CPUState *cs = ENV_GET_CPU(env); 583 584 tlb_flush_by_mmuidx_all_cpus_synced(cs, 585 (1 << ARMMMUIdx_S12NSE1) | 586 (1 << ARMMMUIdx_S12NSE0) | 587 (1 << ARMMMUIdx_S2NS)); 588 } 589 590 static void tlbiipas2_write(CPUARMState *env, const ARMCPRegInfo *ri, 591 uint64_t value) 592 { 593 /* Invalidate by IPA. This has to invalidate any structures that 594 * contain only stage 2 translation information, but does not need 595 * to apply to structures that contain combined stage 1 and stage 2 596 * translation information. 597 * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero. 598 */ 599 CPUState *cs = ENV_GET_CPU(env); 600 uint64_t pageaddr; 601 602 if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { 603 return; 604 } 605 606 pageaddr = sextract64(value << 12, 0, 40); 607 608 tlb_flush_page_by_mmuidx(cs, pageaddr, (1 << ARMMMUIdx_S2NS)); 609 } 610 611 static void tlbiipas2_is_write(CPUARMState *env, const ARMCPRegInfo *ri, 612 uint64_t value) 613 { 614 CPUState *cs = ENV_GET_CPU(env); 615 uint64_t pageaddr; 616 617 if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { 618 return; 619 } 620 621 pageaddr = sextract64(value << 12, 0, 40); 622 623 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, 624 (1 << ARMMMUIdx_S2NS)); 625 } 626 627 static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, 628 uint64_t value) 629 { 630 CPUState *cs = ENV_GET_CPU(env); 631 632 tlb_flush_by_mmuidx(cs, (1 << ARMMMUIdx_S1E2)); 633 } 634 635 static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, 636 uint64_t value) 637 { 638 CPUState *cs = ENV_GET_CPU(env); 639 640 tlb_flush_by_mmuidx_all_cpus_synced(cs, (1 << ARMMMUIdx_S1E2)); 641 } 642 643 static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, 644 uint64_t value) 645 { 646 CPUState *cs = ENV_GET_CPU(env); 647 uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12); 648 649 tlb_flush_page_by_mmuidx(cs, pageaddr, (1 << ARMMMUIdx_S1E2)); 650 } 651 652 static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, 653 uint64_t value) 654 { 655 CPUState *cs = ENV_GET_CPU(env); 656 uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12); 657 658 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, 659 (1 << ARMMMUIdx_S1E2)); 660 } 661 662 static const ARMCPRegInfo cp_reginfo[] = { 663 /* Define the secure and non-secure FCSE identifier CP registers 664 * separately because there is no secure bank in V8 (no _EL3). This allows 665 * the secure register to be properly reset and migrated. There is also no 666 * v8 EL1 version of the register so the non-secure instance stands alone. 667 */ 668 { .name = "FCSEIDR(NS)", 669 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0, 670 .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS, 671 .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_ns), 672 .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, }, 673 { .name = "FCSEIDR(S)", 674 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0, 675 .access = PL1_RW, .secure = ARM_CP_SECSTATE_S, 676 .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s), 677 .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, }, 678 /* Define the secure and non-secure context identifier CP registers 679 * separately because there is no secure bank in V8 (no _EL3). This allows 680 * the secure register to be properly reset and migrated. In the 681 * non-secure case, the 32-bit register will have reset and migration 682 * disabled during registration as it is handled by the 64-bit instance. 683 */ 684 { .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH, 685 .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, 686 .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS, 687 .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]), 688 .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, 689 { .name = "CONTEXTIDR(S)", .state = ARM_CP_STATE_AA32, 690 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, 691 .access = PL1_RW, .secure = ARM_CP_SECSTATE_S, 692 .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s), 693 .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, 694 REGINFO_SENTINEL 695 }; 696 697 static const ARMCPRegInfo not_v8_cp_reginfo[] = { 698 /* NB: Some of these registers exist in v8 but with more precise 699 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]). 700 */ 701 /* MMU Domain access control / MPU write buffer control */ 702 { .name = "DACR", 703 .cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY, 704 .access = PL1_RW, .resetvalue = 0, 705 .writefn = dacr_write, .raw_writefn = raw_write, 706 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s), 707 offsetoflow32(CPUARMState, cp15.dacr_ns) } }, 708 /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs. 709 * For v6 and v5, these mappings are overly broad. 710 */ 711 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 0, 712 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, 713 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 1, 714 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, 715 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 4, 716 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, 717 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 8, 718 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, 719 /* Cache maintenance ops; some of this space may be overridden later. */ 720 { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, 721 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, 722 .type = ARM_CP_NOP | ARM_CP_OVERRIDE }, 723 REGINFO_SENTINEL 724 }; 725 726 static const ARMCPRegInfo not_v6_cp_reginfo[] = { 727 /* Not all pre-v6 cores implemented this WFI, so this is slightly 728 * over-broad. 729 */ 730 { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2, 731 .access = PL1_W, .type = ARM_CP_WFI }, 732 REGINFO_SENTINEL 733 }; 734 735 static const ARMCPRegInfo not_v7_cp_reginfo[] = { 736 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which 737 * is UNPREDICTABLE; we choose to NOP as most implementations do). 738 */ 739 { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, 740 .access = PL1_W, .type = ARM_CP_WFI }, 741 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice 742 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and 743 * OMAPCP will override this space. 744 */ 745 { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0, 746 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data), 747 .resetvalue = 0 }, 748 { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1, 749 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn), 750 .resetvalue = 0 }, 751 /* v6 doesn't have the cache ID registers but Linux reads them anyway */ 752 { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY, 753 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, 754 .resetvalue = 0 }, 755 /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR; 756 * implementing it as RAZ means the "debug architecture version" bits 757 * will read as a reserved value, which should cause Linux to not try 758 * to use the debug hardware. 759 */ 760 { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, 761 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 762 /* MMU TLB control. Note that the wildcarding means we cover not just 763 * the unified TLB ops but also the dside/iside/inner-shareable variants. 764 */ 765 { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY, 766 .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write, 767 .type = ARM_CP_NO_RAW }, 768 { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY, 769 .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write, 770 .type = ARM_CP_NO_RAW }, 771 { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY, 772 .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write, 773 .type = ARM_CP_NO_RAW }, 774 { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY, 775 .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write, 776 .type = ARM_CP_NO_RAW }, 777 { .name = "PRRR", .cp = 15, .crn = 10, .crm = 2, 778 .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP }, 779 { .name = "NMRR", .cp = 15, .crn = 10, .crm = 2, 780 .opc1 = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_NOP }, 781 REGINFO_SENTINEL 782 }; 783 784 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, 785 uint64_t value) 786 { 787 uint32_t mask = 0; 788 789 /* In ARMv8 most bits of CPACR_EL1 are RES0. */ 790 if (!arm_feature(env, ARM_FEATURE_V8)) { 791 /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI. 792 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP. 793 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell. 794 */ 795 if (arm_feature(env, ARM_FEATURE_VFP)) { 796 /* VFP coprocessor: cp10 & cp11 [23:20] */ 797 mask |= (1 << 31) | (1 << 30) | (0xf << 20); 798 799 if (!arm_feature(env, ARM_FEATURE_NEON)) { 800 /* ASEDIS [31] bit is RAO/WI */ 801 value |= (1 << 31); 802 } 803 804 /* VFPv3 and upwards with NEON implement 32 double precision 805 * registers (D0-D31). 806 */ 807 if (!arm_feature(env, ARM_FEATURE_NEON) || 808 !arm_feature(env, ARM_FEATURE_VFP3)) { 809 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */ 810 value |= (1 << 30); 811 } 812 } 813 value &= mask; 814 } 815 env->cp15.cpacr_el1 = value; 816 } 817 818 static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri, 819 bool isread) 820 { 821 if (arm_feature(env, ARM_FEATURE_V8)) { 822 /* Check if CPACR accesses are to be trapped to EL2 */ 823 if (arm_current_el(env) == 1 && 824 (env->cp15.cptr_el[2] & CPTR_TCPAC) && !arm_is_secure(env)) { 825 return CP_ACCESS_TRAP_EL2; 826 /* Check if CPACR accesses are to be trapped to EL3 */ 827 } else if (arm_current_el(env) < 3 && 828 (env->cp15.cptr_el[3] & CPTR_TCPAC)) { 829 return CP_ACCESS_TRAP_EL3; 830 } 831 } 832 833 return CP_ACCESS_OK; 834 } 835 836 static CPAccessResult cptr_access(CPUARMState *env, const ARMCPRegInfo *ri, 837 bool isread) 838 { 839 /* Check if CPTR accesses are set to trap to EL3 */ 840 if (arm_current_el(env) == 2 && (env->cp15.cptr_el[3] & CPTR_TCPAC)) { 841 return CP_ACCESS_TRAP_EL3; 842 } 843 844 return CP_ACCESS_OK; 845 } 846 847 static const ARMCPRegInfo v6_cp_reginfo[] = { 848 /* prefetch by MVA in v6, NOP in v7 */ 849 { .name = "MVA_prefetch", 850 .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1, 851 .access = PL1_W, .type = ARM_CP_NOP }, 852 /* We need to break the TB after ISB to execute self-modifying code 853 * correctly and also to take any pending interrupts immediately. 854 * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag. 855 */ 856 { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4, 857 .access = PL0_W, .type = ARM_CP_NO_RAW, .writefn = arm_cp_write_ignore }, 858 { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4, 859 .access = PL0_W, .type = ARM_CP_NOP }, 860 { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5, 861 .access = PL0_W, .type = ARM_CP_NOP }, 862 { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2, 863 .access = PL1_RW, 864 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s), 865 offsetof(CPUARMState, cp15.ifar_ns) }, 866 .resetvalue = 0, }, 867 /* Watchpoint Fault Address Register : should actually only be present 868 * for 1136, 1176, 11MPCore. 869 */ 870 { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, 871 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, }, 872 { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, 873 .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access, 874 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1), 875 .resetvalue = 0, .writefn = cpacr_write }, 876 REGINFO_SENTINEL 877 }; 878 879 static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri, 880 bool isread) 881 { 882 /* Performance monitor registers user accessibility is controlled 883 * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable 884 * trapping to EL2 or EL3 for other accesses. 885 */ 886 int el = arm_current_el(env); 887 888 if (el == 0 && !env->cp15.c9_pmuserenr) { 889 return CP_ACCESS_TRAP; 890 } 891 if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM) 892 && !arm_is_secure_below_el3(env)) { 893 return CP_ACCESS_TRAP_EL2; 894 } 895 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { 896 return CP_ACCESS_TRAP_EL3; 897 } 898 899 return CP_ACCESS_OK; 900 } 901 902 #ifndef CONFIG_USER_ONLY 903 904 static inline bool arm_ccnt_enabled(CPUARMState *env) 905 { 906 /* This does not support checking PMCCFILTR_EL0 register */ 907 908 if (!(env->cp15.c9_pmcr & PMCRE)) { 909 return false; 910 } 911 912 return true; 913 } 914 915 void pmccntr_sync(CPUARMState *env) 916 { 917 uint64_t temp_ticks; 918 919 temp_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 920 ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); 921 922 if (env->cp15.c9_pmcr & PMCRD) { 923 /* Increment once every 64 processor clock cycles */ 924 temp_ticks /= 64; 925 } 926 927 if (arm_ccnt_enabled(env)) { 928 env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt; 929 } 930 } 931 932 static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, 933 uint64_t value) 934 { 935 pmccntr_sync(env); 936 937 if (value & PMCRC) { 938 /* The counter has been reset */ 939 env->cp15.c15_ccnt = 0; 940 } 941 942 /* only the DP, X, D and E bits are writable */ 943 env->cp15.c9_pmcr &= ~0x39; 944 env->cp15.c9_pmcr |= (value & 0x39); 945 946 pmccntr_sync(env); 947 } 948 949 static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) 950 { 951 uint64_t total_ticks; 952 953 if (!arm_ccnt_enabled(env)) { 954 /* Counter is disabled, do not change value */ 955 return env->cp15.c15_ccnt; 956 } 957 958 total_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 959 ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); 960 961 if (env->cp15.c9_pmcr & PMCRD) { 962 /* Increment once every 64 processor clock cycles */ 963 total_ticks /= 64; 964 } 965 return total_ticks - env->cp15.c15_ccnt; 966 } 967 968 static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri, 969 uint64_t value) 970 { 971 /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and 972 * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the 973 * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are 974 * accessed. 975 */ 976 env->cp15.c9_pmselr = value & 0x1f; 977 } 978 979 static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, 980 uint64_t value) 981 { 982 uint64_t total_ticks; 983 984 if (!arm_ccnt_enabled(env)) { 985 /* Counter is disabled, set the absolute value */ 986 env->cp15.c15_ccnt = value; 987 return; 988 } 989 990 total_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 991 ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); 992 993 if (env->cp15.c9_pmcr & PMCRD) { 994 /* Increment once every 64 processor clock cycles */ 995 total_ticks /= 64; 996 } 997 env->cp15.c15_ccnt = total_ticks - value; 998 } 999 1000 static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri, 1001 uint64_t value) 1002 { 1003 uint64_t cur_val = pmccntr_read(env, NULL); 1004 1005 pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value)); 1006 } 1007 1008 #else /* CONFIG_USER_ONLY */ 1009 1010 void pmccntr_sync(CPUARMState *env) 1011 { 1012 } 1013 1014 #endif 1015 1016 static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1017 uint64_t value) 1018 { 1019 pmccntr_sync(env); 1020 env->cp15.pmccfiltr_el0 = value & 0x7E000000; 1021 pmccntr_sync(env); 1022 } 1023 1024 static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, 1025 uint64_t value) 1026 { 1027 value &= (1 << 31); 1028 env->cp15.c9_pmcnten |= value; 1029 } 1030 1031 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1032 uint64_t value) 1033 { 1034 value &= (1 << 31); 1035 env->cp15.c9_pmcnten &= ~value; 1036 } 1037 1038 static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1039 uint64_t value) 1040 { 1041 env->cp15.c9_pmovsr &= ~value; 1042 } 1043 1044 static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, 1045 uint64_t value) 1046 { 1047 /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when 1048 * PMSELR value is equal to or greater than the number of implemented 1049 * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI. 1050 */ 1051 if (env->cp15.c9_pmselr == 0x1f) { 1052 pmccfiltr_write(env, ri, value); 1053 } 1054 } 1055 1056 static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri) 1057 { 1058 /* We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER 1059 * are CONSTRAINED UNPREDICTABLE. See comments in pmxevtyper_write(). 1060 */ 1061 if (env->cp15.c9_pmselr == 0x1f) { 1062 return env->cp15.pmccfiltr_el0; 1063 } else { 1064 return 0; 1065 } 1066 } 1067 1068 static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1069 uint64_t value) 1070 { 1071 env->cp15.c9_pmuserenr = value & 1; 1072 } 1073 1074 static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri, 1075 uint64_t value) 1076 { 1077 /* We have no event counters so only the C bit can be changed */ 1078 value &= (1 << 31); 1079 env->cp15.c9_pminten |= value; 1080 } 1081 1082 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1083 uint64_t value) 1084 { 1085 value &= (1 << 31); 1086 env->cp15.c9_pminten &= ~value; 1087 } 1088 1089 static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, 1090 uint64_t value) 1091 { 1092 /* Note that even though the AArch64 view of this register has bits 1093 * [10:0] all RES0 we can only mask the bottom 5, to comply with the 1094 * architectural requirements for bits which are RES0 only in some 1095 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7 1096 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.) 1097 */ 1098 raw_write(env, ri, value & ~0x1FULL); 1099 } 1100 1101 static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) 1102 { 1103 /* We only mask off bits that are RES0 both for AArch64 and AArch32. 1104 * For bits that vary between AArch32/64, code needs to check the 1105 * current execution mode before directly using the feature bit. 1106 */ 1107 uint32_t valid_mask = SCR_AARCH64_MASK | SCR_AARCH32_MASK; 1108 1109 if (!arm_feature(env, ARM_FEATURE_EL2)) { 1110 valid_mask &= ~SCR_HCE; 1111 1112 /* On ARMv7, SMD (or SCD as it is called in v7) is only 1113 * supported if EL2 exists. The bit is UNK/SBZP when 1114 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero 1115 * when EL2 is unavailable. 1116 * On ARMv8, this bit is always available. 1117 */ 1118 if (arm_feature(env, ARM_FEATURE_V7) && 1119 !arm_feature(env, ARM_FEATURE_V8)) { 1120 valid_mask &= ~SCR_SMD; 1121 } 1122 } 1123 1124 /* Clear all-context RES0 bits. */ 1125 value &= valid_mask; 1126 raw_write(env, ri, value); 1127 } 1128 1129 static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) 1130 { 1131 ARMCPU *cpu = arm_env_get_cpu(env); 1132 1133 /* Acquire the CSSELR index from the bank corresponding to the CCSIDR 1134 * bank 1135 */ 1136 uint32_t index = A32_BANKED_REG_GET(env, csselr, 1137 ri->secure & ARM_CP_SECSTATE_S); 1138 1139 return cpu->ccsidr[index]; 1140 } 1141 1142 static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1143 uint64_t value) 1144 { 1145 raw_write(env, ri, value & 0xf); 1146 } 1147 1148 static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) 1149 { 1150 CPUState *cs = ENV_GET_CPU(env); 1151 uint64_t ret = 0; 1152 1153 if (cs->interrupt_request & CPU_INTERRUPT_HARD) { 1154 ret |= CPSR_I; 1155 } 1156 if (cs->interrupt_request & CPU_INTERRUPT_FIQ) { 1157 ret |= CPSR_F; 1158 } 1159 /* External aborts are not possible in QEMU so A bit is always clear */ 1160 return ret; 1161 } 1162 1163 static const ARMCPRegInfo v7_cp_reginfo[] = { 1164 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */ 1165 { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, 1166 .access = PL1_W, .type = ARM_CP_NOP }, 1167 /* Performance monitors are implementation defined in v7, 1168 * but with an ARM recommended set of registers, which we 1169 * follow (although we don't actually implement any counters) 1170 * 1171 * Performance registers fall into three categories: 1172 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR) 1173 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR) 1174 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others) 1175 * For the cases controlled by PMUSERENR we must set .access to PL0_RW 1176 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn. 1177 */ 1178 { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1, 1179 .access = PL0_RW, .type = ARM_CP_ALIAS, 1180 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten), 1181 .writefn = pmcntenset_write, 1182 .accessfn = pmreg_access, 1183 .raw_writefn = raw_write }, 1184 { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64, 1185 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1, 1186 .access = PL0_RW, .accessfn = pmreg_access, 1187 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0, 1188 .writefn = pmcntenset_write, .raw_writefn = raw_write }, 1189 { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2, 1190 .access = PL0_RW, 1191 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten), 1192 .accessfn = pmreg_access, 1193 .writefn = pmcntenclr_write, 1194 .type = ARM_CP_ALIAS }, 1195 { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64, 1196 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2, 1197 .access = PL0_RW, .accessfn = pmreg_access, 1198 .type = ARM_CP_ALIAS, 1199 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), 1200 .writefn = pmcntenclr_write }, 1201 { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3, 1202 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), 1203 .accessfn = pmreg_access, 1204 .writefn = pmovsr_write, 1205 .raw_writefn = raw_write }, 1206 { .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64, 1207 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 3, 1208 .access = PL0_RW, .accessfn = pmreg_access, 1209 .type = ARM_CP_ALIAS, 1210 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), 1211 .writefn = pmovsr_write, 1212 .raw_writefn = raw_write }, 1213 /* Unimplemented so WI. */ 1214 { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4, 1215 .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP }, 1216 #ifndef CONFIG_USER_ONLY 1217 { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5, 1218 .access = PL0_RW, .type = ARM_CP_ALIAS, 1219 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr), 1220 .accessfn = pmreg_access, .writefn = pmselr_write, 1221 .raw_writefn = raw_write}, 1222 { .name = "PMSELR_EL0", .state = ARM_CP_STATE_AA64, 1223 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 5, 1224 .access = PL0_RW, .accessfn = pmreg_access, 1225 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmselr), 1226 .writefn = pmselr_write, .raw_writefn = raw_write, }, 1227 { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0, 1228 .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO, 1229 .readfn = pmccntr_read, .writefn = pmccntr_write32, 1230 .accessfn = pmreg_access }, 1231 { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64, 1232 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0, 1233 .access = PL0_RW, .accessfn = pmreg_access, 1234 .type = ARM_CP_IO, 1235 .readfn = pmccntr_read, .writefn = pmccntr_write, }, 1236 #endif 1237 { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64, 1238 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7, 1239 .writefn = pmccfiltr_write, 1240 .access = PL0_RW, .accessfn = pmreg_access, 1241 .type = ARM_CP_IO, 1242 .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0), 1243 .resetvalue = 0, }, 1244 { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1, 1245 .access = PL0_RW, .type = ARM_CP_NO_RAW, .accessfn = pmreg_access, 1246 .writefn = pmxevtyper_write, .readfn = pmxevtyper_read }, 1247 { .name = "PMXEVTYPER_EL0", .state = ARM_CP_STATE_AA64, 1248 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 1, 1249 .access = PL0_RW, .type = ARM_CP_NO_RAW, .accessfn = pmreg_access, 1250 .writefn = pmxevtyper_write, .readfn = pmxevtyper_read }, 1251 /* Unimplemented, RAZ/WI. */ 1252 { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2, 1253 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0, 1254 .accessfn = pmreg_access }, 1255 { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0, 1256 .access = PL0_R | PL1_RW, .accessfn = access_tpm, 1257 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr), 1258 .resetvalue = 0, 1259 .writefn = pmuserenr_write, .raw_writefn = raw_write }, 1260 { .name = "PMUSERENR_EL0", .state = ARM_CP_STATE_AA64, 1261 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 0, 1262 .access = PL0_R | PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS, 1263 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr), 1264 .resetvalue = 0, 1265 .writefn = pmuserenr_write, .raw_writefn = raw_write }, 1266 { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1, 1267 .access = PL1_RW, .accessfn = access_tpm, 1268 .type = ARM_CP_ALIAS, 1269 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pminten), 1270 .resetvalue = 0, 1271 .writefn = pmintenset_write, .raw_writefn = raw_write }, 1272 { .name = "PMINTENSET_EL1", .state = ARM_CP_STATE_AA64, 1273 .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 1, 1274 .access = PL1_RW, .accessfn = access_tpm, 1275 .type = ARM_CP_IO, 1276 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), 1277 .writefn = pmintenset_write, .raw_writefn = raw_write, 1278 .resetvalue = 0x0 }, 1279 { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2, 1280 .access = PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS, 1281 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), 1282 .writefn = pmintenclr_write, }, 1283 { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64, 1284 .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2, 1285 .access = PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS, 1286 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), 1287 .writefn = pmintenclr_write }, 1288 { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, 1289 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, 1290 .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_RAW }, 1291 { .name = "CSSELR", .state = ARM_CP_STATE_BOTH, 1292 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0, 1293 .access = PL1_RW, .writefn = csselr_write, .resetvalue = 0, 1294 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s), 1295 offsetof(CPUARMState, cp15.csselr_ns) } }, 1296 /* Auxiliary ID register: this actually has an IMPDEF value but for now 1297 * just RAZ for all cores: 1298 */ 1299 { .name = "AIDR", .state = ARM_CP_STATE_BOTH, 1300 .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7, 1301 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 1302 /* Auxiliary fault status registers: these also are IMPDEF, and we 1303 * choose to RAZ/WI for all cores. 1304 */ 1305 { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH, 1306 .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0, 1307 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1308 { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH, 1309 .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1, 1310 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1311 /* MAIR can just read-as-written because we don't implement caches 1312 * and so don't need to care about memory attributes. 1313 */ 1314 { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64, 1315 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, 1316 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]), 1317 .resetvalue = 0 }, 1318 { .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64, 1319 .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0, 1320 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]), 1321 .resetvalue = 0 }, 1322 /* For non-long-descriptor page tables these are PRRR and NMRR; 1323 * regardless they still act as reads-as-written for QEMU. 1324 */ 1325 /* MAIR0/1 are defined separately from their 64-bit counterpart which 1326 * allows them to assign the correct fieldoffset based on the endianness 1327 * handled in the field definitions. 1328 */ 1329 { .name = "MAIR0", .state = ARM_CP_STATE_AA32, 1330 .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW, 1331 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair0_s), 1332 offsetof(CPUARMState, cp15.mair0_ns) }, 1333 .resetfn = arm_cp_reset_ignore }, 1334 { .name = "MAIR1", .state = ARM_CP_STATE_AA32, 1335 .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW, 1336 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair1_s), 1337 offsetof(CPUARMState, cp15.mair1_ns) }, 1338 .resetfn = arm_cp_reset_ignore }, 1339 { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH, 1340 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0, 1341 .type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read }, 1342 /* 32 bit ITLB invalidates */ 1343 { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0, 1344 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write }, 1345 { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1, 1346 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, 1347 { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2, 1348 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write }, 1349 /* 32 bit DTLB invalidates */ 1350 { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0, 1351 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write }, 1352 { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1, 1353 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, 1354 { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2, 1355 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write }, 1356 /* 32 bit TLB invalidates */ 1357 { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, 1358 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write }, 1359 { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, 1360 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, 1361 { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, 1362 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write }, 1363 { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, 1364 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write }, 1365 REGINFO_SENTINEL 1366 }; 1367 1368 static const ARMCPRegInfo v7mp_cp_reginfo[] = { 1369 /* 32 bit TLB invalidates, Inner Shareable */ 1370 { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, 1371 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_is_write }, 1372 { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, 1373 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write }, 1374 { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, 1375 .type = ARM_CP_NO_RAW, .access = PL1_W, 1376 .writefn = tlbiasid_is_write }, 1377 { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, 1378 .type = ARM_CP_NO_RAW, .access = PL1_W, 1379 .writefn = tlbimvaa_is_write }, 1380 REGINFO_SENTINEL 1381 }; 1382 1383 static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, 1384 uint64_t value) 1385 { 1386 value &= 1; 1387 env->teecr = value; 1388 } 1389 1390 static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri, 1391 bool isread) 1392 { 1393 if (arm_current_el(env) == 0 && (env->teecr & 1)) { 1394 return CP_ACCESS_TRAP; 1395 } 1396 return CP_ACCESS_OK; 1397 } 1398 1399 static const ARMCPRegInfo t2ee_cp_reginfo[] = { 1400 { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0, 1401 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr), 1402 .resetvalue = 0, 1403 .writefn = teecr_write }, 1404 { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0, 1405 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr), 1406 .accessfn = teehbr_access, .resetvalue = 0 }, 1407 REGINFO_SENTINEL 1408 }; 1409 1410 static const ARMCPRegInfo v6k_cp_reginfo[] = { 1411 { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64, 1412 .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0, 1413 .access = PL0_RW, 1414 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 }, 1415 { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2, 1416 .access = PL0_RW, 1417 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s), 1418 offsetoflow32(CPUARMState, cp15.tpidrurw_ns) }, 1419 .resetfn = arm_cp_reset_ignore }, 1420 { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64, 1421 .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0, 1422 .access = PL0_R|PL1_W, 1423 .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]), 1424 .resetvalue = 0}, 1425 { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3, 1426 .access = PL0_R|PL1_W, 1427 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s), 1428 offsetoflow32(CPUARMState, cp15.tpidruro_ns) }, 1429 .resetfn = arm_cp_reset_ignore }, 1430 { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64, 1431 .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0, 1432 .access = PL1_RW, 1433 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 }, 1434 { .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4, 1435 .access = PL1_RW, 1436 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s), 1437 offsetoflow32(CPUARMState, cp15.tpidrprw_ns) }, 1438 .resetvalue = 0 }, 1439 REGINFO_SENTINEL 1440 }; 1441 1442 #ifndef CONFIG_USER_ONLY 1443 1444 static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri, 1445 bool isread) 1446 { 1447 /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero. 1448 * Writable only at the highest implemented exception level. 1449 */ 1450 int el = arm_current_el(env); 1451 1452 switch (el) { 1453 case 0: 1454 if (!extract32(env->cp15.c14_cntkctl, 0, 2)) { 1455 return CP_ACCESS_TRAP; 1456 } 1457 break; 1458 case 1: 1459 if (!isread && ri->state == ARM_CP_STATE_AA32 && 1460 arm_is_secure_below_el3(env)) { 1461 /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */ 1462 return CP_ACCESS_TRAP_UNCATEGORIZED; 1463 } 1464 break; 1465 case 2: 1466 case 3: 1467 break; 1468 } 1469 1470 if (!isread && el < arm_highest_el(env)) { 1471 return CP_ACCESS_TRAP_UNCATEGORIZED; 1472 } 1473 1474 return CP_ACCESS_OK; 1475 } 1476 1477 static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx, 1478 bool isread) 1479 { 1480 unsigned int cur_el = arm_current_el(env); 1481 bool secure = arm_is_secure(env); 1482 1483 /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */ 1484 if (cur_el == 0 && 1485 !extract32(env->cp15.c14_cntkctl, timeridx, 1)) { 1486 return CP_ACCESS_TRAP; 1487 } 1488 1489 if (arm_feature(env, ARM_FEATURE_EL2) && 1490 timeridx == GTIMER_PHYS && !secure && cur_el < 2 && 1491 !extract32(env->cp15.cnthctl_el2, 0, 1)) { 1492 return CP_ACCESS_TRAP_EL2; 1493 } 1494 return CP_ACCESS_OK; 1495 } 1496 1497 static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx, 1498 bool isread) 1499 { 1500 unsigned int cur_el = arm_current_el(env); 1501 bool secure = arm_is_secure(env); 1502 1503 /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if 1504 * EL0[PV]TEN is zero. 1505 */ 1506 if (cur_el == 0 && 1507 !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) { 1508 return CP_ACCESS_TRAP; 1509 } 1510 1511 if (arm_feature(env, ARM_FEATURE_EL2) && 1512 timeridx == GTIMER_PHYS && !secure && cur_el < 2 && 1513 !extract32(env->cp15.cnthctl_el2, 1, 1)) { 1514 return CP_ACCESS_TRAP_EL2; 1515 } 1516 return CP_ACCESS_OK; 1517 } 1518 1519 static CPAccessResult gt_pct_access(CPUARMState *env, 1520 const ARMCPRegInfo *ri, 1521 bool isread) 1522 { 1523 return gt_counter_access(env, GTIMER_PHYS, isread); 1524 } 1525 1526 static CPAccessResult gt_vct_access(CPUARMState *env, 1527 const ARMCPRegInfo *ri, 1528 bool isread) 1529 { 1530 return gt_counter_access(env, GTIMER_VIRT, isread); 1531 } 1532 1533 static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri, 1534 bool isread) 1535 { 1536 return gt_timer_access(env, GTIMER_PHYS, isread); 1537 } 1538 1539 static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri, 1540 bool isread) 1541 { 1542 return gt_timer_access(env, GTIMER_VIRT, isread); 1543 } 1544 1545 static CPAccessResult gt_stimer_access(CPUARMState *env, 1546 const ARMCPRegInfo *ri, 1547 bool isread) 1548 { 1549 /* The AArch64 register view of the secure physical timer is 1550 * always accessible from EL3, and configurably accessible from 1551 * Secure EL1. 1552 */ 1553 switch (arm_current_el(env)) { 1554 case 1: 1555 if (!arm_is_secure(env)) { 1556 return CP_ACCESS_TRAP; 1557 } 1558 if (!(env->cp15.scr_el3 & SCR_ST)) { 1559 return CP_ACCESS_TRAP_EL3; 1560 } 1561 return CP_ACCESS_OK; 1562 case 0: 1563 case 2: 1564 return CP_ACCESS_TRAP; 1565 case 3: 1566 return CP_ACCESS_OK; 1567 default: 1568 g_assert_not_reached(); 1569 } 1570 } 1571 1572 static uint64_t gt_get_countervalue(CPUARMState *env) 1573 { 1574 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE; 1575 } 1576 1577 static void gt_recalc_timer(ARMCPU *cpu, int timeridx) 1578 { 1579 ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx]; 1580 1581 if (gt->ctl & 1) { 1582 /* Timer enabled: calculate and set current ISTATUS, irq, and 1583 * reset timer to when ISTATUS next has to change 1584 */ 1585 uint64_t offset = timeridx == GTIMER_VIRT ? 1586 cpu->env.cp15.cntvoff_el2 : 0; 1587 uint64_t count = gt_get_countervalue(&cpu->env); 1588 /* Note that this must be unsigned 64 bit arithmetic: */ 1589 int istatus = count - offset >= gt->cval; 1590 uint64_t nexttick; 1591 int irqstate; 1592 1593 gt->ctl = deposit32(gt->ctl, 2, 1, istatus); 1594 1595 irqstate = (istatus && !(gt->ctl & 2)); 1596 qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate); 1597 1598 if (istatus) { 1599 /* Next transition is when count rolls back over to zero */ 1600 nexttick = UINT64_MAX; 1601 } else { 1602 /* Next transition is when we hit cval */ 1603 nexttick = gt->cval + offset; 1604 } 1605 /* Note that the desired next expiry time might be beyond the 1606 * signed-64-bit range of a QEMUTimer -- in this case we just 1607 * set the timer for as far in the future as possible. When the 1608 * timer expires we will reset the timer for any remaining period. 1609 */ 1610 if (nexttick > INT64_MAX / GTIMER_SCALE) { 1611 nexttick = INT64_MAX / GTIMER_SCALE; 1612 } 1613 timer_mod(cpu->gt_timer[timeridx], nexttick); 1614 trace_arm_gt_recalc(timeridx, irqstate, nexttick); 1615 } else { 1616 /* Timer disabled: ISTATUS and timer output always clear */ 1617 gt->ctl &= ~4; 1618 qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0); 1619 timer_del(cpu->gt_timer[timeridx]); 1620 trace_arm_gt_recalc_disabled(timeridx); 1621 } 1622 } 1623 1624 static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri, 1625 int timeridx) 1626 { 1627 ARMCPU *cpu = arm_env_get_cpu(env); 1628 1629 timer_del(cpu->gt_timer[timeridx]); 1630 } 1631 1632 static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) 1633 { 1634 return gt_get_countervalue(env); 1635 } 1636 1637 static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) 1638 { 1639 return gt_get_countervalue(env) - env->cp15.cntvoff_el2; 1640 } 1641 1642 static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1643 int timeridx, 1644 uint64_t value) 1645 { 1646 trace_arm_gt_cval_write(timeridx, value); 1647 env->cp15.c14_timer[timeridx].cval = value; 1648 gt_recalc_timer(arm_env_get_cpu(env), timeridx); 1649 } 1650 1651 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri, 1652 int timeridx) 1653 { 1654 uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0; 1655 1656 return (uint32_t)(env->cp15.c14_timer[timeridx].cval - 1657 (gt_get_countervalue(env) - offset)); 1658 } 1659 1660 static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1661 int timeridx, 1662 uint64_t value) 1663 { 1664 uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0; 1665 1666 trace_arm_gt_tval_write(timeridx, value); 1667 env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset + 1668 sextract64(value, 0, 32); 1669 gt_recalc_timer(arm_env_get_cpu(env), timeridx); 1670 } 1671 1672 static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, 1673 int timeridx, 1674 uint64_t value) 1675 { 1676 ARMCPU *cpu = arm_env_get_cpu(env); 1677 uint32_t oldval = env->cp15.c14_timer[timeridx].ctl; 1678 1679 trace_arm_gt_ctl_write(timeridx, value); 1680 env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value); 1681 if ((oldval ^ value) & 1) { 1682 /* Enable toggled */ 1683 gt_recalc_timer(cpu, timeridx); 1684 } else if ((oldval ^ value) & 2) { 1685 /* IMASK toggled: don't need to recalculate, 1686 * just set the interrupt line based on ISTATUS 1687 */ 1688 int irqstate = (oldval & 4) && !(value & 2); 1689 1690 trace_arm_gt_imask_toggle(timeridx, irqstate); 1691 qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate); 1692 } 1693 } 1694 1695 static void gt_phys_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) 1696 { 1697 gt_timer_reset(env, ri, GTIMER_PHYS); 1698 } 1699 1700 static void gt_phys_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1701 uint64_t value) 1702 { 1703 gt_cval_write(env, ri, GTIMER_PHYS, value); 1704 } 1705 1706 static uint64_t gt_phys_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) 1707 { 1708 return gt_tval_read(env, ri, GTIMER_PHYS); 1709 } 1710 1711 static void gt_phys_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1712 uint64_t value) 1713 { 1714 gt_tval_write(env, ri, GTIMER_PHYS, value); 1715 } 1716 1717 static void gt_phys_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, 1718 uint64_t value) 1719 { 1720 gt_ctl_write(env, ri, GTIMER_PHYS, value); 1721 } 1722 1723 static void gt_virt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) 1724 { 1725 gt_timer_reset(env, ri, GTIMER_VIRT); 1726 } 1727 1728 static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1729 uint64_t value) 1730 { 1731 gt_cval_write(env, ri, GTIMER_VIRT, value); 1732 } 1733 1734 static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) 1735 { 1736 return gt_tval_read(env, ri, GTIMER_VIRT); 1737 } 1738 1739 static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1740 uint64_t value) 1741 { 1742 gt_tval_write(env, ri, GTIMER_VIRT, value); 1743 } 1744 1745 static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, 1746 uint64_t value) 1747 { 1748 gt_ctl_write(env, ri, GTIMER_VIRT, value); 1749 } 1750 1751 static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri, 1752 uint64_t value) 1753 { 1754 ARMCPU *cpu = arm_env_get_cpu(env); 1755 1756 trace_arm_gt_cntvoff_write(value); 1757 raw_write(env, ri, value); 1758 gt_recalc_timer(cpu, GTIMER_VIRT); 1759 } 1760 1761 static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) 1762 { 1763 gt_timer_reset(env, ri, GTIMER_HYP); 1764 } 1765 1766 static void gt_hyp_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1767 uint64_t value) 1768 { 1769 gt_cval_write(env, ri, GTIMER_HYP, value); 1770 } 1771 1772 static uint64_t gt_hyp_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) 1773 { 1774 return gt_tval_read(env, ri, GTIMER_HYP); 1775 } 1776 1777 static void gt_hyp_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1778 uint64_t value) 1779 { 1780 gt_tval_write(env, ri, GTIMER_HYP, value); 1781 } 1782 1783 static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, 1784 uint64_t value) 1785 { 1786 gt_ctl_write(env, ri, GTIMER_HYP, value); 1787 } 1788 1789 static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) 1790 { 1791 gt_timer_reset(env, ri, GTIMER_SEC); 1792 } 1793 1794 static void gt_sec_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1795 uint64_t value) 1796 { 1797 gt_cval_write(env, ri, GTIMER_SEC, value); 1798 } 1799 1800 static uint64_t gt_sec_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) 1801 { 1802 return gt_tval_read(env, ri, GTIMER_SEC); 1803 } 1804 1805 static void gt_sec_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, 1806 uint64_t value) 1807 { 1808 gt_tval_write(env, ri, GTIMER_SEC, value); 1809 } 1810 1811 static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, 1812 uint64_t value) 1813 { 1814 gt_ctl_write(env, ri, GTIMER_SEC, value); 1815 } 1816 1817 void arm_gt_ptimer_cb(void *opaque) 1818 { 1819 ARMCPU *cpu = opaque; 1820 1821 gt_recalc_timer(cpu, GTIMER_PHYS); 1822 } 1823 1824 void arm_gt_vtimer_cb(void *opaque) 1825 { 1826 ARMCPU *cpu = opaque; 1827 1828 gt_recalc_timer(cpu, GTIMER_VIRT); 1829 } 1830 1831 void arm_gt_htimer_cb(void *opaque) 1832 { 1833 ARMCPU *cpu = opaque; 1834 1835 gt_recalc_timer(cpu, GTIMER_HYP); 1836 } 1837 1838 void arm_gt_stimer_cb(void *opaque) 1839 { 1840 ARMCPU *cpu = opaque; 1841 1842 gt_recalc_timer(cpu, GTIMER_SEC); 1843 } 1844 1845 static const ARMCPRegInfo generic_timer_cp_reginfo[] = { 1846 /* Note that CNTFRQ is purely reads-as-written for the benefit 1847 * of software; writing it doesn't actually change the timer frequency. 1848 * Our reset value matches the fixed frequency we implement the timer at. 1849 */ 1850 { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0, 1851 .type = ARM_CP_ALIAS, 1852 .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, 1853 .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq), 1854 }, 1855 { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64, 1856 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0, 1857 .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, 1858 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq), 1859 .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE, 1860 }, 1861 /* overall control: mostly access permissions */ 1862 { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH, 1863 .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0, 1864 .access = PL1_RW, 1865 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl), 1866 .resetvalue = 0, 1867 }, 1868 /* per-timer control */ 1869 { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1, 1870 .secure = ARM_CP_SECSTATE_NS, 1871 .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R, 1872 .accessfn = gt_ptimer_access, 1873 .fieldoffset = offsetoflow32(CPUARMState, 1874 cp15.c14_timer[GTIMER_PHYS].ctl), 1875 .writefn = gt_phys_ctl_write, .raw_writefn = raw_write, 1876 }, 1877 { .name = "CNTP_CTL(S)", 1878 .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1, 1879 .secure = ARM_CP_SECSTATE_S, 1880 .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R, 1881 .accessfn = gt_ptimer_access, 1882 .fieldoffset = offsetoflow32(CPUARMState, 1883 cp15.c14_timer[GTIMER_SEC].ctl), 1884 .writefn = gt_sec_ctl_write, .raw_writefn = raw_write, 1885 }, 1886 { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64, 1887 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1, 1888 .type = ARM_CP_IO, .access = PL1_RW | PL0_R, 1889 .accessfn = gt_ptimer_access, 1890 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl), 1891 .resetvalue = 0, 1892 .writefn = gt_phys_ctl_write, .raw_writefn = raw_write, 1893 }, 1894 { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1, 1895 .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R, 1896 .accessfn = gt_vtimer_access, 1897 .fieldoffset = offsetoflow32(CPUARMState, 1898 cp15.c14_timer[GTIMER_VIRT].ctl), 1899 .writefn = gt_virt_ctl_write, .raw_writefn = raw_write, 1900 }, 1901 { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64, 1902 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1, 1903 .type = ARM_CP_IO, .access = PL1_RW | PL0_R, 1904 .accessfn = gt_vtimer_access, 1905 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl), 1906 .resetvalue = 0, 1907 .writefn = gt_virt_ctl_write, .raw_writefn = raw_write, 1908 }, 1909 /* TimerValue views: a 32 bit downcounting view of the underlying state */ 1910 { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0, 1911 .secure = ARM_CP_SECSTATE_NS, 1912 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R, 1913 .accessfn = gt_ptimer_access, 1914 .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write, 1915 }, 1916 { .name = "CNTP_TVAL(S)", 1917 .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0, 1918 .secure = ARM_CP_SECSTATE_S, 1919 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R, 1920 .accessfn = gt_ptimer_access, 1921 .readfn = gt_sec_tval_read, .writefn = gt_sec_tval_write, 1922 }, 1923 { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64, 1924 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0, 1925 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R, 1926 .accessfn = gt_ptimer_access, .resetfn = gt_phys_timer_reset, 1927 .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write, 1928 }, 1929 { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0, 1930 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R, 1931 .accessfn = gt_vtimer_access, 1932 .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write, 1933 }, 1934 { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64, 1935 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0, 1936 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R, 1937 .accessfn = gt_vtimer_access, .resetfn = gt_virt_timer_reset, 1938 .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write, 1939 }, 1940 /* The counter itself */ 1941 { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0, 1942 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, 1943 .accessfn = gt_pct_access, 1944 .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore, 1945 }, 1946 { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64, 1947 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1, 1948 .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, 1949 .accessfn = gt_pct_access, .readfn = gt_cnt_read, 1950 }, 1951 { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1, 1952 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, 1953 .accessfn = gt_vct_access, 1954 .readfn = gt_virt_cnt_read, .resetfn = arm_cp_reset_ignore, 1955 }, 1956 { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64, 1957 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2, 1958 .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, 1959 .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read, 1960 }, 1961 /* Comparison value, indicating when the timer goes off */ 1962 { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2, 1963 .secure = ARM_CP_SECSTATE_NS, 1964 .access = PL1_RW | PL0_R, 1965 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, 1966 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), 1967 .accessfn = gt_ptimer_access, 1968 .writefn = gt_phys_cval_write, .raw_writefn = raw_write, 1969 }, 1970 { .name = "CNTP_CVAL(S)", .cp = 15, .crm = 14, .opc1 = 2, 1971 .secure = ARM_CP_SECSTATE_S, 1972 .access = PL1_RW | PL0_R, 1973 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, 1974 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval), 1975 .accessfn = gt_ptimer_access, 1976 .writefn = gt_sec_cval_write, .raw_writefn = raw_write, 1977 }, 1978 { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64, 1979 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2, 1980 .access = PL1_RW | PL0_R, 1981 .type = ARM_CP_IO, 1982 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), 1983 .resetvalue = 0, .accessfn = gt_ptimer_access, 1984 .writefn = gt_phys_cval_write, .raw_writefn = raw_write, 1985 }, 1986 { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3, 1987 .access = PL1_RW | PL0_R, 1988 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, 1989 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), 1990 .accessfn = gt_vtimer_access, 1991 .writefn = gt_virt_cval_write, .raw_writefn = raw_write, 1992 }, 1993 { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64, 1994 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2, 1995 .access = PL1_RW | PL0_R, 1996 .type = ARM_CP_IO, 1997 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), 1998 .resetvalue = 0, .accessfn = gt_vtimer_access, 1999 .writefn = gt_virt_cval_write, .raw_writefn = raw_write, 2000 }, 2001 /* Secure timer -- this is actually restricted to only EL3 2002 * and configurably Secure-EL1 via the accessfn. 2003 */ 2004 { .name = "CNTPS_TVAL_EL1", .state = ARM_CP_STATE_AA64, 2005 .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 0, 2006 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW, 2007 .accessfn = gt_stimer_access, 2008 .readfn = gt_sec_tval_read, 2009 .writefn = gt_sec_tval_write, 2010 .resetfn = gt_sec_timer_reset, 2011 }, 2012 { .name = "CNTPS_CTL_EL1", .state = ARM_CP_STATE_AA64, 2013 .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 1, 2014 .type = ARM_CP_IO, .access = PL1_RW, 2015 .accessfn = gt_stimer_access, 2016 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].ctl), 2017 .resetvalue = 0, 2018 .writefn = gt_sec_ctl_write, .raw_writefn = raw_write, 2019 }, 2020 { .name = "CNTPS_CVAL_EL1", .state = ARM_CP_STATE_AA64, 2021 .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 2, 2022 .type = ARM_CP_IO, .access = PL1_RW, 2023 .accessfn = gt_stimer_access, 2024 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval), 2025 .writefn = gt_sec_cval_write, .raw_writefn = raw_write, 2026 }, 2027 REGINFO_SENTINEL 2028 }; 2029 2030 #else 2031 /* In user-mode none of the generic timer registers are accessible, 2032 * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs, 2033 * so instead just don't register any of them. 2034 */ 2035 static const ARMCPRegInfo generic_timer_cp_reginfo[] = { 2036 REGINFO_SENTINEL 2037 }; 2038 2039 #endif 2040 2041 static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) 2042 { 2043 if (arm_feature(env, ARM_FEATURE_LPAE)) { 2044 raw_write(env, ri, value); 2045 } else if (arm_feature(env, ARM_FEATURE_V7)) { 2046 raw_write(env, ri, value & 0xfffff6ff); 2047 } else { 2048 raw_write(env, ri, value & 0xfffff1ff); 2049 } 2050 } 2051 2052 #ifndef CONFIG_USER_ONLY 2053 /* get_phys_addr() isn't present for user-mode-only targets */ 2054 2055 static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri, 2056 bool isread) 2057 { 2058 if (ri->opc2 & 4) { 2059 /* The ATS12NSO* operations must trap to EL3 if executed in 2060 * Secure EL1 (which can only happen if EL3 is AArch64). 2061 * They are simply UNDEF if executed from NS EL1. 2062 * They function normally from EL2 or EL3. 2063 */ 2064 if (arm_current_el(env) == 1) { 2065 if (arm_is_secure_below_el3(env)) { 2066 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3; 2067 } 2068 return CP_ACCESS_TRAP_UNCATEGORIZED; 2069 } 2070 } 2071 return CP_ACCESS_OK; 2072 } 2073 2074 static uint64_t do_ats_write(CPUARMState *env, uint64_t value, 2075 int access_type, ARMMMUIdx mmu_idx) 2076 { 2077 hwaddr phys_addr; 2078 target_ulong page_size; 2079 int prot; 2080 uint32_t fsr; 2081 bool ret; 2082 uint64_t par64; 2083 MemTxAttrs attrs = {}; 2084 ARMMMUFaultInfo fi = {}; 2085 2086 ret = get_phys_addr(env, value, access_type, mmu_idx, 2087 &phys_addr, &attrs, &prot, &page_size, &fsr, &fi); 2088 if (extended_addresses_enabled(env)) { 2089 /* fsr is a DFSR/IFSR value for the long descriptor 2090 * translation table format, but with WnR always clear. 2091 * Convert it to a 64-bit PAR. 2092 */ 2093 par64 = (1 << 11); /* LPAE bit always set */ 2094 if (!ret) { 2095 par64 |= phys_addr & ~0xfffULL; 2096 if (!attrs.secure) { 2097 par64 |= (1 << 9); /* NS */ 2098 } 2099 /* We don't set the ATTR or SH fields in the PAR. */ 2100 } else { 2101 par64 |= 1; /* F */ 2102 par64 |= (fsr & 0x3f) << 1; /* FS */ 2103 /* Note that S2WLK and FSTAGE are always zero, because we don't 2104 * implement virtualization and therefore there can't be a stage 2 2105 * fault. 2106 */ 2107 } 2108 } else { 2109 /* fsr is a DFSR/IFSR value for the short descriptor 2110 * translation table format (with WnR always clear). 2111 * Convert it to a 32-bit PAR. 2112 */ 2113 if (!ret) { 2114 /* We do not set any attribute bits in the PAR */ 2115 if (page_size == (1 << 24) 2116 && arm_feature(env, ARM_FEATURE_V7)) { 2117 par64 = (phys_addr & 0xff000000) | (1 << 1); 2118 } else { 2119 par64 = phys_addr & 0xfffff000; 2120 } 2121 if (!attrs.secure) { 2122 par64 |= (1 << 9); /* NS */ 2123 } 2124 } else { 2125 par64 = ((fsr & (1 << 10)) >> 5) | ((fsr & (1 << 12)) >> 6) | 2126 ((fsr & 0xf) << 1) | 1; 2127 } 2128 } 2129 return par64; 2130 } 2131 2132 static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) 2133 { 2134 int access_type = ri->opc2 & 1; 2135 uint64_t par64; 2136 ARMMMUIdx mmu_idx; 2137 int el = arm_current_el(env); 2138 bool secure = arm_is_secure_below_el3(env); 2139 2140 switch (ri->opc2 & 6) { 2141 case 0: 2142 /* stage 1 current state PL1: ATS1CPR, ATS1CPW */ 2143 switch (el) { 2144 case 3: 2145 mmu_idx = ARMMMUIdx_S1E3; 2146 break; 2147 case 2: 2148 mmu_idx = ARMMMUIdx_S1NSE1; 2149 break; 2150 case 1: 2151 mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1; 2152 break; 2153 default: 2154 g_assert_not_reached(); 2155 } 2156 break; 2157 case 2: 2158 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */ 2159 switch (el) { 2160 case 3: 2161 mmu_idx = ARMMMUIdx_S1SE0; 2162 break; 2163 case 2: 2164 mmu_idx = ARMMMUIdx_S1NSE0; 2165 break; 2166 case 1: 2167 mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0; 2168 break; 2169 default: 2170 g_assert_not_reached(); 2171 } 2172 break; 2173 case 4: 2174 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */ 2175 mmu_idx = ARMMMUIdx_S12NSE1; 2176 break; 2177 case 6: 2178 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */ 2179 mmu_idx = ARMMMUIdx_S12NSE0; 2180 break; 2181 default: 2182 g_assert_not_reached(); 2183 } 2184 2185 par64 = do_ats_write(env, value, access_type, mmu_idx); 2186 2187 A32_BANKED_CURRENT_REG_SET(env, par, par64); 2188 } 2189 2190 static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri, 2191 uint64_t value) 2192 { 2193 int access_type = ri->opc2 & 1; 2194 uint64_t par64; 2195 2196 par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S2NS); 2197 2198 A32_BANKED_CURRENT_REG_SET(env, par, par64); 2199 } 2200 2201 static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri, 2202 bool isread) 2203 { 2204 if (arm_current_el(env) == 3 && !(env->cp15.scr_el3 & SCR_NS)) { 2205 return CP_ACCESS_TRAP; 2206 } 2207 return CP_ACCESS_OK; 2208 } 2209 2210 static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, 2211 uint64_t value) 2212 { 2213 int access_type = ri->opc2 & 1; 2214 ARMMMUIdx mmu_idx; 2215 int secure = arm_is_secure_below_el3(env); 2216 2217 switch (ri->opc2 & 6) { 2218 case 0: 2219 switch (ri->opc1) { 2220 case 0: /* AT S1E1R, AT S1E1W */ 2221 mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1; 2222 break; 2223 case 4: /* AT S1E2R, AT S1E2W */ 2224 mmu_idx = ARMMMUIdx_S1E2; 2225 break; 2226 case 6: /* AT S1E3R, AT S1E3W */ 2227 mmu_idx = ARMMMUIdx_S1E3; 2228 break; 2229 default: 2230 g_assert_not_reached(); 2231 } 2232 break; 2233 case 2: /* AT S1E0R, AT S1E0W */ 2234 mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0; 2235 break; 2236 case 4: /* AT S12E1R, AT S12E1W */ 2237 mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S12NSE1; 2238 break; 2239 case 6: /* AT S12E0R, AT S12E0W */ 2240 mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S12NSE0; 2241 break; 2242 default: 2243 g_assert_not_reached(); 2244 } 2245 2246 env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx); 2247 } 2248 #endif 2249 2250 static const ARMCPRegInfo vapa_cp_reginfo[] = { 2251 { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0, 2252 .access = PL1_RW, .resetvalue = 0, 2253 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s), 2254 offsetoflow32(CPUARMState, cp15.par_ns) }, 2255 .writefn = par_write }, 2256 #ifndef CONFIG_USER_ONLY 2257 /* This underdecoding is safe because the reginfo is NO_RAW. */ 2258 { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY, 2259 .access = PL1_W, .accessfn = ats_access, 2260 .writefn = ats_write, .type = ARM_CP_NO_RAW }, 2261 #endif 2262 REGINFO_SENTINEL 2263 }; 2264 2265 /* Return basic MPU access permission bits. */ 2266 static uint32_t simple_mpu_ap_bits(uint32_t val) 2267 { 2268 uint32_t ret; 2269 uint32_t mask; 2270 int i; 2271 ret = 0; 2272 mask = 3; 2273 for (i = 0; i < 16; i += 2) { 2274 ret |= (val >> i) & mask; 2275 mask <<= 2; 2276 } 2277 return ret; 2278 } 2279 2280 /* Pad basic MPU access permission bits to extended format. */ 2281 static uint32_t extended_mpu_ap_bits(uint32_t val) 2282 { 2283 uint32_t ret; 2284 uint32_t mask; 2285 int i; 2286 ret = 0; 2287 mask = 3; 2288 for (i = 0; i < 16; i += 2) { 2289 ret |= (val & mask) << i; 2290 mask <<= 2; 2291 } 2292 return ret; 2293 } 2294 2295 static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, 2296 uint64_t value) 2297 { 2298 env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value); 2299 } 2300 2301 static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) 2302 { 2303 return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap); 2304 } 2305 2306 static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, 2307 uint64_t value) 2308 { 2309 env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value); 2310 } 2311 2312 static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) 2313 { 2314 return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap); 2315 } 2316 2317 static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri) 2318 { 2319 uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri); 2320 2321 if (!u32p) { 2322 return 0; 2323 } 2324 2325 u32p += env->cp15.c6_rgnr; 2326 return *u32p; 2327 } 2328 2329 static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri, 2330 uint64_t value) 2331 { 2332 ARMCPU *cpu = arm_env_get_cpu(env); 2333 uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri); 2334 2335 if (!u32p) { 2336 return; 2337 } 2338 2339 u32p += env->cp15.c6_rgnr; 2340 tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ 2341 *u32p = value; 2342 } 2343 2344 static void pmsav7_reset(CPUARMState *env, const ARMCPRegInfo *ri) 2345 { 2346 ARMCPU *cpu = arm_env_get_cpu(env); 2347 uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri); 2348 2349 if (!u32p) { 2350 return; 2351 } 2352 2353 memset(u32p, 0, sizeof(*u32p) * cpu->pmsav7_dregion); 2354 } 2355 2356 static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri, 2357 uint64_t value) 2358 { 2359 ARMCPU *cpu = arm_env_get_cpu(env); 2360 uint32_t nrgs = cpu->pmsav7_dregion; 2361 2362 if (value >= nrgs) { 2363 qemu_log_mask(LOG_GUEST_ERROR, 2364 "PMSAv7 RGNR write >= # supported regions, %" PRIu32 2365 " > %" PRIu32 "\n", (uint32_t)value, nrgs); 2366 return; 2367 } 2368 2369 raw_write(env, ri, value); 2370 } 2371 2372 static const ARMCPRegInfo pmsav7_cp_reginfo[] = { 2373 { .name = "DRBAR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 0, 2374 .access = PL1_RW, .type = ARM_CP_NO_RAW, 2375 .fieldoffset = offsetof(CPUARMState, pmsav7.drbar), 2376 .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset }, 2377 { .name = "DRSR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 2, 2378 .access = PL1_RW, .type = ARM_CP_NO_RAW, 2379 .fieldoffset = offsetof(CPUARMState, pmsav7.drsr), 2380 .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset }, 2381 { .name = "DRACR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 4, 2382 .access = PL1_RW, .type = ARM_CP_NO_RAW, 2383 .fieldoffset = offsetof(CPUARMState, pmsav7.dracr), 2384 .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset }, 2385 { .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0, 2386 .access = PL1_RW, 2387 .fieldoffset = offsetof(CPUARMState, cp15.c6_rgnr), 2388 .writefn = pmsav7_rgnr_write }, 2389 REGINFO_SENTINEL 2390 }; 2391 2392 static const ARMCPRegInfo pmsav5_cp_reginfo[] = { 2393 { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, 2394 .access = PL1_RW, .type = ARM_CP_ALIAS, 2395 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap), 2396 .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, }, 2397 { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, 2398 .access = PL1_RW, .type = ARM_CP_ALIAS, 2399 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap), 2400 .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, }, 2401 { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2, 2402 .access = PL1_RW, 2403 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap), 2404 .resetvalue = 0, }, 2405 { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3, 2406 .access = PL1_RW, 2407 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap), 2408 .resetvalue = 0, }, 2409 { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, 2410 .access = PL1_RW, 2411 .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, }, 2412 { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1, 2413 .access = PL1_RW, 2414 .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, }, 2415 /* Protection region base and size registers */ 2416 { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, 2417 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, 2418 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) }, 2419 { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0, 2420 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, 2421 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) }, 2422 { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0, 2423 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, 2424 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) }, 2425 { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0, 2426 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, 2427 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) }, 2428 { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0, 2429 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, 2430 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) }, 2431 { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0, 2432 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, 2433 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) }, 2434 { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0, 2435 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, 2436 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) }, 2437 { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0, 2438 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, 2439 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) }, 2440 REGINFO_SENTINEL 2441 }; 2442 2443 static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, 2444 uint64_t value) 2445 { 2446 TCR *tcr = raw_ptr(env, ri); 2447 int maskshift = extract32(value, 0, 3); 2448 2449 if (!arm_feature(env, ARM_FEATURE_V8)) { 2450 if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) { 2451 /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when 2452 * using Long-desciptor translation table format */ 2453 value &= ~((7 << 19) | (3 << 14) | (0xf << 3)); 2454 } else if (arm_feature(env, ARM_FEATURE_EL3)) { 2455 /* In an implementation that includes the Security Extensions 2456 * TTBCR has additional fields PD0 [4] and PD1 [5] for 2457 * Short-descriptor translation table format. 2458 */ 2459 value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N; 2460 } else { 2461 value &= TTBCR_N; 2462 } 2463 } 2464 2465 /* Update the masks corresponding to the TCR bank being written 2466 * Note that we always calculate mask and base_mask, but 2467 * they are only used for short-descriptor tables (ie if EAE is 0); 2468 * for long-descriptor tables the TCR fields are used differently 2469 * and the mask and base_mask values are meaningless. 2470 */ 2471 tcr->raw_tcr = value; 2472 tcr->mask = ~(((uint32_t)0xffffffffu) >> maskshift); 2473 tcr->base_mask = ~((uint32_t)0x3fffu >> maskshift); 2474 } 2475 2476 static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, 2477 uint64_t value) 2478 { 2479 ARMCPU *cpu = arm_env_get_cpu(env); 2480 2481 if (arm_feature(env, ARM_FEATURE_LPAE)) { 2482 /* With LPAE the TTBCR could result in a change of ASID 2483 * via the TTBCR.A1 bit, so do a TLB flush. 2484 */ 2485 tlb_flush(CPU(cpu)); 2486 } 2487 vmsa_ttbcr_raw_write(env, ri, value); 2488 } 2489 2490 static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri) 2491 { 2492 TCR *tcr = raw_ptr(env, ri); 2493 2494 /* Reset both the TCR as well as the masks corresponding to the bank of 2495 * the TCR being reset. 2496 */ 2497 tcr->raw_tcr = 0; 2498 tcr->mask = 0; 2499 tcr->base_mask = 0xffffc000u; 2500 } 2501 2502 static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, 2503 uint64_t value) 2504 { 2505 ARMCPU *cpu = arm_env_get_cpu(env); 2506 TCR *tcr = raw_ptr(env, ri); 2507 2508 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */ 2509 tlb_flush(CPU(cpu)); 2510 tcr->raw_tcr = value; 2511 } 2512 2513 static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, 2514 uint64_t value) 2515 { 2516 /* 64 bit accesses to the TTBRs can change the ASID and so we 2517 * must flush the TLB. 2518 */ 2519 if (cpreg_field_is_64bit(ri)) { 2520 ARMCPU *cpu = arm_env_get_cpu(env); 2521 2522 tlb_flush(CPU(cpu)); 2523 } 2524 raw_write(env, ri, value); 2525 } 2526 2527 static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, 2528 uint64_t value) 2529 { 2530 ARMCPU *cpu = arm_env_get_cpu(env); 2531 CPUState *cs = CPU(cpu); 2532 2533 /* Accesses to VTTBR may change the VMID so we must flush the TLB. */ 2534 if (raw_read(env, ri) != value) { 2535 tlb_flush_by_mmuidx(cs, 2536 (1 << ARMMMUIdx_S12NSE1) | 2537 (1 << ARMMMUIdx_S12NSE0) | 2538 (1 << ARMMMUIdx_S2NS)); 2539 raw_write(env, ri, value); 2540 } 2541 } 2542 2543 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = { 2544 { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, 2545 .access = PL1_RW, .type = ARM_CP_ALIAS, 2546 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s), 2547 offsetoflow32(CPUARMState, cp15.dfsr_ns) }, }, 2548 { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, 2549 .access = PL1_RW, .resetvalue = 0, 2550 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s), 2551 offsetoflow32(CPUARMState, cp15.ifsr_ns) } }, 2552 { .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0, 2553 .access = PL1_RW, .resetvalue = 0, 2554 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s), 2555 offsetof(CPUARMState, cp15.dfar_ns) } }, 2556 { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64, 2557 .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, 2558 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]), 2559 .resetvalue = 0, }, 2560 REGINFO_SENTINEL 2561 }; 2562 2563 static const ARMCPRegInfo vmsa_cp_reginfo[] = { 2564 { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64, 2565 .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0, 2566 .access = PL1_RW, 2567 .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, }, 2568 { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH, 2569 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0, 2570 .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0, 2571 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), 2572 offsetof(CPUARMState, cp15.ttbr0_ns) } }, 2573 { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH, 2574 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1, 2575 .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0, 2576 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), 2577 offsetof(CPUARMState, cp15.ttbr1_ns) } }, 2578 { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64, 2579 .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, 2580 .access = PL1_RW, .writefn = vmsa_tcr_el1_write, 2581 .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write, 2582 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) }, 2583 { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, 2584 .access = PL1_RW, .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write, 2585 .raw_writefn = vmsa_ttbcr_raw_write, 2586 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]), 2587 offsetoflow32(CPUARMState, cp15.tcr_el[1])} }, 2588 REGINFO_SENTINEL 2589 }; 2590 2591 static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri, 2592 uint64_t value) 2593 { 2594 env->cp15.c15_ticonfig = value & 0xe7; 2595 /* The OS_TYPE bit in this register changes the reported CPUID! */ 2596 env->cp15.c0_cpuid = (value & (1 << 5)) ? 2597 ARM_CPUID_TI915T : ARM_CPUID_TI925T; 2598 } 2599 2600 static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri, 2601 uint64_t value) 2602 { 2603 env->cp15.c15_threadid = value & 0xffff; 2604 } 2605 2606 static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri, 2607 uint64_t value) 2608 { 2609 /* Wait-for-interrupt (deprecated) */ 2610 cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT); 2611 } 2612 2613 static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri, 2614 uint64_t value) 2615 { 2616 /* On OMAP there are registers indicating the max/min index of dcache lines 2617 * containing a dirty line; cache flush operations have to reset these. 2618 */ 2619 env->cp15.c15_i_max = 0x000; 2620 env->cp15.c15_i_min = 0xff0; 2621 } 2622 2623 static const ARMCPRegInfo omap_cp_reginfo[] = { 2624 { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY, 2625 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE, 2626 .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]), 2627 .resetvalue = 0, }, 2628 { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, 2629 .access = PL1_RW, .type = ARM_CP_NOP }, 2630 { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, 2631 .access = PL1_RW, 2632 .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0, 2633 .writefn = omap_ticonfig_write }, 2634 { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0, 2635 .access = PL1_RW, 2636 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, }, 2637 { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0, 2638 .access = PL1_RW, .resetvalue = 0xff0, 2639 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) }, 2640 { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0, 2641 .access = PL1_RW, 2642 .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0, 2643 .writefn = omap_threadid_write }, 2644 { .name = "TI925T_STATUS", .cp = 15, .crn = 15, 2645 .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW, 2646 .type = ARM_CP_NO_RAW, 2647 .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, }, 2648 /* TODO: Peripheral port remap register: 2649 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller 2650 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff), 2651 * when MMU is off. 2652 */ 2653 { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, 2654 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, 2655 .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW, 2656 .writefn = omap_cachemaint_write }, 2657 { .name = "C9", .cp = 15, .crn = 9, 2658 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, 2659 .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 }, 2660 REGINFO_SENTINEL 2661 }; 2662 2663 static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri, 2664 uint64_t value) 2665 { 2666 env->cp15.c15_cpar = value & 0x3fff; 2667 } 2668 2669 static const ARMCPRegInfo xscale_cp_reginfo[] = { 2670 { .name = "XSCALE_CPAR", 2671 .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW, 2672 .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0, 2673 .writefn = xscale_cpar_write, }, 2674 { .name = "XSCALE_AUXCR", 2675 .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW, 2676 .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr), 2677 .resetvalue = 0, }, 2678 /* XScale specific cache-lockdown: since we have no cache we NOP these 2679 * and hope the guest does not really rely on cache behaviour. 2680 */ 2681 { .name = "XSCALE_LOCK_ICACHE_LINE", 2682 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, 2683 .access = PL1_W, .type = ARM_CP_NOP }, 2684 { .name = "XSCALE_UNLOCK_ICACHE", 2685 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, 2686 .access = PL1_W, .type = ARM_CP_NOP }, 2687 { .name = "XSCALE_DCACHE_LOCK", 2688 .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0, 2689 .access = PL1_RW, .type = ARM_CP_NOP }, 2690 { .name = "XSCALE_UNLOCK_DCACHE", 2691 .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1, 2692 .access = PL1_W, .type = ARM_CP_NOP }, 2693 REGINFO_SENTINEL 2694 }; 2695 2696 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = { 2697 /* RAZ/WI the whole crn=15 space, when we don't have a more specific 2698 * implementation of this implementation-defined space. 2699 * Ideally this should eventually disappear in favour of actually 2700 * implementing the correct behaviour for all cores. 2701 */ 2702 { .name = "C15_IMPDEF", .cp = 15, .crn = 15, 2703 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, 2704 .access = PL1_RW, 2705 .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE, 2706 .resetvalue = 0 }, 2707 REGINFO_SENTINEL 2708 }; 2709 2710 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = { 2711 /* Cache status: RAZ because we have no cache so it's always clean */ 2712 { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6, 2713 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, 2714 .resetvalue = 0 }, 2715 REGINFO_SENTINEL 2716 }; 2717 2718 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = { 2719 /* We never have a a block transfer operation in progress */ 2720 { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4, 2721 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, 2722 .resetvalue = 0 }, 2723 /* The cache ops themselves: these all NOP for QEMU */ 2724 { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0, 2725 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, 2726 { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0, 2727 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, 2728 { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0, 2729 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, 2730 { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1, 2731 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, 2732 { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2, 2733 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, 2734 { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0, 2735 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, 2736 REGINFO_SENTINEL 2737 }; 2738 2739 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = { 2740 /* The cache test-and-clean instructions always return (1 << 30) 2741 * to indicate that there are no dirty cache lines. 2742 */ 2743 { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3, 2744 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, 2745 .resetvalue = (1 << 30) }, 2746 { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3, 2747 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, 2748 .resetvalue = (1 << 30) }, 2749 REGINFO_SENTINEL 2750 }; 2751 2752 static const ARMCPRegInfo strongarm_cp_reginfo[] = { 2753 /* Ignore ReadBuffer accesses */ 2754 { .name = "C9_READBUFFER", .cp = 15, .crn = 9, 2755 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, 2756 .access = PL1_RW, .resetvalue = 0, 2757 .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW }, 2758 REGINFO_SENTINEL 2759 }; 2760 2761 static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri) 2762 { 2763 ARMCPU *cpu = arm_env_get_cpu(env); 2764 unsigned int cur_el = arm_current_el(env); 2765 bool secure = arm_is_secure(env); 2766 2767 if (arm_feature(&cpu->env, ARM_FEATURE_EL2) && !secure && cur_el == 1) { 2768 return env->cp15.vpidr_el2; 2769 } 2770 return raw_read(env, ri); 2771 } 2772 2773 static uint64_t mpidr_read_val(CPUARMState *env) 2774 { 2775 ARMCPU *cpu = ARM_CPU(arm_env_get_cpu(env)); 2776 uint64_t mpidr = cpu->mp_affinity; 2777 2778 if (arm_feature(env, ARM_FEATURE_V7MP)) { 2779 mpidr |= (1U << 31); 2780 /* Cores which are uniprocessor (non-coherent) 2781 * but still implement the MP extensions set 2782 * bit 30. (For instance, Cortex-R5). 2783 */ 2784 if (cpu->mp_is_up) { 2785 mpidr |= (1u << 30); 2786 } 2787 } 2788 return mpidr; 2789 } 2790 2791 static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri) 2792 { 2793 unsigned int cur_el = arm_current_el(env); 2794 bool secure = arm_is_secure(env); 2795 2796 if (arm_feature(env, ARM_FEATURE_EL2) && !secure && cur_el == 1) { 2797 return env->cp15.vmpidr_el2; 2798 } 2799 return mpidr_read_val(env); 2800 } 2801 2802 static const ARMCPRegInfo mpidr_cp_reginfo[] = { 2803 { .name = "MPIDR", .state = ARM_CP_STATE_BOTH, 2804 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5, 2805 .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW }, 2806 REGINFO_SENTINEL 2807 }; 2808 2809 static const ARMCPRegInfo lpae_cp_reginfo[] = { 2810 /* NOP AMAIR0/1 */ 2811 { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH, 2812 .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0, 2813 .access = PL1_RW, .type = ARM_CP_CONST, 2814 .resetvalue = 0 }, 2815 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */ 2816 { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1, 2817 .access = PL1_RW, .type = ARM_CP_CONST, 2818 .resetvalue = 0 }, 2819 { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0, 2820 .access = PL1_RW, .type = ARM_CP_64BIT, .resetvalue = 0, 2821 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.par_s), 2822 offsetof(CPUARMState, cp15.par_ns)} }, 2823 { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0, 2824 .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, 2825 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), 2826 offsetof(CPUARMState, cp15.ttbr0_ns) }, 2827 .writefn = vmsa_ttbr_write, }, 2828 { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1, 2829 .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, 2830 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), 2831 offsetof(CPUARMState, cp15.ttbr1_ns) }, 2832 .writefn = vmsa_ttbr_write, }, 2833 REGINFO_SENTINEL 2834 }; 2835 2836 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri) 2837 { 2838 return vfp_get_fpcr(env); 2839 } 2840 2841 static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri, 2842 uint64_t value) 2843 { 2844 vfp_set_fpcr(env, value); 2845 } 2846 2847 static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri) 2848 { 2849 return vfp_get_fpsr(env); 2850 } 2851 2852 static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri, 2853 uint64_t value) 2854 { 2855 vfp_set_fpsr(env, value); 2856 } 2857 2858 static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri, 2859 bool isread) 2860 { 2861 if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) { 2862 return CP_ACCESS_TRAP; 2863 } 2864 return CP_ACCESS_OK; 2865 } 2866 2867 static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri, 2868 uint64_t value) 2869 { 2870 env->daif = value & PSTATE_DAIF; 2871 } 2872 2873 static CPAccessResult aa64_cacheop_access(CPUARMState *env, 2874 const ARMCPRegInfo *ri, 2875 bool isread) 2876 { 2877 /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless 2878 * SCTLR_EL1.UCI is set. 2879 */ 2880 if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCI)) { 2881 return CP_ACCESS_TRAP; 2882 } 2883 return CP_ACCESS_OK; 2884 } 2885 2886 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions 2887 * Page D4-1736 (DDI0487A.b) 2888 */ 2889 2890 static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri, 2891 uint64_t value) 2892 { 2893 CPUState *cs = ENV_GET_CPU(env); 2894 2895 if (arm_is_secure_below_el3(env)) { 2896 tlb_flush_by_mmuidx(cs, 2897 (1 << ARMMMUIdx_S1SE1) | 2898 (1 << ARMMMUIdx_S1SE0)); 2899 } else { 2900 tlb_flush_by_mmuidx(cs, 2901 (1 << ARMMMUIdx_S12NSE1) | 2902 (1 << ARMMMUIdx_S12NSE0)); 2903 } 2904 } 2905 2906 static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, 2907 uint64_t value) 2908 { 2909 CPUState *cs = ENV_GET_CPU(env); 2910 bool sec = arm_is_secure_below_el3(env); 2911 2912 if (sec) { 2913 tlb_flush_by_mmuidx_all_cpus_synced(cs, 2914 (1 << ARMMMUIdx_S1SE1) | 2915 (1 << ARMMMUIdx_S1SE0)); 2916 } else { 2917 tlb_flush_by_mmuidx_all_cpus_synced(cs, 2918 (1 << ARMMMUIdx_S12NSE1) | 2919 (1 << ARMMMUIdx_S12NSE0)); 2920 } 2921 } 2922 2923 static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, 2924 uint64_t value) 2925 { 2926 /* Note that the 'ALL' scope must invalidate both stage 1 and 2927 * stage 2 translations, whereas most other scopes only invalidate 2928 * stage 1 translations. 2929 */ 2930 ARMCPU *cpu = arm_env_get_cpu(env); 2931 CPUState *cs = CPU(cpu); 2932 2933 if (arm_is_secure_below_el3(env)) { 2934 tlb_flush_by_mmuidx(cs, 2935 (1 << ARMMMUIdx_S1SE1) | 2936 (1 << ARMMMUIdx_S1SE0)); 2937 } else { 2938 if (arm_feature(env, ARM_FEATURE_EL2)) { 2939 tlb_flush_by_mmuidx(cs, 2940 (1 << ARMMMUIdx_S12NSE1) | 2941 (1 << ARMMMUIdx_S12NSE0) | 2942 (1 << ARMMMUIdx_S2NS)); 2943 } else { 2944 tlb_flush_by_mmuidx(cs, 2945 (1 << ARMMMUIdx_S12NSE1) | 2946 (1 << ARMMMUIdx_S12NSE0)); 2947 } 2948 } 2949 } 2950 2951 static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri, 2952 uint64_t value) 2953 { 2954 ARMCPU *cpu = arm_env_get_cpu(env); 2955 CPUState *cs = CPU(cpu); 2956 2957 tlb_flush_by_mmuidx(cs, (1 << ARMMMUIdx_S1E2)); 2958 } 2959 2960 static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri, 2961 uint64_t value) 2962 { 2963 ARMCPU *cpu = arm_env_get_cpu(env); 2964 CPUState *cs = CPU(cpu); 2965 2966 tlb_flush_by_mmuidx(cs, (1 << ARMMMUIdx_S1E3)); 2967 } 2968 2969 static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, 2970 uint64_t value) 2971 { 2972 /* Note that the 'ALL' scope must invalidate both stage 1 and 2973 * stage 2 translations, whereas most other scopes only invalidate 2974 * stage 1 translations. 2975 */ 2976 CPUState *cs = ENV_GET_CPU(env); 2977 bool sec = arm_is_secure_below_el3(env); 2978 bool has_el2 = arm_feature(env, ARM_FEATURE_EL2); 2979 2980 if (sec) { 2981 tlb_flush_by_mmuidx_all_cpus_synced(cs, 2982 (1 << ARMMMUIdx_S1SE1) | 2983 (1 << ARMMMUIdx_S1SE0)); 2984 } else if (has_el2) { 2985 tlb_flush_by_mmuidx_all_cpus_synced(cs, 2986 (1 << ARMMMUIdx_S12NSE1) | 2987 (1 << ARMMMUIdx_S12NSE0) | 2988 (1 << ARMMMUIdx_S2NS)); 2989 } else { 2990 tlb_flush_by_mmuidx_all_cpus_synced(cs, 2991 (1 << ARMMMUIdx_S12NSE1) | 2992 (1 << ARMMMUIdx_S12NSE0)); 2993 } 2994 } 2995 2996 static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri, 2997 uint64_t value) 2998 { 2999 CPUState *cs = ENV_GET_CPU(env); 3000 3001 tlb_flush_by_mmuidx_all_cpus_synced(cs, (1 << ARMMMUIdx_S1E2)); 3002 } 3003 3004 static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri, 3005 uint64_t value) 3006 { 3007 CPUState *cs = ENV_GET_CPU(env); 3008 3009 tlb_flush_by_mmuidx_all_cpus_synced(cs, (1 << ARMMMUIdx_S1E3)); 3010 } 3011 3012 static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri, 3013 uint64_t value) 3014 { 3015 /* Invalidate by VA, EL1&0 (AArch64 version). 3016 * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1, 3017 * since we don't support flush-for-specific-ASID-only or 3018 * flush-last-level-only. 3019 */ 3020 ARMCPU *cpu = arm_env_get_cpu(env); 3021 CPUState *cs = CPU(cpu); 3022 uint64_t pageaddr = sextract64(value << 12, 0, 56); 3023 3024 if (arm_is_secure_below_el3(env)) { 3025 tlb_flush_page_by_mmuidx(cs, pageaddr, 3026 (1 << ARMMMUIdx_S1SE1) | 3027 (1 << ARMMMUIdx_S1SE0)); 3028 } else { 3029 tlb_flush_page_by_mmuidx(cs, pageaddr, 3030 (1 << ARMMMUIdx_S12NSE1) | 3031 (1 << ARMMMUIdx_S12NSE0)); 3032 } 3033 } 3034 3035 static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri, 3036 uint64_t value) 3037 { 3038 /* Invalidate by VA, EL2 3039 * Currently handles both VAE2 and VALE2, since we don't support 3040 * flush-last-level-only. 3041 */ 3042 ARMCPU *cpu = arm_env_get_cpu(env); 3043 CPUState *cs = CPU(cpu); 3044 uint64_t pageaddr = sextract64(value << 12, 0, 56); 3045 3046 tlb_flush_page_by_mmuidx(cs, pageaddr, (1 << ARMMMUIdx_S1E2)); 3047 } 3048 3049 static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri, 3050 uint64_t value) 3051 { 3052 /* Invalidate by VA, EL3 3053 * Currently handles both VAE3 and VALE3, since we don't support 3054 * flush-last-level-only. 3055 */ 3056 ARMCPU *cpu = arm_env_get_cpu(env); 3057 CPUState *cs = CPU(cpu); 3058 uint64_t pageaddr = sextract64(value << 12, 0, 56); 3059 3060 tlb_flush_page_by_mmuidx(cs, pageaddr, (1 << ARMMMUIdx_S1E3)); 3061 } 3062 3063 static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri, 3064 uint64_t value) 3065 { 3066 ARMCPU *cpu = arm_env_get_cpu(env); 3067 CPUState *cs = CPU(cpu); 3068 bool sec = arm_is_secure_below_el3(env); 3069 uint64_t pageaddr = sextract64(value << 12, 0, 56); 3070 3071 if (sec) { 3072 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, 3073 (1 << ARMMMUIdx_S1SE1) | 3074 (1 << ARMMMUIdx_S1SE0)); 3075 } else { 3076 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, 3077 (1 << ARMMMUIdx_S12NSE1) | 3078 (1 << ARMMMUIdx_S12NSE0)); 3079 } 3080 } 3081 3082 static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri, 3083 uint64_t value) 3084 { 3085 CPUState *cs = ENV_GET_CPU(env); 3086 uint64_t pageaddr = sextract64(value << 12, 0, 56); 3087 3088 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, 3089 (1 << ARMMMUIdx_S1E2)); 3090 } 3091 3092 static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri, 3093 uint64_t value) 3094 { 3095 CPUState *cs = ENV_GET_CPU(env); 3096 uint64_t pageaddr = sextract64(value << 12, 0, 56); 3097 3098 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, 3099 (1 << ARMMMUIdx_S1E3)); 3100 } 3101 3102 static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri, 3103 uint64_t value) 3104 { 3105 /* Invalidate by IPA. This has to invalidate any structures that 3106 * contain only stage 2 translation information, but does not need 3107 * to apply to structures that contain combined stage 1 and stage 2 3108 * translation information. 3109 * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero. 3110 */ 3111 ARMCPU *cpu = arm_env_get_cpu(env); 3112 CPUState *cs = CPU(cpu); 3113 uint64_t pageaddr; 3114 3115 if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { 3116 return; 3117 } 3118 3119 pageaddr = sextract64(value << 12, 0, 48); 3120 3121 tlb_flush_page_by_mmuidx(cs, pageaddr, (1 << ARMMMUIdx_S2NS)); 3122 } 3123 3124 static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri, 3125 uint64_t value) 3126 { 3127 CPUState *cs = ENV_GET_CPU(env); 3128 uint64_t pageaddr; 3129 3130 if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { 3131 return; 3132 } 3133 3134 pageaddr = sextract64(value << 12, 0, 48); 3135 3136 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, 3137 (1 << ARMMMUIdx_S2NS)); 3138 } 3139 3140 static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri, 3141 bool isread) 3142 { 3143 /* We don't implement EL2, so the only control on DC ZVA is the 3144 * bit in the SCTLR which can prohibit access for EL0. 3145 */ 3146 if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_DZE)) { 3147 return CP_ACCESS_TRAP; 3148 } 3149 return CP_ACCESS_OK; 3150 } 3151 3152 static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri) 3153 { 3154 ARMCPU *cpu = arm_env_get_cpu(env); 3155 int dzp_bit = 1 << 4; 3156 3157 /* DZP indicates whether DC ZVA access is allowed */ 3158 if (aa64_zva_access(env, NULL, false) == CP_ACCESS_OK) { 3159 dzp_bit = 0; 3160 } 3161 return cpu->dcz_blocksize | dzp_bit; 3162 } 3163 3164 static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri, 3165 bool isread) 3166 { 3167 if (!(env->pstate & PSTATE_SP)) { 3168 /* Access to SP_EL0 is undefined if it's being used as 3169 * the stack pointer. 3170 */ 3171 return CP_ACCESS_TRAP_UNCATEGORIZED; 3172 } 3173 return CP_ACCESS_OK; 3174 } 3175 3176 static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri) 3177 { 3178 return env->pstate & PSTATE_SP; 3179 } 3180 3181 static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) 3182 { 3183 update_spsel(env, val); 3184 } 3185 3186 static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, 3187 uint64_t value) 3188 { 3189 ARMCPU *cpu = arm_env_get_cpu(env); 3190 3191 if (raw_read(env, ri) == value) { 3192 /* Skip the TLB flush if nothing actually changed; Linux likes 3193 * to do a lot of pointless SCTLR writes. 3194 */ 3195 return; 3196 } 3197 3198 raw_write(env, ri, value); 3199 /* ??? Lots of these bits are not implemented. */ 3200 /* This may enable/disable the MMU, so do a TLB flush. */ 3201 tlb_flush(CPU(cpu)); 3202 } 3203 3204 static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri, 3205 bool isread) 3206 { 3207 if ((env->cp15.cptr_el[2] & CPTR_TFP) && arm_current_el(env) == 2) { 3208 return CP_ACCESS_TRAP_FP_EL2; 3209 } 3210 if (env->cp15.cptr_el[3] & CPTR_TFP) { 3211 return CP_ACCESS_TRAP_FP_EL3; 3212 } 3213 return CP_ACCESS_OK; 3214 } 3215 3216 static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri, 3217 uint64_t value) 3218 { 3219 env->cp15.mdcr_el3 = value & SDCR_VALID_MASK; 3220 } 3221 3222 static const ARMCPRegInfo v8_cp_reginfo[] = { 3223 /* Minimal set of EL0-visible registers. This will need to be expanded 3224 * significantly for system emulation of AArch64 CPUs. 3225 */ 3226 { .name = "NZCV", .state = ARM_CP_STATE_AA64, 3227 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2, 3228 .access = PL0_RW, .type = ARM_CP_NZCV }, 3229 { .name = "DAIF", .state = ARM_CP_STATE_AA64, 3230 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2, 3231 .type = ARM_CP_NO_RAW, 3232 .access = PL0_RW, .accessfn = aa64_daif_access, 3233 .fieldoffset = offsetof(CPUARMState, daif), 3234 .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore }, 3235 { .name = "FPCR", .state = ARM_CP_STATE_AA64, 3236 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4, 3237 .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write }, 3238 { .name = "FPSR", .state = ARM_CP_STATE_AA64, 3239 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4, 3240 .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write }, 3241 { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64, 3242 .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0, 3243 .access = PL0_R, .type = ARM_CP_NO_RAW, 3244 .readfn = aa64_dczid_read }, 3245 { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64, 3246 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1, 3247 .access = PL0_W, .type = ARM_CP_DC_ZVA, 3248 #ifndef CONFIG_USER_ONLY 3249 /* Avoid overhead of an access check that always passes in user-mode */ 3250 .accessfn = aa64_zva_access, 3251 #endif 3252 }, 3253 { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64, 3254 .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2, 3255 .access = PL1_R, .type = ARM_CP_CURRENTEL }, 3256 /* Cache ops: all NOPs since we don't emulate caches */ 3257 { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64, 3258 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, 3259 .access = PL1_W, .type = ARM_CP_NOP }, 3260 { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64, 3261 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, 3262 .access = PL1_W, .type = ARM_CP_NOP }, 3263 { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64, 3264 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1, 3265 .access = PL0_W, .type = ARM_CP_NOP, 3266 .accessfn = aa64_cacheop_access }, 3267 { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64, 3268 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, 3269 .access = PL1_W, .type = ARM_CP_NOP }, 3270 { .name = "DC_ISW", .state = ARM_CP_STATE_AA64, 3271 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, 3272 .access = PL1_W, .type = ARM_CP_NOP }, 3273 { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64, 3274 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1, 3275 .access = PL0_W, .type = ARM_CP_NOP, 3276 .accessfn = aa64_cacheop_access }, 3277 { .name = "DC_CSW", .state = ARM_CP_STATE_AA64, 3278 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, 3279 .access = PL1_W, .type = ARM_CP_NOP }, 3280 { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64, 3281 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1, 3282 .access = PL0_W, .type = ARM_CP_NOP, 3283 .accessfn = aa64_cacheop_access }, 3284 { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64, 3285 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1, 3286 .access = PL0_W, .type = ARM_CP_NOP, 3287 .accessfn = aa64_cacheop_access }, 3288 { .name = "DC_CISW", .state = ARM_CP_STATE_AA64, 3289 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, 3290 .access = PL1_W, .type = ARM_CP_NOP }, 3291 /* TLBI operations */ 3292 { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64, 3293 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, 3294 .access = PL1_W, .type = ARM_CP_NO_RAW, 3295 .writefn = tlbi_aa64_vmalle1is_write }, 3296 { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64, 3297 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, 3298 .access = PL1_W, .type = ARM_CP_NO_RAW, 3299 .writefn = tlbi_aa64_vae1is_write }, 3300 { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64, 3301 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, 3302 .access = PL1_W, .type = ARM_CP_NO_RAW, 3303 .writefn = tlbi_aa64_vmalle1is_write }, 3304 { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64, 3305 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, 3306 .access = PL1_W, .type = ARM_CP_NO_RAW, 3307 .writefn = tlbi_aa64_vae1is_write }, 3308 { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64, 3309 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, 3310 .access = PL1_W, .type = ARM_CP_NO_RAW, 3311 .writefn = tlbi_aa64_vae1is_write }, 3312 { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64, 3313 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, 3314 .access = PL1_W, .type = ARM_CP_NO_RAW, 3315 .writefn = tlbi_aa64_vae1is_write }, 3316 { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64, 3317 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, 3318 .access = PL1_W, .type = ARM_CP_NO_RAW, 3319 .writefn = tlbi_aa64_vmalle1_write }, 3320 { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64, 3321 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, 3322 .access = PL1_W, .type = ARM_CP_NO_RAW, 3323 .writefn = tlbi_aa64_vae1_write }, 3324 { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64, 3325 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, 3326 .access = PL1_W, .type = ARM_CP_NO_RAW, 3327 .writefn = tlbi_aa64_vmalle1_write }, 3328 { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64, 3329 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, 3330 .access = PL1_W, .type = ARM_CP_NO_RAW, 3331 .writefn = tlbi_aa64_vae1_write }, 3332 { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64, 3333 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, 3334 .access = PL1_W, .type = ARM_CP_NO_RAW, 3335 .writefn = tlbi_aa64_vae1_write }, 3336 { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64, 3337 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, 3338 .access = PL1_W, .type = ARM_CP_NO_RAW, 3339 .writefn = tlbi_aa64_vae1_write }, 3340 { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64, 3341 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1, 3342 .access = PL2_W, .type = ARM_CP_NO_RAW, 3343 .writefn = tlbi_aa64_ipas2e1is_write }, 3344 { .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64, 3345 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5, 3346 .access = PL2_W, .type = ARM_CP_NO_RAW, 3347 .writefn = tlbi_aa64_ipas2e1is_write }, 3348 { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64, 3349 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4, 3350 .access = PL2_W, .type = ARM_CP_NO_RAW, 3351 .writefn = tlbi_aa64_alle1is_write }, 3352 { .name = "TLBI_VMALLS12E1IS", .state = ARM_CP_STATE_AA64, 3353 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 6, 3354 .access = PL2_W, .type = ARM_CP_NO_RAW, 3355 .writefn = tlbi_aa64_alle1is_write }, 3356 { .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64, 3357 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1, 3358 .access = PL2_W, .type = ARM_CP_NO_RAW, 3359 .writefn = tlbi_aa64_ipas2e1_write }, 3360 { .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64, 3361 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5, 3362 .access = PL2_W, .type = ARM_CP_NO_RAW, 3363 .writefn = tlbi_aa64_ipas2e1_write }, 3364 { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64, 3365 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4, 3366 .access = PL2_W, .type = ARM_CP_NO_RAW, 3367 .writefn = tlbi_aa64_alle1_write }, 3368 { .name = "TLBI_VMALLS12E1", .state = ARM_CP_STATE_AA64, 3369 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6, 3370 .access = PL2_W, .type = ARM_CP_NO_RAW, 3371 .writefn = tlbi_aa64_alle1is_write }, 3372 #ifndef CONFIG_USER_ONLY 3373 /* 64 bit address translation operations */ 3374 { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64, 3375 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0, 3376 .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3377 { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64, 3378 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1, 3379 .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3380 { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64, 3381 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2, 3382 .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3383 { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64, 3384 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3, 3385 .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3386 { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64, 3387 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4, 3388 .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3389 { .name = "AT_S12E1W", .state = ARM_CP_STATE_AA64, 3390 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 5, 3391 .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3392 { .name = "AT_S12E0R", .state = ARM_CP_STATE_AA64, 3393 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 6, 3394 .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3395 { .name = "AT_S12E0W", .state = ARM_CP_STATE_AA64, 3396 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 7, 3397 .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3398 /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */ 3399 { .name = "AT_S1E3R", .state = ARM_CP_STATE_AA64, 3400 .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 0, 3401 .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3402 { .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64, 3403 .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1, 3404 .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3405 { .name = "PAR_EL1", .state = ARM_CP_STATE_AA64, 3406 .type = ARM_CP_ALIAS, 3407 .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0, 3408 .access = PL1_RW, .resetvalue = 0, 3409 .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]), 3410 .writefn = par_write }, 3411 #endif 3412 /* TLB invalidate last level of translation table walk */ 3413 { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, 3414 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write }, 3415 { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, 3416 .type = ARM_CP_NO_RAW, .access = PL1_W, 3417 .writefn = tlbimvaa_is_write }, 3418 { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, 3419 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, 3420 { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, 3421 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write }, 3422 { .name = "TLBIMVALH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5, 3423 .type = ARM_CP_NO_RAW, .access = PL2_W, 3424 .writefn = tlbimva_hyp_write }, 3425 { .name = "TLBIMVALHIS", 3426 .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5, 3427 .type = ARM_CP_NO_RAW, .access = PL2_W, 3428 .writefn = tlbimva_hyp_is_write }, 3429 { .name = "TLBIIPAS2", 3430 .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1, 3431 .type = ARM_CP_NO_RAW, .access = PL2_W, 3432 .writefn = tlbiipas2_write }, 3433 { .name = "TLBIIPAS2IS", 3434 .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1, 3435 .type = ARM_CP_NO_RAW, .access = PL2_W, 3436 .writefn = tlbiipas2_is_write }, 3437 { .name = "TLBIIPAS2L", 3438 .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5, 3439 .type = ARM_CP_NO_RAW, .access = PL2_W, 3440 .writefn = tlbiipas2_write }, 3441 { .name = "TLBIIPAS2LIS", 3442 .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5, 3443 .type = ARM_CP_NO_RAW, .access = PL2_W, 3444 .writefn = tlbiipas2_is_write }, 3445 /* 32 bit cache operations */ 3446 { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, 3447 .type = ARM_CP_NOP, .access = PL1_W }, 3448 { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6, 3449 .type = ARM_CP_NOP, .access = PL1_W }, 3450 { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, 3451 .type = ARM_CP_NOP, .access = PL1_W }, 3452 { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1, 3453 .type = ARM_CP_NOP, .access = PL1_W }, 3454 { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6, 3455 .type = ARM_CP_NOP, .access = PL1_W }, 3456 { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7, 3457 .type = ARM_CP_NOP, .access = PL1_W }, 3458 { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, 3459 .type = ARM_CP_NOP, .access = PL1_W }, 3460 { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, 3461 .type = ARM_CP_NOP, .access = PL1_W }, 3462 { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1, 3463 .type = ARM_CP_NOP, .access = PL1_W }, 3464 { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, 3465 .type = ARM_CP_NOP, .access = PL1_W }, 3466 { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1, 3467 .type = ARM_CP_NOP, .access = PL1_W }, 3468 { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1, 3469 .type = ARM_CP_NOP, .access = PL1_W }, 3470 { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, 3471 .type = ARM_CP_NOP, .access = PL1_W }, 3472 /* MMU Domain access control / MPU write buffer control */ 3473 { .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0, 3474 .access = PL1_RW, .resetvalue = 0, 3475 .writefn = dacr_write, .raw_writefn = raw_write, 3476 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s), 3477 offsetoflow32(CPUARMState, cp15.dacr_ns) } }, 3478 { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64, 3479 .type = ARM_CP_ALIAS, 3480 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1, 3481 .access = PL1_RW, 3482 .fieldoffset = offsetof(CPUARMState, elr_el[1]) }, 3483 { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64, 3484 .type = ARM_CP_ALIAS, 3485 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0, 3486 .access = PL1_RW, 3487 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_SVC]) }, 3488 /* We rely on the access checks not allowing the guest to write to the 3489 * state field when SPSel indicates that it's being used as the stack 3490 * pointer. 3491 */ 3492 { .name = "SP_EL0", .state = ARM_CP_STATE_AA64, 3493 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0, 3494 .access = PL1_RW, .accessfn = sp_el0_access, 3495 .type = ARM_CP_ALIAS, 3496 .fieldoffset = offsetof(CPUARMState, sp_el[0]) }, 3497 { .name = "SP_EL1", .state = ARM_CP_STATE_AA64, 3498 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0, 3499 .access = PL2_RW, .type = ARM_CP_ALIAS, 3500 .fieldoffset = offsetof(CPUARMState, sp_el[1]) }, 3501 { .name = "SPSel", .state = ARM_CP_STATE_AA64, 3502 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0, 3503 .type = ARM_CP_NO_RAW, 3504 .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write }, 3505 { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64, 3506 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0, 3507 .type = ARM_CP_ALIAS, 3508 .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]), 3509 .access = PL2_RW, .accessfn = fpexc32_access }, 3510 { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64, 3511 .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0, 3512 .access = PL2_RW, .resetvalue = 0, 3513 .writefn = dacr_write, .raw_writefn = raw_write, 3514 .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) }, 3515 { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64, 3516 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1, 3517 .access = PL2_RW, .resetvalue = 0, 3518 .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) }, 3519 { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64, 3520 .type = ARM_CP_ALIAS, 3521 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 0, 3522 .access = PL2_RW, 3523 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_IRQ]) }, 3524 { .name = "SPSR_ABT", .state = ARM_CP_STATE_AA64, 3525 .type = ARM_CP_ALIAS, 3526 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 1, 3527 .access = PL2_RW, 3528 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_ABT]) }, 3529 { .name = "SPSR_UND", .state = ARM_CP_STATE_AA64, 3530 .type = ARM_CP_ALIAS, 3531 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 2, 3532 .access = PL2_RW, 3533 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_UND]) }, 3534 { .name = "SPSR_FIQ", .state = ARM_CP_STATE_AA64, 3535 .type = ARM_CP_ALIAS, 3536 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 3, 3537 .access = PL2_RW, 3538 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) }, 3539 { .name = "MDCR_EL3", .state = ARM_CP_STATE_AA64, 3540 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1, 3541 .resetvalue = 0, 3542 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) }, 3543 { .name = "SDCR", .type = ARM_CP_ALIAS, 3544 .cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1, 3545 .access = PL1_RW, .accessfn = access_trap_aa32s_el1, 3546 .writefn = sdcr_write, 3547 .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) }, 3548 REGINFO_SENTINEL 3549 }; 3550 3551 /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */ 3552 static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { 3553 { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64, 3554 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, 3555 .access = PL2_RW, 3556 .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, 3557 { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64, 3558 .type = ARM_CP_NO_RAW, 3559 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, 3560 .access = PL2_RW, 3561 .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, 3562 { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH, 3563 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, 3564 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3565 { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH, 3566 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0, 3567 .access = PL2_RW, .type = ARM_CP_CONST, 3568 .resetvalue = 0 }, 3569 { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, 3570 .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, 3571 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3572 { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH, 3573 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0, 3574 .access = PL2_RW, .type = ARM_CP_CONST, 3575 .resetvalue = 0 }, 3576 { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, 3577 .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, 3578 .access = PL2_RW, .type = ARM_CP_CONST, 3579 .resetvalue = 0 }, 3580 { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH, 3581 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0, 3582 .access = PL2_RW, .type = ARM_CP_CONST, 3583 .resetvalue = 0 }, 3584 { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH, 3585 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1, 3586 .access = PL2_RW, .type = ARM_CP_CONST, 3587 .resetvalue = 0 }, 3588 { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, 3589 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, 3590 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3591 { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH, 3592 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, 3593 .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, 3594 .type = ARM_CP_CONST, .resetvalue = 0 }, 3595 { .name = "VTTBR", .state = ARM_CP_STATE_AA32, 3596 .cp = 15, .opc1 = 6, .crm = 2, 3597 .access = PL2_RW, .accessfn = access_el3_aa32ns, 3598 .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 3599 { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64, 3600 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0, 3601 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3602 { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH, 3603 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, 3604 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3605 { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH, 3606 .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2, 3607 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3608 { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64, 3609 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, 3610 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3611 { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2, 3612 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, 3613 .resetvalue = 0 }, 3614 { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH, 3615 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0, 3616 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3617 { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64, 3618 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3, 3619 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3620 { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14, 3621 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, 3622 .resetvalue = 0 }, 3623 { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64, 3624 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2, 3625 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3626 { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14, 3627 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, 3628 .resetvalue = 0 }, 3629 { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH, 3630 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0, 3631 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3632 { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, 3633 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, 3634 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3635 { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, 3636 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1, 3637 .access = PL2_RW, .accessfn = access_tda, 3638 .type = ARM_CP_CONST, .resetvalue = 0 }, 3639 { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH, 3640 .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, 3641 .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, 3642 .type = ARM_CP_CONST, .resetvalue = 0 }, 3643 { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH, 3644 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3, 3645 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 3646 REGINFO_SENTINEL 3647 }; 3648 3649 static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) 3650 { 3651 ARMCPU *cpu = arm_env_get_cpu(env); 3652 uint64_t valid_mask = HCR_MASK; 3653 3654 if (arm_feature(env, ARM_FEATURE_EL3)) { 3655 valid_mask &= ~HCR_HCD; 3656 } else { 3657 valid_mask &= ~HCR_TSC; 3658 } 3659 3660 /* Clear RES0 bits. */ 3661 value &= valid_mask; 3662 3663 /* These bits change the MMU setup: 3664 * HCR_VM enables stage 2 translation 3665 * HCR_PTW forbids certain page-table setups 3666 * HCR_DC Disables stage1 and enables stage2 translation 3667 */ 3668 if ((raw_read(env, ri) ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) { 3669 tlb_flush(CPU(cpu)); 3670 } 3671 raw_write(env, ri, value); 3672 } 3673 3674 static const ARMCPRegInfo el2_cp_reginfo[] = { 3675 { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64, 3676 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, 3677 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), 3678 .writefn = hcr_write }, 3679 { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64, 3680 .type = ARM_CP_ALIAS, 3681 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1, 3682 .access = PL2_RW, 3683 .fieldoffset = offsetof(CPUARMState, elr_el[2]) }, 3684 { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64, 3685 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, 3686 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) }, 3687 { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64, 3688 .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, 3689 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) }, 3690 { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64, 3691 .type = ARM_CP_ALIAS, 3692 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0, 3693 .access = PL2_RW, 3694 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_HYP]) }, 3695 { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64, 3696 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, 3697 .access = PL2_RW, .writefn = vbar_write, 3698 .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]), 3699 .resetvalue = 0 }, 3700 { .name = "SP_EL2", .state = ARM_CP_STATE_AA64, 3701 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0, 3702 .access = PL3_RW, .type = ARM_CP_ALIAS, 3703 .fieldoffset = offsetof(CPUARMState, sp_el[2]) }, 3704 { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH, 3705 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, 3706 .access = PL2_RW, .accessfn = cptr_access, .resetvalue = 0, 3707 .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[2]) }, 3708 { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH, 3709 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0, 3710 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[2]), 3711 .resetvalue = 0 }, 3712 { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, 3713 .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, 3714 .access = PL2_RW, .type = ARM_CP_ALIAS, 3715 .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el[2]) }, 3716 { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH, 3717 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0, 3718 .access = PL2_RW, .type = ARM_CP_CONST, 3719 .resetvalue = 0 }, 3720 /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */ 3721 { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, 3722 .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, 3723 .access = PL2_RW, .type = ARM_CP_CONST, 3724 .resetvalue = 0 }, 3725 { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH, 3726 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0, 3727 .access = PL2_RW, .type = ARM_CP_CONST, 3728 .resetvalue = 0 }, 3729 { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH, 3730 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1, 3731 .access = PL2_RW, .type = ARM_CP_CONST, 3732 .resetvalue = 0 }, 3733 { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, 3734 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, 3735 .access = PL2_RW, 3736 /* no .writefn needed as this can't cause an ASID change; 3737 * no .raw_writefn or .resetfn needed as we never use mask/base_mask 3738 */ 3739 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) }, 3740 { .name = "VTCR", .state = ARM_CP_STATE_AA32, 3741 .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, 3742 .type = ARM_CP_ALIAS, 3743 .access = PL2_RW, .accessfn = access_el3_aa32ns, 3744 .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) }, 3745 { .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64, 3746 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, 3747 .access = PL2_RW, 3748 /* no .writefn needed as this can't cause an ASID change; 3749 * no .raw_writefn or .resetfn needed as we never use mask/base_mask 3750 */ 3751 .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) }, 3752 { .name = "VTTBR", .state = ARM_CP_STATE_AA32, 3753 .cp = 15, .opc1 = 6, .crm = 2, 3754 .type = ARM_CP_64BIT | ARM_CP_ALIAS, 3755 .access = PL2_RW, .accessfn = access_el3_aa32ns, 3756 .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2), 3757 .writefn = vttbr_write }, 3758 { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64, 3759 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0, 3760 .access = PL2_RW, .writefn = vttbr_write, 3761 .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2) }, 3762 { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH, 3763 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, 3764 .access = PL2_RW, .raw_writefn = raw_write, .writefn = sctlr_write, 3765 .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[2]) }, 3766 { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH, 3767 .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2, 3768 .access = PL2_RW, .resetvalue = 0, 3769 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) }, 3770 { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64, 3771 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, 3772 .access = PL2_RW, .resetvalue = 0, 3773 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) }, 3774 { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2, 3775 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, 3776 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) }, 3777 { .name = "TLBIALLNSNH", 3778 .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4, 3779 .type = ARM_CP_NO_RAW, .access = PL2_W, 3780 .writefn = tlbiall_nsnh_write }, 3781 { .name = "TLBIALLNSNHIS", 3782 .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4, 3783 .type = ARM_CP_NO_RAW, .access = PL2_W, 3784 .writefn = tlbiall_nsnh_is_write }, 3785 { .name = "TLBIALLH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0, 3786 .type = ARM_CP_NO_RAW, .access = PL2_W, 3787 .writefn = tlbiall_hyp_write }, 3788 { .name = "TLBIALLHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0, 3789 .type = ARM_CP_NO_RAW, .access = PL2_W, 3790 .writefn = tlbiall_hyp_is_write }, 3791 { .name = "TLBIMVAH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1, 3792 .type = ARM_CP_NO_RAW, .access = PL2_W, 3793 .writefn = tlbimva_hyp_write }, 3794 { .name = "TLBIMVAHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1, 3795 .type = ARM_CP_NO_RAW, .access = PL2_W, 3796 .writefn = tlbimva_hyp_is_write }, 3797 { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64, 3798 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0, 3799 .type = ARM_CP_NO_RAW, .access = PL2_W, 3800 .writefn = tlbi_aa64_alle2_write }, 3801 { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64, 3802 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1, 3803 .type = ARM_CP_NO_RAW, .access = PL2_W, 3804 .writefn = tlbi_aa64_vae2_write }, 3805 { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64, 3806 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5, 3807 .access = PL2_W, .type = ARM_CP_NO_RAW, 3808 .writefn = tlbi_aa64_vae2_write }, 3809 { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64, 3810 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0, 3811 .access = PL2_W, .type = ARM_CP_NO_RAW, 3812 .writefn = tlbi_aa64_alle2is_write }, 3813 { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64, 3814 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1, 3815 .type = ARM_CP_NO_RAW, .access = PL2_W, 3816 .writefn = tlbi_aa64_vae2is_write }, 3817 { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64, 3818 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5, 3819 .access = PL2_W, .type = ARM_CP_NO_RAW, 3820 .writefn = tlbi_aa64_vae2is_write }, 3821 #ifndef CONFIG_USER_ONLY 3822 /* Unlike the other EL2-related AT operations, these must 3823 * UNDEF from EL3 if EL2 is not implemented, which is why we 3824 * define them here rather than with the rest of the AT ops. 3825 */ 3826 { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64, 3827 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, 3828 .access = PL2_W, .accessfn = at_s1e2_access, 3829 .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3830 { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64, 3831 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, 3832 .access = PL2_W, .accessfn = at_s1e2_access, 3833 .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, 3834 /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE 3835 * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3 3836 * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose 3837 * to behave as if SCR.NS was 1. 3838 */ 3839 { .name = "ATS1HR", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, 3840 .access = PL2_W, 3841 .writefn = ats1h_write, .type = ARM_CP_NO_RAW }, 3842 { .name = "ATS1HW", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, 3843 .access = PL2_W, 3844 .writefn = ats1h_write, .type = ARM_CP_NO_RAW }, 3845 { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH, 3846 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0, 3847 /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the 3848 * reset values as IMPDEF. We choose to reset to 3 to comply with 3849 * both ARMv7 and ARMv8. 3850 */ 3851 .access = PL2_RW, .resetvalue = 3, 3852 .fieldoffset = offsetof(CPUARMState, cp15.cnthctl_el2) }, 3853 { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64, 3854 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3, 3855 .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0, 3856 .writefn = gt_cntvoff_write, 3857 .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) }, 3858 { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14, 3859 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS | ARM_CP_IO, 3860 .writefn = gt_cntvoff_write, 3861 .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) }, 3862 { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64, 3863 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2, 3864 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval), 3865 .type = ARM_CP_IO, .access = PL2_RW, 3866 .writefn = gt_hyp_cval_write, .raw_writefn = raw_write }, 3867 { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14, 3868 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval), 3869 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_IO, 3870 .writefn = gt_hyp_cval_write, .raw_writefn = raw_write }, 3871 { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH, 3872 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0, 3873 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW, 3874 .resetfn = gt_hyp_timer_reset, 3875 .readfn = gt_hyp_tval_read, .writefn = gt_hyp_tval_write }, 3876 { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, 3877 .type = ARM_CP_IO, 3878 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, 3879 .access = PL2_RW, 3880 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].ctl), 3881 .resetvalue = 0, 3882 .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write }, 3883 #endif 3884 /* The only field of MDCR_EL2 that has a defined architectural reset value 3885 * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but we 3886 * don't impelment any PMU event counters, so using zero as a reset 3887 * value for MDCR_EL2 is okay 3888 */ 3889 { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, 3890 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1, 3891 .access = PL2_RW, .resetvalue = 0, 3892 .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), }, 3893 { .name = "HPFAR", .state = ARM_CP_STATE_AA32, 3894 .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, 3895 .access = PL2_RW, .accessfn = access_el3_aa32ns, 3896 .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, 3897 { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64, 3898 .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, 3899 .access = PL2_RW, 3900 .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, 3901 { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH, 3902 .cp = 15, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3, 3903 .access = PL2_RW, 3904 .fieldoffset = offsetof(CPUARMState, cp15.hstr_el2) }, 3905 REGINFO_SENTINEL 3906 }; 3907 3908 static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri, 3909 bool isread) 3910 { 3911 /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2. 3912 * At Secure EL1 it traps to EL3. 3913 */ 3914 if (arm_current_el(env) == 3) { 3915 return CP_ACCESS_OK; 3916 } 3917 if (arm_is_secure_below_el3(env)) { 3918 return CP_ACCESS_TRAP_EL3; 3919 } 3920 /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */ 3921 if (isread) { 3922 return CP_ACCESS_OK; 3923 } 3924 return CP_ACCESS_TRAP_UNCATEGORIZED; 3925 } 3926 3927 static const ARMCPRegInfo el3_cp_reginfo[] = { 3928 { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64, 3929 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0, 3930 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), 3931 .resetvalue = 0, .writefn = scr_write }, 3932 { .name = "SCR", .type = ARM_CP_ALIAS, 3933 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0, 3934 .access = PL1_RW, .accessfn = access_trap_aa32s_el1, 3935 .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3), 3936 .writefn = scr_write }, 3937 { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64, 3938 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1, 3939 .access = PL3_RW, .resetvalue = 0, 3940 .fieldoffset = offsetof(CPUARMState, cp15.sder) }, 3941 { .name = "SDER", 3942 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1, 3943 .access = PL3_RW, .resetvalue = 0, 3944 .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) }, 3945 { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, 3946 .access = PL1_RW, .accessfn = access_trap_aa32s_el1, 3947 .writefn = vbar_write, .resetvalue = 0, 3948 .fieldoffset = offsetof(CPUARMState, cp15.mvbar) }, 3949 { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64, 3950 .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0, 3951 .access = PL3_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0, 3952 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) }, 3953 { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64, 3954 .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2, 3955 .access = PL3_RW, 3956 /* no .writefn needed as this can't cause an ASID change; 3957 * we must provide a .raw_writefn and .resetfn because we handle 3958 * reset and migration for the AArch32 TTBCR(S), which might be 3959 * using mask and base_mask. 3960 */ 3961 .resetfn = vmsa_ttbcr_reset, .raw_writefn = vmsa_ttbcr_raw_write, 3962 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) }, 3963 { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64, 3964 .type = ARM_CP_ALIAS, 3965 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1, 3966 .access = PL3_RW, 3967 .fieldoffset = offsetof(CPUARMState, elr_el[3]) }, 3968 { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64, 3969 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0, 3970 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) }, 3971 { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64, 3972 .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0, 3973 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) }, 3974 { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64, 3975 .type = ARM_CP_ALIAS, 3976 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0, 3977 .access = PL3_RW, 3978 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_MON]) }, 3979 { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64, 3980 .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0, 3981 .access = PL3_RW, .writefn = vbar_write, 3982 .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]), 3983 .resetvalue = 0 }, 3984 { .name = "CPTR_EL3", .state = ARM_CP_STATE_AA64, 3985 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 2, 3986 .access = PL3_RW, .accessfn = cptr_access, .resetvalue = 0, 3987 .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[3]) }, 3988 { .name = "TPIDR_EL3", .state = ARM_CP_STATE_AA64, 3989 .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 2, 3990 .access = PL3_RW, .resetvalue = 0, 3991 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[3]) }, 3992 { .name = "AMAIR_EL3", .state = ARM_CP_STATE_AA64, 3993 .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0, 3994 .access = PL3_RW, .type = ARM_CP_CONST, 3995 .resetvalue = 0 }, 3996 { .name = "AFSR0_EL3", .state = ARM_CP_STATE_BOTH, 3997 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 0, 3998 .access = PL3_RW, .type = ARM_CP_CONST, 3999 .resetvalue = 0 }, 4000 { .name = "AFSR1_EL3", .state = ARM_CP_STATE_BOTH, 4001 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 1, 4002 .access = PL3_RW, .type = ARM_CP_CONST, 4003 .resetvalue = 0 }, 4004 { .name = "TLBI_ALLE3IS", .state = ARM_CP_STATE_AA64, 4005 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 0, 4006 .access = PL3_W, .type = ARM_CP_NO_RAW, 4007 .writefn = tlbi_aa64_alle3is_write }, 4008 { .name = "TLBI_VAE3IS", .state = ARM_CP_STATE_AA64, 4009 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 1, 4010 .access = PL3_W, .type = ARM_CP_NO_RAW, 4011 .writefn = tlbi_aa64_vae3is_write }, 4012 { .name = "TLBI_VALE3IS", .state = ARM_CP_STATE_AA64, 4013 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 5, 4014 .access = PL3_W, .type = ARM_CP_NO_RAW, 4015 .writefn = tlbi_aa64_vae3is_write }, 4016 { .name = "TLBI_ALLE3", .state = ARM_CP_STATE_AA64, 4017 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 0, 4018 .access = PL3_W, .type = ARM_CP_NO_RAW, 4019 .writefn = tlbi_aa64_alle3_write }, 4020 { .name = "TLBI_VAE3", .state = ARM_CP_STATE_AA64, 4021 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 1, 4022 .access = PL3_W, .type = ARM_CP_NO_RAW, 4023 .writefn = tlbi_aa64_vae3_write }, 4024 { .name = "TLBI_VALE3", .state = ARM_CP_STATE_AA64, 4025 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5, 4026 .access = PL3_W, .type = ARM_CP_NO_RAW, 4027 .writefn = tlbi_aa64_vae3_write }, 4028 REGINFO_SENTINEL 4029 }; 4030 4031 static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri, 4032 bool isread) 4033 { 4034 /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64, 4035 * but the AArch32 CTR has its own reginfo struct) 4036 */ 4037 if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCT)) { 4038 return CP_ACCESS_TRAP; 4039 } 4040 return CP_ACCESS_OK; 4041 } 4042 4043 static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri, 4044 uint64_t value) 4045 { 4046 /* Writes to OSLAR_EL1 may update the OS lock status, which can be 4047 * read via a bit in OSLSR_EL1. 4048 */ 4049 int oslock; 4050 4051 if (ri->state == ARM_CP_STATE_AA32) { 4052 oslock = (value == 0xC5ACCE55); 4053 } else { 4054 oslock = value & 1; 4055 } 4056 4057 env->cp15.oslsr_el1 = deposit32(env->cp15.oslsr_el1, 1, 1, oslock); 4058 } 4059 4060 static const ARMCPRegInfo debug_cp_reginfo[] = { 4061 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped 4062 * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1; 4063 * unlike DBGDRAR it is never accessible from EL0. 4064 * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64 4065 * accessor. 4066 */ 4067 { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0, 4068 .access = PL0_R, .accessfn = access_tdra, 4069 .type = ARM_CP_CONST, .resetvalue = 0 }, 4070 { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64, 4071 .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, 4072 .access = PL1_R, .accessfn = access_tdra, 4073 .type = ARM_CP_CONST, .resetvalue = 0 }, 4074 { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, 4075 .access = PL0_R, .accessfn = access_tdra, 4076 .type = ARM_CP_CONST, .resetvalue = 0 }, 4077 /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */ 4078 { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH, 4079 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, 4080 .access = PL1_RW, .accessfn = access_tda, 4081 .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), 4082 .resetvalue = 0 }, 4083 /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1. 4084 * We don't implement the configurable EL0 access. 4085 */ 4086 { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH, 4087 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, 4088 .type = ARM_CP_ALIAS, 4089 .access = PL1_R, .accessfn = access_tda, 4090 .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), }, 4091 { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH, 4092 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4, 4093 .access = PL1_W, .type = ARM_CP_NO_RAW, 4094 .accessfn = access_tdosa, 4095 .writefn = oslar_write }, 4096 { .name = "OSLSR_EL1", .state = ARM_CP_STATE_BOTH, 4097 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 4, 4098 .access = PL1_R, .resetvalue = 10, 4099 .accessfn = access_tdosa, 4100 .fieldoffset = offsetof(CPUARMState, cp15.oslsr_el1) }, 4101 /* Dummy OSDLR_EL1: 32-bit Linux will read this */ 4102 { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH, 4103 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4, 4104 .access = PL1_RW, .accessfn = access_tdosa, 4105 .type = ARM_CP_NOP }, 4106 /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't 4107 * implement vector catch debug events yet. 4108 */ 4109 { .name = "DBGVCR", 4110 .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, 4111 .access = PL1_RW, .accessfn = access_tda, 4112 .type = ARM_CP_NOP }, 4113 /* Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor 4114 * to save and restore a 32-bit guest's DBGVCR) 4115 */ 4116 { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64, 4117 .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0, 4118 .access = PL2_RW, .accessfn = access_tda, 4119 .type = ARM_CP_NOP }, 4120 /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications 4121 * Channel but Linux may try to access this register. The 32-bit 4122 * alias is DBGDCCINT. 4123 */ 4124 { .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH, 4125 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, 4126 .access = PL1_RW, .accessfn = access_tda, 4127 .type = ARM_CP_NOP }, 4128 REGINFO_SENTINEL 4129 }; 4130 4131 static const ARMCPRegInfo debug_lpae_cp_reginfo[] = { 4132 /* 64 bit access versions of the (dummy) debug registers */ 4133 { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0, 4134 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, 4135 { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0, 4136 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, 4137 REGINFO_SENTINEL 4138 }; 4139 4140 void hw_watchpoint_update(ARMCPU *cpu, int n) 4141 { 4142 CPUARMState *env = &cpu->env; 4143 vaddr len = 0; 4144 vaddr wvr = env->cp15.dbgwvr[n]; 4145 uint64_t wcr = env->cp15.dbgwcr[n]; 4146 int mask; 4147 int flags = BP_CPU | BP_STOP_BEFORE_ACCESS; 4148 4149 if (env->cpu_watchpoint[n]) { 4150 cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]); 4151 env->cpu_watchpoint[n] = NULL; 4152 } 4153 4154 if (!extract64(wcr, 0, 1)) { 4155 /* E bit clear : watchpoint disabled */ 4156 return; 4157 } 4158 4159 switch (extract64(wcr, 3, 2)) { 4160 case 0: 4161 /* LSC 00 is reserved and must behave as if the wp is disabled */ 4162 return; 4163 case 1: 4164 flags |= BP_MEM_READ; 4165 break; 4166 case 2: 4167 flags |= BP_MEM_WRITE; 4168 break; 4169 case 3: 4170 flags |= BP_MEM_ACCESS; 4171 break; 4172 } 4173 4174 /* Attempts to use both MASK and BAS fields simultaneously are 4175 * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case, 4176 * thus generating a watchpoint for every byte in the masked region. 4177 */ 4178 mask = extract64(wcr, 24, 4); 4179 if (mask == 1 || mask == 2) { 4180 /* Reserved values of MASK; we must act as if the mask value was 4181 * some non-reserved value, or as if the watchpoint were disabled. 4182 * We choose the latter. 4183 */ 4184 return; 4185 } else if (mask) { 4186 /* Watchpoint covers an aligned area up to 2GB in size */ 4187 len = 1ULL << mask; 4188 /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE 4189 * whether the watchpoint fires when the unmasked bits match; we opt 4190 * to generate the exceptions. 4191 */ 4192 wvr &= ~(len - 1); 4193 } else { 4194 /* Watchpoint covers bytes defined by the byte address select bits */ 4195 int bas = extract64(wcr, 5, 8); 4196 int basstart; 4197 4198 if (bas == 0) { 4199 /* This must act as if the watchpoint is disabled */ 4200 return; 4201 } 4202 4203 if (extract64(wvr, 2, 1)) { 4204 /* Deprecated case of an only 4-aligned address. BAS[7:4] are 4205 * ignored, and BAS[3:0] define which bytes to watch. 4206 */ 4207 bas &= 0xf; 4208 } 4209 /* The BAS bits are supposed to be programmed to indicate a contiguous 4210 * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether 4211 * we fire for each byte in the word/doubleword addressed by the WVR. 4212 * We choose to ignore any non-zero bits after the first range of 1s. 4213 */ 4214 basstart = ctz32(bas); 4215 len = cto32(bas >> basstart); 4216 wvr += basstart; 4217 } 4218 4219 cpu_watchpoint_insert(CPU(cpu), wvr, len, flags, 4220 &env->cpu_watchpoint[n]); 4221 } 4222 4223 void hw_watchpoint_update_all(ARMCPU *cpu) 4224 { 4225 int i; 4226 CPUARMState *env = &cpu->env; 4227 4228 /* Completely clear out existing QEMU watchpoints and our array, to 4229 * avoid possible stale entries following migration load. 4230 */ 4231 cpu_watchpoint_remove_all(CPU(cpu), BP_CPU); 4232 memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint)); 4233 4234 for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) { 4235 hw_watchpoint_update(cpu, i); 4236 } 4237 } 4238 4239 static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri, 4240 uint64_t value) 4241 { 4242 ARMCPU *cpu = arm_env_get_cpu(env); 4243 int i = ri->crm; 4244 4245 /* Bits [63:49] are hardwired to the value of bit [48]; that is, the 4246 * register reads and behaves as if values written are sign extended. 4247 * Bits [1:0] are RES0. 4248 */ 4249 value = sextract64(value, 0, 49) & ~3ULL; 4250 4251 raw_write(env, ri, value); 4252 hw_watchpoint_update(cpu, i); 4253 } 4254 4255 static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri, 4256 uint64_t value) 4257 { 4258 ARMCPU *cpu = arm_env_get_cpu(env); 4259 int i = ri->crm; 4260 4261 raw_write(env, ri, value); 4262 hw_watchpoint_update(cpu, i); 4263 } 4264 4265 void hw_breakpoint_update(ARMCPU *cpu, int n) 4266 { 4267 CPUARMState *env = &cpu->env; 4268 uint64_t bvr = env->cp15.dbgbvr[n]; 4269 uint64_t bcr = env->cp15.dbgbcr[n]; 4270 vaddr addr; 4271 int bt; 4272 int flags = BP_CPU; 4273 4274 if (env->cpu_breakpoint[n]) { 4275 cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]); 4276 env->cpu_breakpoint[n] = NULL; 4277 } 4278 4279 if (!extract64(bcr, 0, 1)) { 4280 /* E bit clear : watchpoint disabled */ 4281 return; 4282 } 4283 4284 bt = extract64(bcr, 20, 4); 4285 4286 switch (bt) { 4287 case 4: /* unlinked address mismatch (reserved if AArch64) */ 4288 case 5: /* linked address mismatch (reserved if AArch64) */ 4289 qemu_log_mask(LOG_UNIMP, 4290 "arm: address mismatch breakpoint types not implemented"); 4291 return; 4292 case 0: /* unlinked address match */ 4293 case 1: /* linked address match */ 4294 { 4295 /* Bits [63:49] are hardwired to the value of bit [48]; that is, 4296 * we behave as if the register was sign extended. Bits [1:0] are 4297 * RES0. The BAS field is used to allow setting breakpoints on 16 4298 * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether 4299 * a bp will fire if the addresses covered by the bp and the addresses 4300 * covered by the insn overlap but the insn doesn't start at the 4301 * start of the bp address range. We choose to require the insn and 4302 * the bp to have the same address. The constraints on writing to 4303 * BAS enforced in dbgbcr_write mean we have only four cases: 4304 * 0b0000 => no breakpoint 4305 * 0b0011 => breakpoint on addr 4306 * 0b1100 => breakpoint on addr + 2 4307 * 0b1111 => breakpoint on addr 4308 * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c). 4309 */ 4310 int bas = extract64(bcr, 5, 4); 4311 addr = sextract64(bvr, 0, 49) & ~3ULL; 4312 if (bas == 0) { 4313 return; 4314 } 4315 if (bas == 0xc) { 4316 addr += 2; 4317 } 4318 break; 4319 } 4320 case 2: /* unlinked context ID match */ 4321 case 8: /* unlinked VMID match (reserved if no EL2) */ 4322 case 10: /* unlinked context ID and VMID match (reserved if no EL2) */ 4323 qemu_log_mask(LOG_UNIMP, 4324 "arm: unlinked context breakpoint types not implemented"); 4325 return; 4326 case 9: /* linked VMID match (reserved if no EL2) */ 4327 case 11: /* linked context ID and VMID match (reserved if no EL2) */ 4328 case 3: /* linked context ID match */ 4329 default: 4330 /* We must generate no events for Linked context matches (unless 4331 * they are linked to by some other bp/wp, which is handled in 4332 * updates for the linking bp/wp). We choose to also generate no events 4333 * for reserved values. 4334 */ 4335 return; 4336 } 4337 4338 cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]); 4339 } 4340 4341 void hw_breakpoint_update_all(ARMCPU *cpu) 4342 { 4343 int i; 4344 CPUARMState *env = &cpu->env; 4345 4346 /* Completely clear out existing QEMU breakpoints and our array, to 4347 * avoid possible stale entries following migration load. 4348 */ 4349 cpu_breakpoint_remove_all(CPU(cpu), BP_CPU); 4350 memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint)); 4351 4352 for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) { 4353 hw_breakpoint_update(cpu, i); 4354 } 4355 } 4356 4357 static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri, 4358 uint64_t value) 4359 { 4360 ARMCPU *cpu = arm_env_get_cpu(env); 4361 int i = ri->crm; 4362 4363 raw_write(env, ri, value); 4364 hw_breakpoint_update(cpu, i); 4365 } 4366 4367 static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, 4368 uint64_t value) 4369 { 4370 ARMCPU *cpu = arm_env_get_cpu(env); 4371 int i = ri->crm; 4372 4373 /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only 4374 * copy of BAS[0]. 4375 */ 4376 value = deposit64(value, 6, 1, extract64(value, 5, 1)); 4377 value = deposit64(value, 8, 1, extract64(value, 7, 1)); 4378 4379 raw_write(env, ri, value); 4380 hw_breakpoint_update(cpu, i); 4381 } 4382 4383 static void define_debug_regs(ARMCPU *cpu) 4384 { 4385 /* Define v7 and v8 architectural debug registers. 4386 * These are just dummy implementations for now. 4387 */ 4388 int i; 4389 int wrps, brps, ctx_cmps; 4390 ARMCPRegInfo dbgdidr = { 4391 .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, 4392 .access = PL0_R, .accessfn = access_tda, 4393 .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr, 4394 }; 4395 4396 /* Note that all these register fields hold "number of Xs minus 1". */ 4397 brps = extract32(cpu->dbgdidr, 24, 4); 4398 wrps = extract32(cpu->dbgdidr, 28, 4); 4399 ctx_cmps = extract32(cpu->dbgdidr, 20, 4); 4400 4401 assert(ctx_cmps <= brps); 4402 4403 /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties 4404 * of the debug registers such as number of breakpoints; 4405 * check that if they both exist then they agree. 4406 */ 4407 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 4408 assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps); 4409 assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps); 4410 assert(extract32(cpu->id_aa64dfr0, 28, 4) == ctx_cmps); 4411 } 4412 4413 define_one_arm_cp_reg(cpu, &dbgdidr); 4414 define_arm_cp_regs(cpu, debug_cp_reginfo); 4415 4416 if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) { 4417 define_arm_cp_regs(cpu, debug_lpae_cp_reginfo); 4418 } 4419 4420 for (i = 0; i < brps + 1; i++) { 4421 ARMCPRegInfo dbgregs[] = { 4422 { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH, 4423 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4, 4424 .access = PL1_RW, .accessfn = access_tda, 4425 .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]), 4426 .writefn = dbgbvr_write, .raw_writefn = raw_write 4427 }, 4428 { .name = "DBGBCR", .state = ARM_CP_STATE_BOTH, 4429 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5, 4430 .access = PL1_RW, .accessfn = access_tda, 4431 .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]), 4432 .writefn = dbgbcr_write, .raw_writefn = raw_write 4433 }, 4434 REGINFO_SENTINEL 4435 }; 4436 define_arm_cp_regs(cpu, dbgregs); 4437 } 4438 4439 for (i = 0; i < wrps + 1; i++) { 4440 ARMCPRegInfo dbgregs[] = { 4441 { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH, 4442 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6, 4443 .access = PL1_RW, .accessfn = access_tda, 4444 .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]), 4445 .writefn = dbgwvr_write, .raw_writefn = raw_write 4446 }, 4447 { .name = "DBGWCR", .state = ARM_CP_STATE_BOTH, 4448 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7, 4449 .access = PL1_RW, .accessfn = access_tda, 4450 .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]), 4451 .writefn = dbgwcr_write, .raw_writefn = raw_write 4452 }, 4453 REGINFO_SENTINEL 4454 }; 4455 define_arm_cp_regs(cpu, dbgregs); 4456 } 4457 } 4458 4459 void register_cp_regs_for_features(ARMCPU *cpu) 4460 { 4461 /* Register all the coprocessor registers based on feature bits */ 4462 CPUARMState *env = &cpu->env; 4463 if (arm_feature(env, ARM_FEATURE_M)) { 4464 /* M profile has no coprocessor registers */ 4465 return; 4466 } 4467 4468 define_arm_cp_regs(cpu, cp_reginfo); 4469 if (!arm_feature(env, ARM_FEATURE_V8)) { 4470 /* Must go early as it is full of wildcards that may be 4471 * overridden by later definitions. 4472 */ 4473 define_arm_cp_regs(cpu, not_v8_cp_reginfo); 4474 } 4475 4476 if (arm_feature(env, ARM_FEATURE_V6)) { 4477 /* The ID registers all have impdef reset values */ 4478 ARMCPRegInfo v6_idregs[] = { 4479 { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH, 4480 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, 4481 .access = PL1_R, .type = ARM_CP_CONST, 4482 .resetvalue = cpu->id_pfr0 }, 4483 { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH, 4484 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1, 4485 .access = PL1_R, .type = ARM_CP_CONST, 4486 .resetvalue = cpu->id_pfr1 }, 4487 { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH, 4488 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2, 4489 .access = PL1_R, .type = ARM_CP_CONST, 4490 .resetvalue = cpu->id_dfr0 }, 4491 { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH, 4492 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3, 4493 .access = PL1_R, .type = ARM_CP_CONST, 4494 .resetvalue = cpu->id_afr0 }, 4495 { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH, 4496 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4, 4497 .access = PL1_R, .type = ARM_CP_CONST, 4498 .resetvalue = cpu->id_mmfr0 }, 4499 { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH, 4500 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5, 4501 .access = PL1_R, .type = ARM_CP_CONST, 4502 .resetvalue = cpu->id_mmfr1 }, 4503 { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH, 4504 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6, 4505 .access = PL1_R, .type = ARM_CP_CONST, 4506 .resetvalue = cpu->id_mmfr2 }, 4507 { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH, 4508 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7, 4509 .access = PL1_R, .type = ARM_CP_CONST, 4510 .resetvalue = cpu->id_mmfr3 }, 4511 { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH, 4512 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, 4513 .access = PL1_R, .type = ARM_CP_CONST, 4514 .resetvalue = cpu->id_isar0 }, 4515 { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH, 4516 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1, 4517 .access = PL1_R, .type = ARM_CP_CONST, 4518 .resetvalue = cpu->id_isar1 }, 4519 { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH, 4520 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, 4521 .access = PL1_R, .type = ARM_CP_CONST, 4522 .resetvalue = cpu->id_isar2 }, 4523 { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH, 4524 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3, 4525 .access = PL1_R, .type = ARM_CP_CONST, 4526 .resetvalue = cpu->id_isar3 }, 4527 { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH, 4528 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4, 4529 .access = PL1_R, .type = ARM_CP_CONST, 4530 .resetvalue = cpu->id_isar4 }, 4531 { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH, 4532 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5, 4533 .access = PL1_R, .type = ARM_CP_CONST, 4534 .resetvalue = cpu->id_isar5 }, 4535 { .name = "ID_MMFR4", .state = ARM_CP_STATE_BOTH, 4536 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6, 4537 .access = PL1_R, .type = ARM_CP_CONST, 4538 .resetvalue = cpu->id_mmfr4 }, 4539 /* 7 is as yet unallocated and must RAZ */ 4540 { .name = "ID_ISAR7_RESERVED", .state = ARM_CP_STATE_BOTH, 4541 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7, 4542 .access = PL1_R, .type = ARM_CP_CONST, 4543 .resetvalue = 0 }, 4544 REGINFO_SENTINEL 4545 }; 4546 define_arm_cp_regs(cpu, v6_idregs); 4547 define_arm_cp_regs(cpu, v6_cp_reginfo); 4548 } else { 4549 define_arm_cp_regs(cpu, not_v6_cp_reginfo); 4550 } 4551 if (arm_feature(env, ARM_FEATURE_V6K)) { 4552 define_arm_cp_regs(cpu, v6k_cp_reginfo); 4553 } 4554 if (arm_feature(env, ARM_FEATURE_V7MP) && 4555 !arm_feature(env, ARM_FEATURE_MPU)) { 4556 define_arm_cp_regs(cpu, v7mp_cp_reginfo); 4557 } 4558 if (arm_feature(env, ARM_FEATURE_V7)) { 4559 /* v7 performance monitor control register: same implementor 4560 * field as main ID register, and we implement only the cycle 4561 * count register. 4562 */ 4563 #ifndef CONFIG_USER_ONLY 4564 ARMCPRegInfo pmcr = { 4565 .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0, 4566 .access = PL0_RW, 4567 .type = ARM_CP_IO | ARM_CP_ALIAS, 4568 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr), 4569 .accessfn = pmreg_access, .writefn = pmcr_write, 4570 .raw_writefn = raw_write, 4571 }; 4572 ARMCPRegInfo pmcr64 = { 4573 .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64, 4574 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0, 4575 .access = PL0_RW, .accessfn = pmreg_access, 4576 .type = ARM_CP_IO, 4577 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr), 4578 .resetvalue = cpu->midr & 0xff000000, 4579 .writefn = pmcr_write, .raw_writefn = raw_write, 4580 }; 4581 define_one_arm_cp_reg(cpu, &pmcr); 4582 define_one_arm_cp_reg(cpu, &pmcr64); 4583 #endif 4584 ARMCPRegInfo clidr = { 4585 .name = "CLIDR", .state = ARM_CP_STATE_BOTH, 4586 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1, 4587 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr 4588 }; 4589 define_one_arm_cp_reg(cpu, &clidr); 4590 define_arm_cp_regs(cpu, v7_cp_reginfo); 4591 define_debug_regs(cpu); 4592 } else { 4593 define_arm_cp_regs(cpu, not_v7_cp_reginfo); 4594 } 4595 if (arm_feature(env, ARM_FEATURE_V8)) { 4596 /* AArch64 ID registers, which all have impdef reset values. 4597 * Note that within the ID register ranges the unused slots 4598 * must all RAZ, not UNDEF; future architecture versions may 4599 * define new registers here. 4600 */ 4601 ARMCPRegInfo v8_idregs[] = { 4602 { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64, 4603 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0, 4604 .access = PL1_R, .type = ARM_CP_CONST, 4605 .resetvalue = cpu->id_aa64pfr0 }, 4606 { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64, 4607 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1, 4608 .access = PL1_R, .type = ARM_CP_CONST, 4609 .resetvalue = cpu->id_aa64pfr1}, 4610 { .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4611 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2, 4612 .access = PL1_R, .type = ARM_CP_CONST, 4613 .resetvalue = 0 }, 4614 { .name = "ID_AA64PFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4615 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3, 4616 .access = PL1_R, .type = ARM_CP_CONST, 4617 .resetvalue = 0 }, 4618 { .name = "ID_AA64PFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4619 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4, 4620 .access = PL1_R, .type = ARM_CP_CONST, 4621 .resetvalue = 0 }, 4622 { .name = "ID_AA64PFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4623 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5, 4624 .access = PL1_R, .type = ARM_CP_CONST, 4625 .resetvalue = 0 }, 4626 { .name = "ID_AA64PFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4627 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6, 4628 .access = PL1_R, .type = ARM_CP_CONST, 4629 .resetvalue = 0 }, 4630 { .name = "ID_AA64PFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4631 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 7, 4632 .access = PL1_R, .type = ARM_CP_CONST, 4633 .resetvalue = 0 }, 4634 { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64, 4635 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0, 4636 .access = PL1_R, .type = ARM_CP_CONST, 4637 .resetvalue = cpu->id_aa64dfr0 }, 4638 { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64, 4639 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1, 4640 .access = PL1_R, .type = ARM_CP_CONST, 4641 .resetvalue = cpu->id_aa64dfr1 }, 4642 { .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4643 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2, 4644 .access = PL1_R, .type = ARM_CP_CONST, 4645 .resetvalue = 0 }, 4646 { .name = "ID_AA64DFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4647 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 3, 4648 .access = PL1_R, .type = ARM_CP_CONST, 4649 .resetvalue = 0 }, 4650 { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64, 4651 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4, 4652 .access = PL1_R, .type = ARM_CP_CONST, 4653 .resetvalue = cpu->id_aa64afr0 }, 4654 { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64, 4655 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5, 4656 .access = PL1_R, .type = ARM_CP_CONST, 4657 .resetvalue = cpu->id_aa64afr1 }, 4658 { .name = "ID_AA64AFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4659 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 6, 4660 .access = PL1_R, .type = ARM_CP_CONST, 4661 .resetvalue = 0 }, 4662 { .name = "ID_AA64AFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4663 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 7, 4664 .access = PL1_R, .type = ARM_CP_CONST, 4665 .resetvalue = 0 }, 4666 { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64, 4667 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0, 4668 .access = PL1_R, .type = ARM_CP_CONST, 4669 .resetvalue = cpu->id_aa64isar0 }, 4670 { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64, 4671 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1, 4672 .access = PL1_R, .type = ARM_CP_CONST, 4673 .resetvalue = cpu->id_aa64isar1 }, 4674 { .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4675 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2, 4676 .access = PL1_R, .type = ARM_CP_CONST, 4677 .resetvalue = 0 }, 4678 { .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4679 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3, 4680 .access = PL1_R, .type = ARM_CP_CONST, 4681 .resetvalue = 0 }, 4682 { .name = "ID_AA64ISAR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4683 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 4, 4684 .access = PL1_R, .type = ARM_CP_CONST, 4685 .resetvalue = 0 }, 4686 { .name = "ID_AA64ISAR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4687 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 5, 4688 .access = PL1_R, .type = ARM_CP_CONST, 4689 .resetvalue = 0 }, 4690 { .name = "ID_AA64ISAR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4691 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 6, 4692 .access = PL1_R, .type = ARM_CP_CONST, 4693 .resetvalue = 0 }, 4694 { .name = "ID_AA64ISAR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4695 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 7, 4696 .access = PL1_R, .type = ARM_CP_CONST, 4697 .resetvalue = 0 }, 4698 { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64, 4699 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, 4700 .access = PL1_R, .type = ARM_CP_CONST, 4701 .resetvalue = cpu->id_aa64mmfr0 }, 4702 { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64, 4703 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1, 4704 .access = PL1_R, .type = ARM_CP_CONST, 4705 .resetvalue = cpu->id_aa64mmfr1 }, 4706 { .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4707 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2, 4708 .access = PL1_R, .type = ARM_CP_CONST, 4709 .resetvalue = 0 }, 4710 { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4711 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3, 4712 .access = PL1_R, .type = ARM_CP_CONST, 4713 .resetvalue = 0 }, 4714 { .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4715 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4, 4716 .access = PL1_R, .type = ARM_CP_CONST, 4717 .resetvalue = 0 }, 4718 { .name = "ID_AA64MMFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4719 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5, 4720 .access = PL1_R, .type = ARM_CP_CONST, 4721 .resetvalue = 0 }, 4722 { .name = "ID_AA64MMFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4723 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 6, 4724 .access = PL1_R, .type = ARM_CP_CONST, 4725 .resetvalue = 0 }, 4726 { .name = "ID_AA64MMFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4727 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 7, 4728 .access = PL1_R, .type = ARM_CP_CONST, 4729 .resetvalue = 0 }, 4730 { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64, 4731 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0, 4732 .access = PL1_R, .type = ARM_CP_CONST, 4733 .resetvalue = cpu->mvfr0 }, 4734 { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64, 4735 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1, 4736 .access = PL1_R, .type = ARM_CP_CONST, 4737 .resetvalue = cpu->mvfr1 }, 4738 { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64, 4739 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2, 4740 .access = PL1_R, .type = ARM_CP_CONST, 4741 .resetvalue = cpu->mvfr2 }, 4742 { .name = "MVFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4743 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3, 4744 .access = PL1_R, .type = ARM_CP_CONST, 4745 .resetvalue = 0 }, 4746 { .name = "MVFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4747 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4, 4748 .access = PL1_R, .type = ARM_CP_CONST, 4749 .resetvalue = 0 }, 4750 { .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4751 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5, 4752 .access = PL1_R, .type = ARM_CP_CONST, 4753 .resetvalue = 0 }, 4754 { .name = "MVFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4755 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6, 4756 .access = PL1_R, .type = ARM_CP_CONST, 4757 .resetvalue = 0 }, 4758 { .name = "MVFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, 4759 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7, 4760 .access = PL1_R, .type = ARM_CP_CONST, 4761 .resetvalue = 0 }, 4762 { .name = "PMCEID0", .state = ARM_CP_STATE_AA32, 4763 .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6, 4764 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, 4765 .resetvalue = cpu->pmceid0 }, 4766 { .name = "PMCEID0_EL0", .state = ARM_CP_STATE_AA64, 4767 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 6, 4768 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, 4769 .resetvalue = cpu->pmceid0 }, 4770 { .name = "PMCEID1", .state = ARM_CP_STATE_AA32, 4771 .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 7, 4772 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, 4773 .resetvalue = cpu->pmceid1 }, 4774 { .name = "PMCEID1_EL0", .state = ARM_CP_STATE_AA64, 4775 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7, 4776 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, 4777 .resetvalue = cpu->pmceid1 }, 4778 REGINFO_SENTINEL 4779 }; 4780 /* RVBAR_EL1 is only implemented if EL1 is the highest EL */ 4781 if (!arm_feature(env, ARM_FEATURE_EL3) && 4782 !arm_feature(env, ARM_FEATURE_EL2)) { 4783 ARMCPRegInfo rvbar = { 4784 .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64, 4785 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, 4786 .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar 4787 }; 4788 define_one_arm_cp_reg(cpu, &rvbar); 4789 } 4790 define_arm_cp_regs(cpu, v8_idregs); 4791 define_arm_cp_regs(cpu, v8_cp_reginfo); 4792 } 4793 if (arm_feature(env, ARM_FEATURE_EL2)) { 4794 uint64_t vmpidr_def = mpidr_read_val(env); 4795 ARMCPRegInfo vpidr_regs[] = { 4796 { .name = "VPIDR", .state = ARM_CP_STATE_AA32, 4797 .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, 4798 .access = PL2_RW, .accessfn = access_el3_aa32ns, 4799 .resetvalue = cpu->midr, 4800 .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, 4801 { .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64, 4802 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, 4803 .access = PL2_RW, .resetvalue = cpu->midr, 4804 .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, 4805 { .name = "VMPIDR", .state = ARM_CP_STATE_AA32, 4806 .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, 4807 .access = PL2_RW, .accessfn = access_el3_aa32ns, 4808 .resetvalue = vmpidr_def, 4809 .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) }, 4810 { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64, 4811 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, 4812 .access = PL2_RW, 4813 .resetvalue = vmpidr_def, 4814 .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) }, 4815 REGINFO_SENTINEL 4816 }; 4817 define_arm_cp_regs(cpu, vpidr_regs); 4818 define_arm_cp_regs(cpu, el2_cp_reginfo); 4819 /* RVBAR_EL2 is only implemented if EL2 is the highest EL */ 4820 if (!arm_feature(env, ARM_FEATURE_EL3)) { 4821 ARMCPRegInfo rvbar = { 4822 .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64, 4823 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1, 4824 .type = ARM_CP_CONST, .access = PL2_R, .resetvalue = cpu->rvbar 4825 }; 4826 define_one_arm_cp_reg(cpu, &rvbar); 4827 } 4828 } else { 4829 /* If EL2 is missing but higher ELs are enabled, we need to 4830 * register the no_el2 reginfos. 4831 */ 4832 if (arm_feature(env, ARM_FEATURE_EL3)) { 4833 /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value 4834 * of MIDR_EL1 and MPIDR_EL1. 4835 */ 4836 ARMCPRegInfo vpidr_regs[] = { 4837 { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH, 4838 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, 4839 .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, 4840 .type = ARM_CP_CONST, .resetvalue = cpu->midr, 4841 .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, 4842 { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH, 4843 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, 4844 .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, 4845 .type = ARM_CP_NO_RAW, 4846 .writefn = arm_cp_write_ignore, .readfn = mpidr_read }, 4847 REGINFO_SENTINEL 4848 }; 4849 define_arm_cp_regs(cpu, vpidr_regs); 4850 define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo); 4851 } 4852 } 4853 if (arm_feature(env, ARM_FEATURE_EL3)) { 4854 define_arm_cp_regs(cpu, el3_cp_reginfo); 4855 ARMCPRegInfo el3_regs[] = { 4856 { .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64, 4857 .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1, 4858 .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar }, 4859 { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64, 4860 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0, 4861 .access = PL3_RW, 4862 .raw_writefn = raw_write, .writefn = sctlr_write, 4863 .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]), 4864 .resetvalue = cpu->reset_sctlr }, 4865 REGINFO_SENTINEL 4866 }; 4867 4868 define_arm_cp_regs(cpu, el3_regs); 4869 } 4870 /* The behaviour of NSACR is sufficiently various that we don't 4871 * try to describe it in a single reginfo: 4872 * if EL3 is 64 bit, then trap to EL3 from S EL1, 4873 * reads as constant 0xc00 from NS EL1 and NS EL2 4874 * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2 4875 * if v7 without EL3, register doesn't exist 4876 * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2 4877 */ 4878 if (arm_feature(env, ARM_FEATURE_EL3)) { 4879 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 4880 ARMCPRegInfo nsacr = { 4881 .name = "NSACR", .type = ARM_CP_CONST, 4882 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, 4883 .access = PL1_RW, .accessfn = nsacr_access, 4884 .resetvalue = 0xc00 4885 }; 4886 define_one_arm_cp_reg(cpu, &nsacr); 4887 } else { 4888 ARMCPRegInfo nsacr = { 4889 .name = "NSACR", 4890 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, 4891 .access = PL3_RW | PL1_R, 4892 .resetvalue = 0, 4893 .fieldoffset = offsetof(CPUARMState, cp15.nsacr) 4894 }; 4895 define_one_arm_cp_reg(cpu, &nsacr); 4896 } 4897 } else { 4898 if (arm_feature(env, ARM_FEATURE_V8)) { 4899 ARMCPRegInfo nsacr = { 4900 .name = "NSACR", .type = ARM_CP_CONST, 4901 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, 4902 .access = PL1_R, 4903 .resetvalue = 0xc00 4904 }; 4905 define_one_arm_cp_reg(cpu, &nsacr); 4906 } 4907 } 4908 4909 if (arm_feature(env, ARM_FEATURE_MPU)) { 4910 if (arm_feature(env, ARM_FEATURE_V6)) { 4911 /* PMSAv6 not implemented */ 4912 assert(arm_feature(env, ARM_FEATURE_V7)); 4913 define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); 4914 define_arm_cp_regs(cpu, pmsav7_cp_reginfo); 4915 } else { 4916 define_arm_cp_regs(cpu, pmsav5_cp_reginfo); 4917 } 4918 } else { 4919 define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); 4920 define_arm_cp_regs(cpu, vmsa_cp_reginfo); 4921 } 4922 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { 4923 define_arm_cp_regs(cpu, t2ee_cp_reginfo); 4924 } 4925 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { 4926 define_arm_cp_regs(cpu, generic_timer_cp_reginfo); 4927 } 4928 if (arm_feature(env, ARM_FEATURE_VAPA)) { 4929 define_arm_cp_regs(cpu, vapa_cp_reginfo); 4930 } 4931 if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) { 4932 define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo); 4933 } 4934 if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) { 4935 define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo); 4936 } 4937 if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) { 4938 define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo); 4939 } 4940 if (arm_feature(env, ARM_FEATURE_OMAPCP)) { 4941 define_arm_cp_regs(cpu, omap_cp_reginfo); 4942 } 4943 if (arm_feature(env, ARM_FEATURE_STRONGARM)) { 4944 define_arm_cp_regs(cpu, strongarm_cp_reginfo); 4945 } 4946 if (arm_feature(env, ARM_FEATURE_XSCALE)) { 4947 define_arm_cp_regs(cpu, xscale_cp_reginfo); 4948 } 4949 if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) { 4950 define_arm_cp_regs(cpu, dummy_c15_cp_reginfo); 4951 } 4952 if (arm_feature(env, ARM_FEATURE_LPAE)) { 4953 define_arm_cp_regs(cpu, lpae_cp_reginfo); 4954 } 4955 /* Slightly awkwardly, the OMAP and StrongARM cores need all of 4956 * cp15 crn=0 to be writes-ignored, whereas for other cores they should 4957 * be read-only (ie write causes UNDEF exception). 4958 */ 4959 { 4960 ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = { 4961 /* Pre-v8 MIDR space. 4962 * Note that the MIDR isn't a simple constant register because 4963 * of the TI925 behaviour where writes to another register can 4964 * cause the MIDR value to change. 4965 * 4966 * Unimplemented registers in the c15 0 0 0 space default to 4967 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR 4968 * and friends override accordingly. 4969 */ 4970 { .name = "MIDR", 4971 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY, 4972 .access = PL1_R, .resetvalue = cpu->midr, 4973 .writefn = arm_cp_write_ignore, .raw_writefn = raw_write, 4974 .readfn = midr_read, 4975 .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), 4976 .type = ARM_CP_OVERRIDE }, 4977 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */ 4978 { .name = "DUMMY", 4979 .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY, 4980 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 4981 { .name = "DUMMY", 4982 .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY, 4983 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 4984 { .name = "DUMMY", 4985 .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY, 4986 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 4987 { .name = "DUMMY", 4988 .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY, 4989 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 4990 { .name = "DUMMY", 4991 .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY, 4992 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 4993 REGINFO_SENTINEL 4994 }; 4995 ARMCPRegInfo id_v8_midr_cp_reginfo[] = { 4996 { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH, 4997 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0, 4998 .access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr, 4999 .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), 5000 .readfn = midr_read }, 5001 /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */ 5002 { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST, 5003 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4, 5004 .access = PL1_R, .resetvalue = cpu->midr }, 5005 { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST, 5006 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7, 5007 .access = PL1_R, .resetvalue = cpu->midr }, 5008 { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH, 5009 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6, 5010 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->revidr }, 5011 REGINFO_SENTINEL 5012 }; 5013 ARMCPRegInfo id_cp_reginfo[] = { 5014 /* These are common to v8 and pre-v8 */ 5015 { .name = "CTR", 5016 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1, 5017 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, 5018 { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64, 5019 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0, 5020 .access = PL0_R, .accessfn = ctr_el0_access, 5021 .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, 5022 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */ 5023 { .name = "TCMTR", 5024 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2, 5025 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 5026 REGINFO_SENTINEL 5027 }; 5028 /* TLBTR is specific to VMSA */ 5029 ARMCPRegInfo id_tlbtr_reginfo = { 5030 .name = "TLBTR", 5031 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3, 5032 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0, 5033 }; 5034 /* MPUIR is specific to PMSA V6+ */ 5035 ARMCPRegInfo id_mpuir_reginfo = { 5036 .name = "MPUIR", 5037 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4, 5038 .access = PL1_R, .type = ARM_CP_CONST, 5039 .resetvalue = cpu->pmsav7_dregion << 8 5040 }; 5041 ARMCPRegInfo crn0_wi_reginfo = { 5042 .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY, 5043 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W, 5044 .type = ARM_CP_NOP | ARM_CP_OVERRIDE 5045 }; 5046 if (arm_feature(env, ARM_FEATURE_OMAPCP) || 5047 arm_feature(env, ARM_FEATURE_STRONGARM)) { 5048 ARMCPRegInfo *r; 5049 /* Register the blanket "writes ignored" value first to cover the 5050 * whole space. Then update the specific ID registers to allow write 5051 * access, so that they ignore writes rather than causing them to 5052 * UNDEF. 5053 */ 5054 define_one_arm_cp_reg(cpu, &crn0_wi_reginfo); 5055 for (r = id_pre_v8_midr_cp_reginfo; 5056 r->type != ARM_CP_SENTINEL; r++) { 5057 r->access = PL1_RW; 5058 } 5059 for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) { 5060 r->access = PL1_RW; 5061 } 5062 id_tlbtr_reginfo.access = PL1_RW; 5063 id_tlbtr_reginfo.access = PL1_RW; 5064 } 5065 if (arm_feature(env, ARM_FEATURE_V8)) { 5066 define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo); 5067 } else { 5068 define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo); 5069 } 5070 define_arm_cp_regs(cpu, id_cp_reginfo); 5071 if (!arm_feature(env, ARM_FEATURE_MPU)) { 5072 define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo); 5073 } else if (arm_feature(env, ARM_FEATURE_V7)) { 5074 define_one_arm_cp_reg(cpu, &id_mpuir_reginfo); 5075 } 5076 } 5077 5078 if (arm_feature(env, ARM_FEATURE_MPIDR)) { 5079 define_arm_cp_regs(cpu, mpidr_cp_reginfo); 5080 } 5081 5082 if (arm_feature(env, ARM_FEATURE_AUXCR)) { 5083 ARMCPRegInfo auxcr_reginfo[] = { 5084 { .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH, 5085 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1, 5086 .access = PL1_RW, .type = ARM_CP_CONST, 5087 .resetvalue = cpu->reset_auxcr }, 5088 { .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH, 5089 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1, 5090 .access = PL2_RW, .type = ARM_CP_CONST, 5091 .resetvalue = 0 }, 5092 { .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64, 5093 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1, 5094 .access = PL3_RW, .type = ARM_CP_CONST, 5095 .resetvalue = 0 }, 5096 REGINFO_SENTINEL 5097 }; 5098 define_arm_cp_regs(cpu, auxcr_reginfo); 5099 } 5100 5101 if (arm_feature(env, ARM_FEATURE_CBAR)) { 5102 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 5103 /* 32 bit view is [31:18] 0...0 [43:32]. */ 5104 uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18) 5105 | extract64(cpu->reset_cbar, 32, 12); 5106 ARMCPRegInfo cbar_reginfo[] = { 5107 { .name = "CBAR", 5108 .type = ARM_CP_CONST, 5109 .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0, 5110 .access = PL1_R, .resetvalue = cpu->reset_cbar }, 5111 { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64, 5112 .type = ARM_CP_CONST, 5113 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0, 5114 .access = PL1_R, .resetvalue = cbar32 }, 5115 REGINFO_SENTINEL 5116 }; 5117 /* We don't implement a r/w 64 bit CBAR currently */ 5118 assert(arm_feature(env, ARM_FEATURE_CBAR_RO)); 5119 define_arm_cp_regs(cpu, cbar_reginfo); 5120 } else { 5121 ARMCPRegInfo cbar = { 5122 .name = "CBAR", 5123 .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0, 5124 .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar, 5125 .fieldoffset = offsetof(CPUARMState, 5126 cp15.c15_config_base_address) 5127 }; 5128 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 5129 cbar.access = PL1_R; 5130 cbar.fieldoffset = 0; 5131 cbar.type = ARM_CP_CONST; 5132 } 5133 define_one_arm_cp_reg(cpu, &cbar); 5134 } 5135 } 5136 5137 if (arm_feature(env, ARM_FEATURE_VBAR)) { 5138 ARMCPRegInfo vbar_cp_reginfo[] = { 5139 { .name = "VBAR", .state = ARM_CP_STATE_BOTH, 5140 .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0, 5141 .access = PL1_RW, .writefn = vbar_write, 5142 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s), 5143 offsetof(CPUARMState, cp15.vbar_ns) }, 5144 .resetvalue = 0 }, 5145 REGINFO_SENTINEL 5146 }; 5147 define_arm_cp_regs(cpu, vbar_cp_reginfo); 5148 } 5149 5150 /* Generic registers whose values depend on the implementation */ 5151 { 5152 ARMCPRegInfo sctlr = { 5153 .name = "SCTLR", .state = ARM_CP_STATE_BOTH, 5154 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, 5155 .access = PL1_RW, 5156 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s), 5157 offsetof(CPUARMState, cp15.sctlr_ns) }, 5158 .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr, 5159 .raw_writefn = raw_write, 5160 }; 5161 if (arm_feature(env, ARM_FEATURE_XSCALE)) { 5162 /* Normally we would always end the TB on an SCTLR write, but Linux 5163 * arch/arm/mach-pxa/sleep.S expects two instructions following 5164 * an MMU enable to execute from cache. Imitate this behaviour. 5165 */ 5166 sctlr.type |= ARM_CP_SUPPRESS_TB_END; 5167 } 5168 define_one_arm_cp_reg(cpu, &sctlr); 5169 } 5170 } 5171 5172 ARMCPU *cpu_arm_init(const char *cpu_model) 5173 { 5174 return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model)); 5175 } 5176 5177 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) 5178 { 5179 CPUState *cs = CPU(cpu); 5180 CPUARMState *env = &cpu->env; 5181 5182 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 5183 gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg, 5184 aarch64_fpu_gdb_set_reg, 5185 34, "aarch64-fpu.xml", 0); 5186 } else if (arm_feature(env, ARM_FEATURE_NEON)) { 5187 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 5188 51, "arm-neon.xml", 0); 5189 } else if (arm_feature(env, ARM_FEATURE_VFP3)) { 5190 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 5191 35, "arm-vfp3.xml", 0); 5192 } else if (arm_feature(env, ARM_FEATURE_VFP)) { 5193 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 5194 19, "arm-vfp.xml", 0); 5195 } 5196 } 5197 5198 /* Sort alphabetically by type name, except for "any". */ 5199 static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b) 5200 { 5201 ObjectClass *class_a = (ObjectClass *)a; 5202 ObjectClass *class_b = (ObjectClass *)b; 5203 const char *name_a, *name_b; 5204 5205 name_a = object_class_get_name(class_a); 5206 name_b = object_class_get_name(class_b); 5207 if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) { 5208 return 1; 5209 } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) { 5210 return -1; 5211 } else { 5212 return strcmp(name_a, name_b); 5213 } 5214 } 5215 5216 static void arm_cpu_list_entry(gpointer data, gpointer user_data) 5217 { 5218 ObjectClass *oc = data; 5219 CPUListState *s = user_data; 5220 const char *typename; 5221 char *name; 5222 5223 typename = object_class_get_name(oc); 5224 name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU)); 5225 (*s->cpu_fprintf)(s->file, " %s\n", 5226 name); 5227 g_free(name); 5228 } 5229 5230 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf) 5231 { 5232 CPUListState s = { 5233 .file = f, 5234 .cpu_fprintf = cpu_fprintf, 5235 }; 5236 GSList *list; 5237 5238 list = object_class_get_list(TYPE_ARM_CPU, false); 5239 list = g_slist_sort(list, arm_cpu_list_compare); 5240 (*cpu_fprintf)(f, "Available CPUs:\n"); 5241 g_slist_foreach(list, arm_cpu_list_entry, &s); 5242 g_slist_free(list); 5243 #ifdef CONFIG_KVM 5244 /* The 'host' CPU type is dynamically registered only if KVM is 5245 * enabled, so we have to special-case it here: 5246 */ 5247 (*cpu_fprintf)(f, " host (only available in KVM mode)\n"); 5248 #endif 5249 } 5250 5251 static void arm_cpu_add_definition(gpointer data, gpointer user_data) 5252 { 5253 ObjectClass *oc = data; 5254 CpuDefinitionInfoList **cpu_list = user_data; 5255 CpuDefinitionInfoList *entry; 5256 CpuDefinitionInfo *info; 5257 const char *typename; 5258 5259 typename = object_class_get_name(oc); 5260 info = g_malloc0(sizeof(*info)); 5261 info->name = g_strndup(typename, 5262 strlen(typename) - strlen("-" TYPE_ARM_CPU)); 5263 info->q_typename = g_strdup(typename); 5264 5265 entry = g_malloc0(sizeof(*entry)); 5266 entry->value = info; 5267 entry->next = *cpu_list; 5268 *cpu_list = entry; 5269 } 5270 5271 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp) 5272 { 5273 CpuDefinitionInfoList *cpu_list = NULL; 5274 GSList *list; 5275 5276 list = object_class_get_list(TYPE_ARM_CPU, false); 5277 g_slist_foreach(list, arm_cpu_add_definition, &cpu_list); 5278 g_slist_free(list); 5279 5280 return cpu_list; 5281 } 5282 5283 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, 5284 void *opaque, int state, int secstate, 5285 int crm, int opc1, int opc2) 5286 { 5287 /* Private utility function for define_one_arm_cp_reg_with_opaque(): 5288 * add a single reginfo struct to the hash table. 5289 */ 5290 uint32_t *key = g_new(uint32_t, 1); 5291 ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo)); 5292 int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0; 5293 int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; 5294 5295 /* Reset the secure state to the specific incoming state. This is 5296 * necessary as the register may have been defined with both states. 5297 */ 5298 r2->secure = secstate; 5299 5300 if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { 5301 /* Register is banked (using both entries in array). 5302 * Overwriting fieldoffset as the array is only used to define 5303 * banked registers but later only fieldoffset is used. 5304 */ 5305 r2->fieldoffset = r->bank_fieldoffsets[ns]; 5306 } 5307 5308 if (state == ARM_CP_STATE_AA32) { 5309 if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { 5310 /* If the register is banked then we don't need to migrate or 5311 * reset the 32-bit instance in certain cases: 5312 * 5313 * 1) If the register has both 32-bit and 64-bit instances then we 5314 * can count on the 64-bit instance taking care of the 5315 * non-secure bank. 5316 * 2) If ARMv8 is enabled then we can count on a 64-bit version 5317 * taking care of the secure bank. This requires that separate 5318 * 32 and 64-bit definitions are provided. 5319 */ 5320 if ((r->state == ARM_CP_STATE_BOTH && ns) || 5321 (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) { 5322 r2->type |= ARM_CP_ALIAS; 5323 } 5324 } else if ((secstate != r->secure) && !ns) { 5325 /* The register is not banked so we only want to allow migration of 5326 * the non-secure instance. 5327 */ 5328 r2->type |= ARM_CP_ALIAS; 5329 } 5330 5331 if (r->state == ARM_CP_STATE_BOTH) { 5332 /* We assume it is a cp15 register if the .cp field is left unset. 5333 */ 5334 if (r2->cp == 0) { 5335 r2->cp = 15; 5336 } 5337 5338 #ifdef HOST_WORDS_BIGENDIAN 5339 if (r2->fieldoffset) { 5340 r2->fieldoffset += sizeof(uint32_t); 5341 } 5342 #endif 5343 } 5344 } 5345 if (state == ARM_CP_STATE_AA64) { 5346 /* To allow abbreviation of ARMCPRegInfo 5347 * definitions, we treat cp == 0 as equivalent to 5348 * the value for "standard guest-visible sysreg". 5349 * STATE_BOTH definitions are also always "standard 5350 * sysreg" in their AArch64 view (the .cp value may 5351 * be non-zero for the benefit of the AArch32 view). 5352 */ 5353 if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) { 5354 r2->cp = CP_REG_ARM64_SYSREG_CP; 5355 } 5356 *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm, 5357 r2->opc0, opc1, opc2); 5358 } else { 5359 *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2); 5360 } 5361 if (opaque) { 5362 r2->opaque = opaque; 5363 } 5364 /* reginfo passed to helpers is correct for the actual access, 5365 * and is never ARM_CP_STATE_BOTH: 5366 */ 5367 r2->state = state; 5368 /* Make sure reginfo passed to helpers for wildcarded regs 5369 * has the correct crm/opc1/opc2 for this reg, not CP_ANY: 5370 */ 5371 r2->crm = crm; 5372 r2->opc1 = opc1; 5373 r2->opc2 = opc2; 5374 /* By convention, for wildcarded registers only the first 5375 * entry is used for migration; the others are marked as 5376 * ALIAS so we don't try to transfer the register 5377 * multiple times. Special registers (ie NOP/WFI) are 5378 * never migratable and not even raw-accessible. 5379 */ 5380 if ((r->type & ARM_CP_SPECIAL)) { 5381 r2->type |= ARM_CP_NO_RAW; 5382 } 5383 if (((r->crm == CP_ANY) && crm != 0) || 5384 ((r->opc1 == CP_ANY) && opc1 != 0) || 5385 ((r->opc2 == CP_ANY) && opc2 != 0)) { 5386 r2->type |= ARM_CP_ALIAS; 5387 } 5388 5389 /* Check that raw accesses are either forbidden or handled. Note that 5390 * we can't assert this earlier because the setup of fieldoffset for 5391 * banked registers has to be done first. 5392 */ 5393 if (!(r2->type & ARM_CP_NO_RAW)) { 5394 assert(!raw_accessors_invalid(r2)); 5395 } 5396 5397 /* Overriding of an existing definition must be explicitly 5398 * requested. 5399 */ 5400 if (!(r->type & ARM_CP_OVERRIDE)) { 5401 ARMCPRegInfo *oldreg; 5402 oldreg = g_hash_table_lookup(cpu->cp_regs, key); 5403 if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) { 5404 fprintf(stderr, "Register redefined: cp=%d %d bit " 5405 "crn=%d crm=%d opc1=%d opc2=%d, " 5406 "was %s, now %s\n", r2->cp, 32 + 32 * is64, 5407 r2->crn, r2->crm, r2->opc1, r2->opc2, 5408 oldreg->name, r2->name); 5409 g_assert_not_reached(); 5410 } 5411 } 5412 g_hash_table_insert(cpu->cp_regs, key, r2); 5413 } 5414 5415 5416 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, 5417 const ARMCPRegInfo *r, void *opaque) 5418 { 5419 /* Define implementations of coprocessor registers. 5420 * We store these in a hashtable because typically 5421 * there are less than 150 registers in a space which 5422 * is 16*16*16*8*8 = 262144 in size. 5423 * Wildcarding is supported for the crm, opc1 and opc2 fields. 5424 * If a register is defined twice then the second definition is 5425 * used, so this can be used to define some generic registers and 5426 * then override them with implementation specific variations. 5427 * At least one of the original and the second definition should 5428 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard 5429 * against accidental use. 5430 * 5431 * The state field defines whether the register is to be 5432 * visible in the AArch32 or AArch64 execution state. If the 5433 * state is set to ARM_CP_STATE_BOTH then we synthesise a 5434 * reginfo structure for the AArch32 view, which sees the lower 5435 * 32 bits of the 64 bit register. 5436 * 5437 * Only registers visible in AArch64 may set r->opc0; opc0 cannot 5438 * be wildcarded. AArch64 registers are always considered to be 64 5439 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of 5440 * the register, if any. 5441 */ 5442 int crm, opc1, opc2, state; 5443 int crmmin = (r->crm == CP_ANY) ? 0 : r->crm; 5444 int crmmax = (r->crm == CP_ANY) ? 15 : r->crm; 5445 int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1; 5446 int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1; 5447 int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2; 5448 int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2; 5449 /* 64 bit registers have only CRm and Opc1 fields */ 5450 assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn))); 5451 /* op0 only exists in the AArch64 encodings */ 5452 assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0)); 5453 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */ 5454 assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT)); 5455 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1 5456 * encodes a minimum access level for the register. We roll this 5457 * runtime check into our general permission check code, so check 5458 * here that the reginfo's specified permissions are strict enough 5459 * to encompass the generic architectural permission check. 5460 */ 5461 if (r->state != ARM_CP_STATE_AA32) { 5462 int mask = 0; 5463 switch (r->opc1) { 5464 case 0: case 1: case 2: 5465 /* min_EL EL1 */ 5466 mask = PL1_RW; 5467 break; 5468 case 3: 5469 /* min_EL EL0 */ 5470 mask = PL0_RW; 5471 break; 5472 case 4: 5473 /* min_EL EL2 */ 5474 mask = PL2_RW; 5475 break; 5476 case 5: 5477 /* unallocated encoding, so not possible */ 5478 assert(false); 5479 break; 5480 case 6: 5481 /* min_EL EL3 */ 5482 mask = PL3_RW; 5483 break; 5484 case 7: 5485 /* min_EL EL1, secure mode only (we don't check the latter) */ 5486 mask = PL1_RW; 5487 break; 5488 default: 5489 /* broken reginfo with out-of-range opc1 */ 5490 assert(false); 5491 break; 5492 } 5493 /* assert our permissions are not too lax (stricter is fine) */ 5494 assert((r->access & ~mask) == 0); 5495 } 5496 5497 /* Check that the register definition has enough info to handle 5498 * reads and writes if they are permitted. 5499 */ 5500 if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) { 5501 if (r->access & PL3_R) { 5502 assert((r->fieldoffset || 5503 (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || 5504 r->readfn); 5505 } 5506 if (r->access & PL3_W) { 5507 assert((r->fieldoffset || 5508 (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || 5509 r->writefn); 5510 } 5511 } 5512 /* Bad type field probably means missing sentinel at end of reg list */ 5513 assert(cptype_valid(r->type)); 5514 for (crm = crmmin; crm <= crmmax; crm++) { 5515 for (opc1 = opc1min; opc1 <= opc1max; opc1++) { 5516 for (opc2 = opc2min; opc2 <= opc2max; opc2++) { 5517 for (state = ARM_CP_STATE_AA32; 5518 state <= ARM_CP_STATE_AA64; state++) { 5519 if (r->state != state && r->state != ARM_CP_STATE_BOTH) { 5520 continue; 5521 } 5522 if (state == ARM_CP_STATE_AA32) { 5523 /* Under AArch32 CP registers can be common 5524 * (same for secure and non-secure world) or banked. 5525 */ 5526 switch (r->secure) { 5527 case ARM_CP_SECSTATE_S: 5528 case ARM_CP_SECSTATE_NS: 5529 add_cpreg_to_hashtable(cpu, r, opaque, state, 5530 r->secure, crm, opc1, opc2); 5531 break; 5532 default: 5533 add_cpreg_to_hashtable(cpu, r, opaque, state, 5534 ARM_CP_SECSTATE_S, 5535 crm, opc1, opc2); 5536 add_cpreg_to_hashtable(cpu, r, opaque, state, 5537 ARM_CP_SECSTATE_NS, 5538 crm, opc1, opc2); 5539 break; 5540 } 5541 } else { 5542 /* AArch64 registers get mapped to non-secure instance 5543 * of AArch32 */ 5544 add_cpreg_to_hashtable(cpu, r, opaque, state, 5545 ARM_CP_SECSTATE_NS, 5546 crm, opc1, opc2); 5547 } 5548 } 5549 } 5550 } 5551 } 5552 } 5553 5554 void define_arm_cp_regs_with_opaque(ARMCPU *cpu, 5555 const ARMCPRegInfo *regs, void *opaque) 5556 { 5557 /* Define a whole list of registers */ 5558 const ARMCPRegInfo *r; 5559 for (r = regs; r->type != ARM_CP_SENTINEL; r++) { 5560 define_one_arm_cp_reg_with_opaque(cpu, r, opaque); 5561 } 5562 } 5563 5564 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp) 5565 { 5566 return g_hash_table_lookup(cpregs, &encoded_cp); 5567 } 5568 5569 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, 5570 uint64_t value) 5571 { 5572 /* Helper coprocessor write function for write-ignore registers */ 5573 } 5574 5575 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri) 5576 { 5577 /* Helper coprocessor write function for read-as-zero registers */ 5578 return 0; 5579 } 5580 5581 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque) 5582 { 5583 /* Helper coprocessor reset function for do-nothing-on-reset registers */ 5584 } 5585 5586 static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type) 5587 { 5588 /* Return true if it is not valid for us to switch to 5589 * this CPU mode (ie all the UNPREDICTABLE cases in 5590 * the ARM ARM CPSRWriteByInstr pseudocode). 5591 */ 5592 5593 /* Changes to or from Hyp via MSR and CPS are illegal. */ 5594 if (write_type == CPSRWriteByInstr && 5595 ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_HYP || 5596 mode == ARM_CPU_MODE_HYP)) { 5597 return 1; 5598 } 5599 5600 switch (mode) { 5601 case ARM_CPU_MODE_USR: 5602 return 0; 5603 case ARM_CPU_MODE_SYS: 5604 case ARM_CPU_MODE_SVC: 5605 case ARM_CPU_MODE_ABT: 5606 case ARM_CPU_MODE_UND: 5607 case ARM_CPU_MODE_IRQ: 5608 case ARM_CPU_MODE_FIQ: 5609 /* Note that we don't implement the IMPDEF NSACR.RFR which in v7 5610 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.) 5611 */ 5612 /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR 5613 * and CPS are treated as illegal mode changes. 5614 */ 5615 if (write_type == CPSRWriteByInstr && 5616 (env->cp15.hcr_el2 & HCR_TGE) && 5617 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON && 5618 !arm_is_secure_below_el3(env)) { 5619 return 1; 5620 } 5621 return 0; 5622 case ARM_CPU_MODE_HYP: 5623 return !arm_feature(env, ARM_FEATURE_EL2) 5624 || arm_current_el(env) < 2 || arm_is_secure(env); 5625 case ARM_CPU_MODE_MON: 5626 return arm_current_el(env) < 3; 5627 default: 5628 return 1; 5629 } 5630 } 5631 5632 uint32_t cpsr_read(CPUARMState *env) 5633 { 5634 int ZF; 5635 ZF = (env->ZF == 0); 5636 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) | 5637 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 5638 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25) 5639 | ((env->condexec_bits & 0xfc) << 8) 5640 | (env->GE << 16) | (env->daif & CPSR_AIF); 5641 } 5642 5643 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 5644 CPSRWriteType write_type) 5645 { 5646 uint32_t changed_daif; 5647 5648 if (mask & CPSR_NZCV) { 5649 env->ZF = (~val) & CPSR_Z; 5650 env->NF = val; 5651 env->CF = (val >> 29) & 1; 5652 env->VF = (val << 3) & 0x80000000; 5653 } 5654 if (mask & CPSR_Q) 5655 env->QF = ((val & CPSR_Q) != 0); 5656 if (mask & CPSR_T) 5657 env->thumb = ((val & CPSR_T) != 0); 5658 if (mask & CPSR_IT_0_1) { 5659 env->condexec_bits &= ~3; 5660 env->condexec_bits |= (val >> 25) & 3; 5661 } 5662 if (mask & CPSR_IT_2_7) { 5663 env->condexec_bits &= 3; 5664 env->condexec_bits |= (val >> 8) & 0xfc; 5665 } 5666 if (mask & CPSR_GE) { 5667 env->GE = (val >> 16) & 0xf; 5668 } 5669 5670 /* In a V7 implementation that includes the security extensions but does 5671 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control 5672 * whether non-secure software is allowed to change the CPSR_F and CPSR_A 5673 * bits respectively. 5674 * 5675 * In a V8 implementation, it is permitted for privileged software to 5676 * change the CPSR A/F bits regardless of the SCR.AW/FW bits. 5677 */ 5678 if (write_type != CPSRWriteRaw && !arm_feature(env, ARM_FEATURE_V8) && 5679 arm_feature(env, ARM_FEATURE_EL3) && 5680 !arm_feature(env, ARM_FEATURE_EL2) && 5681 !arm_is_secure(env)) { 5682 5683 changed_daif = (env->daif ^ val) & mask; 5684 5685 if (changed_daif & CPSR_A) { 5686 /* Check to see if we are allowed to change the masking of async 5687 * abort exceptions from a non-secure state. 5688 */ 5689 if (!(env->cp15.scr_el3 & SCR_AW)) { 5690 qemu_log_mask(LOG_GUEST_ERROR, 5691 "Ignoring attempt to switch CPSR_A flag from " 5692 "non-secure world with SCR.AW bit clear\n"); 5693 mask &= ~CPSR_A; 5694 } 5695 } 5696 5697 if (changed_daif & CPSR_F) { 5698 /* Check to see if we are allowed to change the masking of FIQ 5699 * exceptions from a non-secure state. 5700 */ 5701 if (!(env->cp15.scr_el3 & SCR_FW)) { 5702 qemu_log_mask(LOG_GUEST_ERROR, 5703 "Ignoring attempt to switch CPSR_F flag from " 5704 "non-secure world with SCR.FW bit clear\n"); 5705 mask &= ~CPSR_F; 5706 } 5707 5708 /* Check whether non-maskable FIQ (NMFI) support is enabled. 5709 * If this bit is set software is not allowed to mask 5710 * FIQs, but is allowed to set CPSR_F to 0. 5711 */ 5712 if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) && 5713 (val & CPSR_F)) { 5714 qemu_log_mask(LOG_GUEST_ERROR, 5715 "Ignoring attempt to enable CPSR_F flag " 5716 "(non-maskable FIQ [NMFI] support enabled)\n"); 5717 mask &= ~CPSR_F; 5718 } 5719 } 5720 } 5721 5722 env->daif &= ~(CPSR_AIF & mask); 5723 env->daif |= val & CPSR_AIF & mask; 5724 5725 if (write_type != CPSRWriteRaw && 5726 ((env->uncached_cpsr ^ val) & mask & CPSR_M)) { 5727 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR) { 5728 /* Note that we can only get here in USR mode if this is a 5729 * gdb stub write; for this case we follow the architectural 5730 * behaviour for guest writes in USR mode of ignoring an attempt 5731 * to switch mode. (Those are caught by translate.c for writes 5732 * triggered by guest instructions.) 5733 */ 5734 mask &= ~CPSR_M; 5735 } else if (bad_mode_switch(env, val & CPSR_M, write_type)) { 5736 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in 5737 * v7, and has defined behaviour in v8: 5738 * + leave CPSR.M untouched 5739 * + allow changes to the other CPSR fields 5740 * + set PSTATE.IL 5741 * For user changes via the GDB stub, we don't set PSTATE.IL, 5742 * as this would be unnecessarily harsh for a user error. 5743 */ 5744 mask &= ~CPSR_M; 5745 if (write_type != CPSRWriteByGDBStub && 5746 arm_feature(env, ARM_FEATURE_V8)) { 5747 mask |= CPSR_IL; 5748 val |= CPSR_IL; 5749 } 5750 } else { 5751 switch_mode(env, val & CPSR_M); 5752 } 5753 } 5754 mask &= ~CACHED_CPSR_BITS; 5755 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask); 5756 } 5757 5758 /* Sign/zero extend */ 5759 uint32_t HELPER(sxtb16)(uint32_t x) 5760 { 5761 uint32_t res; 5762 res = (uint16_t)(int8_t)x; 5763 res |= (uint32_t)(int8_t)(x >> 16) << 16; 5764 return res; 5765 } 5766 5767 uint32_t HELPER(uxtb16)(uint32_t x) 5768 { 5769 uint32_t res; 5770 res = (uint16_t)(uint8_t)x; 5771 res |= (uint32_t)(uint8_t)(x >> 16) << 16; 5772 return res; 5773 } 5774 5775 int32_t HELPER(sdiv)(int32_t num, int32_t den) 5776 { 5777 if (den == 0) 5778 return 0; 5779 if (num == INT_MIN && den == -1) 5780 return INT_MIN; 5781 return num / den; 5782 } 5783 5784 uint32_t HELPER(udiv)(uint32_t num, uint32_t den) 5785 { 5786 if (den == 0) 5787 return 0; 5788 return num / den; 5789 } 5790 5791 uint32_t HELPER(rbit)(uint32_t x) 5792 { 5793 return revbit32(x); 5794 } 5795 5796 #if defined(CONFIG_USER_ONLY) 5797 5798 /* These should probably raise undefined insn exceptions. */ 5799 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) 5800 { 5801 ARMCPU *cpu = arm_env_get_cpu(env); 5802 5803 cpu_abort(CPU(cpu), "v7m_msr %d\n", reg); 5804 } 5805 5806 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) 5807 { 5808 ARMCPU *cpu = arm_env_get_cpu(env); 5809 5810 cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg); 5811 return 0; 5812 } 5813 5814 void switch_mode(CPUARMState *env, int mode) 5815 { 5816 ARMCPU *cpu = arm_env_get_cpu(env); 5817 5818 if (mode != ARM_CPU_MODE_USR) { 5819 cpu_abort(CPU(cpu), "Tried to switch out of user mode\n"); 5820 } 5821 } 5822 5823 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 5824 uint32_t cur_el, bool secure) 5825 { 5826 return 1; 5827 } 5828 5829 void aarch64_sync_64_to_32(CPUARMState *env) 5830 { 5831 g_assert_not_reached(); 5832 } 5833 5834 #else 5835 5836 void switch_mode(CPUARMState *env, int mode) 5837 { 5838 int old_mode; 5839 int i; 5840 5841 old_mode = env->uncached_cpsr & CPSR_M; 5842 if (mode == old_mode) 5843 return; 5844 5845 if (old_mode == ARM_CPU_MODE_FIQ) { 5846 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t)); 5847 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t)); 5848 } else if (mode == ARM_CPU_MODE_FIQ) { 5849 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t)); 5850 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t)); 5851 } 5852 5853 i = bank_number(old_mode); 5854 env->banked_r13[i] = env->regs[13]; 5855 env->banked_r14[i] = env->regs[14]; 5856 env->banked_spsr[i] = env->spsr; 5857 5858 i = bank_number(mode); 5859 env->regs[13] = env->banked_r13[i]; 5860 env->regs[14] = env->banked_r14[i]; 5861 env->spsr = env->banked_spsr[i]; 5862 } 5863 5864 /* Physical Interrupt Target EL Lookup Table 5865 * 5866 * [ From ARM ARM section G1.13.4 (Table G1-15) ] 5867 * 5868 * The below multi-dimensional table is used for looking up the target 5869 * exception level given numerous condition criteria. Specifically, the 5870 * target EL is based on SCR and HCR routing controls as well as the 5871 * currently executing EL and secure state. 5872 * 5873 * Dimensions: 5874 * target_el_table[2][2][2][2][2][4] 5875 * | | | | | +--- Current EL 5876 * | | | | +------ Non-secure(0)/Secure(1) 5877 * | | | +--------- HCR mask override 5878 * | | +------------ SCR exec state control 5879 * | +--------------- SCR mask override 5880 * +------------------ 32-bit(0)/64-bit(1) EL3 5881 * 5882 * The table values are as such: 5883 * 0-3 = EL0-EL3 5884 * -1 = Cannot occur 5885 * 5886 * The ARM ARM target EL table includes entries indicating that an "exception 5887 * is not taken". The two cases where this is applicable are: 5888 * 1) An exception is taken from EL3 but the SCR does not have the exception 5889 * routed to EL3. 5890 * 2) An exception is taken from EL2 but the HCR does not have the exception 5891 * routed to EL2. 5892 * In these two cases, the below table contain a target of EL1. This value is 5893 * returned as it is expected that the consumer of the table data will check 5894 * for "target EL >= current EL" to ensure the exception is not taken. 5895 * 5896 * SCR HCR 5897 * 64 EA AMO From 5898 * BIT IRQ IMO Non-secure Secure 5899 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3 5900 */ 5901 static const int8_t target_el_table[2][2][2][2][2][4] = { 5902 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },}, 5903 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},}, 5904 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },}, 5905 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},}, 5906 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },}, 5907 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},}, 5908 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },}, 5909 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},}, 5910 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },}, 5911 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},}, 5912 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, -1, 1 },}, 5913 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},}, 5914 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },}, 5915 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},}, 5916 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },}, 5917 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},},}, 5918 }; 5919 5920 /* 5921 * Determine the target EL for physical exceptions 5922 */ 5923 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 5924 uint32_t cur_el, bool secure) 5925 { 5926 CPUARMState *env = cs->env_ptr; 5927 int rw; 5928 int scr; 5929 int hcr; 5930 int target_el; 5931 /* Is the highest EL AArch64? */ 5932 int is64 = arm_feature(env, ARM_FEATURE_AARCH64); 5933 5934 if (arm_feature(env, ARM_FEATURE_EL3)) { 5935 rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW); 5936 } else { 5937 /* Either EL2 is the highest EL (and so the EL2 register width 5938 * is given by is64); or there is no EL2 or EL3, in which case 5939 * the value of 'rw' does not affect the table lookup anyway. 5940 */ 5941 rw = is64; 5942 } 5943 5944 switch (excp_idx) { 5945 case EXCP_IRQ: 5946 scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ); 5947 hcr = ((env->cp15.hcr_el2 & HCR_IMO) == HCR_IMO); 5948 break; 5949 case EXCP_FIQ: 5950 scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ); 5951 hcr = ((env->cp15.hcr_el2 & HCR_FMO) == HCR_FMO); 5952 break; 5953 default: 5954 scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA); 5955 hcr = ((env->cp15.hcr_el2 & HCR_AMO) == HCR_AMO); 5956 break; 5957 }; 5958 5959 /* If HCR.TGE is set then HCR is treated as being 1 */ 5960 hcr |= ((env->cp15.hcr_el2 & HCR_TGE) == HCR_TGE); 5961 5962 /* Perform a table-lookup for the target EL given the current state */ 5963 target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el]; 5964 5965 assert(target_el > 0); 5966 5967 return target_el; 5968 } 5969 5970 static void v7m_push(CPUARMState *env, uint32_t val) 5971 { 5972 CPUState *cs = CPU(arm_env_get_cpu(env)); 5973 5974 env->regs[13] -= 4; 5975 stl_phys(cs->as, env->regs[13], val); 5976 } 5977 5978 static uint32_t v7m_pop(CPUARMState *env) 5979 { 5980 CPUState *cs = CPU(arm_env_get_cpu(env)); 5981 uint32_t val; 5982 5983 val = ldl_phys(cs->as, env->regs[13]); 5984 env->regs[13] += 4; 5985 return val; 5986 } 5987 5988 /* Switch to V7M main or process stack pointer. */ 5989 static void switch_v7m_sp(CPUARMState *env, bool new_spsel) 5990 { 5991 uint32_t tmp; 5992 bool old_spsel = env->v7m.control & R_V7M_CONTROL_SPSEL_MASK; 5993 5994 if (old_spsel != new_spsel) { 5995 tmp = env->v7m.other_sp; 5996 env->v7m.other_sp = env->regs[13]; 5997 env->regs[13] = tmp; 5998 5999 env->v7m.control = deposit32(env->v7m.control, 6000 R_V7M_CONTROL_SPSEL_SHIFT, 6001 R_V7M_CONTROL_SPSEL_LENGTH, new_spsel); 6002 } 6003 } 6004 6005 static void do_v7m_exception_exit(CPUARMState *env) 6006 { 6007 uint32_t type; 6008 uint32_t xpsr; 6009 6010 type = env->regs[15]; 6011 if (env->v7m.exception != ARMV7M_EXCP_NMI) { 6012 /* Auto-clear FAULTMASK on return from other than NMI */ 6013 env->daif &= ~PSTATE_F; 6014 } 6015 if (env->v7m.exception != 0) { 6016 armv7m_nvic_complete_irq(env->nvic, env->v7m.exception); 6017 } 6018 6019 /* Switch to the target stack. */ 6020 switch_v7m_sp(env, (type & 4) != 0); 6021 /* Pop registers. */ 6022 env->regs[0] = v7m_pop(env); 6023 env->regs[1] = v7m_pop(env); 6024 env->regs[2] = v7m_pop(env); 6025 env->regs[3] = v7m_pop(env); 6026 env->regs[12] = v7m_pop(env); 6027 env->regs[14] = v7m_pop(env); 6028 env->regs[15] = v7m_pop(env); 6029 if (env->regs[15] & 1) { 6030 qemu_log_mask(LOG_GUEST_ERROR, 6031 "M profile return from interrupt with misaligned " 6032 "PC is UNPREDICTABLE\n"); 6033 /* Actual hardware seems to ignore the lsbit, and there are several 6034 * RTOSes out there which incorrectly assume the r15 in the stack 6035 * frame should be a Thumb-style "lsbit indicates ARM/Thumb" value. 6036 */ 6037 env->regs[15] &= ~1U; 6038 } 6039 xpsr = v7m_pop(env); 6040 xpsr_write(env, xpsr, 0xfffffdff); 6041 /* Undo stack alignment. */ 6042 if (xpsr & 0x200) 6043 env->regs[13] |= 4; 6044 /* ??? The exception return type specifies Thread/Handler mode. However 6045 this is also implied by the xPSR value. Not sure what to do 6046 if there is a mismatch. */ 6047 /* ??? Likewise for mismatches between the CONTROL register and the stack 6048 pointer. */ 6049 } 6050 6051 static void arm_log_exception(int idx) 6052 { 6053 if (qemu_loglevel_mask(CPU_LOG_INT)) { 6054 const char *exc = NULL; 6055 6056 if (idx >= 0 && idx < ARRAY_SIZE(excnames)) { 6057 exc = excnames[idx]; 6058 } 6059 if (!exc) { 6060 exc = "unknown"; 6061 } 6062 qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc); 6063 } 6064 } 6065 6066 static uint32_t arm_v7m_load_vector(ARMCPU *cpu) 6067 6068 { 6069 CPUState *cs = CPU(cpu); 6070 CPUARMState *env = &cpu->env; 6071 MemTxResult result; 6072 hwaddr vec = env->v7m.vecbase + env->v7m.exception * 4; 6073 uint32_t addr; 6074 6075 addr = address_space_ldl(cs->as, vec, 6076 MEMTXATTRS_UNSPECIFIED, &result); 6077 if (result != MEMTX_OK) { 6078 /* Architecturally this should cause a HardFault setting HSFR.VECTTBL, 6079 * which would then be immediately followed by our failing to load 6080 * the entry vector for that HardFault, which is a Lockup case. 6081 * Since we don't model Lockup, we just report this guest error 6082 * via cpu_abort(). 6083 */ 6084 cpu_abort(cs, "Failed to read from exception vector table " 6085 "entry %08x\n", (unsigned)vec); 6086 } 6087 return addr; 6088 } 6089 6090 void arm_v7m_cpu_do_interrupt(CPUState *cs) 6091 { 6092 ARMCPU *cpu = ARM_CPU(cs); 6093 CPUARMState *env = &cpu->env; 6094 uint32_t xpsr = xpsr_read(env); 6095 uint32_t lr; 6096 uint32_t addr; 6097 6098 arm_log_exception(cs->exception_index); 6099 6100 lr = 0xfffffff1; 6101 if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) { 6102 lr |= 4; 6103 } 6104 if (env->v7m.exception == 0) 6105 lr |= 8; 6106 6107 /* For exceptions we just mark as pending on the NVIC, and let that 6108 handle it. */ 6109 /* TODO: Need to escalate if the current priority is higher than the 6110 one we're raising. */ 6111 switch (cs->exception_index) { 6112 case EXCP_UDEF: 6113 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); 6114 env->v7m.cfsr |= R_V7M_CFSR_UNDEFINSTR_MASK; 6115 return; 6116 case EXCP_NOCP: 6117 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); 6118 env->v7m.cfsr |= R_V7M_CFSR_NOCP_MASK; 6119 return; 6120 case EXCP_SWI: 6121 /* The PC already points to the next instruction. */ 6122 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC); 6123 return; 6124 case EXCP_PREFETCH_ABORT: 6125 case EXCP_DATA_ABORT: 6126 /* TODO: if we implemented the MPU registers, this is where we 6127 * should set the MMFAR, etc from exception.fsr and exception.vaddress. 6128 */ 6129 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM); 6130 return; 6131 case EXCP_BKPT: 6132 if (semihosting_enabled()) { 6133 int nr; 6134 nr = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env)) & 0xff; 6135 if (nr == 0xab) { 6136 env->regs[15] += 2; 6137 qemu_log_mask(CPU_LOG_INT, 6138 "...handling as semihosting call 0x%x\n", 6139 env->regs[0]); 6140 env->regs[0] = do_arm_semihosting(env); 6141 return; 6142 } 6143 } 6144 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG); 6145 return; 6146 case EXCP_IRQ: 6147 env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic); 6148 break; 6149 case EXCP_EXCEPTION_EXIT: 6150 do_v7m_exception_exit(env); 6151 return; 6152 default: 6153 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); 6154 return; /* Never happens. Keep compiler happy. */ 6155 } 6156 6157 /* Align stack pointer if the guest wants that */ 6158 if ((env->regs[13] & 4) && (env->v7m.ccr & R_V7M_CCR_STKALIGN_MASK)) { 6159 env->regs[13] -= 4; 6160 xpsr |= 0x200; 6161 } 6162 /* Switch to the handler mode. */ 6163 v7m_push(env, xpsr); 6164 v7m_push(env, env->regs[15]); 6165 v7m_push(env, env->regs[14]); 6166 v7m_push(env, env->regs[12]); 6167 v7m_push(env, env->regs[3]); 6168 v7m_push(env, env->regs[2]); 6169 v7m_push(env, env->regs[1]); 6170 v7m_push(env, env->regs[0]); 6171 switch_v7m_sp(env, 0); 6172 /* Clear IT bits */ 6173 env->condexec_bits = 0; 6174 env->regs[14] = lr; 6175 addr = arm_v7m_load_vector(cpu); 6176 env->regs[15] = addr & 0xfffffffe; 6177 env->thumb = addr & 1; 6178 } 6179 6180 /* Function used to synchronize QEMU's AArch64 register set with AArch32 6181 * register set. This is necessary when switching between AArch32 and AArch64 6182 * execution state. 6183 */ 6184 void aarch64_sync_32_to_64(CPUARMState *env) 6185 { 6186 int i; 6187 uint32_t mode = env->uncached_cpsr & CPSR_M; 6188 6189 /* We can blanket copy R[0:7] to X[0:7] */ 6190 for (i = 0; i < 8; i++) { 6191 env->xregs[i] = env->regs[i]; 6192 } 6193 6194 /* Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12. 6195 * Otherwise, they come from the banked user regs. 6196 */ 6197 if (mode == ARM_CPU_MODE_FIQ) { 6198 for (i = 8; i < 13; i++) { 6199 env->xregs[i] = env->usr_regs[i - 8]; 6200 } 6201 } else { 6202 for (i = 8; i < 13; i++) { 6203 env->xregs[i] = env->regs[i]; 6204 } 6205 } 6206 6207 /* Registers x13-x23 are the various mode SP and FP registers. Registers 6208 * r13 and r14 are only copied if we are in that mode, otherwise we copy 6209 * from the mode banked register. 6210 */ 6211 if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) { 6212 env->xregs[13] = env->regs[13]; 6213 env->xregs[14] = env->regs[14]; 6214 } else { 6215 env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)]; 6216 /* HYP is an exception in that it is copied from r14 */ 6217 if (mode == ARM_CPU_MODE_HYP) { 6218 env->xregs[14] = env->regs[14]; 6219 } else { 6220 env->xregs[14] = env->banked_r14[bank_number(ARM_CPU_MODE_USR)]; 6221 } 6222 } 6223 6224 if (mode == ARM_CPU_MODE_HYP) { 6225 env->xregs[15] = env->regs[13]; 6226 } else { 6227 env->xregs[15] = env->banked_r13[bank_number(ARM_CPU_MODE_HYP)]; 6228 } 6229 6230 if (mode == ARM_CPU_MODE_IRQ) { 6231 env->xregs[16] = env->regs[14]; 6232 env->xregs[17] = env->regs[13]; 6233 } else { 6234 env->xregs[16] = env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)]; 6235 env->xregs[17] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)]; 6236 } 6237 6238 if (mode == ARM_CPU_MODE_SVC) { 6239 env->xregs[18] = env->regs[14]; 6240 env->xregs[19] = env->regs[13]; 6241 } else { 6242 env->xregs[18] = env->banked_r14[bank_number(ARM_CPU_MODE_SVC)]; 6243 env->xregs[19] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)]; 6244 } 6245 6246 if (mode == ARM_CPU_MODE_ABT) { 6247 env->xregs[20] = env->regs[14]; 6248 env->xregs[21] = env->regs[13]; 6249 } else { 6250 env->xregs[20] = env->banked_r14[bank_number(ARM_CPU_MODE_ABT)]; 6251 env->xregs[21] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)]; 6252 } 6253 6254 if (mode == ARM_CPU_MODE_UND) { 6255 env->xregs[22] = env->regs[14]; 6256 env->xregs[23] = env->regs[13]; 6257 } else { 6258 env->xregs[22] = env->banked_r14[bank_number(ARM_CPU_MODE_UND)]; 6259 env->xregs[23] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)]; 6260 } 6261 6262 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ 6263 * mode, then we can copy from r8-r14. Otherwise, we copy from the 6264 * FIQ bank for r8-r14. 6265 */ 6266 if (mode == ARM_CPU_MODE_FIQ) { 6267 for (i = 24; i < 31; i++) { 6268 env->xregs[i] = env->regs[i - 16]; /* X[24:30] <- R[8:14] */ 6269 } 6270 } else { 6271 for (i = 24; i < 29; i++) { 6272 env->xregs[i] = env->fiq_regs[i - 24]; 6273 } 6274 env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)]; 6275 env->xregs[30] = env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)]; 6276 } 6277 6278 env->pc = env->regs[15]; 6279 } 6280 6281 /* Function used to synchronize QEMU's AArch32 register set with AArch64 6282 * register set. This is necessary when switching between AArch32 and AArch64 6283 * execution state. 6284 */ 6285 void aarch64_sync_64_to_32(CPUARMState *env) 6286 { 6287 int i; 6288 uint32_t mode = env->uncached_cpsr & CPSR_M; 6289 6290 /* We can blanket copy X[0:7] to R[0:7] */ 6291 for (i = 0; i < 8; i++) { 6292 env->regs[i] = env->xregs[i]; 6293 } 6294 6295 /* Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12. 6296 * Otherwise, we copy x8-x12 into the banked user regs. 6297 */ 6298 if (mode == ARM_CPU_MODE_FIQ) { 6299 for (i = 8; i < 13; i++) { 6300 env->usr_regs[i - 8] = env->xregs[i]; 6301 } 6302 } else { 6303 for (i = 8; i < 13; i++) { 6304 env->regs[i] = env->xregs[i]; 6305 } 6306 } 6307 6308 /* Registers r13 & r14 depend on the current mode. 6309 * If we are in a given mode, we copy the corresponding x registers to r13 6310 * and r14. Otherwise, we copy the x register to the banked r13 and r14 6311 * for the mode. 6312 */ 6313 if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) { 6314 env->regs[13] = env->xregs[13]; 6315 env->regs[14] = env->xregs[14]; 6316 } else { 6317 env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13]; 6318 6319 /* HYP is an exception in that it does not have its own banked r14 but 6320 * shares the USR r14 6321 */ 6322 if (mode == ARM_CPU_MODE_HYP) { 6323 env->regs[14] = env->xregs[14]; 6324 } else { 6325 env->banked_r14[bank_number(ARM_CPU_MODE_USR)] = env->xregs[14]; 6326 } 6327 } 6328 6329 if (mode == ARM_CPU_MODE_HYP) { 6330 env->regs[13] = env->xregs[15]; 6331 } else { 6332 env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] = env->xregs[15]; 6333 } 6334 6335 if (mode == ARM_CPU_MODE_IRQ) { 6336 env->regs[14] = env->xregs[16]; 6337 env->regs[13] = env->xregs[17]; 6338 } else { 6339 env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16]; 6340 env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17]; 6341 } 6342 6343 if (mode == ARM_CPU_MODE_SVC) { 6344 env->regs[14] = env->xregs[18]; 6345 env->regs[13] = env->xregs[19]; 6346 } else { 6347 env->banked_r14[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18]; 6348 env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19]; 6349 } 6350 6351 if (mode == ARM_CPU_MODE_ABT) { 6352 env->regs[14] = env->xregs[20]; 6353 env->regs[13] = env->xregs[21]; 6354 } else { 6355 env->banked_r14[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20]; 6356 env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21]; 6357 } 6358 6359 if (mode == ARM_CPU_MODE_UND) { 6360 env->regs[14] = env->xregs[22]; 6361 env->regs[13] = env->xregs[23]; 6362 } else { 6363 env->banked_r14[bank_number(ARM_CPU_MODE_UND)] = env->xregs[22]; 6364 env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23]; 6365 } 6366 6367 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ 6368 * mode, then we can copy to r8-r14. Otherwise, we copy to the 6369 * FIQ bank for r8-r14. 6370 */ 6371 if (mode == ARM_CPU_MODE_FIQ) { 6372 for (i = 24; i < 31; i++) { 6373 env->regs[i - 16] = env->xregs[i]; /* X[24:30] -> R[8:14] */ 6374 } 6375 } else { 6376 for (i = 24; i < 29; i++) { 6377 env->fiq_regs[i - 24] = env->xregs[i]; 6378 } 6379 env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29]; 6380 env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30]; 6381 } 6382 6383 env->regs[15] = env->pc; 6384 } 6385 6386 static void arm_cpu_do_interrupt_aarch32(CPUState *cs) 6387 { 6388 ARMCPU *cpu = ARM_CPU(cs); 6389 CPUARMState *env = &cpu->env; 6390 uint32_t addr; 6391 uint32_t mask; 6392 int new_mode; 6393 uint32_t offset; 6394 uint32_t moe; 6395 6396 /* If this is a debug exception we must update the DBGDSCR.MOE bits */ 6397 switch (env->exception.syndrome >> ARM_EL_EC_SHIFT) { 6398 case EC_BREAKPOINT: 6399 case EC_BREAKPOINT_SAME_EL: 6400 moe = 1; 6401 break; 6402 case EC_WATCHPOINT: 6403 case EC_WATCHPOINT_SAME_EL: 6404 moe = 10; 6405 break; 6406 case EC_AA32_BKPT: 6407 moe = 3; 6408 break; 6409 case EC_VECTORCATCH: 6410 moe = 5; 6411 break; 6412 default: 6413 moe = 0; 6414 break; 6415 } 6416 6417 if (moe) { 6418 env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe); 6419 } 6420 6421 /* TODO: Vectored interrupt controller. */ 6422 switch (cs->exception_index) { 6423 case EXCP_UDEF: 6424 new_mode = ARM_CPU_MODE_UND; 6425 addr = 0x04; 6426 mask = CPSR_I; 6427 if (env->thumb) 6428 offset = 2; 6429 else 6430 offset = 4; 6431 break; 6432 case EXCP_SWI: 6433 new_mode = ARM_CPU_MODE_SVC; 6434 addr = 0x08; 6435 mask = CPSR_I; 6436 /* The PC already points to the next instruction. */ 6437 offset = 0; 6438 break; 6439 case EXCP_BKPT: 6440 env->exception.fsr = 2; 6441 /* Fall through to prefetch abort. */ 6442 case EXCP_PREFETCH_ABORT: 6443 A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr); 6444 A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress); 6445 qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n", 6446 env->exception.fsr, (uint32_t)env->exception.vaddress); 6447 new_mode = ARM_CPU_MODE_ABT; 6448 addr = 0x0c; 6449 mask = CPSR_A | CPSR_I; 6450 offset = 4; 6451 break; 6452 case EXCP_DATA_ABORT: 6453 A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); 6454 A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress); 6455 qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n", 6456 env->exception.fsr, 6457 (uint32_t)env->exception.vaddress); 6458 new_mode = ARM_CPU_MODE_ABT; 6459 addr = 0x10; 6460 mask = CPSR_A | CPSR_I; 6461 offset = 8; 6462 break; 6463 case EXCP_IRQ: 6464 new_mode = ARM_CPU_MODE_IRQ; 6465 addr = 0x18; 6466 /* Disable IRQ and imprecise data aborts. */ 6467 mask = CPSR_A | CPSR_I; 6468 offset = 4; 6469 if (env->cp15.scr_el3 & SCR_IRQ) { 6470 /* IRQ routed to monitor mode */ 6471 new_mode = ARM_CPU_MODE_MON; 6472 mask |= CPSR_F; 6473 } 6474 break; 6475 case EXCP_FIQ: 6476 new_mode = ARM_CPU_MODE_FIQ; 6477 addr = 0x1c; 6478 /* Disable FIQ, IRQ and imprecise data aborts. */ 6479 mask = CPSR_A | CPSR_I | CPSR_F; 6480 if (env->cp15.scr_el3 & SCR_FIQ) { 6481 /* FIQ routed to monitor mode */ 6482 new_mode = ARM_CPU_MODE_MON; 6483 } 6484 offset = 4; 6485 break; 6486 case EXCP_VIRQ: 6487 new_mode = ARM_CPU_MODE_IRQ; 6488 addr = 0x18; 6489 /* Disable IRQ and imprecise data aborts. */ 6490 mask = CPSR_A | CPSR_I; 6491 offset = 4; 6492 break; 6493 case EXCP_VFIQ: 6494 new_mode = ARM_CPU_MODE_FIQ; 6495 addr = 0x1c; 6496 /* Disable FIQ, IRQ and imprecise data aborts. */ 6497 mask = CPSR_A | CPSR_I | CPSR_F; 6498 offset = 4; 6499 break; 6500 case EXCP_SMC: 6501 new_mode = ARM_CPU_MODE_MON; 6502 addr = 0x08; 6503 mask = CPSR_A | CPSR_I | CPSR_F; 6504 offset = 0; 6505 break; 6506 default: 6507 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); 6508 return; /* Never happens. Keep compiler happy. */ 6509 } 6510 6511 if (new_mode == ARM_CPU_MODE_MON) { 6512 addr += env->cp15.mvbar; 6513 } else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 6514 /* High vectors. When enabled, base address cannot be remapped. */ 6515 addr += 0xffff0000; 6516 } else { 6517 /* ARM v7 architectures provide a vector base address register to remap 6518 * the interrupt vector table. 6519 * This register is only followed in non-monitor mode, and is banked. 6520 * Note: only bits 31:5 are valid. 6521 */ 6522 addr += A32_BANKED_CURRENT_REG_GET(env, vbar); 6523 } 6524 6525 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 6526 env->cp15.scr_el3 &= ~SCR_NS; 6527 } 6528 6529 switch_mode (env, new_mode); 6530 /* For exceptions taken to AArch32 we must clear the SS bit in both 6531 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now. 6532 */ 6533 env->uncached_cpsr &= ~PSTATE_SS; 6534 env->spsr = cpsr_read(env); 6535 /* Clear IT bits. */ 6536 env->condexec_bits = 0; 6537 /* Switch to the new mode, and to the correct instruction set. */ 6538 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; 6539 /* Set new mode endianness */ 6540 env->uncached_cpsr &= ~CPSR_E; 6541 if (env->cp15.sctlr_el[arm_current_el(env)] & SCTLR_EE) { 6542 env->uncached_cpsr |= CPSR_E; 6543 } 6544 env->daif |= mask; 6545 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares 6546 * and we should just guard the thumb mode on V4 */ 6547 if (arm_feature(env, ARM_FEATURE_V4T)) { 6548 env->thumb = (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) != 0; 6549 } 6550 env->regs[14] = env->regs[15] + offset; 6551 env->regs[15] = addr; 6552 } 6553 6554 /* Handle exception entry to a target EL which is using AArch64 */ 6555 static void arm_cpu_do_interrupt_aarch64(CPUState *cs) 6556 { 6557 ARMCPU *cpu = ARM_CPU(cs); 6558 CPUARMState *env = &cpu->env; 6559 unsigned int new_el = env->exception.target_el; 6560 target_ulong addr = env->cp15.vbar_el[new_el]; 6561 unsigned int new_mode = aarch64_pstate_mode(new_el, true); 6562 6563 if (arm_current_el(env) < new_el) { 6564 /* Entry vector offset depends on whether the implemented EL 6565 * immediately lower than the target level is using AArch32 or AArch64 6566 */ 6567 bool is_aa64; 6568 6569 switch (new_el) { 6570 case 3: 6571 is_aa64 = (env->cp15.scr_el3 & SCR_RW) != 0; 6572 break; 6573 case 2: 6574 is_aa64 = (env->cp15.hcr_el2 & HCR_RW) != 0; 6575 break; 6576 case 1: 6577 is_aa64 = is_a64(env); 6578 break; 6579 default: 6580 g_assert_not_reached(); 6581 } 6582 6583 if (is_aa64) { 6584 addr += 0x400; 6585 } else { 6586 addr += 0x600; 6587 } 6588 } else if (pstate_read(env) & PSTATE_SP) { 6589 addr += 0x200; 6590 } 6591 6592 switch (cs->exception_index) { 6593 case EXCP_PREFETCH_ABORT: 6594 case EXCP_DATA_ABORT: 6595 env->cp15.far_el[new_el] = env->exception.vaddress; 6596 qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n", 6597 env->cp15.far_el[new_el]); 6598 /* fall through */ 6599 case EXCP_BKPT: 6600 case EXCP_UDEF: 6601 case EXCP_SWI: 6602 case EXCP_HVC: 6603 case EXCP_HYP_TRAP: 6604 case EXCP_SMC: 6605 env->cp15.esr_el[new_el] = env->exception.syndrome; 6606 break; 6607 case EXCP_IRQ: 6608 case EXCP_VIRQ: 6609 addr += 0x80; 6610 break; 6611 case EXCP_FIQ: 6612 case EXCP_VFIQ: 6613 addr += 0x100; 6614 break; 6615 case EXCP_SEMIHOST: 6616 qemu_log_mask(CPU_LOG_INT, 6617 "...handling as semihosting call 0x%" PRIx64 "\n", 6618 env->xregs[0]); 6619 env->xregs[0] = do_arm_semihosting(env); 6620 return; 6621 default: 6622 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); 6623 } 6624 6625 if (is_a64(env)) { 6626 env->banked_spsr[aarch64_banked_spsr_index(new_el)] = pstate_read(env); 6627 aarch64_save_sp(env, arm_current_el(env)); 6628 env->elr_el[new_el] = env->pc; 6629 } else { 6630 env->banked_spsr[aarch64_banked_spsr_index(new_el)] = cpsr_read(env); 6631 env->elr_el[new_el] = env->regs[15]; 6632 6633 aarch64_sync_32_to_64(env); 6634 6635 env->condexec_bits = 0; 6636 } 6637 qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n", 6638 env->elr_el[new_el]); 6639 6640 pstate_write(env, PSTATE_DAIF | new_mode); 6641 env->aarch64 = 1; 6642 aarch64_restore_sp(env, new_el); 6643 6644 env->pc = addr; 6645 6646 qemu_log_mask(CPU_LOG_INT, "...to EL%d PC 0x%" PRIx64 " PSTATE 0x%x\n", 6647 new_el, env->pc, pstate_read(env)); 6648 } 6649 6650 static inline bool check_for_semihosting(CPUState *cs) 6651 { 6652 /* Check whether this exception is a semihosting call; if so 6653 * then handle it and return true; otherwise return false. 6654 */ 6655 ARMCPU *cpu = ARM_CPU(cs); 6656 CPUARMState *env = &cpu->env; 6657 6658 if (is_a64(env)) { 6659 if (cs->exception_index == EXCP_SEMIHOST) { 6660 /* This is always the 64-bit semihosting exception. 6661 * The "is this usermode" and "is semihosting enabled" 6662 * checks have been done at translate time. 6663 */ 6664 qemu_log_mask(CPU_LOG_INT, 6665 "...handling as semihosting call 0x%" PRIx64 "\n", 6666 env->xregs[0]); 6667 env->xregs[0] = do_arm_semihosting(env); 6668 return true; 6669 } 6670 return false; 6671 } else { 6672 uint32_t imm; 6673 6674 /* Only intercept calls from privileged modes, to provide some 6675 * semblance of security. 6676 */ 6677 if (cs->exception_index != EXCP_SEMIHOST && 6678 (!semihosting_enabled() || 6679 ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR))) { 6680 return false; 6681 } 6682 6683 switch (cs->exception_index) { 6684 case EXCP_SEMIHOST: 6685 /* This is always a semihosting call; the "is this usermode" 6686 * and "is semihosting enabled" checks have been done at 6687 * translate time. 6688 */ 6689 break; 6690 case EXCP_SWI: 6691 /* Check for semihosting interrupt. */ 6692 if (env->thumb) { 6693 imm = arm_lduw_code(env, env->regs[15] - 2, arm_sctlr_b(env)) 6694 & 0xff; 6695 if (imm == 0xab) { 6696 break; 6697 } 6698 } else { 6699 imm = arm_ldl_code(env, env->regs[15] - 4, arm_sctlr_b(env)) 6700 & 0xffffff; 6701 if (imm == 0x123456) { 6702 break; 6703 } 6704 } 6705 return false; 6706 case EXCP_BKPT: 6707 /* See if this is a semihosting syscall. */ 6708 if (env->thumb) { 6709 imm = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env)) 6710 & 0xff; 6711 if (imm == 0xab) { 6712 env->regs[15] += 2; 6713 break; 6714 } 6715 } 6716 return false; 6717 default: 6718 return false; 6719 } 6720 6721 qemu_log_mask(CPU_LOG_INT, 6722 "...handling as semihosting call 0x%x\n", 6723 env->regs[0]); 6724 env->regs[0] = do_arm_semihosting(env); 6725 return true; 6726 } 6727 } 6728 6729 /* Handle a CPU exception for A and R profile CPUs. 6730 * Do any appropriate logging, handle PSCI calls, and then hand off 6731 * to the AArch64-entry or AArch32-entry function depending on the 6732 * target exception level's register width. 6733 */ 6734 void arm_cpu_do_interrupt(CPUState *cs) 6735 { 6736 ARMCPU *cpu = ARM_CPU(cs); 6737 CPUARMState *env = &cpu->env; 6738 unsigned int new_el = env->exception.target_el; 6739 6740 assert(!arm_feature(env, ARM_FEATURE_M)); 6741 6742 arm_log_exception(cs->exception_index); 6743 qemu_log_mask(CPU_LOG_INT, "...from EL%d to EL%d\n", arm_current_el(env), 6744 new_el); 6745 if (qemu_loglevel_mask(CPU_LOG_INT) 6746 && !excp_is_internal(cs->exception_index)) { 6747 qemu_log_mask(CPU_LOG_INT, "...with ESR %x/0x%" PRIx32 "\n", 6748 env->exception.syndrome >> ARM_EL_EC_SHIFT, 6749 env->exception.syndrome); 6750 } 6751 6752 if (arm_is_psci_call(cpu, cs->exception_index)) { 6753 arm_handle_psci_call(cpu); 6754 qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n"); 6755 return; 6756 } 6757 6758 /* Semihosting semantics depend on the register width of the 6759 * code that caused the exception, not the target exception level, 6760 * so must be handled here. 6761 */ 6762 if (check_for_semihosting(cs)) { 6763 return; 6764 } 6765 6766 assert(!excp_is_internal(cs->exception_index)); 6767 if (arm_el_is_aa64(env, new_el)) { 6768 arm_cpu_do_interrupt_aarch64(cs); 6769 } else { 6770 arm_cpu_do_interrupt_aarch32(cs); 6771 } 6772 6773 /* Hooks may change global state so BQL should be held, also the 6774 * BQL needs to be held for any modification of 6775 * cs->interrupt_request. 6776 */ 6777 g_assert(qemu_mutex_iothread_locked()); 6778 6779 arm_call_el_change_hook(cpu); 6780 6781 if (!kvm_enabled()) { 6782 cs->interrupt_request |= CPU_INTERRUPT_EXITTB; 6783 } 6784 } 6785 6786 /* Return the exception level which controls this address translation regime */ 6787 static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) 6788 { 6789 switch (mmu_idx) { 6790 case ARMMMUIdx_S2NS: 6791 case ARMMMUIdx_S1E2: 6792 return 2; 6793 case ARMMMUIdx_S1E3: 6794 return 3; 6795 case ARMMMUIdx_S1SE0: 6796 return arm_el_is_aa64(env, 3) ? 1 : 3; 6797 case ARMMMUIdx_S1SE1: 6798 case ARMMMUIdx_S1NSE0: 6799 case ARMMMUIdx_S1NSE1: 6800 return 1; 6801 default: 6802 g_assert_not_reached(); 6803 } 6804 } 6805 6806 /* Return true if this address translation regime is secure */ 6807 static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) 6808 { 6809 switch (mmu_idx) { 6810 case ARMMMUIdx_S12NSE0: 6811 case ARMMMUIdx_S12NSE1: 6812 case ARMMMUIdx_S1NSE0: 6813 case ARMMMUIdx_S1NSE1: 6814 case ARMMMUIdx_S1E2: 6815 case ARMMMUIdx_S2NS: 6816 return false; 6817 case ARMMMUIdx_S1E3: 6818 case ARMMMUIdx_S1SE0: 6819 case ARMMMUIdx_S1SE1: 6820 return true; 6821 default: 6822 g_assert_not_reached(); 6823 } 6824 } 6825 6826 /* Return the SCTLR value which controls this address translation regime */ 6827 static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) 6828 { 6829 return env->cp15.sctlr_el[regime_el(env, mmu_idx)]; 6830 } 6831 6832 /* Return true if the specified stage of address translation is disabled */ 6833 static inline bool regime_translation_disabled(CPUARMState *env, 6834 ARMMMUIdx mmu_idx) 6835 { 6836 if (mmu_idx == ARMMMUIdx_S2NS) { 6837 return (env->cp15.hcr_el2 & HCR_VM) == 0; 6838 } 6839 return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0; 6840 } 6841 6842 static inline bool regime_translation_big_endian(CPUARMState *env, 6843 ARMMMUIdx mmu_idx) 6844 { 6845 return (regime_sctlr(env, mmu_idx) & SCTLR_EE) != 0; 6846 } 6847 6848 /* Return the TCR controlling this translation regime */ 6849 static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) 6850 { 6851 if (mmu_idx == ARMMMUIdx_S2NS) { 6852 return &env->cp15.vtcr_el2; 6853 } 6854 return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; 6855 } 6856 6857 /* Returns TBI0 value for current regime el */ 6858 uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx) 6859 { 6860 TCR *tcr; 6861 uint32_t el; 6862 6863 /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert 6864 * a stage 1+2 mmu index into the appropriate stage 1 mmu index. 6865 */ 6866 if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { 6867 mmu_idx += ARMMMUIdx_S1NSE0; 6868 } 6869 6870 tcr = regime_tcr(env, mmu_idx); 6871 el = regime_el(env, mmu_idx); 6872 6873 if (el > 1) { 6874 return extract64(tcr->raw_tcr, 20, 1); 6875 } else { 6876 return extract64(tcr->raw_tcr, 37, 1); 6877 } 6878 } 6879 6880 /* Returns TBI1 value for current regime el */ 6881 uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx) 6882 { 6883 TCR *tcr; 6884 uint32_t el; 6885 6886 /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert 6887 * a stage 1+2 mmu index into the appropriate stage 1 mmu index. 6888 */ 6889 if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { 6890 mmu_idx += ARMMMUIdx_S1NSE0; 6891 } 6892 6893 tcr = regime_tcr(env, mmu_idx); 6894 el = regime_el(env, mmu_idx); 6895 6896 if (el > 1) { 6897 return 0; 6898 } else { 6899 return extract64(tcr->raw_tcr, 38, 1); 6900 } 6901 } 6902 6903 /* Return the TTBR associated with this translation regime */ 6904 static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, 6905 int ttbrn) 6906 { 6907 if (mmu_idx == ARMMMUIdx_S2NS) { 6908 return env->cp15.vttbr_el2; 6909 } 6910 if (ttbrn == 0) { 6911 return env->cp15.ttbr0_el[regime_el(env, mmu_idx)]; 6912 } else { 6913 return env->cp15.ttbr1_el[regime_el(env, mmu_idx)]; 6914 } 6915 } 6916 6917 /* Return true if the translation regime is using LPAE format page tables */ 6918 static inline bool regime_using_lpae_format(CPUARMState *env, 6919 ARMMMUIdx mmu_idx) 6920 { 6921 int el = regime_el(env, mmu_idx); 6922 if (el == 2 || arm_el_is_aa64(env, el)) { 6923 return true; 6924 } 6925 if (arm_feature(env, ARM_FEATURE_LPAE) 6926 && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) { 6927 return true; 6928 } 6929 return false; 6930 } 6931 6932 /* Returns true if the stage 1 translation regime is using LPAE format page 6933 * tables. Used when raising alignment exceptions, whose FSR changes depending 6934 * on whether the long or short descriptor format is in use. */ 6935 bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) 6936 { 6937 if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { 6938 mmu_idx += ARMMMUIdx_S1NSE0; 6939 } 6940 6941 return regime_using_lpae_format(env, mmu_idx); 6942 } 6943 6944 static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) 6945 { 6946 switch (mmu_idx) { 6947 case ARMMMUIdx_S1SE0: 6948 case ARMMMUIdx_S1NSE0: 6949 return true; 6950 default: 6951 return false; 6952 case ARMMMUIdx_S12NSE0: 6953 case ARMMMUIdx_S12NSE1: 6954 g_assert_not_reached(); 6955 } 6956 } 6957 6958 /* Translate section/page access permissions to page 6959 * R/W protection flags 6960 * 6961 * @env: CPUARMState 6962 * @mmu_idx: MMU index indicating required translation regime 6963 * @ap: The 3-bit access permissions (AP[2:0]) 6964 * @domain_prot: The 2-bit domain access permissions 6965 */ 6966 static inline int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, 6967 int ap, int domain_prot) 6968 { 6969 bool is_user = regime_is_user(env, mmu_idx); 6970 6971 if (domain_prot == 3) { 6972 return PAGE_READ | PAGE_WRITE; 6973 } 6974 6975 switch (ap) { 6976 case 0: 6977 if (arm_feature(env, ARM_FEATURE_V7)) { 6978 return 0; 6979 } 6980 switch (regime_sctlr(env, mmu_idx) & (SCTLR_S | SCTLR_R)) { 6981 case SCTLR_S: 6982 return is_user ? 0 : PAGE_READ; 6983 case SCTLR_R: 6984 return PAGE_READ; 6985 default: 6986 return 0; 6987 } 6988 case 1: 6989 return is_user ? 0 : PAGE_READ | PAGE_WRITE; 6990 case 2: 6991 if (is_user) { 6992 return PAGE_READ; 6993 } else { 6994 return PAGE_READ | PAGE_WRITE; 6995 } 6996 case 3: 6997 return PAGE_READ | PAGE_WRITE; 6998 case 4: /* Reserved. */ 6999 return 0; 7000 case 5: 7001 return is_user ? 0 : PAGE_READ; 7002 case 6: 7003 return PAGE_READ; 7004 case 7: 7005 if (!arm_feature(env, ARM_FEATURE_V6K)) { 7006 return 0; 7007 } 7008 return PAGE_READ; 7009 default: 7010 g_assert_not_reached(); 7011 } 7012 } 7013 7014 /* Translate section/page access permissions to page 7015 * R/W protection flags. 7016 * 7017 * @ap: The 2-bit simple AP (AP[2:1]) 7018 * @is_user: TRUE if accessing from PL0 7019 */ 7020 static inline int simple_ap_to_rw_prot_is_user(int ap, bool is_user) 7021 { 7022 switch (ap) { 7023 case 0: 7024 return is_user ? 0 : PAGE_READ | PAGE_WRITE; 7025 case 1: 7026 return PAGE_READ | PAGE_WRITE; 7027 case 2: 7028 return is_user ? 0 : PAGE_READ; 7029 case 3: 7030 return PAGE_READ; 7031 default: 7032 g_assert_not_reached(); 7033 } 7034 } 7035 7036 static inline int 7037 simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap) 7038 { 7039 return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx)); 7040 } 7041 7042 /* Translate S2 section/page access permissions to protection flags 7043 * 7044 * @env: CPUARMState 7045 * @s2ap: The 2-bit stage2 access permissions (S2AP) 7046 * @xn: XN (execute-never) bit 7047 */ 7048 static int get_S2prot(CPUARMState *env, int s2ap, int xn) 7049 { 7050 int prot = 0; 7051 7052 if (s2ap & 1) { 7053 prot |= PAGE_READ; 7054 } 7055 if (s2ap & 2) { 7056 prot |= PAGE_WRITE; 7057 } 7058 if (!xn) { 7059 if (arm_el_is_aa64(env, 2) || prot & PAGE_READ) { 7060 prot |= PAGE_EXEC; 7061 } 7062 } 7063 return prot; 7064 } 7065 7066 /* Translate section/page access permissions to protection flags 7067 * 7068 * @env: CPUARMState 7069 * @mmu_idx: MMU index indicating required translation regime 7070 * @is_aa64: TRUE if AArch64 7071 * @ap: The 2-bit simple AP (AP[2:1]) 7072 * @ns: NS (non-secure) bit 7073 * @xn: XN (execute-never) bit 7074 * @pxn: PXN (privileged execute-never) bit 7075 */ 7076 static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, 7077 int ap, int ns, int xn, int pxn) 7078 { 7079 bool is_user = regime_is_user(env, mmu_idx); 7080 int prot_rw, user_rw; 7081 bool have_wxn; 7082 int wxn = 0; 7083 7084 assert(mmu_idx != ARMMMUIdx_S2NS); 7085 7086 user_rw = simple_ap_to_rw_prot_is_user(ap, true); 7087 if (is_user) { 7088 prot_rw = user_rw; 7089 } else { 7090 prot_rw = simple_ap_to_rw_prot_is_user(ap, false); 7091 } 7092 7093 if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) { 7094 return prot_rw; 7095 } 7096 7097 /* TODO have_wxn should be replaced with 7098 * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2) 7099 * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE 7100 * compatible processors have EL2, which is required for [U]WXN. 7101 */ 7102 have_wxn = arm_feature(env, ARM_FEATURE_LPAE); 7103 7104 if (have_wxn) { 7105 wxn = regime_sctlr(env, mmu_idx) & SCTLR_WXN; 7106 } 7107 7108 if (is_aa64) { 7109 switch (regime_el(env, mmu_idx)) { 7110 case 1: 7111 if (!is_user) { 7112 xn = pxn || (user_rw & PAGE_WRITE); 7113 } 7114 break; 7115 case 2: 7116 case 3: 7117 break; 7118 } 7119 } else if (arm_feature(env, ARM_FEATURE_V7)) { 7120 switch (regime_el(env, mmu_idx)) { 7121 case 1: 7122 case 3: 7123 if (is_user) { 7124 xn = xn || !(user_rw & PAGE_READ); 7125 } else { 7126 int uwxn = 0; 7127 if (have_wxn) { 7128 uwxn = regime_sctlr(env, mmu_idx) & SCTLR_UWXN; 7129 } 7130 xn = xn || !(prot_rw & PAGE_READ) || pxn || 7131 (uwxn && (user_rw & PAGE_WRITE)); 7132 } 7133 break; 7134 case 2: 7135 break; 7136 } 7137 } else { 7138 xn = wxn = 0; 7139 } 7140 7141 if (xn || (wxn && (prot_rw & PAGE_WRITE))) { 7142 return prot_rw; 7143 } 7144 return prot_rw | PAGE_EXEC; 7145 } 7146 7147 static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, 7148 uint32_t *table, uint32_t address) 7149 { 7150 /* Note that we can only get here for an AArch32 PL0/PL1 lookup */ 7151 TCR *tcr = regime_tcr(env, mmu_idx); 7152 7153 if (address & tcr->mask) { 7154 if (tcr->raw_tcr & TTBCR_PD1) { 7155 /* Translation table walk disabled for TTBR1 */ 7156 return false; 7157 } 7158 *table = regime_ttbr(env, mmu_idx, 1) & 0xffffc000; 7159 } else { 7160 if (tcr->raw_tcr & TTBCR_PD0) { 7161 /* Translation table walk disabled for TTBR0 */ 7162 return false; 7163 } 7164 *table = regime_ttbr(env, mmu_idx, 0) & tcr->base_mask; 7165 } 7166 *table |= (address >> 18) & 0x3ffc; 7167 return true; 7168 } 7169 7170 /* Translate a S1 pagetable walk through S2 if needed. */ 7171 static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, 7172 hwaddr addr, MemTxAttrs txattrs, 7173 uint32_t *fsr, 7174 ARMMMUFaultInfo *fi) 7175 { 7176 if ((mmu_idx == ARMMMUIdx_S1NSE0 || mmu_idx == ARMMMUIdx_S1NSE1) && 7177 !regime_translation_disabled(env, ARMMMUIdx_S2NS)) { 7178 target_ulong s2size; 7179 hwaddr s2pa; 7180 int s2prot; 7181 int ret; 7182 7183 ret = get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_S2NS, &s2pa, 7184 &txattrs, &s2prot, &s2size, fsr, fi); 7185 if (ret) { 7186 fi->s2addr = addr; 7187 fi->stage2 = true; 7188 fi->s1ptw = true; 7189 return ~0; 7190 } 7191 addr = s2pa; 7192 } 7193 return addr; 7194 } 7195 7196 /* All loads done in the course of a page table walk go through here. 7197 * TODO: rather than ignoring errors from physical memory reads (which 7198 * are external aborts in ARM terminology) we should propagate this 7199 * error out so that we can turn it into a Data Abort if this walk 7200 * was being done for a CPU load/store or an address translation instruction 7201 * (but not if it was for a debug access). 7202 */ 7203 static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure, 7204 ARMMMUIdx mmu_idx, uint32_t *fsr, 7205 ARMMMUFaultInfo *fi) 7206 { 7207 ARMCPU *cpu = ARM_CPU(cs); 7208 CPUARMState *env = &cpu->env; 7209 MemTxAttrs attrs = {}; 7210 AddressSpace *as; 7211 7212 attrs.secure = is_secure; 7213 as = arm_addressspace(cs, attrs); 7214 addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi); 7215 if (fi->s1ptw) { 7216 return 0; 7217 } 7218 if (regime_translation_big_endian(env, mmu_idx)) { 7219 return address_space_ldl_be(as, addr, attrs, NULL); 7220 } else { 7221 return address_space_ldl_le(as, addr, attrs, NULL); 7222 } 7223 } 7224 7225 static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, 7226 ARMMMUIdx mmu_idx, uint32_t *fsr, 7227 ARMMMUFaultInfo *fi) 7228 { 7229 ARMCPU *cpu = ARM_CPU(cs); 7230 CPUARMState *env = &cpu->env; 7231 MemTxAttrs attrs = {}; 7232 AddressSpace *as; 7233 7234 attrs.secure = is_secure; 7235 as = arm_addressspace(cs, attrs); 7236 addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi); 7237 if (fi->s1ptw) { 7238 return 0; 7239 } 7240 if (regime_translation_big_endian(env, mmu_idx)) { 7241 return address_space_ldq_be(as, addr, attrs, NULL); 7242 } else { 7243 return address_space_ldq_le(as, addr, attrs, NULL); 7244 } 7245 } 7246 7247 static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, 7248 int access_type, ARMMMUIdx mmu_idx, 7249 hwaddr *phys_ptr, int *prot, 7250 target_ulong *page_size, uint32_t *fsr, 7251 ARMMMUFaultInfo *fi) 7252 { 7253 CPUState *cs = CPU(arm_env_get_cpu(env)); 7254 int code; 7255 uint32_t table; 7256 uint32_t desc; 7257 int type; 7258 int ap; 7259 int domain = 0; 7260 int domain_prot; 7261 hwaddr phys_addr; 7262 uint32_t dacr; 7263 7264 /* Pagetable walk. */ 7265 /* Lookup l1 descriptor. */ 7266 if (!get_level1_table_address(env, mmu_idx, &table, address)) { 7267 /* Section translation fault if page walk is disabled by PD0 or PD1 */ 7268 code = 5; 7269 goto do_fault; 7270 } 7271 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), 7272 mmu_idx, fsr, fi); 7273 type = (desc & 3); 7274 domain = (desc >> 5) & 0x0f; 7275 if (regime_el(env, mmu_idx) == 1) { 7276 dacr = env->cp15.dacr_ns; 7277 } else { 7278 dacr = env->cp15.dacr_s; 7279 } 7280 domain_prot = (dacr >> (domain * 2)) & 3; 7281 if (type == 0) { 7282 /* Section translation fault. */ 7283 code = 5; 7284 goto do_fault; 7285 } 7286 if (domain_prot == 0 || domain_prot == 2) { 7287 if (type == 2) 7288 code = 9; /* Section domain fault. */ 7289 else 7290 code = 11; /* Page domain fault. */ 7291 goto do_fault; 7292 } 7293 if (type == 2) { 7294 /* 1Mb section. */ 7295 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); 7296 ap = (desc >> 10) & 3; 7297 code = 13; 7298 *page_size = 1024 * 1024; 7299 } else { 7300 /* Lookup l2 entry. */ 7301 if (type == 1) { 7302 /* Coarse pagetable. */ 7303 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); 7304 } else { 7305 /* Fine pagetable. */ 7306 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc); 7307 } 7308 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), 7309 mmu_idx, fsr, fi); 7310 switch (desc & 3) { 7311 case 0: /* Page translation fault. */ 7312 code = 7; 7313 goto do_fault; 7314 case 1: /* 64k page. */ 7315 phys_addr = (desc & 0xffff0000) | (address & 0xffff); 7316 ap = (desc >> (4 + ((address >> 13) & 6))) & 3; 7317 *page_size = 0x10000; 7318 break; 7319 case 2: /* 4k page. */ 7320 phys_addr = (desc & 0xfffff000) | (address & 0xfff); 7321 ap = (desc >> (4 + ((address >> 9) & 6))) & 3; 7322 *page_size = 0x1000; 7323 break; 7324 case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */ 7325 if (type == 1) { 7326 /* ARMv6/XScale extended small page format */ 7327 if (arm_feature(env, ARM_FEATURE_XSCALE) 7328 || arm_feature(env, ARM_FEATURE_V6)) { 7329 phys_addr = (desc & 0xfffff000) | (address & 0xfff); 7330 *page_size = 0x1000; 7331 } else { 7332 /* UNPREDICTABLE in ARMv5; we choose to take a 7333 * page translation fault. 7334 */ 7335 code = 7; 7336 goto do_fault; 7337 } 7338 } else { 7339 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff); 7340 *page_size = 0x400; 7341 } 7342 ap = (desc >> 4) & 3; 7343 break; 7344 default: 7345 /* Never happens, but compiler isn't smart enough to tell. */ 7346 abort(); 7347 } 7348 code = 15; 7349 } 7350 *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot); 7351 *prot |= *prot ? PAGE_EXEC : 0; 7352 if (!(*prot & (1 << access_type))) { 7353 /* Access permission fault. */ 7354 goto do_fault; 7355 } 7356 *phys_ptr = phys_addr; 7357 return false; 7358 do_fault: 7359 *fsr = code | (domain << 4); 7360 return true; 7361 } 7362 7363 static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, 7364 int access_type, ARMMMUIdx mmu_idx, 7365 hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, 7366 target_ulong *page_size, uint32_t *fsr, 7367 ARMMMUFaultInfo *fi) 7368 { 7369 CPUState *cs = CPU(arm_env_get_cpu(env)); 7370 int code; 7371 uint32_t table; 7372 uint32_t desc; 7373 uint32_t xn; 7374 uint32_t pxn = 0; 7375 int type; 7376 int ap; 7377 int domain = 0; 7378 int domain_prot; 7379 hwaddr phys_addr; 7380 uint32_t dacr; 7381 bool ns; 7382 7383 /* Pagetable walk. */ 7384 /* Lookup l1 descriptor. */ 7385 if (!get_level1_table_address(env, mmu_idx, &table, address)) { 7386 /* Section translation fault if page walk is disabled by PD0 or PD1 */ 7387 code = 5; 7388 goto do_fault; 7389 } 7390 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), 7391 mmu_idx, fsr, fi); 7392 type = (desc & 3); 7393 if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) { 7394 /* Section translation fault, or attempt to use the encoding 7395 * which is Reserved on implementations without PXN. 7396 */ 7397 code = 5; 7398 goto do_fault; 7399 } 7400 if ((type == 1) || !(desc & (1 << 18))) { 7401 /* Page or Section. */ 7402 domain = (desc >> 5) & 0x0f; 7403 } 7404 if (regime_el(env, mmu_idx) == 1) { 7405 dacr = env->cp15.dacr_ns; 7406 } else { 7407 dacr = env->cp15.dacr_s; 7408 } 7409 domain_prot = (dacr >> (domain * 2)) & 3; 7410 if (domain_prot == 0 || domain_prot == 2) { 7411 if (type != 1) { 7412 code = 9; /* Section domain fault. */ 7413 } else { 7414 code = 11; /* Page domain fault. */ 7415 } 7416 goto do_fault; 7417 } 7418 if (type != 1) { 7419 if (desc & (1 << 18)) { 7420 /* Supersection. */ 7421 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff); 7422 phys_addr |= (uint64_t)extract32(desc, 20, 4) << 32; 7423 phys_addr |= (uint64_t)extract32(desc, 5, 4) << 36; 7424 *page_size = 0x1000000; 7425 } else { 7426 /* Section. */ 7427 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); 7428 *page_size = 0x100000; 7429 } 7430 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4); 7431 xn = desc & (1 << 4); 7432 pxn = desc & 1; 7433 code = 13; 7434 ns = extract32(desc, 19, 1); 7435 } else { 7436 if (arm_feature(env, ARM_FEATURE_PXN)) { 7437 pxn = (desc >> 2) & 1; 7438 } 7439 ns = extract32(desc, 3, 1); 7440 /* Lookup l2 entry. */ 7441 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); 7442 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), 7443 mmu_idx, fsr, fi); 7444 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4); 7445 switch (desc & 3) { 7446 case 0: /* Page translation fault. */ 7447 code = 7; 7448 goto do_fault; 7449 case 1: /* 64k page. */ 7450 phys_addr = (desc & 0xffff0000) | (address & 0xffff); 7451 xn = desc & (1 << 15); 7452 *page_size = 0x10000; 7453 break; 7454 case 2: case 3: /* 4k page. */ 7455 phys_addr = (desc & 0xfffff000) | (address & 0xfff); 7456 xn = desc & 1; 7457 *page_size = 0x1000; 7458 break; 7459 default: 7460 /* Never happens, but compiler isn't smart enough to tell. */ 7461 abort(); 7462 } 7463 code = 15; 7464 } 7465 if (domain_prot == 3) { 7466 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 7467 } else { 7468 if (pxn && !regime_is_user(env, mmu_idx)) { 7469 xn = 1; 7470 } 7471 if (xn && access_type == 2) 7472 goto do_fault; 7473 7474 if (arm_feature(env, ARM_FEATURE_V6K) && 7475 (regime_sctlr(env, mmu_idx) & SCTLR_AFE)) { 7476 /* The simplified model uses AP[0] as an access control bit. */ 7477 if ((ap & 1) == 0) { 7478 /* Access flag fault. */ 7479 code = (code == 15) ? 6 : 3; 7480 goto do_fault; 7481 } 7482 *prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1); 7483 } else { 7484 *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot); 7485 } 7486 if (*prot && !xn) { 7487 *prot |= PAGE_EXEC; 7488 } 7489 if (!(*prot & (1 << access_type))) { 7490 /* Access permission fault. */ 7491 goto do_fault; 7492 } 7493 } 7494 if (ns) { 7495 /* The NS bit will (as required by the architecture) have no effect if 7496 * the CPU doesn't support TZ or this is a non-secure translation 7497 * regime, because the attribute will already be non-secure. 7498 */ 7499 attrs->secure = false; 7500 } 7501 *phys_ptr = phys_addr; 7502 return false; 7503 do_fault: 7504 *fsr = code | (domain << 4); 7505 return true; 7506 } 7507 7508 /* Fault type for long-descriptor MMU fault reporting; this corresponds 7509 * to bits [5..2] in the STATUS field in long-format DFSR/IFSR. 7510 */ 7511 typedef enum { 7512 translation_fault = 1, 7513 access_fault = 2, 7514 permission_fault = 3, 7515 } MMUFaultType; 7516 7517 /* 7518 * check_s2_mmu_setup 7519 * @cpu: ARMCPU 7520 * @is_aa64: True if the translation regime is in AArch64 state 7521 * @startlevel: Suggested starting level 7522 * @inputsize: Bitsize of IPAs 7523 * @stride: Page-table stride (See the ARM ARM) 7524 * 7525 * Returns true if the suggested S2 translation parameters are OK and 7526 * false otherwise. 7527 */ 7528 static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, 7529 int inputsize, int stride) 7530 { 7531 const int grainsize = stride + 3; 7532 int startsizecheck; 7533 7534 /* Negative levels are never allowed. */ 7535 if (level < 0) { 7536 return false; 7537 } 7538 7539 startsizecheck = inputsize - ((3 - level) * stride + grainsize); 7540 if (startsizecheck < 1 || startsizecheck > stride + 4) { 7541 return false; 7542 } 7543 7544 if (is_aa64) { 7545 CPUARMState *env = &cpu->env; 7546 unsigned int pamax = arm_pamax(cpu); 7547 7548 switch (stride) { 7549 case 13: /* 64KB Pages. */ 7550 if (level == 0 || (level == 1 && pamax <= 42)) { 7551 return false; 7552 } 7553 break; 7554 case 11: /* 16KB Pages. */ 7555 if (level == 0 || (level == 1 && pamax <= 40)) { 7556 return false; 7557 } 7558 break; 7559 case 9: /* 4KB Pages. */ 7560 if (level == 0 && pamax <= 42) { 7561 return false; 7562 } 7563 break; 7564 default: 7565 g_assert_not_reached(); 7566 } 7567 7568 /* Inputsize checks. */ 7569 if (inputsize > pamax && 7570 (arm_el_is_aa64(env, 1) || inputsize > 40)) { 7571 /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */ 7572 return false; 7573 } 7574 } else { 7575 /* AArch32 only supports 4KB pages. Assert on that. */ 7576 assert(stride == 9); 7577 7578 if (level == 0) { 7579 return false; 7580 } 7581 } 7582 return true; 7583 } 7584 7585 static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, 7586 int access_type, ARMMMUIdx mmu_idx, 7587 hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, 7588 target_ulong *page_size_ptr, uint32_t *fsr, 7589 ARMMMUFaultInfo *fi) 7590 { 7591 ARMCPU *cpu = arm_env_get_cpu(env); 7592 CPUState *cs = CPU(cpu); 7593 /* Read an LPAE long-descriptor translation table. */ 7594 MMUFaultType fault_type = translation_fault; 7595 uint32_t level; 7596 uint32_t epd = 0; 7597 int32_t t0sz, t1sz; 7598 uint32_t tg; 7599 uint64_t ttbr; 7600 int ttbr_select; 7601 hwaddr descaddr, indexmask, indexmask_grainsize; 7602 uint32_t tableattrs; 7603 target_ulong page_size; 7604 uint32_t attrs; 7605 int32_t stride = 9; 7606 int32_t addrsize; 7607 int inputsize; 7608 int32_t tbi = 0; 7609 TCR *tcr = regime_tcr(env, mmu_idx); 7610 int ap, ns, xn, pxn; 7611 uint32_t el = regime_el(env, mmu_idx); 7612 bool ttbr1_valid = true; 7613 uint64_t descaddrmask; 7614 bool aarch64 = arm_el_is_aa64(env, el); 7615 7616 /* TODO: 7617 * This code does not handle the different format TCR for VTCR_EL2. 7618 * This code also does not support shareability levels. 7619 * Attribute and permission bit handling should also be checked when adding 7620 * support for those page table walks. 7621 */ 7622 if (aarch64) { 7623 level = 0; 7624 addrsize = 64; 7625 if (el > 1) { 7626 if (mmu_idx != ARMMMUIdx_S2NS) { 7627 tbi = extract64(tcr->raw_tcr, 20, 1); 7628 } 7629 } else { 7630 if (extract64(address, 55, 1)) { 7631 tbi = extract64(tcr->raw_tcr, 38, 1); 7632 } else { 7633 tbi = extract64(tcr->raw_tcr, 37, 1); 7634 } 7635 } 7636 tbi *= 8; 7637 7638 /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it 7639 * invalid. 7640 */ 7641 if (el > 1) { 7642 ttbr1_valid = false; 7643 } 7644 } else { 7645 level = 1; 7646 addrsize = 32; 7647 /* There is no TTBR1 for EL2 */ 7648 if (el == 2) { 7649 ttbr1_valid = false; 7650 } 7651 } 7652 7653 /* Determine whether this address is in the region controlled by 7654 * TTBR0 or TTBR1 (or if it is in neither region and should fault). 7655 * This is a Non-secure PL0/1 stage 1 translation, so controlled by 7656 * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32: 7657 */ 7658 if (aarch64) { 7659 /* AArch64 translation. */ 7660 t0sz = extract32(tcr->raw_tcr, 0, 6); 7661 t0sz = MIN(t0sz, 39); 7662 t0sz = MAX(t0sz, 16); 7663 } else if (mmu_idx != ARMMMUIdx_S2NS) { 7664 /* AArch32 stage 1 translation. */ 7665 t0sz = extract32(tcr->raw_tcr, 0, 3); 7666 } else { 7667 /* AArch32 stage 2 translation. */ 7668 bool sext = extract32(tcr->raw_tcr, 4, 1); 7669 bool sign = extract32(tcr->raw_tcr, 3, 1); 7670 /* Address size is 40-bit for a stage 2 translation, 7671 * and t0sz can be negative (from -8 to 7), 7672 * so we need to adjust it to use the TTBR selecting logic below. 7673 */ 7674 addrsize = 40; 7675 t0sz = sextract32(tcr->raw_tcr, 0, 4) + 8; 7676 7677 /* If the sign-extend bit is not the same as t0sz[3], the result 7678 * is unpredictable. Flag this as a guest error. */ 7679 if (sign != sext) { 7680 qemu_log_mask(LOG_GUEST_ERROR, 7681 "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n"); 7682 } 7683 } 7684 t1sz = extract32(tcr->raw_tcr, 16, 6); 7685 if (aarch64) { 7686 t1sz = MIN(t1sz, 39); 7687 t1sz = MAX(t1sz, 16); 7688 } 7689 if (t0sz && !extract64(address, addrsize - t0sz, t0sz - tbi)) { 7690 /* there is a ttbr0 region and we are in it (high bits all zero) */ 7691 ttbr_select = 0; 7692 } else if (ttbr1_valid && t1sz && 7693 !extract64(~address, addrsize - t1sz, t1sz - tbi)) { 7694 /* there is a ttbr1 region and we are in it (high bits all one) */ 7695 ttbr_select = 1; 7696 } else if (!t0sz) { 7697 /* ttbr0 region is "everything not in the ttbr1 region" */ 7698 ttbr_select = 0; 7699 } else if (!t1sz && ttbr1_valid) { 7700 /* ttbr1 region is "everything not in the ttbr0 region" */ 7701 ttbr_select = 1; 7702 } else { 7703 /* in the gap between the two regions, this is a Translation fault */ 7704 fault_type = translation_fault; 7705 goto do_fault; 7706 } 7707 7708 /* Note that QEMU ignores shareability and cacheability attributes, 7709 * so we don't need to do anything with the SH, ORGN, IRGN fields 7710 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the 7711 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently 7712 * implement any ASID-like capability so we can ignore it (instead 7713 * we will always flush the TLB any time the ASID is changed). 7714 */ 7715 if (ttbr_select == 0) { 7716 ttbr = regime_ttbr(env, mmu_idx, 0); 7717 if (el < 2) { 7718 epd = extract32(tcr->raw_tcr, 7, 1); 7719 } 7720 inputsize = addrsize - t0sz; 7721 7722 tg = extract32(tcr->raw_tcr, 14, 2); 7723 if (tg == 1) { /* 64KB pages */ 7724 stride = 13; 7725 } 7726 if (tg == 2) { /* 16KB pages */ 7727 stride = 11; 7728 } 7729 } else { 7730 /* We should only be here if TTBR1 is valid */ 7731 assert(ttbr1_valid); 7732 7733 ttbr = regime_ttbr(env, mmu_idx, 1); 7734 epd = extract32(tcr->raw_tcr, 23, 1); 7735 inputsize = addrsize - t1sz; 7736 7737 tg = extract32(tcr->raw_tcr, 30, 2); 7738 if (tg == 3) { /* 64KB pages */ 7739 stride = 13; 7740 } 7741 if (tg == 1) { /* 16KB pages */ 7742 stride = 11; 7743 } 7744 } 7745 7746 /* Here we should have set up all the parameters for the translation: 7747 * inputsize, ttbr, epd, stride, tbi 7748 */ 7749 7750 if (epd) { 7751 /* Translation table walk disabled => Translation fault on TLB miss 7752 * Note: This is always 0 on 64-bit EL2 and EL3. 7753 */ 7754 goto do_fault; 7755 } 7756 7757 if (mmu_idx != ARMMMUIdx_S2NS) { 7758 /* The starting level depends on the virtual address size (which can 7759 * be up to 48 bits) and the translation granule size. It indicates 7760 * the number of strides (stride bits at a time) needed to 7761 * consume the bits of the input address. In the pseudocode this is: 7762 * level = 4 - RoundUp((inputsize - grainsize) / stride) 7763 * where their 'inputsize' is our 'inputsize', 'grainsize' is 7764 * our 'stride + 3' and 'stride' is our 'stride'. 7765 * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying: 7766 * = 4 - (inputsize - stride - 3 + stride - 1) / stride 7767 * = 4 - (inputsize - 4) / stride; 7768 */ 7769 level = 4 - (inputsize - 4) / stride; 7770 } else { 7771 /* For stage 2 translations the starting level is specified by the 7772 * VTCR_EL2.SL0 field (whose interpretation depends on the page size) 7773 */ 7774 uint32_t sl0 = extract32(tcr->raw_tcr, 6, 2); 7775 uint32_t startlevel; 7776 bool ok; 7777 7778 if (!aarch64 || stride == 9) { 7779 /* AArch32 or 4KB pages */ 7780 startlevel = 2 - sl0; 7781 } else { 7782 /* 16KB or 64KB pages */ 7783 startlevel = 3 - sl0; 7784 } 7785 7786 /* Check that the starting level is valid. */ 7787 ok = check_s2_mmu_setup(cpu, aarch64, startlevel, 7788 inputsize, stride); 7789 if (!ok) { 7790 fault_type = translation_fault; 7791 goto do_fault; 7792 } 7793 level = startlevel; 7794 } 7795 7796 indexmask_grainsize = (1ULL << (stride + 3)) - 1; 7797 indexmask = (1ULL << (inputsize - (stride * (4 - level)))) - 1; 7798 7799 /* Now we can extract the actual base address from the TTBR */ 7800 descaddr = extract64(ttbr, 0, 48); 7801 descaddr &= ~indexmask; 7802 7803 /* The address field in the descriptor goes up to bit 39 for ARMv7 7804 * but up to bit 47 for ARMv8, but we use the descaddrmask 7805 * up to bit 39 for AArch32, because we don't need other bits in that case 7806 * to construct next descriptor address (anyway they should be all zeroes). 7807 */ 7808 descaddrmask = ((1ull << (aarch64 ? 48 : 40)) - 1) & 7809 ~indexmask_grainsize; 7810 7811 /* Secure accesses start with the page table in secure memory and 7812 * can be downgraded to non-secure at any step. Non-secure accesses 7813 * remain non-secure. We implement this by just ORing in the NSTable/NS 7814 * bits at each step. 7815 */ 7816 tableattrs = regime_is_secure(env, mmu_idx) ? 0 : (1 << 4); 7817 for (;;) { 7818 uint64_t descriptor; 7819 bool nstable; 7820 7821 descaddr |= (address >> (stride * (4 - level))) & indexmask; 7822 descaddr &= ~7ULL; 7823 nstable = extract32(tableattrs, 4, 1); 7824 descriptor = arm_ldq_ptw(cs, descaddr, !nstable, mmu_idx, fsr, fi); 7825 if (fi->s1ptw) { 7826 goto do_fault; 7827 } 7828 7829 if (!(descriptor & 1) || 7830 (!(descriptor & 2) && (level == 3))) { 7831 /* Invalid, or the Reserved level 3 encoding */ 7832 goto do_fault; 7833 } 7834 descaddr = descriptor & descaddrmask; 7835 7836 if ((descriptor & 2) && (level < 3)) { 7837 /* Table entry. The top five bits are attributes which may 7838 * propagate down through lower levels of the table (and 7839 * which are all arranged so that 0 means "no effect", so 7840 * we can gather them up by ORing in the bits at each level). 7841 */ 7842 tableattrs |= extract64(descriptor, 59, 5); 7843 level++; 7844 indexmask = indexmask_grainsize; 7845 continue; 7846 } 7847 /* Block entry at level 1 or 2, or page entry at level 3. 7848 * These are basically the same thing, although the number 7849 * of bits we pull in from the vaddr varies. 7850 */ 7851 page_size = (1ULL << ((stride * (4 - level)) + 3)); 7852 descaddr |= (address & (page_size - 1)); 7853 /* Extract attributes from the descriptor */ 7854 attrs = extract64(descriptor, 2, 10) 7855 | (extract64(descriptor, 52, 12) << 10); 7856 7857 if (mmu_idx == ARMMMUIdx_S2NS) { 7858 /* Stage 2 table descriptors do not include any attribute fields */ 7859 break; 7860 } 7861 /* Merge in attributes from table descriptors */ 7862 attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */ 7863 attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */ 7864 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1 7865 * means "force PL1 access only", which means forcing AP[1] to 0. 7866 */ 7867 if (extract32(tableattrs, 2, 1)) { 7868 attrs &= ~(1 << 4); 7869 } 7870 attrs |= nstable << 3; /* NS */ 7871 break; 7872 } 7873 /* Here descaddr is the final physical address, and attributes 7874 * are all in attrs. 7875 */ 7876 fault_type = access_fault; 7877 if ((attrs & (1 << 8)) == 0) { 7878 /* Access flag */ 7879 goto do_fault; 7880 } 7881 7882 ap = extract32(attrs, 4, 2); 7883 xn = extract32(attrs, 12, 1); 7884 7885 if (mmu_idx == ARMMMUIdx_S2NS) { 7886 ns = true; 7887 *prot = get_S2prot(env, ap, xn); 7888 } else { 7889 ns = extract32(attrs, 3, 1); 7890 pxn = extract32(attrs, 11, 1); 7891 *prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn); 7892 } 7893 7894 fault_type = permission_fault; 7895 if (!(*prot & (1 << access_type))) { 7896 goto do_fault; 7897 } 7898 7899 if (ns) { 7900 /* The NS bit will (as required by the architecture) have no effect if 7901 * the CPU doesn't support TZ or this is a non-secure translation 7902 * regime, because the attribute will already be non-secure. 7903 */ 7904 txattrs->secure = false; 7905 } 7906 *phys_ptr = descaddr; 7907 *page_size_ptr = page_size; 7908 return false; 7909 7910 do_fault: 7911 /* Long-descriptor format IFSR/DFSR value */ 7912 *fsr = (1 << 9) | (fault_type << 2) | level; 7913 /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */ 7914 fi->stage2 = fi->s1ptw || (mmu_idx == ARMMMUIdx_S2NS); 7915 return true; 7916 } 7917 7918 static inline void get_phys_addr_pmsav7_default(CPUARMState *env, 7919 ARMMMUIdx mmu_idx, 7920 int32_t address, int *prot) 7921 { 7922 *prot = PAGE_READ | PAGE_WRITE; 7923 switch (address) { 7924 case 0xF0000000 ... 0xFFFFFFFF: 7925 if (regime_sctlr(env, mmu_idx) & SCTLR_V) { /* hivecs execing is ok */ 7926 *prot |= PAGE_EXEC; 7927 } 7928 break; 7929 case 0x00000000 ... 0x7FFFFFFF: 7930 *prot |= PAGE_EXEC; 7931 break; 7932 } 7933 7934 } 7935 7936 static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, 7937 int access_type, ARMMMUIdx mmu_idx, 7938 hwaddr *phys_ptr, int *prot, uint32_t *fsr) 7939 { 7940 ARMCPU *cpu = arm_env_get_cpu(env); 7941 int n; 7942 bool is_user = regime_is_user(env, mmu_idx); 7943 7944 *phys_ptr = address; 7945 *prot = 0; 7946 7947 if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */ 7948 get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); 7949 } else { /* MPU enabled */ 7950 for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) { 7951 /* region search */ 7952 uint32_t base = env->pmsav7.drbar[n]; 7953 uint32_t rsize = extract32(env->pmsav7.drsr[n], 1, 5); 7954 uint32_t rmask; 7955 bool srdis = false; 7956 7957 if (!(env->pmsav7.drsr[n] & 0x1)) { 7958 continue; 7959 } 7960 7961 if (!rsize) { 7962 qemu_log_mask(LOG_GUEST_ERROR, "DRSR.Rsize field can not be 0"); 7963 continue; 7964 } 7965 rsize++; 7966 rmask = (1ull << rsize) - 1; 7967 7968 if (base & rmask) { 7969 qemu_log_mask(LOG_GUEST_ERROR, "DRBAR %" PRIx32 " misaligned " 7970 "to DRSR region size, mask = %" PRIx32, 7971 base, rmask); 7972 continue; 7973 } 7974 7975 if (address < base || address > base + rmask) { 7976 continue; 7977 } 7978 7979 /* Region matched */ 7980 7981 if (rsize >= 8) { /* no subregions for regions < 256 bytes */ 7982 int i, snd; 7983 uint32_t srdis_mask; 7984 7985 rsize -= 3; /* sub region size (power of 2) */ 7986 snd = ((address - base) >> rsize) & 0x7; 7987 srdis = extract32(env->pmsav7.drsr[n], snd + 8, 1); 7988 7989 srdis_mask = srdis ? 0x3 : 0x0; 7990 for (i = 2; i <= 8 && rsize < TARGET_PAGE_BITS; i *= 2) { 7991 /* This will check in groups of 2, 4 and then 8, whether 7992 * the subregion bits are consistent. rsize is incremented 7993 * back up to give the region size, considering consistent 7994 * adjacent subregions as one region. Stop testing if rsize 7995 * is already big enough for an entire QEMU page. 7996 */ 7997 int snd_rounded = snd & ~(i - 1); 7998 uint32_t srdis_multi = extract32(env->pmsav7.drsr[n], 7999 snd_rounded + 8, i); 8000 if (srdis_mask ^ srdis_multi) { 8001 break; 8002 } 8003 srdis_mask = (srdis_mask << i) | srdis_mask; 8004 rsize++; 8005 } 8006 } 8007 if (rsize < TARGET_PAGE_BITS) { 8008 qemu_log_mask(LOG_UNIMP, "No support for MPU (sub)region" 8009 "alignment of %" PRIu32 " bits. Minimum is %d\n", 8010 rsize, TARGET_PAGE_BITS); 8011 continue; 8012 } 8013 if (srdis) { 8014 continue; 8015 } 8016 break; 8017 } 8018 8019 if (n == -1) { /* no hits */ 8020 if (cpu->pmsav7_dregion && 8021 (is_user || !(regime_sctlr(env, mmu_idx) & SCTLR_BR))) { 8022 /* background fault */ 8023 *fsr = 0; 8024 return true; 8025 } 8026 get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); 8027 } else { /* a MPU hit! */ 8028 uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3); 8029 8030 if (is_user) { /* User mode AP bit decoding */ 8031 switch (ap) { 8032 case 0: 8033 case 1: 8034 case 5: 8035 break; /* no access */ 8036 case 3: 8037 *prot |= PAGE_WRITE; 8038 /* fall through */ 8039 case 2: 8040 case 6: 8041 *prot |= PAGE_READ | PAGE_EXEC; 8042 break; 8043 default: 8044 qemu_log_mask(LOG_GUEST_ERROR, 8045 "Bad value for AP bits in DRACR %" 8046 PRIx32 "\n", ap); 8047 } 8048 } else { /* Priv. mode AP bits decoding */ 8049 switch (ap) { 8050 case 0: 8051 break; /* no access */ 8052 case 1: 8053 case 2: 8054 case 3: 8055 *prot |= PAGE_WRITE; 8056 /* fall through */ 8057 case 5: 8058 case 6: 8059 *prot |= PAGE_READ | PAGE_EXEC; 8060 break; 8061 default: 8062 qemu_log_mask(LOG_GUEST_ERROR, 8063 "Bad value for AP bits in DRACR %" 8064 PRIx32 "\n", ap); 8065 } 8066 } 8067 8068 /* execute never */ 8069 if (env->pmsav7.dracr[n] & (1 << 12)) { 8070 *prot &= ~PAGE_EXEC; 8071 } 8072 } 8073 } 8074 8075 *fsr = 0x00d; /* Permission fault */ 8076 return !(*prot & (1 << access_type)); 8077 } 8078 8079 static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, 8080 int access_type, ARMMMUIdx mmu_idx, 8081 hwaddr *phys_ptr, int *prot, uint32_t *fsr) 8082 { 8083 int n; 8084 uint32_t mask; 8085 uint32_t base; 8086 bool is_user = regime_is_user(env, mmu_idx); 8087 8088 *phys_ptr = address; 8089 for (n = 7; n >= 0; n--) { 8090 base = env->cp15.c6_region[n]; 8091 if ((base & 1) == 0) { 8092 continue; 8093 } 8094 mask = 1 << ((base >> 1) & 0x1f); 8095 /* Keep this shift separate from the above to avoid an 8096 (undefined) << 32. */ 8097 mask = (mask << 1) - 1; 8098 if (((base ^ address) & ~mask) == 0) { 8099 break; 8100 } 8101 } 8102 if (n < 0) { 8103 *fsr = 2; 8104 return true; 8105 } 8106 8107 if (access_type == 2) { 8108 mask = env->cp15.pmsav5_insn_ap; 8109 } else { 8110 mask = env->cp15.pmsav5_data_ap; 8111 } 8112 mask = (mask >> (n * 4)) & 0xf; 8113 switch (mask) { 8114 case 0: 8115 *fsr = 1; 8116 return true; 8117 case 1: 8118 if (is_user) { 8119 *fsr = 1; 8120 return true; 8121 } 8122 *prot = PAGE_READ | PAGE_WRITE; 8123 break; 8124 case 2: 8125 *prot = PAGE_READ; 8126 if (!is_user) { 8127 *prot |= PAGE_WRITE; 8128 } 8129 break; 8130 case 3: 8131 *prot = PAGE_READ | PAGE_WRITE; 8132 break; 8133 case 5: 8134 if (is_user) { 8135 *fsr = 1; 8136 return true; 8137 } 8138 *prot = PAGE_READ; 8139 break; 8140 case 6: 8141 *prot = PAGE_READ; 8142 break; 8143 default: 8144 /* Bad permission. */ 8145 *fsr = 1; 8146 return true; 8147 } 8148 *prot |= PAGE_EXEC; 8149 return false; 8150 } 8151 8152 /* get_phys_addr - get the physical address for this virtual address 8153 * 8154 * Find the physical address corresponding to the given virtual address, 8155 * by doing a translation table walk on MMU based systems or using the 8156 * MPU state on MPU based systems. 8157 * 8158 * Returns false if the translation was successful. Otherwise, phys_ptr, attrs, 8159 * prot and page_size may not be filled in, and the populated fsr value provides 8160 * information on why the translation aborted, in the format of a 8161 * DFSR/IFSR fault register, with the following caveats: 8162 * * we honour the short vs long DFSR format differences. 8163 * * the WnR bit is never set (the caller must do this). 8164 * * for PSMAv5 based systems we don't bother to return a full FSR format 8165 * value. 8166 * 8167 * @env: CPUARMState 8168 * @address: virtual address to get physical address for 8169 * @access_type: 0 for read, 1 for write, 2 for execute 8170 * @mmu_idx: MMU index indicating required translation regime 8171 * @phys_ptr: set to the physical address corresponding to the virtual address 8172 * @attrs: set to the memory transaction attributes to use 8173 * @prot: set to the permissions for the page containing phys_ptr 8174 * @page_size: set to the size of the page containing phys_ptr 8175 * @fsr: set to the DFSR/IFSR value on failure 8176 */ 8177 static bool get_phys_addr(CPUARMState *env, target_ulong address, 8178 int access_type, ARMMMUIdx mmu_idx, 8179 hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, 8180 target_ulong *page_size, uint32_t *fsr, 8181 ARMMMUFaultInfo *fi) 8182 { 8183 if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { 8184 /* Call ourselves recursively to do the stage 1 and then stage 2 8185 * translations. 8186 */ 8187 if (arm_feature(env, ARM_FEATURE_EL2)) { 8188 hwaddr ipa; 8189 int s2_prot; 8190 int ret; 8191 8192 ret = get_phys_addr(env, address, access_type, 8193 mmu_idx + ARMMMUIdx_S1NSE0, &ipa, attrs, 8194 prot, page_size, fsr, fi); 8195 8196 /* If S1 fails or S2 is disabled, return early. */ 8197 if (ret || regime_translation_disabled(env, ARMMMUIdx_S2NS)) { 8198 *phys_ptr = ipa; 8199 return ret; 8200 } 8201 8202 /* S1 is done. Now do S2 translation. */ 8203 ret = get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_S2NS, 8204 phys_ptr, attrs, &s2_prot, 8205 page_size, fsr, fi); 8206 fi->s2addr = ipa; 8207 /* Combine the S1 and S2 perms. */ 8208 *prot &= s2_prot; 8209 return ret; 8210 } else { 8211 /* 8212 * For non-EL2 CPUs a stage1+stage2 translation is just stage 1. 8213 */ 8214 mmu_idx += ARMMMUIdx_S1NSE0; 8215 } 8216 } 8217 8218 /* The page table entries may downgrade secure to non-secure, but 8219 * cannot upgrade an non-secure translation regime's attributes 8220 * to secure. 8221 */ 8222 attrs->secure = regime_is_secure(env, mmu_idx); 8223 attrs->user = regime_is_user(env, mmu_idx); 8224 8225 /* Fast Context Switch Extension. This doesn't exist at all in v8. 8226 * In v7 and earlier it affects all stage 1 translations. 8227 */ 8228 if (address < 0x02000000 && mmu_idx != ARMMMUIdx_S2NS 8229 && !arm_feature(env, ARM_FEATURE_V8)) { 8230 if (regime_el(env, mmu_idx) == 3) { 8231 address += env->cp15.fcseidr_s; 8232 } else { 8233 address += env->cp15.fcseidr_ns; 8234 } 8235 } 8236 8237 /* pmsav7 has special handling for when MPU is disabled so call it before 8238 * the common MMU/MPU disabled check below. 8239 */ 8240 if (arm_feature(env, ARM_FEATURE_MPU) && 8241 arm_feature(env, ARM_FEATURE_V7)) { 8242 *page_size = TARGET_PAGE_SIZE; 8243 return get_phys_addr_pmsav7(env, address, access_type, mmu_idx, 8244 phys_ptr, prot, fsr); 8245 } 8246 8247 if (regime_translation_disabled(env, mmu_idx)) { 8248 /* MMU/MPU disabled. */ 8249 *phys_ptr = address; 8250 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 8251 *page_size = TARGET_PAGE_SIZE; 8252 return 0; 8253 } 8254 8255 if (arm_feature(env, ARM_FEATURE_MPU)) { 8256 /* Pre-v7 MPU */ 8257 *page_size = TARGET_PAGE_SIZE; 8258 return get_phys_addr_pmsav5(env, address, access_type, mmu_idx, 8259 phys_ptr, prot, fsr); 8260 } 8261 8262 if (regime_using_lpae_format(env, mmu_idx)) { 8263 return get_phys_addr_lpae(env, address, access_type, mmu_idx, phys_ptr, 8264 attrs, prot, page_size, fsr, fi); 8265 } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { 8266 return get_phys_addr_v6(env, address, access_type, mmu_idx, phys_ptr, 8267 attrs, prot, page_size, fsr, fi); 8268 } else { 8269 return get_phys_addr_v5(env, address, access_type, mmu_idx, phys_ptr, 8270 prot, page_size, fsr, fi); 8271 } 8272 } 8273 8274 /* Walk the page table and (if the mapping exists) add the page 8275 * to the TLB. Return false on success, or true on failure. Populate 8276 * fsr with ARM DFSR/IFSR fault register format value on failure. 8277 */ 8278 bool arm_tlb_fill(CPUState *cs, vaddr address, 8279 int access_type, int mmu_idx, uint32_t *fsr, 8280 ARMMMUFaultInfo *fi) 8281 { 8282 ARMCPU *cpu = ARM_CPU(cs); 8283 CPUARMState *env = &cpu->env; 8284 hwaddr phys_addr; 8285 target_ulong page_size; 8286 int prot; 8287 int ret; 8288 MemTxAttrs attrs = {}; 8289 8290 ret = get_phys_addr(env, address, access_type, mmu_idx, &phys_addr, 8291 &attrs, &prot, &page_size, fsr, fi); 8292 if (!ret) { 8293 /* Map a single [sub]page. */ 8294 phys_addr &= TARGET_PAGE_MASK; 8295 address &= TARGET_PAGE_MASK; 8296 tlb_set_page_with_attrs(cs, address, phys_addr, attrs, 8297 prot, mmu_idx, page_size); 8298 return 0; 8299 } 8300 8301 return ret; 8302 } 8303 8304 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, 8305 MemTxAttrs *attrs) 8306 { 8307 ARMCPU *cpu = ARM_CPU(cs); 8308 CPUARMState *env = &cpu->env; 8309 hwaddr phys_addr; 8310 target_ulong page_size; 8311 int prot; 8312 bool ret; 8313 uint32_t fsr; 8314 ARMMMUFaultInfo fi = {}; 8315 8316 *attrs = (MemTxAttrs) {}; 8317 8318 ret = get_phys_addr(env, addr, 0, cpu_mmu_index(env, false), &phys_addr, 8319 attrs, &prot, &page_size, &fsr, &fi); 8320 8321 if (ret) { 8322 return -1; 8323 } 8324 return phys_addr; 8325 } 8326 8327 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) 8328 { 8329 uint32_t mask; 8330 unsigned el = arm_current_el(env); 8331 8332 /* First handle registers which unprivileged can read */ 8333 8334 switch (reg) { 8335 case 0 ... 7: /* xPSR sub-fields */ 8336 mask = 0; 8337 if ((reg & 1) && el) { 8338 mask |= 0x000001ff; /* IPSR (unpriv. reads as zero) */ 8339 } 8340 if (!(reg & 4)) { 8341 mask |= 0xf8000000; /* APSR */ 8342 } 8343 /* EPSR reads as zero */ 8344 return xpsr_read(env) & mask; 8345 break; 8346 case 20: /* CONTROL */ 8347 return env->v7m.control; 8348 } 8349 8350 if (el == 0) { 8351 return 0; /* unprivileged reads others as zero */ 8352 } 8353 8354 switch (reg) { 8355 case 8: /* MSP */ 8356 return (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) ? 8357 env->v7m.other_sp : env->regs[13]; 8358 case 9: /* PSP */ 8359 return (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) ? 8360 env->regs[13] : env->v7m.other_sp; 8361 case 16: /* PRIMASK */ 8362 return (env->daif & PSTATE_I) != 0; 8363 case 17: /* BASEPRI */ 8364 case 18: /* BASEPRI_MAX */ 8365 return env->v7m.basepri; 8366 case 19: /* FAULTMASK */ 8367 return (env->daif & PSTATE_F) != 0; 8368 default: 8369 qemu_log_mask(LOG_GUEST_ERROR, "Attempt to read unknown special" 8370 " register %d\n", reg); 8371 return 0; 8372 } 8373 } 8374 8375 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) 8376 { 8377 if (arm_current_el(env) == 0 && reg > 7) { 8378 /* only xPSR sub-fields may be written by unprivileged */ 8379 return; 8380 } 8381 8382 switch (reg) { 8383 case 0 ... 7: /* xPSR sub-fields */ 8384 /* only APSR is actually writable */ 8385 if (reg & 4) { 8386 xpsr_write(env, val, 0xf8000000); /* APSR */ 8387 } 8388 break; 8389 case 8: /* MSP */ 8390 if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) { 8391 env->v7m.other_sp = val; 8392 } else { 8393 env->regs[13] = val; 8394 } 8395 break; 8396 case 9: /* PSP */ 8397 if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) { 8398 env->regs[13] = val; 8399 } else { 8400 env->v7m.other_sp = val; 8401 } 8402 break; 8403 case 16: /* PRIMASK */ 8404 if (val & 1) { 8405 env->daif |= PSTATE_I; 8406 } else { 8407 env->daif &= ~PSTATE_I; 8408 } 8409 break; 8410 case 17: /* BASEPRI */ 8411 env->v7m.basepri = val & 0xff; 8412 break; 8413 case 18: /* BASEPRI_MAX */ 8414 val &= 0xff; 8415 if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0)) 8416 env->v7m.basepri = val; 8417 break; 8418 case 19: /* FAULTMASK */ 8419 if (val & 1) { 8420 env->daif |= PSTATE_F; 8421 } else { 8422 env->daif &= ~PSTATE_F; 8423 } 8424 break; 8425 case 20: /* CONTROL */ 8426 switch_v7m_sp(env, (val & R_V7M_CONTROL_SPSEL_MASK) != 0); 8427 env->v7m.control = val & (R_V7M_CONTROL_SPSEL_MASK | 8428 R_V7M_CONTROL_NPRIV_MASK); 8429 break; 8430 default: 8431 qemu_log_mask(LOG_GUEST_ERROR, "Attempt to write unknown special" 8432 " register %d\n", reg); 8433 return; 8434 } 8435 } 8436 8437 #endif 8438 8439 void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in) 8440 { 8441 /* Implement DC ZVA, which zeroes a fixed-length block of memory. 8442 * Note that we do not implement the (architecturally mandated) 8443 * alignment fault for attempts to use this on Device memory 8444 * (which matches the usual QEMU behaviour of not implementing either 8445 * alignment faults or any memory attribute handling). 8446 */ 8447 8448 ARMCPU *cpu = arm_env_get_cpu(env); 8449 uint64_t blocklen = 4 << cpu->dcz_blocksize; 8450 uint64_t vaddr = vaddr_in & ~(blocklen - 1); 8451 8452 #ifndef CONFIG_USER_ONLY 8453 { 8454 /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than 8455 * the block size so we might have to do more than one TLB lookup. 8456 * We know that in fact for any v8 CPU the page size is at least 4K 8457 * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only 8458 * 1K as an artefact of legacy v5 subpage support being present in the 8459 * same QEMU executable. 8460 */ 8461 int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE); 8462 void *hostaddr[maxidx]; 8463 int try, i; 8464 unsigned mmu_idx = cpu_mmu_index(env, false); 8465 TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx); 8466 8467 for (try = 0; try < 2; try++) { 8468 8469 for (i = 0; i < maxidx; i++) { 8470 hostaddr[i] = tlb_vaddr_to_host(env, 8471 vaddr + TARGET_PAGE_SIZE * i, 8472 1, mmu_idx); 8473 if (!hostaddr[i]) { 8474 break; 8475 } 8476 } 8477 if (i == maxidx) { 8478 /* If it's all in the TLB it's fair game for just writing to; 8479 * we know we don't need to update dirty status, etc. 8480 */ 8481 for (i = 0; i < maxidx - 1; i++) { 8482 memset(hostaddr[i], 0, TARGET_PAGE_SIZE); 8483 } 8484 memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE)); 8485 return; 8486 } 8487 /* OK, try a store and see if we can populate the tlb. This 8488 * might cause an exception if the memory isn't writable, 8489 * in which case we will longjmp out of here. We must for 8490 * this purpose use the actual register value passed to us 8491 * so that we get the fault address right. 8492 */ 8493 helper_ret_stb_mmu(env, vaddr_in, 0, oi, GETPC()); 8494 /* Now we can populate the other TLB entries, if any */ 8495 for (i = 0; i < maxidx; i++) { 8496 uint64_t va = vaddr + TARGET_PAGE_SIZE * i; 8497 if (va != (vaddr_in & TARGET_PAGE_MASK)) { 8498 helper_ret_stb_mmu(env, va, 0, oi, GETPC()); 8499 } 8500 } 8501 } 8502 8503 /* Slow path (probably attempt to do this to an I/O device or 8504 * similar, or clearing of a block of code we have translations 8505 * cached for). Just do a series of byte writes as the architecture 8506 * demands. It's not worth trying to use a cpu_physical_memory_map(), 8507 * memset(), unmap() sequence here because: 8508 * + we'd need to account for the blocksize being larger than a page 8509 * + the direct-RAM access case is almost always going to be dealt 8510 * with in the fastpath code above, so there's no speed benefit 8511 * + we would have to deal with the map returning NULL because the 8512 * bounce buffer was in use 8513 */ 8514 for (i = 0; i < blocklen; i++) { 8515 helper_ret_stb_mmu(env, vaddr + i, 0, oi, GETPC()); 8516 } 8517 } 8518 #else 8519 memset(g2h(vaddr), 0, blocklen); 8520 #endif 8521 } 8522 8523 /* Note that signed overflow is undefined in C. The following routines are 8524 careful to use unsigned types where modulo arithmetic is required. 8525 Failure to do so _will_ break on newer gcc. */ 8526 8527 /* Signed saturating arithmetic. */ 8528 8529 /* Perform 16-bit signed saturating addition. */ 8530 static inline uint16_t add16_sat(uint16_t a, uint16_t b) 8531 { 8532 uint16_t res; 8533 8534 res = a + b; 8535 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) { 8536 if (a & 0x8000) 8537 res = 0x8000; 8538 else 8539 res = 0x7fff; 8540 } 8541 return res; 8542 } 8543 8544 /* Perform 8-bit signed saturating addition. */ 8545 static inline uint8_t add8_sat(uint8_t a, uint8_t b) 8546 { 8547 uint8_t res; 8548 8549 res = a + b; 8550 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) { 8551 if (a & 0x80) 8552 res = 0x80; 8553 else 8554 res = 0x7f; 8555 } 8556 return res; 8557 } 8558 8559 /* Perform 16-bit signed saturating subtraction. */ 8560 static inline uint16_t sub16_sat(uint16_t a, uint16_t b) 8561 { 8562 uint16_t res; 8563 8564 res = a - b; 8565 if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) { 8566 if (a & 0x8000) 8567 res = 0x8000; 8568 else 8569 res = 0x7fff; 8570 } 8571 return res; 8572 } 8573 8574 /* Perform 8-bit signed saturating subtraction. */ 8575 static inline uint8_t sub8_sat(uint8_t a, uint8_t b) 8576 { 8577 uint8_t res; 8578 8579 res = a - b; 8580 if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) { 8581 if (a & 0x80) 8582 res = 0x80; 8583 else 8584 res = 0x7f; 8585 } 8586 return res; 8587 } 8588 8589 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16); 8590 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16); 8591 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8); 8592 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8); 8593 #define PFX q 8594 8595 #include "op_addsub.h" 8596 8597 /* Unsigned saturating arithmetic. */ 8598 static inline uint16_t add16_usat(uint16_t a, uint16_t b) 8599 { 8600 uint16_t res; 8601 res = a + b; 8602 if (res < a) 8603 res = 0xffff; 8604 return res; 8605 } 8606 8607 static inline uint16_t sub16_usat(uint16_t a, uint16_t b) 8608 { 8609 if (a > b) 8610 return a - b; 8611 else 8612 return 0; 8613 } 8614 8615 static inline uint8_t add8_usat(uint8_t a, uint8_t b) 8616 { 8617 uint8_t res; 8618 res = a + b; 8619 if (res < a) 8620 res = 0xff; 8621 return res; 8622 } 8623 8624 static inline uint8_t sub8_usat(uint8_t a, uint8_t b) 8625 { 8626 if (a > b) 8627 return a - b; 8628 else 8629 return 0; 8630 } 8631 8632 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16); 8633 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16); 8634 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8); 8635 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8); 8636 #define PFX uq 8637 8638 #include "op_addsub.h" 8639 8640 /* Signed modulo arithmetic. */ 8641 #define SARITH16(a, b, n, op) do { \ 8642 int32_t sum; \ 8643 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \ 8644 RESULT(sum, n, 16); \ 8645 if (sum >= 0) \ 8646 ge |= 3 << (n * 2); \ 8647 } while(0) 8648 8649 #define SARITH8(a, b, n, op) do { \ 8650 int32_t sum; \ 8651 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \ 8652 RESULT(sum, n, 8); \ 8653 if (sum >= 0) \ 8654 ge |= 1 << n; \ 8655 } while(0) 8656 8657 8658 #define ADD16(a, b, n) SARITH16(a, b, n, +) 8659 #define SUB16(a, b, n) SARITH16(a, b, n, -) 8660 #define ADD8(a, b, n) SARITH8(a, b, n, +) 8661 #define SUB8(a, b, n) SARITH8(a, b, n, -) 8662 #define PFX s 8663 #define ARITH_GE 8664 8665 #include "op_addsub.h" 8666 8667 /* Unsigned modulo arithmetic. */ 8668 #define ADD16(a, b, n) do { \ 8669 uint32_t sum; \ 8670 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \ 8671 RESULT(sum, n, 16); \ 8672 if ((sum >> 16) == 1) \ 8673 ge |= 3 << (n * 2); \ 8674 } while(0) 8675 8676 #define ADD8(a, b, n) do { \ 8677 uint32_t sum; \ 8678 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \ 8679 RESULT(sum, n, 8); \ 8680 if ((sum >> 8) == 1) \ 8681 ge |= 1 << n; \ 8682 } while(0) 8683 8684 #define SUB16(a, b, n) do { \ 8685 uint32_t sum; \ 8686 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \ 8687 RESULT(sum, n, 16); \ 8688 if ((sum >> 16) == 0) \ 8689 ge |= 3 << (n * 2); \ 8690 } while(0) 8691 8692 #define SUB8(a, b, n) do { \ 8693 uint32_t sum; \ 8694 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \ 8695 RESULT(sum, n, 8); \ 8696 if ((sum >> 8) == 0) \ 8697 ge |= 1 << n; \ 8698 } while(0) 8699 8700 #define PFX u 8701 #define ARITH_GE 8702 8703 #include "op_addsub.h" 8704 8705 /* Halved signed arithmetic. */ 8706 #define ADD16(a, b, n) \ 8707 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16) 8708 #define SUB16(a, b, n) \ 8709 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16) 8710 #define ADD8(a, b, n) \ 8711 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8) 8712 #define SUB8(a, b, n) \ 8713 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8) 8714 #define PFX sh 8715 8716 #include "op_addsub.h" 8717 8718 /* Halved unsigned arithmetic. */ 8719 #define ADD16(a, b, n) \ 8720 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16) 8721 #define SUB16(a, b, n) \ 8722 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16) 8723 #define ADD8(a, b, n) \ 8724 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8) 8725 #define SUB8(a, b, n) \ 8726 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8) 8727 #define PFX uh 8728 8729 #include "op_addsub.h" 8730 8731 static inline uint8_t do_usad(uint8_t a, uint8_t b) 8732 { 8733 if (a > b) 8734 return a - b; 8735 else 8736 return b - a; 8737 } 8738 8739 /* Unsigned sum of absolute byte differences. */ 8740 uint32_t HELPER(usad8)(uint32_t a, uint32_t b) 8741 { 8742 uint32_t sum; 8743 sum = do_usad(a, b); 8744 sum += do_usad(a >> 8, b >> 8); 8745 sum += do_usad(a >> 16, b >>16); 8746 sum += do_usad(a >> 24, b >> 24); 8747 return sum; 8748 } 8749 8750 /* For ARMv6 SEL instruction. */ 8751 uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b) 8752 { 8753 uint32_t mask; 8754 8755 mask = 0; 8756 if (flags & 1) 8757 mask |= 0xff; 8758 if (flags & 2) 8759 mask |= 0xff00; 8760 if (flags & 4) 8761 mask |= 0xff0000; 8762 if (flags & 8) 8763 mask |= 0xff000000; 8764 return (a & mask) | (b & ~mask); 8765 } 8766 8767 /* VFP support. We follow the convention used for VFP instructions: 8768 Single precision routines have a "s" suffix, double precision a 8769 "d" suffix. */ 8770 8771 /* Convert host exception flags to vfp form. */ 8772 static inline int vfp_exceptbits_from_host(int host_bits) 8773 { 8774 int target_bits = 0; 8775 8776 if (host_bits & float_flag_invalid) 8777 target_bits |= 1; 8778 if (host_bits & float_flag_divbyzero) 8779 target_bits |= 2; 8780 if (host_bits & float_flag_overflow) 8781 target_bits |= 4; 8782 if (host_bits & (float_flag_underflow | float_flag_output_denormal)) 8783 target_bits |= 8; 8784 if (host_bits & float_flag_inexact) 8785 target_bits |= 0x10; 8786 if (host_bits & float_flag_input_denormal) 8787 target_bits |= 0x80; 8788 return target_bits; 8789 } 8790 8791 uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env) 8792 { 8793 int i; 8794 uint32_t fpscr; 8795 8796 fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff) 8797 | (env->vfp.vec_len << 16) 8798 | (env->vfp.vec_stride << 20); 8799 i = get_float_exception_flags(&env->vfp.fp_status); 8800 i |= get_float_exception_flags(&env->vfp.standard_fp_status); 8801 fpscr |= vfp_exceptbits_from_host(i); 8802 return fpscr; 8803 } 8804 8805 uint32_t vfp_get_fpscr(CPUARMState *env) 8806 { 8807 return HELPER(vfp_get_fpscr)(env); 8808 } 8809 8810 /* Convert vfp exception flags to target form. */ 8811 static inline int vfp_exceptbits_to_host(int target_bits) 8812 { 8813 int host_bits = 0; 8814 8815 if (target_bits & 1) 8816 host_bits |= float_flag_invalid; 8817 if (target_bits & 2) 8818 host_bits |= float_flag_divbyzero; 8819 if (target_bits & 4) 8820 host_bits |= float_flag_overflow; 8821 if (target_bits & 8) 8822 host_bits |= float_flag_underflow; 8823 if (target_bits & 0x10) 8824 host_bits |= float_flag_inexact; 8825 if (target_bits & 0x80) 8826 host_bits |= float_flag_input_denormal; 8827 return host_bits; 8828 } 8829 8830 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) 8831 { 8832 int i; 8833 uint32_t changed; 8834 8835 changed = env->vfp.xregs[ARM_VFP_FPSCR]; 8836 env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff); 8837 env->vfp.vec_len = (val >> 16) & 7; 8838 env->vfp.vec_stride = (val >> 20) & 3; 8839 8840 changed ^= val; 8841 if (changed & (3 << 22)) { 8842 i = (val >> 22) & 3; 8843 switch (i) { 8844 case FPROUNDING_TIEEVEN: 8845 i = float_round_nearest_even; 8846 break; 8847 case FPROUNDING_POSINF: 8848 i = float_round_up; 8849 break; 8850 case FPROUNDING_NEGINF: 8851 i = float_round_down; 8852 break; 8853 case FPROUNDING_ZERO: 8854 i = float_round_to_zero; 8855 break; 8856 } 8857 set_float_rounding_mode(i, &env->vfp.fp_status); 8858 } 8859 if (changed & (1 << 24)) { 8860 set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status); 8861 set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status); 8862 } 8863 if (changed & (1 << 25)) 8864 set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status); 8865 8866 i = vfp_exceptbits_to_host(val); 8867 set_float_exception_flags(i, &env->vfp.fp_status); 8868 set_float_exception_flags(0, &env->vfp.standard_fp_status); 8869 } 8870 8871 void vfp_set_fpscr(CPUARMState *env, uint32_t val) 8872 { 8873 HELPER(vfp_set_fpscr)(env, val); 8874 } 8875 8876 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p)) 8877 8878 #define VFP_BINOP(name) \ 8879 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \ 8880 { \ 8881 float_status *fpst = fpstp; \ 8882 return float32_ ## name(a, b, fpst); \ 8883 } \ 8884 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \ 8885 { \ 8886 float_status *fpst = fpstp; \ 8887 return float64_ ## name(a, b, fpst); \ 8888 } 8889 VFP_BINOP(add) 8890 VFP_BINOP(sub) 8891 VFP_BINOP(mul) 8892 VFP_BINOP(div) 8893 VFP_BINOP(min) 8894 VFP_BINOP(max) 8895 VFP_BINOP(minnum) 8896 VFP_BINOP(maxnum) 8897 #undef VFP_BINOP 8898 8899 float32 VFP_HELPER(neg, s)(float32 a) 8900 { 8901 return float32_chs(a); 8902 } 8903 8904 float64 VFP_HELPER(neg, d)(float64 a) 8905 { 8906 return float64_chs(a); 8907 } 8908 8909 float32 VFP_HELPER(abs, s)(float32 a) 8910 { 8911 return float32_abs(a); 8912 } 8913 8914 float64 VFP_HELPER(abs, d)(float64 a) 8915 { 8916 return float64_abs(a); 8917 } 8918 8919 float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env) 8920 { 8921 return float32_sqrt(a, &env->vfp.fp_status); 8922 } 8923 8924 float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env) 8925 { 8926 return float64_sqrt(a, &env->vfp.fp_status); 8927 } 8928 8929 /* XXX: check quiet/signaling case */ 8930 #define DO_VFP_cmp(p, type) \ 8931 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \ 8932 { \ 8933 uint32_t flags; \ 8934 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \ 8935 case 0: flags = 0x6; break; \ 8936 case -1: flags = 0x8; break; \ 8937 case 1: flags = 0x2; break; \ 8938 default: case 2: flags = 0x3; break; \ 8939 } \ 8940 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \ 8941 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \ 8942 } \ 8943 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \ 8944 { \ 8945 uint32_t flags; \ 8946 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \ 8947 case 0: flags = 0x6; break; \ 8948 case -1: flags = 0x8; break; \ 8949 case 1: flags = 0x2; break; \ 8950 default: case 2: flags = 0x3; break; \ 8951 } \ 8952 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \ 8953 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \ 8954 } 8955 DO_VFP_cmp(s, float32) 8956 DO_VFP_cmp(d, float64) 8957 #undef DO_VFP_cmp 8958 8959 /* Integer to float and float to integer conversions */ 8960 8961 #define CONV_ITOF(name, fsz, sign) \ 8962 float##fsz HELPER(name)(uint32_t x, void *fpstp) \ 8963 { \ 8964 float_status *fpst = fpstp; \ 8965 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \ 8966 } 8967 8968 #define CONV_FTOI(name, fsz, sign, round) \ 8969 uint32_t HELPER(name)(float##fsz x, void *fpstp) \ 8970 { \ 8971 float_status *fpst = fpstp; \ 8972 if (float##fsz##_is_any_nan(x)) { \ 8973 float_raise(float_flag_invalid, fpst); \ 8974 return 0; \ 8975 } \ 8976 return float##fsz##_to_##sign##int32##round(x, fpst); \ 8977 } 8978 8979 #define FLOAT_CONVS(name, p, fsz, sign) \ 8980 CONV_ITOF(vfp_##name##to##p, fsz, sign) \ 8981 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \ 8982 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero) 8983 8984 FLOAT_CONVS(si, s, 32, ) 8985 FLOAT_CONVS(si, d, 64, ) 8986 FLOAT_CONVS(ui, s, 32, u) 8987 FLOAT_CONVS(ui, d, 64, u) 8988 8989 #undef CONV_ITOF 8990 #undef CONV_FTOI 8991 #undef FLOAT_CONVS 8992 8993 /* floating point conversion */ 8994 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env) 8995 { 8996 float64 r = float32_to_float64(x, &env->vfp.fp_status); 8997 /* ARM requires that S<->D conversion of any kind of NaN generates 8998 * a quiet NaN by forcing the most significant frac bit to 1. 8999 */ 9000 return float64_maybe_silence_nan(r, &env->vfp.fp_status); 9001 } 9002 9003 float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env) 9004 { 9005 float32 r = float64_to_float32(x, &env->vfp.fp_status); 9006 /* ARM requires that S<->D conversion of any kind of NaN generates 9007 * a quiet NaN by forcing the most significant frac bit to 1. 9008 */ 9009 return float32_maybe_silence_nan(r, &env->vfp.fp_status); 9010 } 9011 9012 /* VFP3 fixed point conversion. */ 9013 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \ 9014 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \ 9015 void *fpstp) \ 9016 { \ 9017 float_status *fpst = fpstp; \ 9018 float##fsz tmp; \ 9019 tmp = itype##_to_##float##fsz(x, fpst); \ 9020 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \ 9021 } 9022 9023 /* Notice that we want only input-denormal exception flags from the 9024 * scalbn operation: the other possible flags (overflow+inexact if 9025 * we overflow to infinity, output-denormal) aren't correct for the 9026 * complete scale-and-convert operation. 9027 */ 9028 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \ 9029 uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \ 9030 uint32_t shift, \ 9031 void *fpstp) \ 9032 { \ 9033 float_status *fpst = fpstp; \ 9034 int old_exc_flags = get_float_exception_flags(fpst); \ 9035 float##fsz tmp; \ 9036 if (float##fsz##_is_any_nan(x)) { \ 9037 float_raise(float_flag_invalid, fpst); \ 9038 return 0; \ 9039 } \ 9040 tmp = float##fsz##_scalbn(x, shift, fpst); \ 9041 old_exc_flags |= get_float_exception_flags(fpst) \ 9042 & float_flag_input_denormal; \ 9043 set_float_exception_flags(old_exc_flags, fpst); \ 9044 return float##fsz##_to_##itype##round(tmp, fpst); \ 9045 } 9046 9047 #define VFP_CONV_FIX(name, p, fsz, isz, itype) \ 9048 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \ 9049 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \ 9050 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, ) 9051 9052 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype) \ 9053 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \ 9054 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, ) 9055 9056 VFP_CONV_FIX(sh, d, 64, 64, int16) 9057 VFP_CONV_FIX(sl, d, 64, 64, int32) 9058 VFP_CONV_FIX_A64(sq, d, 64, 64, int64) 9059 VFP_CONV_FIX(uh, d, 64, 64, uint16) 9060 VFP_CONV_FIX(ul, d, 64, 64, uint32) 9061 VFP_CONV_FIX_A64(uq, d, 64, 64, uint64) 9062 VFP_CONV_FIX(sh, s, 32, 32, int16) 9063 VFP_CONV_FIX(sl, s, 32, 32, int32) 9064 VFP_CONV_FIX_A64(sq, s, 32, 64, int64) 9065 VFP_CONV_FIX(uh, s, 32, 32, uint16) 9066 VFP_CONV_FIX(ul, s, 32, 32, uint32) 9067 VFP_CONV_FIX_A64(uq, s, 32, 64, uint64) 9068 #undef VFP_CONV_FIX 9069 #undef VFP_CONV_FIX_FLOAT 9070 #undef VFP_CONV_FLOAT_FIX_ROUND 9071 9072 /* Set the current fp rounding mode and return the old one. 9073 * The argument is a softfloat float_round_ value. 9074 */ 9075 uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env) 9076 { 9077 float_status *fp_status = &env->vfp.fp_status; 9078 9079 uint32_t prev_rmode = get_float_rounding_mode(fp_status); 9080 set_float_rounding_mode(rmode, fp_status); 9081 9082 return prev_rmode; 9083 } 9084 9085 /* Set the current fp rounding mode in the standard fp status and return 9086 * the old one. This is for NEON instructions that need to change the 9087 * rounding mode but wish to use the standard FPSCR values for everything 9088 * else. Always set the rounding mode back to the correct value after 9089 * modifying it. 9090 * The argument is a softfloat float_round_ value. 9091 */ 9092 uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env) 9093 { 9094 float_status *fp_status = &env->vfp.standard_fp_status; 9095 9096 uint32_t prev_rmode = get_float_rounding_mode(fp_status); 9097 set_float_rounding_mode(rmode, fp_status); 9098 9099 return prev_rmode; 9100 } 9101 9102 /* Half precision conversions. */ 9103 static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s) 9104 { 9105 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; 9106 float32 r = float16_to_float32(make_float16(a), ieee, s); 9107 if (ieee) { 9108 return float32_maybe_silence_nan(r, s); 9109 } 9110 return r; 9111 } 9112 9113 static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s) 9114 { 9115 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; 9116 float16 r = float32_to_float16(a, ieee, s); 9117 if (ieee) { 9118 r = float16_maybe_silence_nan(r, s); 9119 } 9120 return float16_val(r); 9121 } 9122 9123 float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env) 9124 { 9125 return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status); 9126 } 9127 9128 uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env) 9129 { 9130 return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status); 9131 } 9132 9133 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env) 9134 { 9135 return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status); 9136 } 9137 9138 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env) 9139 { 9140 return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status); 9141 } 9142 9143 float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env) 9144 { 9145 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; 9146 float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status); 9147 if (ieee) { 9148 return float64_maybe_silence_nan(r, &env->vfp.fp_status); 9149 } 9150 return r; 9151 } 9152 9153 uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env) 9154 { 9155 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; 9156 float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status); 9157 if (ieee) { 9158 r = float16_maybe_silence_nan(r, &env->vfp.fp_status); 9159 } 9160 return float16_val(r); 9161 } 9162 9163 #define float32_two make_float32(0x40000000) 9164 #define float32_three make_float32(0x40400000) 9165 #define float32_one_point_five make_float32(0x3fc00000) 9166 9167 float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env) 9168 { 9169 float_status *s = &env->vfp.standard_fp_status; 9170 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) || 9171 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) { 9172 if (!(float32_is_zero(a) || float32_is_zero(b))) { 9173 float_raise(float_flag_input_denormal, s); 9174 } 9175 return float32_two; 9176 } 9177 return float32_sub(float32_two, float32_mul(a, b, s), s); 9178 } 9179 9180 float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env) 9181 { 9182 float_status *s = &env->vfp.standard_fp_status; 9183 float32 product; 9184 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) || 9185 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) { 9186 if (!(float32_is_zero(a) || float32_is_zero(b))) { 9187 float_raise(float_flag_input_denormal, s); 9188 } 9189 return float32_one_point_five; 9190 } 9191 product = float32_mul(a, b, s); 9192 return float32_div(float32_sub(float32_three, product, s), float32_two, s); 9193 } 9194 9195 /* NEON helpers. */ 9196 9197 /* Constants 256 and 512 are used in some helpers; we avoid relying on 9198 * int->float conversions at run-time. */ 9199 #define float64_256 make_float64(0x4070000000000000LL) 9200 #define float64_512 make_float64(0x4080000000000000LL) 9201 #define float32_maxnorm make_float32(0x7f7fffff) 9202 #define float64_maxnorm make_float64(0x7fefffffffffffffLL) 9203 9204 /* Reciprocal functions 9205 * 9206 * The algorithm that must be used to calculate the estimate 9207 * is specified by the ARM ARM, see FPRecipEstimate() 9208 */ 9209 9210 static float64 recip_estimate(float64 a, float_status *real_fp_status) 9211 { 9212 /* These calculations mustn't set any fp exception flags, 9213 * so we use a local copy of the fp_status. 9214 */ 9215 float_status dummy_status = *real_fp_status; 9216 float_status *s = &dummy_status; 9217 /* q = (int)(a * 512.0) */ 9218 float64 q = float64_mul(float64_512, a, s); 9219 int64_t q_int = float64_to_int64_round_to_zero(q, s); 9220 9221 /* r = 1.0 / (((double)q + 0.5) / 512.0) */ 9222 q = int64_to_float64(q_int, s); 9223 q = float64_add(q, float64_half, s); 9224 q = float64_div(q, float64_512, s); 9225 q = float64_div(float64_one, q, s); 9226 9227 /* s = (int)(256.0 * r + 0.5) */ 9228 q = float64_mul(q, float64_256, s); 9229 q = float64_add(q, float64_half, s); 9230 q_int = float64_to_int64_round_to_zero(q, s); 9231 9232 /* return (double)s / 256.0 */ 9233 return float64_div(int64_to_float64(q_int, s), float64_256, s); 9234 } 9235 9236 /* Common wrapper to call recip_estimate */ 9237 static float64 call_recip_estimate(float64 num, int off, float_status *fpst) 9238 { 9239 uint64_t val64 = float64_val(num); 9240 uint64_t frac = extract64(val64, 0, 52); 9241 int64_t exp = extract64(val64, 52, 11); 9242 uint64_t sbit; 9243 float64 scaled, estimate; 9244 9245 /* Generate the scaled number for the estimate function */ 9246 if (exp == 0) { 9247 if (extract64(frac, 51, 1) == 0) { 9248 exp = -1; 9249 frac = extract64(frac, 0, 50) << 2; 9250 } else { 9251 frac = extract64(frac, 0, 51) << 1; 9252 } 9253 } 9254 9255 /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */ 9256 scaled = make_float64((0x3feULL << 52) 9257 | extract64(frac, 44, 8) << 44); 9258 9259 estimate = recip_estimate(scaled, fpst); 9260 9261 /* Build new result */ 9262 val64 = float64_val(estimate); 9263 sbit = 0x8000000000000000ULL & val64; 9264 exp = off - exp; 9265 frac = extract64(val64, 0, 52); 9266 9267 if (exp == 0) { 9268 frac = 1ULL << 51 | extract64(frac, 1, 51); 9269 } else if (exp == -1) { 9270 frac = 1ULL << 50 | extract64(frac, 2, 50); 9271 exp = 0; 9272 } 9273 9274 return make_float64(sbit | (exp << 52) | frac); 9275 } 9276 9277 static bool round_to_inf(float_status *fpst, bool sign_bit) 9278 { 9279 switch (fpst->float_rounding_mode) { 9280 case float_round_nearest_even: /* Round to Nearest */ 9281 return true; 9282 case float_round_up: /* Round to +Inf */ 9283 return !sign_bit; 9284 case float_round_down: /* Round to -Inf */ 9285 return sign_bit; 9286 case float_round_to_zero: /* Round to Zero */ 9287 return false; 9288 } 9289 9290 g_assert_not_reached(); 9291 } 9292 9293 float32 HELPER(recpe_f32)(float32 input, void *fpstp) 9294 { 9295 float_status *fpst = fpstp; 9296 float32 f32 = float32_squash_input_denormal(input, fpst); 9297 uint32_t f32_val = float32_val(f32); 9298 uint32_t f32_sbit = 0x80000000ULL & f32_val; 9299 int32_t f32_exp = extract32(f32_val, 23, 8); 9300 uint32_t f32_frac = extract32(f32_val, 0, 23); 9301 float64 f64, r64; 9302 uint64_t r64_val; 9303 int64_t r64_exp; 9304 uint64_t r64_frac; 9305 9306 if (float32_is_any_nan(f32)) { 9307 float32 nan = f32; 9308 if (float32_is_signaling_nan(f32, fpst)) { 9309 float_raise(float_flag_invalid, fpst); 9310 nan = float32_maybe_silence_nan(f32, fpst); 9311 } 9312 if (fpst->default_nan_mode) { 9313 nan = float32_default_nan(fpst); 9314 } 9315 return nan; 9316 } else if (float32_is_infinity(f32)) { 9317 return float32_set_sign(float32_zero, float32_is_neg(f32)); 9318 } else if (float32_is_zero(f32)) { 9319 float_raise(float_flag_divbyzero, fpst); 9320 return float32_set_sign(float32_infinity, float32_is_neg(f32)); 9321 } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) { 9322 /* Abs(value) < 2.0^-128 */ 9323 float_raise(float_flag_overflow | float_flag_inexact, fpst); 9324 if (round_to_inf(fpst, f32_sbit)) { 9325 return float32_set_sign(float32_infinity, float32_is_neg(f32)); 9326 } else { 9327 return float32_set_sign(float32_maxnorm, float32_is_neg(f32)); 9328 } 9329 } else if (f32_exp >= 253 && fpst->flush_to_zero) { 9330 float_raise(float_flag_underflow, fpst); 9331 return float32_set_sign(float32_zero, float32_is_neg(f32)); 9332 } 9333 9334 9335 f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29); 9336 r64 = call_recip_estimate(f64, 253, fpst); 9337 r64_val = float64_val(r64); 9338 r64_exp = extract64(r64_val, 52, 11); 9339 r64_frac = extract64(r64_val, 0, 52); 9340 9341 /* result = sign : result_exp<7:0> : fraction<51:29>; */ 9342 return make_float32(f32_sbit | 9343 (r64_exp & 0xff) << 23 | 9344 extract64(r64_frac, 29, 24)); 9345 } 9346 9347 float64 HELPER(recpe_f64)(float64 input, void *fpstp) 9348 { 9349 float_status *fpst = fpstp; 9350 float64 f64 = float64_squash_input_denormal(input, fpst); 9351 uint64_t f64_val = float64_val(f64); 9352 uint64_t f64_sbit = 0x8000000000000000ULL & f64_val; 9353 int64_t f64_exp = extract64(f64_val, 52, 11); 9354 float64 r64; 9355 uint64_t r64_val; 9356 int64_t r64_exp; 9357 uint64_t r64_frac; 9358 9359 /* Deal with any special cases */ 9360 if (float64_is_any_nan(f64)) { 9361 float64 nan = f64; 9362 if (float64_is_signaling_nan(f64, fpst)) { 9363 float_raise(float_flag_invalid, fpst); 9364 nan = float64_maybe_silence_nan(f64, fpst); 9365 } 9366 if (fpst->default_nan_mode) { 9367 nan = float64_default_nan(fpst); 9368 } 9369 return nan; 9370 } else if (float64_is_infinity(f64)) { 9371 return float64_set_sign(float64_zero, float64_is_neg(f64)); 9372 } else if (float64_is_zero(f64)) { 9373 float_raise(float_flag_divbyzero, fpst); 9374 return float64_set_sign(float64_infinity, float64_is_neg(f64)); 9375 } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) { 9376 /* Abs(value) < 2.0^-1024 */ 9377 float_raise(float_flag_overflow | float_flag_inexact, fpst); 9378 if (round_to_inf(fpst, f64_sbit)) { 9379 return float64_set_sign(float64_infinity, float64_is_neg(f64)); 9380 } else { 9381 return float64_set_sign(float64_maxnorm, float64_is_neg(f64)); 9382 } 9383 } else if (f64_exp >= 2045 && fpst->flush_to_zero) { 9384 float_raise(float_flag_underflow, fpst); 9385 return float64_set_sign(float64_zero, float64_is_neg(f64)); 9386 } 9387 9388 r64 = call_recip_estimate(f64, 2045, fpst); 9389 r64_val = float64_val(r64); 9390 r64_exp = extract64(r64_val, 52, 11); 9391 r64_frac = extract64(r64_val, 0, 52); 9392 9393 /* result = sign : result_exp<10:0> : fraction<51:0> */ 9394 return make_float64(f64_sbit | 9395 ((r64_exp & 0x7ff) << 52) | 9396 r64_frac); 9397 } 9398 9399 /* The algorithm that must be used to calculate the estimate 9400 * is specified by the ARM ARM. 9401 */ 9402 static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status) 9403 { 9404 /* These calculations mustn't set any fp exception flags, 9405 * so we use a local copy of the fp_status. 9406 */ 9407 float_status dummy_status = *real_fp_status; 9408 float_status *s = &dummy_status; 9409 float64 q; 9410 int64_t q_int; 9411 9412 if (float64_lt(a, float64_half, s)) { 9413 /* range 0.25 <= a < 0.5 */ 9414 9415 /* a in units of 1/512 rounded down */ 9416 /* q0 = (int)(a * 512.0); */ 9417 q = float64_mul(float64_512, a, s); 9418 q_int = float64_to_int64_round_to_zero(q, s); 9419 9420 /* reciprocal root r */ 9421 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */ 9422 q = int64_to_float64(q_int, s); 9423 q = float64_add(q, float64_half, s); 9424 q = float64_div(q, float64_512, s); 9425 q = float64_sqrt(q, s); 9426 q = float64_div(float64_one, q, s); 9427 } else { 9428 /* range 0.5 <= a < 1.0 */ 9429 9430 /* a in units of 1/256 rounded down */ 9431 /* q1 = (int)(a * 256.0); */ 9432 q = float64_mul(float64_256, a, s); 9433 int64_t q_int = float64_to_int64_round_to_zero(q, s); 9434 9435 /* reciprocal root r */ 9436 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */ 9437 q = int64_to_float64(q_int, s); 9438 q = float64_add(q, float64_half, s); 9439 q = float64_div(q, float64_256, s); 9440 q = float64_sqrt(q, s); 9441 q = float64_div(float64_one, q, s); 9442 } 9443 /* r in units of 1/256 rounded to nearest */ 9444 /* s = (int)(256.0 * r + 0.5); */ 9445 9446 q = float64_mul(q, float64_256,s ); 9447 q = float64_add(q, float64_half, s); 9448 q_int = float64_to_int64_round_to_zero(q, s); 9449 9450 /* return (double)s / 256.0;*/ 9451 return float64_div(int64_to_float64(q_int, s), float64_256, s); 9452 } 9453 9454 float32 HELPER(rsqrte_f32)(float32 input, void *fpstp) 9455 { 9456 float_status *s = fpstp; 9457 float32 f32 = float32_squash_input_denormal(input, s); 9458 uint32_t val = float32_val(f32); 9459 uint32_t f32_sbit = 0x80000000 & val; 9460 int32_t f32_exp = extract32(val, 23, 8); 9461 uint32_t f32_frac = extract32(val, 0, 23); 9462 uint64_t f64_frac; 9463 uint64_t val64; 9464 int result_exp; 9465 float64 f64; 9466 9467 if (float32_is_any_nan(f32)) { 9468 float32 nan = f32; 9469 if (float32_is_signaling_nan(f32, s)) { 9470 float_raise(float_flag_invalid, s); 9471 nan = float32_maybe_silence_nan(f32, s); 9472 } 9473 if (s->default_nan_mode) { 9474 nan = float32_default_nan(s); 9475 } 9476 return nan; 9477 } else if (float32_is_zero(f32)) { 9478 float_raise(float_flag_divbyzero, s); 9479 return float32_set_sign(float32_infinity, float32_is_neg(f32)); 9480 } else if (float32_is_neg(f32)) { 9481 float_raise(float_flag_invalid, s); 9482 return float32_default_nan(s); 9483 } else if (float32_is_infinity(f32)) { 9484 return float32_zero; 9485 } 9486 9487 /* Scale and normalize to a double-precision value between 0.25 and 1.0, 9488 * preserving the parity of the exponent. */ 9489 9490 f64_frac = ((uint64_t) f32_frac) << 29; 9491 if (f32_exp == 0) { 9492 while (extract64(f64_frac, 51, 1) == 0) { 9493 f64_frac = f64_frac << 1; 9494 f32_exp = f32_exp-1; 9495 } 9496 f64_frac = extract64(f64_frac, 0, 51) << 1; 9497 } 9498 9499 if (extract64(f32_exp, 0, 1) == 0) { 9500 f64 = make_float64(((uint64_t) f32_sbit) << 32 9501 | (0x3feULL << 52) 9502 | f64_frac); 9503 } else { 9504 f64 = make_float64(((uint64_t) f32_sbit) << 32 9505 | (0x3fdULL << 52) 9506 | f64_frac); 9507 } 9508 9509 result_exp = (380 - f32_exp) / 2; 9510 9511 f64 = recip_sqrt_estimate(f64, s); 9512 9513 val64 = float64_val(f64); 9514 9515 val = ((result_exp & 0xff) << 23) 9516 | ((val64 >> 29) & 0x7fffff); 9517 return make_float32(val); 9518 } 9519 9520 float64 HELPER(rsqrte_f64)(float64 input, void *fpstp) 9521 { 9522 float_status *s = fpstp; 9523 float64 f64 = float64_squash_input_denormal(input, s); 9524 uint64_t val = float64_val(f64); 9525 uint64_t f64_sbit = 0x8000000000000000ULL & val; 9526 int64_t f64_exp = extract64(val, 52, 11); 9527 uint64_t f64_frac = extract64(val, 0, 52); 9528 int64_t result_exp; 9529 uint64_t result_frac; 9530 9531 if (float64_is_any_nan(f64)) { 9532 float64 nan = f64; 9533 if (float64_is_signaling_nan(f64, s)) { 9534 float_raise(float_flag_invalid, s); 9535 nan = float64_maybe_silence_nan(f64, s); 9536 } 9537 if (s->default_nan_mode) { 9538 nan = float64_default_nan(s); 9539 } 9540 return nan; 9541 } else if (float64_is_zero(f64)) { 9542 float_raise(float_flag_divbyzero, s); 9543 return float64_set_sign(float64_infinity, float64_is_neg(f64)); 9544 } else if (float64_is_neg(f64)) { 9545 float_raise(float_flag_invalid, s); 9546 return float64_default_nan(s); 9547 } else if (float64_is_infinity(f64)) { 9548 return float64_zero; 9549 } 9550 9551 /* Scale and normalize to a double-precision value between 0.25 and 1.0, 9552 * preserving the parity of the exponent. */ 9553 9554 if (f64_exp == 0) { 9555 while (extract64(f64_frac, 51, 1) == 0) { 9556 f64_frac = f64_frac << 1; 9557 f64_exp = f64_exp - 1; 9558 } 9559 f64_frac = extract64(f64_frac, 0, 51) << 1; 9560 } 9561 9562 if (extract64(f64_exp, 0, 1) == 0) { 9563 f64 = make_float64(f64_sbit 9564 | (0x3feULL << 52) 9565 | f64_frac); 9566 } else { 9567 f64 = make_float64(f64_sbit 9568 | (0x3fdULL << 52) 9569 | f64_frac); 9570 } 9571 9572 result_exp = (3068 - f64_exp) / 2; 9573 9574 f64 = recip_sqrt_estimate(f64, s); 9575 9576 result_frac = extract64(float64_val(f64), 0, 52); 9577 9578 return make_float64(f64_sbit | 9579 ((result_exp & 0x7ff) << 52) | 9580 result_frac); 9581 } 9582 9583 uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp) 9584 { 9585 float_status *s = fpstp; 9586 float64 f64; 9587 9588 if ((a & 0x80000000) == 0) { 9589 return 0xffffffff; 9590 } 9591 9592 f64 = make_float64((0x3feULL << 52) 9593 | ((int64_t)(a & 0x7fffffff) << 21)); 9594 9595 f64 = recip_estimate(f64, s); 9596 9597 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff); 9598 } 9599 9600 uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp) 9601 { 9602 float_status *fpst = fpstp; 9603 float64 f64; 9604 9605 if ((a & 0xc0000000) == 0) { 9606 return 0xffffffff; 9607 } 9608 9609 if (a & 0x80000000) { 9610 f64 = make_float64((0x3feULL << 52) 9611 | ((uint64_t)(a & 0x7fffffff) << 21)); 9612 } else { /* bits 31-30 == '01' */ 9613 f64 = make_float64((0x3fdULL << 52) 9614 | ((uint64_t)(a & 0x3fffffff) << 22)); 9615 } 9616 9617 f64 = recip_sqrt_estimate(f64, fpst); 9618 9619 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff); 9620 } 9621 9622 /* VFPv4 fused multiply-accumulate */ 9623 float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp) 9624 { 9625 float_status *fpst = fpstp; 9626 return float32_muladd(a, b, c, 0, fpst); 9627 } 9628 9629 float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp) 9630 { 9631 float_status *fpst = fpstp; 9632 return float64_muladd(a, b, c, 0, fpst); 9633 } 9634 9635 /* ARMv8 round to integral */ 9636 float32 HELPER(rints_exact)(float32 x, void *fp_status) 9637 { 9638 return float32_round_to_int(x, fp_status); 9639 } 9640 9641 float64 HELPER(rintd_exact)(float64 x, void *fp_status) 9642 { 9643 return float64_round_to_int(x, fp_status); 9644 } 9645 9646 float32 HELPER(rints)(float32 x, void *fp_status) 9647 { 9648 int old_flags = get_float_exception_flags(fp_status), new_flags; 9649 float32 ret; 9650 9651 ret = float32_round_to_int(x, fp_status); 9652 9653 /* Suppress any inexact exceptions the conversion produced */ 9654 if (!(old_flags & float_flag_inexact)) { 9655 new_flags = get_float_exception_flags(fp_status); 9656 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); 9657 } 9658 9659 return ret; 9660 } 9661 9662 float64 HELPER(rintd)(float64 x, void *fp_status) 9663 { 9664 int old_flags = get_float_exception_flags(fp_status), new_flags; 9665 float64 ret; 9666 9667 ret = float64_round_to_int(x, fp_status); 9668 9669 new_flags = get_float_exception_flags(fp_status); 9670 9671 /* Suppress any inexact exceptions the conversion produced */ 9672 if (!(old_flags & float_flag_inexact)) { 9673 new_flags = get_float_exception_flags(fp_status); 9674 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); 9675 } 9676 9677 return ret; 9678 } 9679 9680 /* Convert ARM rounding mode to softfloat */ 9681 int arm_rmode_to_sf(int rmode) 9682 { 9683 switch (rmode) { 9684 case FPROUNDING_TIEAWAY: 9685 rmode = float_round_ties_away; 9686 break; 9687 case FPROUNDING_ODD: 9688 /* FIXME: add support for TIEAWAY and ODD */ 9689 qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n", 9690 rmode); 9691 case FPROUNDING_TIEEVEN: 9692 default: 9693 rmode = float_round_nearest_even; 9694 break; 9695 case FPROUNDING_POSINF: 9696 rmode = float_round_up; 9697 break; 9698 case FPROUNDING_NEGINF: 9699 rmode = float_round_down; 9700 break; 9701 case FPROUNDING_ZERO: 9702 rmode = float_round_to_zero; 9703 break; 9704 } 9705 return rmode; 9706 } 9707 9708 /* CRC helpers. 9709 * The upper bytes of val (above the number specified by 'bytes') must have 9710 * been zeroed out by the caller. 9711 */ 9712 uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes) 9713 { 9714 uint8_t buf[4]; 9715 9716 stl_le_p(buf, val); 9717 9718 /* zlib crc32 converts the accumulator and output to one's complement. */ 9719 return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff; 9720 } 9721 9722 uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes) 9723 { 9724 uint8_t buf[4]; 9725 9726 stl_le_p(buf, val); 9727 9728 /* Linux crc32c converts the output to one's complement. */ 9729 return crc32c(acc, buf, bytes) ^ 0xffffffff; 9730 } 9731