1 /* 2 * ARM gdb server stub: AArch64 specific functions. 3 * 4 * Copyright (c) 2013 SUSE LINUX Products GmbH 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "cpu.h" 22 #include "internals.h" 23 #include "gdbstub/helpers.h" 24 25 int aarch64_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) 26 { 27 ARMCPU *cpu = ARM_CPU(cs); 28 CPUARMState *env = &cpu->env; 29 30 if (n < 31) { 31 /* Core integer register. */ 32 return gdb_get_reg64(mem_buf, env->xregs[n]); 33 } 34 switch (n) { 35 case 31: 36 return gdb_get_reg64(mem_buf, env->xregs[31]); 37 case 32: 38 return gdb_get_reg64(mem_buf, env->pc); 39 case 33: 40 return gdb_get_reg32(mem_buf, pstate_read(env)); 41 } 42 /* Unknown register. */ 43 return 0; 44 } 45 46 int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) 47 { 48 ARMCPU *cpu = ARM_CPU(cs); 49 CPUARMState *env = &cpu->env; 50 uint64_t tmp; 51 52 tmp = ldq_p(mem_buf); 53 54 if (n < 31) { 55 /* Core integer register. */ 56 env->xregs[n] = tmp; 57 return 8; 58 } 59 switch (n) { 60 case 31: 61 env->xregs[31] = tmp; 62 return 8; 63 case 32: 64 env->pc = tmp; 65 return 8; 66 case 33: 67 /* CPSR */ 68 pstate_write(env, tmp); 69 return 4; 70 } 71 /* Unknown register. */ 72 return 0; 73 } 74 75 int aarch64_gdb_get_fpu_reg(CPUState *cs, GByteArray *buf, int reg) 76 { 77 ARMCPU *cpu = ARM_CPU(cs); 78 CPUARMState *env = &cpu->env; 79 80 switch (reg) { 81 case 0 ... 31: 82 { 83 /* 128 bit FP register - quads are in LE order */ 84 uint64_t *q = aa64_vfp_qreg(env, reg); 85 return gdb_get_reg128(buf, q[1], q[0]); 86 } 87 case 32: 88 /* FPSR */ 89 return gdb_get_reg32(buf, vfp_get_fpsr(env)); 90 case 33: 91 /* FPCR */ 92 return gdb_get_reg32(buf, vfp_get_fpcr(env)); 93 default: 94 return 0; 95 } 96 } 97 98 int aarch64_gdb_set_fpu_reg(CPUState *cs, uint8_t *buf, int reg) 99 { 100 ARMCPU *cpu = ARM_CPU(cs); 101 CPUARMState *env = &cpu->env; 102 103 switch (reg) { 104 case 0 ... 31: 105 /* 128 bit FP register */ 106 { 107 uint64_t *q = aa64_vfp_qreg(env, reg); 108 q[0] = ldq_le_p(buf); 109 q[1] = ldq_le_p(buf + 8); 110 return 16; 111 } 112 case 32: 113 /* FPSR */ 114 vfp_set_fpsr(env, ldl_p(buf)); 115 return 4; 116 case 33: 117 /* FPCR */ 118 vfp_set_fpcr(env, ldl_p(buf)); 119 return 4; 120 default: 121 return 0; 122 } 123 } 124 125 int aarch64_gdb_get_sve_reg(CPUState *cs, GByteArray *buf, int reg) 126 { 127 ARMCPU *cpu = ARM_CPU(cs); 128 CPUARMState *env = &cpu->env; 129 130 switch (reg) { 131 /* The first 32 registers are the zregs */ 132 case 0 ... 31: 133 { 134 int vq, len = 0; 135 for (vq = 0; vq < cpu->sve_max_vq; vq++) { 136 len += gdb_get_reg128(buf, 137 env->vfp.zregs[reg].d[vq * 2 + 1], 138 env->vfp.zregs[reg].d[vq * 2]); 139 } 140 return len; 141 } 142 case 32: 143 return gdb_get_reg32(buf, vfp_get_fpsr(env)); 144 case 33: 145 return gdb_get_reg32(buf, vfp_get_fpcr(env)); 146 /* then 16 predicates and the ffr */ 147 case 34 ... 50: 148 { 149 int preg = reg - 34; 150 int vq, len = 0; 151 for (vq = 0; vq < cpu->sve_max_vq; vq = vq + 4) { 152 len += gdb_get_reg64(buf, env->vfp.pregs[preg].p[vq / 4]); 153 } 154 return len; 155 } 156 case 51: 157 { 158 /* 159 * We report in Vector Granules (VG) which is 64bit in a Z reg 160 * while the ZCR works in Vector Quads (VQ) which is 128bit chunks. 161 */ 162 int vq = sve_vqm1_for_el(env, arm_current_el(env)) + 1; 163 return gdb_get_reg64(buf, vq * 2); 164 } 165 default: 166 /* gdbstub asked for something out our range */ 167 qemu_log_mask(LOG_UNIMP, "%s: out of range register %d", __func__, reg); 168 break; 169 } 170 171 return 0; 172 } 173 174 int aarch64_gdb_set_sve_reg(CPUState *cs, uint8_t *buf, int reg) 175 { 176 ARMCPU *cpu = ARM_CPU(cs); 177 CPUARMState *env = &cpu->env; 178 179 /* The first 32 registers are the zregs */ 180 switch (reg) { 181 /* The first 32 registers are the zregs */ 182 case 0 ... 31: 183 { 184 int vq, len = 0; 185 uint64_t *p = (uint64_t *) buf; 186 for (vq = 0; vq < cpu->sve_max_vq; vq++) { 187 env->vfp.zregs[reg].d[vq * 2 + 1] = *p++; 188 env->vfp.zregs[reg].d[vq * 2] = *p++; 189 len += 16; 190 } 191 return len; 192 } 193 case 32: 194 vfp_set_fpsr(env, *(uint32_t *)buf); 195 return 4; 196 case 33: 197 vfp_set_fpcr(env, *(uint32_t *)buf); 198 return 4; 199 case 34 ... 50: 200 { 201 int preg = reg - 34; 202 int vq, len = 0; 203 uint64_t *p = (uint64_t *) buf; 204 for (vq = 0; vq < cpu->sve_max_vq; vq = vq + 4) { 205 env->vfp.pregs[preg].p[vq / 4] = *p++; 206 len += 8; 207 } 208 return len; 209 } 210 case 51: 211 /* cannot set vg via gdbstub */ 212 return 0; 213 default: 214 /* gdbstub asked for something out our range */ 215 break; 216 } 217 218 return 0; 219 } 220 221 int aarch64_gdb_get_pauth_reg(CPUState *cs, GByteArray *buf, int reg) 222 { 223 ARMCPU *cpu = ARM_CPU(cs); 224 CPUARMState *env = &cpu->env; 225 226 switch (reg) { 227 case 0: /* pauth_dmask */ 228 case 1: /* pauth_cmask */ 229 case 2: /* pauth_dmask_high */ 230 case 3: /* pauth_cmask_high */ 231 /* 232 * Note that older versions of this feature only contained 233 * pauth_{d,c}mask, for use with Linux user processes, and 234 * thus exclusively in the low half of the address space. 235 * 236 * To support system mode, and to debug kernels, two new regs 237 * were added to cover the high half of the address space. 238 * For the purpose of pauth_ptr_mask, we can use any well-formed 239 * address within the address space half -- here, 0 and -1. 240 */ 241 { 242 bool is_data = !(reg & 1); 243 bool is_high = reg & 2; 244 ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env); 245 ARMVAParameters param; 246 247 param = aa64_va_parameters(env, -is_high, mmu_idx, is_data, false); 248 return gdb_get_reg64(buf, pauth_ptr_mask(param)); 249 } 250 default: 251 return 0; 252 } 253 } 254 255 int aarch64_gdb_set_pauth_reg(CPUState *cs, uint8_t *buf, int reg) 256 { 257 /* All pseudo registers are read-only. */ 258 return 0; 259 } 260 261 static void output_vector_union_type(GDBFeatureBuilder *builder, int reg_width, 262 const char *name) 263 { 264 struct TypeSize { 265 const char *gdb_type; 266 short size; 267 char sz, suffix; 268 }; 269 270 static const struct TypeSize vec_lanes[] = { 271 /* quads */ 272 { "uint128", 128, 'q', 'u' }, 273 { "int128", 128, 'q', 's' }, 274 /* 64 bit */ 275 { "ieee_double", 64, 'd', 'f' }, 276 { "uint64", 64, 'd', 'u' }, 277 { "int64", 64, 'd', 's' }, 278 /* 32 bit */ 279 { "ieee_single", 32, 's', 'f' }, 280 { "uint32", 32, 's', 'u' }, 281 { "int32", 32, 's', 's' }, 282 /* 16 bit */ 283 { "ieee_half", 16, 'h', 'f' }, 284 { "uint16", 16, 'h', 'u' }, 285 { "int16", 16, 'h', 's' }, 286 /* bytes */ 287 { "uint8", 8, 'b', 'u' }, 288 { "int8", 8, 'b', 's' }, 289 }; 290 291 static const char suf[] = { 'b', 'h', 's', 'd', 'q' }; 292 int i, j; 293 294 /* First define types and totals in a whole VL */ 295 for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { 296 gdb_feature_builder_append_tag( 297 builder, "<vector id=\"%s%c%c\" type=\"%s\" count=\"%d\"/>", 298 name, vec_lanes[i].sz, vec_lanes[i].suffix, 299 vec_lanes[i].gdb_type, reg_width / vec_lanes[i].size); 300 } 301 302 /* 303 * Now define a union for each size group containing unsigned and 304 * signed and potentially float versions of each size from 128 to 305 * 8 bits. 306 */ 307 for (i = 0; i < ARRAY_SIZE(suf); i++) { 308 int bits = 8 << i; 309 310 gdb_feature_builder_append_tag(builder, "<union id=\"%sn%c\">", 311 name, suf[i]); 312 for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) { 313 if (vec_lanes[j].size == bits) { 314 gdb_feature_builder_append_tag( 315 builder, "<field name=\"%c\" type=\"%s%c%c\"/>", 316 vec_lanes[j].suffix, name, 317 vec_lanes[j].sz, vec_lanes[j].suffix); 318 } 319 } 320 gdb_feature_builder_append_tag(builder, "</union>"); 321 } 322 323 /* And now the final union of unions */ 324 gdb_feature_builder_append_tag(builder, "<union id=\"%s\">", name); 325 for (i = ARRAY_SIZE(suf) - 1; i >= 0; i--) { 326 gdb_feature_builder_append_tag(builder, 327 "<field name=\"%c\" type=\"%sn%c\"/>", 328 suf[i], name, suf[i]); 329 } 330 gdb_feature_builder_append_tag(builder, "</union>"); 331 } 332 333 GDBFeature *arm_gen_dynamic_svereg_feature(CPUState *cs, int base_reg) 334 { 335 ARMCPU *cpu = ARM_CPU(cs); 336 int reg_width = cpu->sve_max_vq * 128; 337 int pred_width = cpu->sve_max_vq * 16; 338 GDBFeatureBuilder builder; 339 char *name; 340 int reg = 0; 341 int i; 342 343 gdb_feature_builder_init(&builder, &cpu->dyn_svereg_feature.desc, 344 "org.gnu.gdb.aarch64.sve", "sve-registers.xml", 345 base_reg); 346 347 /* Create the vector union type. */ 348 output_vector_union_type(&builder, reg_width, "svev"); 349 350 /* Create the predicate vector type. */ 351 gdb_feature_builder_append_tag( 352 &builder, "<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>", 353 pred_width / 8); 354 355 /* Define the vector registers. */ 356 for (i = 0; i < 32; i++) { 357 name = g_strdup_printf("z%d", i); 358 gdb_feature_builder_append_reg(&builder, name, reg_width, reg++, 359 "svev", NULL); 360 } 361 362 /* fpscr & status registers */ 363 gdb_feature_builder_append_reg(&builder, "fpsr", 32, reg++, 364 "int", "float"); 365 gdb_feature_builder_append_reg(&builder, "fpcr", 32, reg++, 366 "int", "float"); 367 368 /* Define the predicate registers. */ 369 for (i = 0; i < 16; i++) { 370 name = g_strdup_printf("p%d", i); 371 gdb_feature_builder_append_reg(&builder, name, pred_width, reg++, 372 "svep", NULL); 373 } 374 gdb_feature_builder_append_reg(&builder, "ffr", pred_width, reg++, 375 "svep", "vector"); 376 377 /* Define the vector length pseudo-register. */ 378 gdb_feature_builder_append_reg(&builder, "vg", 64, reg++, "int", NULL); 379 380 gdb_feature_builder_end(&builder); 381 382 return &cpu->dyn_svereg_feature.desc; 383 } 384