1 /* 2 * ARM gdb server stub 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * Copyright (c) 2013 SUSE LINUX Products GmbH 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 #include "qemu/osdep.h" 21 #include "cpu.h" 22 #include "exec/gdbstub.h" 23 24 typedef struct RegisterSysregXmlParam { 25 CPUState *cs; 26 GString *s; 27 int n; 28 } RegisterSysregXmlParam; 29 30 /* Old gdb always expect FPA registers. Newer (xml-aware) gdb only expect 31 whatever the target description contains. Due to a historical mishap 32 the FPA registers appear in between core integer regs and the CPSR. 33 We hack round this by giving the FPA regs zero size when talking to a 34 newer gdb. */ 35 36 int arm_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) 37 { 38 ARMCPU *cpu = ARM_CPU(cs); 39 CPUARMState *env = &cpu->env; 40 41 if (n < 16) { 42 /* Core integer register. */ 43 return gdb_get_reg32(mem_buf, env->regs[n]); 44 } 45 if (n < 24) { 46 /* FPA registers. */ 47 if (gdb_has_xml) { 48 return 0; 49 } 50 return gdb_get_zeroes(mem_buf, 12); 51 } 52 switch (n) { 53 case 24: 54 /* FPA status register. */ 55 if (gdb_has_xml) { 56 return 0; 57 } 58 return gdb_get_reg32(mem_buf, 0); 59 case 25: 60 /* CPSR */ 61 return gdb_get_reg32(mem_buf, cpsr_read(env)); 62 } 63 /* Unknown register. */ 64 return 0; 65 } 66 67 int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) 68 { 69 ARMCPU *cpu = ARM_CPU(cs); 70 CPUARMState *env = &cpu->env; 71 uint32_t tmp; 72 73 tmp = ldl_p(mem_buf); 74 75 /* Mask out low bit of PC to workaround gdb bugs. This will probably 76 cause problems if we ever implement the Jazelle DBX extensions. */ 77 if (n == 15) { 78 tmp &= ~1; 79 } 80 81 if (n < 16) { 82 /* Core integer register. */ 83 env->regs[n] = tmp; 84 return 4; 85 } 86 if (n < 24) { /* 16-23 */ 87 /* FPA registers (ignored). */ 88 if (gdb_has_xml) { 89 return 0; 90 } 91 return 12; 92 } 93 switch (n) { 94 case 24: 95 /* FPA status register (ignored). */ 96 if (gdb_has_xml) { 97 return 0; 98 } 99 return 4; 100 case 25: 101 /* CPSR */ 102 cpsr_write(env, tmp, 0xffffffff, CPSRWriteByGDBStub); 103 return 4; 104 } 105 /* Unknown register. */ 106 return 0; 107 } 108 109 static void arm_gen_one_xml_sysreg_tag(GString *s, DynamicGDBXMLInfo *dyn_xml, 110 ARMCPRegInfo *ri, uint32_t ri_key, 111 int bitsize, int regnum) 112 { 113 g_string_append_printf(s, "<reg name=\"%s\"", ri->name); 114 g_string_append_printf(s, " bitsize=\"%d\"", bitsize); 115 g_string_append_printf(s, " regnum=\"%d\"", regnum); 116 g_string_append_printf(s, " group=\"cp_regs\"/>"); 117 dyn_xml->data.cpregs.keys[dyn_xml->num] = ri_key; 118 dyn_xml->num++; 119 } 120 121 static void arm_register_sysreg_for_xml(gpointer key, gpointer value, 122 gpointer p) 123 { 124 uint32_t ri_key = *(uint32_t *)key; 125 ARMCPRegInfo *ri = value; 126 RegisterSysregXmlParam *param = (RegisterSysregXmlParam *)p; 127 GString *s = param->s; 128 ARMCPU *cpu = ARM_CPU(param->cs); 129 CPUARMState *env = &cpu->env; 130 DynamicGDBXMLInfo *dyn_xml = &cpu->dyn_sysreg_xml; 131 132 if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_NO_GDB))) { 133 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 134 if (ri->state == ARM_CP_STATE_AA64) { 135 arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 64, 136 param->n++); 137 } 138 } else { 139 if (ri->state == ARM_CP_STATE_AA32) { 140 if (!arm_feature(env, ARM_FEATURE_EL3) && 141 (ri->secure & ARM_CP_SECSTATE_S)) { 142 return; 143 } 144 if (ri->type & ARM_CP_64BIT) { 145 arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 64, 146 param->n++); 147 } else { 148 arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 32, 149 param->n++); 150 } 151 } 152 } 153 } 154 } 155 156 int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg) 157 { 158 ARMCPU *cpu = ARM_CPU(cs); 159 GString *s = g_string_new(NULL); 160 RegisterSysregXmlParam param = {cs, s, base_reg}; 161 162 cpu->dyn_sysreg_xml.num = 0; 163 cpu->dyn_sysreg_xml.data.cpregs.keys = g_new(uint32_t, g_hash_table_size(cpu->cp_regs)); 164 g_string_printf(s, "<?xml version=\"1.0\"?>"); 165 g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"); 166 g_string_append_printf(s, "<feature name=\"org.qemu.gdb.arm.sys.regs\">"); 167 g_hash_table_foreach(cpu->cp_regs, arm_register_sysreg_for_xml, ¶m); 168 g_string_append_printf(s, "</feature>"); 169 cpu->dyn_sysreg_xml.desc = g_string_free(s, false); 170 return cpu->dyn_sysreg_xml.num; 171 } 172 173 struct TypeSize { 174 const char *gdb_type; 175 int size; 176 const char sz, suffix; 177 }; 178 179 static const struct TypeSize vec_lanes[] = { 180 /* quads */ 181 { "uint128", 128, 'q', 'u' }, 182 { "int128", 128, 'q', 's' }, 183 /* 64 bit */ 184 { "uint64", 64, 'd', 'u' }, 185 { "int64", 64, 'd', 's' }, 186 { "ieee_double", 64, 'd', 'f' }, 187 /* 32 bit */ 188 { "uint32", 32, 's', 'u' }, 189 { "int32", 32, 's', 's' }, 190 { "ieee_single", 32, 's', 'f' }, 191 /* 16 bit */ 192 { "uint16", 16, 'h', 'u' }, 193 { "int16", 16, 'h', 's' }, 194 /* 195 * TODO: currently there is no reliable way of telling 196 * if the remote gdb actually understands ieee_half so 197 * we don't expose it in the target description for now. 198 * { "ieee_half", 16, 'h', 'f' }, 199 */ 200 /* bytes */ 201 { "uint8", 8, 'b', 'u' }, 202 { "int8", 8, 'b', 's' }, 203 }; 204 205 206 int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) 207 { 208 ARMCPU *cpu = ARM_CPU(cs); 209 GString *s = g_string_new(NULL); 210 DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml; 211 g_autoptr(GString) ts = g_string_new(""); 212 int i, bits, reg_width = (cpu->sve_max_vq * 128); 213 info->num = 0; 214 g_string_printf(s, "<?xml version=\"1.0\"?>"); 215 g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"); 216 g_string_append_printf(s, "<feature name=\"org.qemu.gdb.aarch64.sve\">"); 217 218 /* First define types and totals in a whole VL */ 219 for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { 220 int count = reg_width / vec_lanes[i].size; 221 g_string_printf(ts, "vq%d%c%c", count, 222 vec_lanes[i].sz, vec_lanes[i].suffix); 223 g_string_append_printf(s, 224 "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>", 225 ts->str, vec_lanes[i].gdb_type, count); 226 } 227 /* 228 * Now define a union for each size group containing unsigned and 229 * signed and potentially float versions of each size from 128 to 230 * 8 bits. 231 */ 232 for (bits = 128; bits >= 8; bits /= 2) { 233 int count = reg_width / bits; 234 g_string_append_printf(s, "<union id=\"vq%dn\">", count); 235 for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { 236 if (vec_lanes[i].size == bits) { 237 g_string_append_printf(s, "<field name=\"%c\" type=\"vq%d%c%c\"/>", 238 vec_lanes[i].suffix, 239 count, 240 vec_lanes[i].sz, vec_lanes[i].suffix); 241 } 242 } 243 g_string_append(s, "</union>"); 244 } 245 /* And now the final union of unions */ 246 g_string_append(s, "<union id=\"vq\">"); 247 for (bits = 128; bits >= 8; bits /= 2) { 248 int count = reg_width / bits; 249 for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { 250 if (vec_lanes[i].size == bits) { 251 g_string_append_printf(s, "<field name=\"%c\" type=\"vq%dn\"/>", 252 vec_lanes[i].sz, count); 253 break; 254 } 255 } 256 } 257 g_string_append(s, "</union>"); 258 259 /* Then define each register in parts for each vq */ 260 for (i = 0; i < 32; i++) { 261 g_string_append_printf(s, 262 "<reg name=\"z%d\" bitsize=\"%d\"" 263 " regnum=\"%d\" group=\"vector\"" 264 " type=\"vq\"/>", 265 i, reg_width, base_reg++); 266 info->num++; 267 } 268 /* fpscr & status registers */ 269 g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\"" 270 " regnum=\"%d\" group=\"float\"" 271 " type=\"int\"/>", base_reg++); 272 g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\"" 273 " regnum=\"%d\" group=\"float\"" 274 " type=\"int\"/>", base_reg++); 275 info->num += 2; 276 /* 277 * Predicate registers aren't so big they are worth splitting up 278 * but we do need to define a type to hold the array of quad 279 * references. 280 */ 281 g_string_append_printf(s, 282 "<vector id=\"vqp\" type=\"uint16\" count=\"%d\"/>", 283 cpu->sve_max_vq); 284 for (i = 0; i < 16; i++) { 285 g_string_append_printf(s, 286 "<reg name=\"p%d\" bitsize=\"%d\"" 287 " regnum=\"%d\" group=\"vector\"" 288 " type=\"vqp\"/>", 289 i, cpu->sve_max_vq * 16, base_reg++); 290 info->num++; 291 } 292 g_string_append_printf(s, 293 "<reg name=\"ffr\" bitsize=\"%d\"" 294 " regnum=\"%d\" group=\"vector\"" 295 " type=\"vqp\"/>", 296 cpu->sve_max_vq * 16, base_reg++); 297 g_string_append_printf(s, 298 "<reg name=\"vg\" bitsize=\"64\"" 299 " regnum=\"%d\" group=\"vector\"" 300 " type=\"uint32\"/>", 301 base_reg++); 302 info->num += 2; 303 g_string_append_printf(s, "</feature>"); 304 cpu->dyn_svereg_xml.desc = g_string_free(s, false); 305 306 return cpu->dyn_svereg_xml.num; 307 } 308 309 310 const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) 311 { 312 ARMCPU *cpu = ARM_CPU(cs); 313 314 if (strcmp(xmlname, "system-registers.xml") == 0) { 315 return cpu->dyn_sysreg_xml.desc; 316 } else if (strcmp(xmlname, "sve-registers.xml") == 0) { 317 return cpu->dyn_svereg_xml.desc; 318 } 319 return NULL; 320 } 321