1 /* 2 * ARM gdb server stub 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * Copyright (c) 2013 SUSE LINUX Products GmbH 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 #include "qemu/osdep.h" 21 #include "cpu.h" 22 #include "exec/gdbstub.h" 23 #include "gdbstub/helpers.h" 24 #include "sysemu/tcg.h" 25 #include "internals.h" 26 #include "cpu-features.h" 27 #include "cpregs.h" 28 29 typedef struct RegisterSysregFeatureParam { 30 CPUState *cs; 31 GDBFeatureBuilder builder; 32 int n; 33 } RegisterSysregFeatureParam; 34 35 /* Old gdb always expect FPA registers. Newer (xml-aware) gdb only expect 36 whatever the target description contains. Due to a historical mishap 37 the FPA registers appear in between core integer regs and the CPSR. 38 We hack round this by giving the FPA regs zero size when talking to a 39 newer gdb. */ 40 41 int arm_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) 42 { 43 ARMCPU *cpu = ARM_CPU(cs); 44 CPUARMState *env = &cpu->env; 45 46 if (n < 16) { 47 /* Core integer register. */ 48 return gdb_get_reg32(mem_buf, env->regs[n]); 49 } 50 if (n == 25) { 51 /* CPSR, or XPSR for M-profile */ 52 if (arm_feature(env, ARM_FEATURE_M)) { 53 return gdb_get_reg32(mem_buf, xpsr_read(env)); 54 } else { 55 return gdb_get_reg32(mem_buf, cpsr_read(env)); 56 } 57 } 58 /* Unknown register. */ 59 return 0; 60 } 61 62 int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) 63 { 64 ARMCPU *cpu = ARM_CPU(cs); 65 CPUARMState *env = &cpu->env; 66 uint32_t tmp; 67 68 tmp = ldl_p(mem_buf); 69 70 /* 71 * Mask out low bits of PC to workaround gdb bugs. 72 * This avoids an assert in thumb_tr_translate_insn, because it is 73 * architecturally impossible to misalign the pc. 74 * This will probably cause problems if we ever implement the 75 * Jazelle DBX extensions. 76 */ 77 if (n == 15) { 78 tmp &= ~1; 79 } 80 81 if (n < 16) { 82 /* Core integer register. */ 83 if (n == 13 && arm_feature(env, ARM_FEATURE_M)) { 84 /* M profile SP low bits are always 0 */ 85 tmp &= ~3; 86 } 87 env->regs[n] = tmp; 88 return 4; 89 } 90 if (n == 25) { 91 /* CPSR, or XPSR for M-profile */ 92 if (arm_feature(env, ARM_FEATURE_M)) { 93 /* 94 * Don't allow writing to XPSR.Exception as it can cause 95 * a transition into or out of handler mode (it's not 96 * writable via the MSR insn so this is a reasonable 97 * restriction). Other fields are safe to update. 98 */ 99 xpsr_write(env, tmp, ~XPSR_EXCP); 100 } else { 101 cpsr_write(env, tmp, 0xffffffff, CPSRWriteByGDBStub); 102 } 103 return 4; 104 } 105 /* Unknown register. */ 106 return 0; 107 } 108 109 static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) 110 { 111 ARMCPU *cpu = env_archcpu(env); 112 int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16; 113 114 /* VFP data registers are always little-endian. */ 115 if (reg < nregs) { 116 return gdb_get_reg64(buf, *aa32_vfp_dreg(env, reg)); 117 } 118 if (arm_feature(env, ARM_FEATURE_NEON)) { 119 /* Aliases for Q regs. */ 120 nregs += 16; 121 if (reg < nregs) { 122 uint64_t *q = aa32_vfp_qreg(env, reg - 32); 123 return gdb_get_reg128(buf, q[0], q[1]); 124 } 125 } 126 switch (reg - nregs) { 127 case 0: 128 return gdb_get_reg32(buf, vfp_get_fpscr(env)); 129 } 130 return 0; 131 } 132 133 static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) 134 { 135 ARMCPU *cpu = env_archcpu(env); 136 int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16; 137 138 if (reg < nregs) { 139 *aa32_vfp_dreg(env, reg) = ldq_le_p(buf); 140 return 8; 141 } 142 if (arm_feature(env, ARM_FEATURE_NEON)) { 143 nregs += 16; 144 if (reg < nregs) { 145 uint64_t *q = aa32_vfp_qreg(env, reg - 32); 146 q[0] = ldq_le_p(buf); 147 q[1] = ldq_le_p(buf + 8); 148 return 16; 149 } 150 } 151 switch (reg - nregs) { 152 case 0: 153 vfp_set_fpscr(env, ldl_p(buf)); 154 return 4; 155 } 156 return 0; 157 } 158 159 static int vfp_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg) 160 { 161 switch (reg) { 162 case 0: 163 return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]); 164 case 1: 165 return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]); 166 } 167 return 0; 168 } 169 170 static int vfp_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg) 171 { 172 switch (reg) { 173 case 0: 174 env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); 175 return 4; 176 case 1: 177 env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); 178 return 4; 179 } 180 return 0; 181 } 182 183 static int mve_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) 184 { 185 switch (reg) { 186 case 0: 187 return gdb_get_reg32(buf, env->v7m.vpr); 188 default: 189 return 0; 190 } 191 } 192 193 static int mve_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) 194 { 195 switch (reg) { 196 case 0: 197 env->v7m.vpr = ldl_p(buf); 198 return 4; 199 default: 200 return 0; 201 } 202 } 203 204 /** 205 * arm_get/set_gdb_*: get/set a gdb register 206 * @env: the CPU state 207 * @buf: a buffer to copy to/from 208 * @reg: register number (offset from start of group) 209 * 210 * We return the number of bytes copied 211 */ 212 213 static int arm_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg) 214 { 215 ARMCPU *cpu = env_archcpu(env); 216 const ARMCPRegInfo *ri; 217 uint32_t key; 218 219 key = cpu->dyn_sysreg_feature.data.cpregs.keys[reg]; 220 ri = get_arm_cp_reginfo(cpu->cp_regs, key); 221 if (ri) { 222 if (cpreg_field_is_64bit(ri)) { 223 return gdb_get_reg64(buf, (uint64_t)read_raw_cp_reg(env, ri)); 224 } else { 225 return gdb_get_reg32(buf, (uint32_t)read_raw_cp_reg(env, ri)); 226 } 227 } 228 return 0; 229 } 230 231 static int arm_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg) 232 { 233 return 0; 234 } 235 236 static void arm_gen_one_feature_sysreg(GDBFeatureBuilder *builder, 237 DynamicGDBFeatureInfo *dyn_feature, 238 ARMCPRegInfo *ri, uint32_t ri_key, 239 int bitsize, int n) 240 { 241 gdb_feature_builder_append_reg(builder, ri->name, bitsize, n, 242 "int", "cp_regs"); 243 244 dyn_feature->data.cpregs.keys[n] = ri_key; 245 } 246 247 static void arm_register_sysreg_for_feature(gpointer key, gpointer value, 248 gpointer p) 249 { 250 uint32_t ri_key = (uintptr_t)key; 251 ARMCPRegInfo *ri = value; 252 RegisterSysregFeatureParam *param = p; 253 ARMCPU *cpu = ARM_CPU(param->cs); 254 CPUARMState *env = &cpu->env; 255 DynamicGDBFeatureInfo *dyn_feature = &cpu->dyn_sysreg_feature; 256 257 if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_NO_GDB))) { 258 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 259 if (ri->state == ARM_CP_STATE_AA64) { 260 arm_gen_one_feature_sysreg(¶m->builder, dyn_feature, 261 ri, ri_key, 64, param->n++); 262 } 263 } else { 264 if (ri->state == ARM_CP_STATE_AA32) { 265 if (!arm_feature(env, ARM_FEATURE_EL3) && 266 (ri->secure & ARM_CP_SECSTATE_S)) { 267 return; 268 } 269 if (ri->type & ARM_CP_64BIT) { 270 arm_gen_one_feature_sysreg(¶m->builder, dyn_feature, 271 ri, ri_key, 64, param->n++); 272 } else { 273 arm_gen_one_feature_sysreg(¶m->builder, dyn_feature, 274 ri, ri_key, 32, param->n++); 275 } 276 } 277 } 278 } 279 } 280 281 static GDBFeature *arm_gen_dynamic_sysreg_feature(CPUState *cs, int base_reg) 282 { 283 ARMCPU *cpu = ARM_CPU(cs); 284 RegisterSysregFeatureParam param = {cs}; 285 gsize num_regs = g_hash_table_size(cpu->cp_regs); 286 287 gdb_feature_builder_init(¶m.builder, 288 &cpu->dyn_sysreg_feature.desc, 289 "org.qemu.gdb.arm.sys.regs", 290 "system-registers.xml", 291 base_reg); 292 cpu->dyn_sysreg_feature.data.cpregs.keys = g_new(uint32_t, num_regs); 293 g_hash_table_foreach(cpu->cp_regs, arm_register_sysreg_for_feature, ¶m); 294 gdb_feature_builder_end(¶m.builder); 295 return &cpu->dyn_sysreg_feature.desc; 296 } 297 298 #ifdef CONFIG_TCG 299 typedef enum { 300 M_SYSREG_MSP, 301 M_SYSREG_PSP, 302 M_SYSREG_PRIMASK, 303 M_SYSREG_CONTROL, 304 M_SYSREG_BASEPRI, 305 M_SYSREG_FAULTMASK, 306 M_SYSREG_MSPLIM, 307 M_SYSREG_PSPLIM, 308 } MProfileSysreg; 309 310 static const struct { 311 const char *name; 312 int feature; 313 } m_sysreg_def[] = { 314 [M_SYSREG_MSP] = { "msp", ARM_FEATURE_M }, 315 [M_SYSREG_PSP] = { "psp", ARM_FEATURE_M }, 316 [M_SYSREG_PRIMASK] = { "primask", ARM_FEATURE_M }, 317 [M_SYSREG_CONTROL] = { "control", ARM_FEATURE_M }, 318 [M_SYSREG_BASEPRI] = { "basepri", ARM_FEATURE_M_MAIN }, 319 [M_SYSREG_FAULTMASK] = { "faultmask", ARM_FEATURE_M_MAIN }, 320 [M_SYSREG_MSPLIM] = { "msplim", ARM_FEATURE_V8 }, 321 [M_SYSREG_PSPLIM] = { "psplim", ARM_FEATURE_V8 }, 322 }; 323 324 static uint32_t *m_sysreg_ptr(CPUARMState *env, MProfileSysreg reg, bool sec) 325 { 326 uint32_t *ptr; 327 328 switch (reg) { 329 case M_SYSREG_MSP: 330 ptr = arm_v7m_get_sp_ptr(env, sec, false, true); 331 break; 332 case M_SYSREG_PSP: 333 ptr = arm_v7m_get_sp_ptr(env, sec, true, true); 334 break; 335 case M_SYSREG_MSPLIM: 336 ptr = &env->v7m.msplim[sec]; 337 break; 338 case M_SYSREG_PSPLIM: 339 ptr = &env->v7m.psplim[sec]; 340 break; 341 case M_SYSREG_PRIMASK: 342 ptr = &env->v7m.primask[sec]; 343 break; 344 case M_SYSREG_BASEPRI: 345 ptr = &env->v7m.basepri[sec]; 346 break; 347 case M_SYSREG_FAULTMASK: 348 ptr = &env->v7m.faultmask[sec]; 349 break; 350 case M_SYSREG_CONTROL: 351 ptr = &env->v7m.control[sec]; 352 break; 353 default: 354 return NULL; 355 } 356 return arm_feature(env, m_sysreg_def[reg].feature) ? ptr : NULL; 357 } 358 359 static int m_sysreg_get(CPUARMState *env, GByteArray *buf, 360 MProfileSysreg reg, bool secure) 361 { 362 uint32_t *ptr = m_sysreg_ptr(env, reg, secure); 363 364 if (ptr == NULL) { 365 return 0; 366 } 367 return gdb_get_reg32(buf, *ptr); 368 } 369 370 static int arm_gdb_get_m_systemreg(CPUARMState *env, GByteArray *buf, int reg) 371 { 372 /* 373 * Here, we emulate MRS instruction, where CONTROL has a mix of 374 * banked and non-banked bits. 375 */ 376 if (reg == M_SYSREG_CONTROL) { 377 return gdb_get_reg32(buf, arm_v7m_mrs_control(env, env->v7m.secure)); 378 } 379 return m_sysreg_get(env, buf, reg, env->v7m.secure); 380 } 381 382 static int arm_gdb_set_m_systemreg(CPUARMState *env, uint8_t *buf, int reg) 383 { 384 return 0; /* TODO */ 385 } 386 387 static GDBFeature *arm_gen_dynamic_m_systemreg_feature(CPUState *cs, 388 int base_reg) 389 { 390 ARMCPU *cpu = ARM_CPU(cs); 391 CPUARMState *env = &cpu->env; 392 GDBFeatureBuilder builder; 393 int reg = 0; 394 int i; 395 396 gdb_feature_builder_init(&builder, &cpu->dyn_m_systemreg_feature.desc, 397 "org.gnu.gdb.arm.m-system", "arm-m-system.xml", 398 base_reg); 399 400 for (i = 0; i < ARRAY_SIZE(m_sysreg_def); i++) { 401 if (arm_feature(env, m_sysreg_def[i].feature)) { 402 gdb_feature_builder_append_reg(&builder, m_sysreg_def[i].name, 32, 403 reg++, "int", NULL); 404 } 405 } 406 407 gdb_feature_builder_end(&builder); 408 409 return &cpu->dyn_m_systemreg_feature.desc; 410 } 411 412 #ifndef CONFIG_USER_ONLY 413 /* 414 * For user-only, we see the non-secure registers via m_systemreg above. 415 * For secext, encode the non-secure view as even and secure view as odd. 416 */ 417 static int arm_gdb_get_m_secextreg(CPUARMState *env, GByteArray *buf, int reg) 418 { 419 return m_sysreg_get(env, buf, reg >> 1, reg & 1); 420 } 421 422 static int arm_gdb_set_m_secextreg(CPUARMState *env, uint8_t *buf, int reg) 423 { 424 return 0; /* TODO */ 425 } 426 427 static GDBFeature *arm_gen_dynamic_m_secextreg_feature(CPUState *cs, 428 int base_reg) 429 { 430 ARMCPU *cpu = ARM_CPU(cs); 431 GDBFeatureBuilder builder; 432 char *name; 433 int reg = 0; 434 int i; 435 436 gdb_feature_builder_init(&builder, &cpu->dyn_m_secextreg_feature.desc, 437 "org.gnu.gdb.arm.secext", "arm-m-secext.xml", 438 base_reg); 439 440 for (i = 0; i < ARRAY_SIZE(m_sysreg_def); i++) { 441 name = g_strconcat(m_sysreg_def[i].name, "_ns", NULL); 442 gdb_feature_builder_append_reg(&builder, name, 32, reg++, 443 "int", NULL); 444 name = g_strconcat(m_sysreg_def[i].name, "_s", NULL); 445 gdb_feature_builder_append_reg(&builder, name, 32, reg++, 446 "int", NULL); 447 } 448 449 gdb_feature_builder_end(&builder); 450 451 return &cpu->dyn_m_secextreg_feature.desc; 452 } 453 #endif 454 #endif /* CONFIG_TCG */ 455 456 const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) 457 { 458 ARMCPU *cpu = ARM_CPU(cs); 459 460 if (strcmp(xmlname, "system-registers.xml") == 0) { 461 return cpu->dyn_sysreg_feature.desc.xml; 462 } else if (strcmp(xmlname, "sve-registers.xml") == 0) { 463 return cpu->dyn_svereg_feature.desc.xml; 464 } else if (strcmp(xmlname, "arm-m-system.xml") == 0) { 465 return cpu->dyn_m_systemreg_feature.desc.xml; 466 #ifndef CONFIG_USER_ONLY 467 } else if (strcmp(xmlname, "arm-m-secext.xml") == 0) { 468 return cpu->dyn_m_secextreg_feature.desc.xml; 469 #endif 470 } 471 return NULL; 472 } 473 474 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) 475 { 476 CPUState *cs = CPU(cpu); 477 CPUARMState *env = &cpu->env; 478 479 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 480 /* 481 * The lower part of each SVE register aliases to the FPU 482 * registers so we don't need to include both. 483 */ 484 #ifdef TARGET_AARCH64 485 if (isar_feature_aa64_sve(&cpu->isar)) { 486 int nreg = arm_gen_dynamic_svereg_feature(cs, cs->gdb_num_regs)->num_regs; 487 gdb_register_coprocessor(cs, aarch64_gdb_get_sve_reg, 488 aarch64_gdb_set_sve_reg, nreg, 489 "sve-registers.xml", 0); 490 } else { 491 gdb_register_coprocessor(cs, aarch64_gdb_get_fpu_reg, 492 aarch64_gdb_set_fpu_reg, 493 34, "aarch64-fpu.xml", 0); 494 } 495 /* 496 * Note that we report pauth information via the feature name 497 * org.gnu.gdb.aarch64.pauth_v2, not org.gnu.gdb.aarch64.pauth. 498 * GDB versions 9 through 12 have a bug where they will crash 499 * if they see the latter XML from QEMU. 500 */ 501 if (isar_feature_aa64_pauth(&cpu->isar)) { 502 gdb_register_coprocessor(cs, aarch64_gdb_get_pauth_reg, 503 aarch64_gdb_set_pauth_reg, 504 4, "aarch64-pauth.xml", 0); 505 } 506 #endif 507 } else { 508 if (arm_feature(env, ARM_FEATURE_NEON)) { 509 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 510 49, "arm-neon.xml", 0); 511 } else if (cpu_isar_feature(aa32_simd_r32, cpu)) { 512 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 513 33, "arm-vfp3.xml", 0); 514 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 515 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 516 17, "arm-vfp.xml", 0); 517 } 518 if (!arm_feature(env, ARM_FEATURE_M)) { 519 /* 520 * A and R profile have FP sysregs FPEXC and FPSID that we 521 * expose to gdb. 522 */ 523 gdb_register_coprocessor(cs, vfp_gdb_get_sysreg, vfp_gdb_set_sysreg, 524 2, "arm-vfp-sysregs.xml", 0); 525 } 526 } 527 if (cpu_isar_feature(aa32_mve, cpu) && tcg_enabled()) { 528 gdb_register_coprocessor(cs, mve_gdb_get_reg, mve_gdb_set_reg, 529 1, "arm-m-profile-mve.xml", 0); 530 } 531 gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg, 532 arm_gen_dynamic_sysreg_feature(cs, cs->gdb_num_regs)->num_regs, 533 "system-registers.xml", 0); 534 535 #ifdef CONFIG_TCG 536 if (arm_feature(env, ARM_FEATURE_M) && tcg_enabled()) { 537 gdb_register_coprocessor(cs, 538 arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg, 539 arm_gen_dynamic_m_systemreg_feature(cs, cs->gdb_num_regs)->num_regs, 540 "arm-m-system.xml", 0); 541 #ifndef CONFIG_USER_ONLY 542 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 543 gdb_register_coprocessor(cs, 544 arm_gdb_get_m_secextreg, arm_gdb_set_m_secextreg, 545 arm_gen_dynamic_m_secextreg_feature(cs, cs->gdb_num_regs)->num_regs, 546 "arm-m-secext.xml", 0); 547 } 548 #endif 549 } 550 #endif /* CONFIG_TCG */ 551 } 552