1 /* 2 * ARM debug helpers. 3 * 4 * This code is licensed under the GNU GPL v2 or later. 5 * 6 * SPDX-License-Identifier: GPL-2.0-or-later 7 */ 8 #include "qemu/osdep.h" 9 #include "qemu/log.h" 10 #include "cpu.h" 11 #include "internals.h" 12 #include "cpregs.h" 13 #include "exec/exec-all.h" 14 #include "exec/helper-proto.h" 15 16 17 /* Return the Exception Level targeted by debug exceptions. */ 18 static int arm_debug_target_el(CPUARMState *env) 19 { 20 bool secure = arm_is_secure(env); 21 bool route_to_el2 = false; 22 23 if (arm_is_el2_enabled(env)) { 24 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || 25 env->cp15.mdcr_el2 & MDCR_TDE; 26 } 27 28 if (route_to_el2) { 29 return 2; 30 } else if (arm_feature(env, ARM_FEATURE_EL3) && 31 !arm_el_is_aa64(env, 3) && secure) { 32 return 3; 33 } else { 34 return 1; 35 } 36 } 37 38 /* 39 * Raise an exception to the debug target el. 40 * Modify syndrome to indicate when origin and target EL are the same. 41 */ 42 G_NORETURN static void 43 raise_exception_debug(CPUARMState *env, uint32_t excp, uint32_t syndrome) 44 { 45 int debug_el = arm_debug_target_el(env); 46 int cur_el = arm_current_el(env); 47 48 /* 49 * If singlestep is targeting a lower EL than the current one, then 50 * DisasContext.ss_active must be false and we can never get here. 51 * Similarly for watchpoint and breakpoint matches. 52 */ 53 assert(debug_el >= cur_el); 54 syndrome |= (debug_el == cur_el) << ARM_EL_EC_SHIFT; 55 raise_exception(env, excp, syndrome, debug_el); 56 } 57 58 /* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */ 59 static bool aa64_generate_debug_exceptions(CPUARMState *env) 60 { 61 int cur_el = arm_current_el(env); 62 int debug_el; 63 64 if (cur_el == 3) { 65 return false; 66 } 67 68 /* MDCR_EL3.SDD disables debug events from Secure state */ 69 if (arm_is_secure_below_el3(env) 70 && extract32(env->cp15.mdcr_el3, 16, 1)) { 71 return false; 72 } 73 74 /* 75 * Same EL to same EL debug exceptions need MDSCR_KDE enabled 76 * while not masking the (D)ebug bit in DAIF. 77 */ 78 debug_el = arm_debug_target_el(env); 79 80 if (cur_el == debug_el) { 81 return extract32(env->cp15.mdscr_el1, 13, 1) 82 && !(env->daif & PSTATE_D); 83 } 84 85 /* Otherwise the debug target needs to be a higher EL */ 86 return debug_el > cur_el; 87 } 88 89 static bool aa32_generate_debug_exceptions(CPUARMState *env) 90 { 91 int el = arm_current_el(env); 92 93 if (el == 0 && arm_el_is_aa64(env, 1)) { 94 return aa64_generate_debug_exceptions(env); 95 } 96 97 if (arm_is_secure(env)) { 98 int spd; 99 100 if (el == 0 && (env->cp15.sder & 1)) { 101 /* 102 * SDER.SUIDEN means debug exceptions from Secure EL0 103 * are always enabled. Otherwise they are controlled by 104 * SDCR.SPD like those from other Secure ELs. 105 */ 106 return true; 107 } 108 109 spd = extract32(env->cp15.mdcr_el3, 14, 2); 110 switch (spd) { 111 case 1: 112 /* SPD == 0b01 is reserved, but behaves as 0b00. */ 113 case 0: 114 /* 115 * For 0b00 we return true if external secure invasive debug 116 * is enabled. On real hardware this is controlled by external 117 * signals to the core. QEMU always permits debug, and behaves 118 * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. 119 */ 120 return true; 121 case 2: 122 return false; 123 case 3: 124 return true; 125 } 126 } 127 128 return el != 2; 129 } 130 131 /* 132 * Return true if debugging exceptions are currently enabled. 133 * This corresponds to what in ARM ARM pseudocode would be 134 * if UsingAArch32() then 135 * return AArch32.GenerateDebugExceptions() 136 * else 137 * return AArch64.GenerateDebugExceptions() 138 * We choose to push the if() down into this function for clarity, 139 * since the pseudocode has it at all callsites except for the one in 140 * CheckSoftwareStep(), where it is elided because both branches would 141 * always return the same value. 142 */ 143 bool arm_generate_debug_exceptions(CPUARMState *env) 144 { 145 if ((env->cp15.oslsr_el1 & 1) || (env->cp15.osdlr_el1 & 1)) { 146 return false; 147 } 148 if (is_a64(env)) { 149 return aa64_generate_debug_exceptions(env); 150 } else { 151 return aa32_generate_debug_exceptions(env); 152 } 153 } 154 155 /* 156 * Is single-stepping active? (Note that the "is EL_D AArch64?" check 157 * implicitly means this always returns false in pre-v8 CPUs.) 158 */ 159 bool arm_singlestep_active(CPUARMState *env) 160 { 161 return extract32(env->cp15.mdscr_el1, 0, 1) 162 && arm_el_is_aa64(env, arm_debug_target_el(env)) 163 && arm_generate_debug_exceptions(env); 164 } 165 166 /* Return true if the linked breakpoint entry lbn passes its checks */ 167 static bool linked_bp_matches(ARMCPU *cpu, int lbn) 168 { 169 CPUARMState *env = &cpu->env; 170 uint64_t bcr = env->cp15.dbgbcr[lbn]; 171 int brps = arm_num_brps(cpu); 172 int ctx_cmps = arm_num_ctx_cmps(cpu); 173 int bt; 174 uint32_t contextidr; 175 uint64_t hcr_el2; 176 177 /* 178 * Links to unimplemented or non-context aware breakpoints are 179 * CONSTRAINED UNPREDICTABLE: either behave as if disabled, or 180 * as if linked to an UNKNOWN context-aware breakpoint (in which 181 * case DBGWCR<n>_EL1.LBN must indicate that breakpoint). 182 * We choose the former. 183 */ 184 if (lbn >= brps || lbn < (brps - ctx_cmps)) { 185 return false; 186 } 187 188 bcr = env->cp15.dbgbcr[lbn]; 189 190 if (extract64(bcr, 0, 1) == 0) { 191 /* Linked breakpoint disabled : generate no events */ 192 return false; 193 } 194 195 bt = extract64(bcr, 20, 4); 196 hcr_el2 = arm_hcr_el2_eff(env); 197 198 switch (bt) { 199 case 3: /* linked context ID match */ 200 switch (arm_current_el(env)) { 201 default: 202 /* Context matches never fire in AArch64 EL3 */ 203 return false; 204 case 2: 205 if (!(hcr_el2 & HCR_E2H)) { 206 /* Context matches never fire in EL2 without E2H enabled. */ 207 return false; 208 } 209 contextidr = env->cp15.contextidr_el[2]; 210 break; 211 case 1: 212 contextidr = env->cp15.contextidr_el[1]; 213 break; 214 case 0: 215 if ((hcr_el2 & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { 216 contextidr = env->cp15.contextidr_el[2]; 217 } else { 218 contextidr = env->cp15.contextidr_el[1]; 219 } 220 break; 221 } 222 break; 223 224 case 7: /* linked contextidr_el1 match */ 225 contextidr = env->cp15.contextidr_el[1]; 226 break; 227 case 13: /* linked contextidr_el2 match */ 228 contextidr = env->cp15.contextidr_el[2]; 229 break; 230 231 case 9: /* linked VMID match (reserved if no EL2) */ 232 case 11: /* linked context ID and VMID match (reserved if no EL2) */ 233 case 15: /* linked full context ID match */ 234 default: 235 /* 236 * Links to Unlinked context breakpoints must generate no 237 * events; we choose to do the same for reserved values too. 238 */ 239 return false; 240 } 241 242 /* 243 * We match the whole register even if this is AArch32 using the 244 * short descriptor format (in which case it holds both PROCID and ASID), 245 * since we don't implement the optional v7 context ID masking. 246 */ 247 return contextidr == (uint32_t)env->cp15.dbgbvr[lbn]; 248 } 249 250 static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_wp) 251 { 252 CPUARMState *env = &cpu->env; 253 uint64_t cr; 254 int pac, hmc, ssc, wt, lbn; 255 /* 256 * Note that for watchpoints the check is against the CPU security 257 * state, not the S/NS attribute on the offending data access. 258 */ 259 bool is_secure = arm_is_secure(env); 260 int access_el = arm_current_el(env); 261 262 if (is_wp) { 263 CPUWatchpoint *wp = env->cpu_watchpoint[n]; 264 265 if (!wp || !(wp->flags & BP_WATCHPOINT_HIT)) { 266 return false; 267 } 268 cr = env->cp15.dbgwcr[n]; 269 if (wp->hitattrs.user) { 270 /* 271 * The LDRT/STRT/LDT/STT "unprivileged access" instructions should 272 * match watchpoints as if they were accesses done at EL0, even if 273 * the CPU is at EL1 or higher. 274 */ 275 access_el = 0; 276 } 277 } else { 278 uint64_t pc = is_a64(env) ? env->pc : env->regs[15]; 279 280 if (!env->cpu_breakpoint[n] || env->cpu_breakpoint[n]->pc != pc) { 281 return false; 282 } 283 cr = env->cp15.dbgbcr[n]; 284 } 285 /* 286 * The WATCHPOINT_HIT flag guarantees us that the watchpoint is 287 * enabled and that the address and access type match; for breakpoints 288 * we know the address matched; check the remaining fields, including 289 * linked breakpoints. We rely on WCR and BCR having the same layout 290 * for the LBN, SSC, HMC, PAC/PMC and is-linked fields. 291 * Note that some combinations of {PAC, HMC, SSC} are reserved and 292 * must act either like some valid combination or as if the watchpoint 293 * were disabled. We choose the former, and use this together with 294 * the fact that EL3 must always be Secure and EL2 must always be 295 * Non-Secure to simplify the code slightly compared to the full 296 * table in the ARM ARM. 297 */ 298 pac = FIELD_EX64(cr, DBGWCR, PAC); 299 hmc = FIELD_EX64(cr, DBGWCR, HMC); 300 ssc = FIELD_EX64(cr, DBGWCR, SSC); 301 302 switch (ssc) { 303 case 0: 304 break; 305 case 1: 306 case 3: 307 if (is_secure) { 308 return false; 309 } 310 break; 311 case 2: 312 if (!is_secure) { 313 return false; 314 } 315 break; 316 } 317 318 switch (access_el) { 319 case 3: 320 case 2: 321 if (!hmc) { 322 return false; 323 } 324 break; 325 case 1: 326 if (extract32(pac, 0, 1) == 0) { 327 return false; 328 } 329 break; 330 case 0: 331 if (extract32(pac, 1, 1) == 0) { 332 return false; 333 } 334 break; 335 default: 336 g_assert_not_reached(); 337 } 338 339 wt = FIELD_EX64(cr, DBGWCR, WT); 340 lbn = FIELD_EX64(cr, DBGWCR, LBN); 341 342 if (wt && !linked_bp_matches(cpu, lbn)) { 343 return false; 344 } 345 346 return true; 347 } 348 349 static bool check_watchpoints(ARMCPU *cpu) 350 { 351 CPUARMState *env = &cpu->env; 352 int n; 353 354 /* 355 * If watchpoints are disabled globally or we can't take debug 356 * exceptions here then watchpoint firings are ignored. 357 */ 358 if (extract32(env->cp15.mdscr_el1, 15, 1) == 0 359 || !arm_generate_debug_exceptions(env)) { 360 return false; 361 } 362 363 for (n = 0; n < ARRAY_SIZE(env->cpu_watchpoint); n++) { 364 if (bp_wp_matches(cpu, n, true)) { 365 return true; 366 } 367 } 368 return false; 369 } 370 371 bool arm_debug_check_breakpoint(CPUState *cs) 372 { 373 ARMCPU *cpu = ARM_CPU(cs); 374 CPUARMState *env = &cpu->env; 375 target_ulong pc; 376 int n; 377 378 /* 379 * If breakpoints are disabled globally or we can't take debug 380 * exceptions here then breakpoint firings are ignored. 381 */ 382 if (extract32(env->cp15.mdscr_el1, 15, 1) == 0 383 || !arm_generate_debug_exceptions(env)) { 384 return false; 385 } 386 387 /* 388 * Single-step exceptions have priority over breakpoint exceptions. 389 * If single-step state is active-pending, suppress the bp. 390 */ 391 if (arm_singlestep_active(env) && !(env->pstate & PSTATE_SS)) { 392 return false; 393 } 394 395 /* 396 * PC alignment faults have priority over breakpoint exceptions. 397 */ 398 pc = is_a64(env) ? env->pc : env->regs[15]; 399 if ((is_a64(env) || !env->thumb) && (pc & 3) != 0) { 400 return false; 401 } 402 403 /* 404 * Instruction aborts have priority over breakpoint exceptions. 405 * TODO: We would need to look up the page for PC and verify that 406 * it is present and executable. 407 */ 408 409 for (n = 0; n < ARRAY_SIZE(env->cpu_breakpoint); n++) { 410 if (bp_wp_matches(cpu, n, false)) { 411 return true; 412 } 413 } 414 return false; 415 } 416 417 bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) 418 { 419 /* 420 * Called by core code when a CPU watchpoint fires; need to check if this 421 * is also an architectural watchpoint match. 422 */ 423 ARMCPU *cpu = ARM_CPU(cs); 424 425 return check_watchpoints(cpu); 426 } 427 428 /* 429 * Return the FSR value for a debug exception (watchpoint, hardware 430 * breakpoint or BKPT insn) targeting the specified exception level. 431 */ 432 static uint32_t arm_debug_exception_fsr(CPUARMState *env) 433 { 434 ARMMMUFaultInfo fi = { .type = ARMFault_Debug }; 435 int target_el = arm_debug_target_el(env); 436 bool using_lpae = false; 437 438 if (target_el == 2 || arm_el_is_aa64(env, target_el)) { 439 using_lpae = true; 440 } else { 441 if (arm_feature(env, ARM_FEATURE_LPAE) && 442 (env->cp15.tcr_el[target_el] & TTBCR_EAE)) { 443 using_lpae = true; 444 } 445 } 446 447 if (using_lpae) { 448 return arm_fi_to_lfsc(&fi); 449 } else { 450 return arm_fi_to_sfsc(&fi); 451 } 452 } 453 454 void arm_debug_excp_handler(CPUState *cs) 455 { 456 /* 457 * Called by core code when a watchpoint or breakpoint fires; 458 * need to check which one and raise the appropriate exception. 459 */ 460 ARMCPU *cpu = ARM_CPU(cs); 461 CPUARMState *env = &cpu->env; 462 CPUWatchpoint *wp_hit = cs->watchpoint_hit; 463 464 if (wp_hit) { 465 if (wp_hit->flags & BP_CPU) { 466 bool wnr = (wp_hit->flags & BP_WATCHPOINT_HIT_WRITE) != 0; 467 468 cs->watchpoint_hit = NULL; 469 470 env->exception.fsr = arm_debug_exception_fsr(env); 471 env->exception.vaddress = wp_hit->hitaddr; 472 raise_exception_debug(env, EXCP_DATA_ABORT, 473 syn_watchpoint(0, 0, wnr)); 474 } 475 } else { 476 uint64_t pc = is_a64(env) ? env->pc : env->regs[15]; 477 478 /* 479 * (1) GDB breakpoints should be handled first. 480 * (2) Do not raise a CPU exception if no CPU breakpoint has fired, 481 * since singlestep is also done by generating a debug internal 482 * exception. 483 */ 484 if (cpu_breakpoint_test(cs, pc, BP_GDB) 485 || !cpu_breakpoint_test(cs, pc, BP_CPU)) { 486 return; 487 } 488 489 env->exception.fsr = arm_debug_exception_fsr(env); 490 /* 491 * FAR is UNKNOWN: clear vaddress to avoid potentially exposing 492 * values to the guest that it shouldn't be able to see at its 493 * exception/security level. 494 */ 495 env->exception.vaddress = 0; 496 raise_exception_debug(env, EXCP_PREFETCH_ABORT, syn_breakpoint(0)); 497 } 498 } 499 500 /* 501 * Raise an EXCP_BKPT with the specified syndrome register value, 502 * targeting the correct exception level for debug exceptions. 503 */ 504 void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome) 505 { 506 int debug_el = arm_debug_target_el(env); 507 int cur_el = arm_current_el(env); 508 509 /* FSR will only be used if the debug target EL is AArch32. */ 510 env->exception.fsr = arm_debug_exception_fsr(env); 511 /* 512 * FAR is UNKNOWN: clear vaddress to avoid potentially exposing 513 * values to the guest that it shouldn't be able to see at its 514 * exception/security level. 515 */ 516 env->exception.vaddress = 0; 517 /* 518 * Other kinds of architectural debug exception are ignored if 519 * they target an exception level below the current one (in QEMU 520 * this is checked by arm_generate_debug_exceptions()). Breakpoint 521 * instructions are special because they always generate an exception 522 * to somewhere: if they can't go to the configured debug exception 523 * level they are taken to the current exception level. 524 */ 525 if (debug_el < cur_el) { 526 debug_el = cur_el; 527 } 528 raise_exception(env, EXCP_BKPT, syndrome, debug_el); 529 } 530 531 void HELPER(exception_swstep)(CPUARMState *env, uint32_t syndrome) 532 { 533 raise_exception_debug(env, EXCP_UDEF, syndrome); 534 } 535 536 /* 537 * Check for traps to "powerdown debug" registers, which are controlled 538 * by MDCR.TDOSA 539 */ 540 static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *ri, 541 bool isread) 542 { 543 int el = arm_current_el(env); 544 uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); 545 bool mdcr_el2_tdosa = (mdcr_el2 & MDCR_TDOSA) || (mdcr_el2 & MDCR_TDE) || 546 (arm_hcr_el2_eff(env) & HCR_TGE); 547 548 if (el < 2 && mdcr_el2_tdosa) { 549 return CP_ACCESS_TRAP_EL2; 550 } 551 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDOSA)) { 552 return CP_ACCESS_TRAP_EL3; 553 } 554 return CP_ACCESS_OK; 555 } 556 557 /* 558 * Check for traps to "debug ROM" registers, which are controlled 559 * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3. 560 */ 561 static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri, 562 bool isread) 563 { 564 int el = arm_current_el(env); 565 uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); 566 bool mdcr_el2_tdra = (mdcr_el2 & MDCR_TDRA) || (mdcr_el2 & MDCR_TDE) || 567 (arm_hcr_el2_eff(env) & HCR_TGE); 568 569 if (el < 2 && mdcr_el2_tdra) { 570 return CP_ACCESS_TRAP_EL2; 571 } 572 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { 573 return CP_ACCESS_TRAP_EL3; 574 } 575 return CP_ACCESS_OK; 576 } 577 578 /* 579 * Check for traps to general debug registers, which are controlled 580 * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3. 581 */ 582 static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri, 583 bool isread) 584 { 585 int el = arm_current_el(env); 586 uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); 587 bool mdcr_el2_tda = (mdcr_el2 & MDCR_TDA) || (mdcr_el2 & MDCR_TDE) || 588 (arm_hcr_el2_eff(env) & HCR_TGE); 589 590 if (el < 2 && mdcr_el2_tda) { 591 return CP_ACCESS_TRAP_EL2; 592 } 593 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { 594 return CP_ACCESS_TRAP_EL3; 595 } 596 return CP_ACCESS_OK; 597 } 598 599 static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri, 600 uint64_t value) 601 { 602 /* 603 * Writes to OSLAR_EL1 may update the OS lock status, which can be 604 * read via a bit in OSLSR_EL1. 605 */ 606 int oslock; 607 608 if (ri->state == ARM_CP_STATE_AA32) { 609 oslock = (value == 0xC5ACCE55); 610 } else { 611 oslock = value & 1; 612 } 613 614 env->cp15.oslsr_el1 = deposit32(env->cp15.oslsr_el1, 1, 1, oslock); 615 } 616 617 static void osdlr_write(CPUARMState *env, const ARMCPRegInfo *ri, 618 uint64_t value) 619 { 620 ARMCPU *cpu = env_archcpu(env); 621 /* 622 * Only defined bit is bit 0 (DLK); if Feat_DoubleLock is not 623 * implemented this is RAZ/WI. 624 */ 625 if(arm_feature(env, ARM_FEATURE_AARCH64) 626 ? cpu_isar_feature(aa64_doublelock, cpu) 627 : cpu_isar_feature(aa32_doublelock, cpu)) { 628 env->cp15.osdlr_el1 = value & 1; 629 } 630 } 631 632 static const ARMCPRegInfo debug_cp_reginfo[] = { 633 /* 634 * DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped 635 * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1; 636 * unlike DBGDRAR it is never accessible from EL0. 637 * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64 638 * accessor. 639 */ 640 { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0, 641 .access = PL0_R, .accessfn = access_tdra, 642 .type = ARM_CP_CONST, .resetvalue = 0 }, 643 { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64, 644 .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, 645 .access = PL1_R, .accessfn = access_tdra, 646 .type = ARM_CP_CONST, .resetvalue = 0 }, 647 { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, 648 .access = PL0_R, .accessfn = access_tdra, 649 .type = ARM_CP_CONST, .resetvalue = 0 }, 650 /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */ 651 { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH, 652 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, 653 .access = PL1_RW, .accessfn = access_tda, 654 .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), 655 .resetvalue = 0 }, 656 /* 657 * MDCCSR_EL0[30:29] map to EDSCR[30:29]. Simply RAZ as the external 658 * Debug Communication Channel is not implemented. 659 */ 660 { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_AA64, 661 .opc0 = 2, .opc1 = 3, .crn = 0, .crm = 1, .opc2 = 0, 662 .access = PL0_R, .accessfn = access_tda, 663 .type = ARM_CP_CONST, .resetvalue = 0 }, 664 /* 665 * DBGDSCRint[15,12,5:2] map to MDSCR_EL1[15,12,5:2]. Map all bits as 666 * it is unlikely a guest will care. 667 * We don't implement the configurable EL0 access. 668 */ 669 { .name = "DBGDSCRint", .state = ARM_CP_STATE_AA32, 670 .cp = 14, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, 671 .type = ARM_CP_ALIAS, 672 .access = PL1_R, .accessfn = access_tda, 673 .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), }, 674 { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH, 675 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4, 676 .access = PL1_W, .type = ARM_CP_NO_RAW, 677 .accessfn = access_tdosa, 678 .writefn = oslar_write }, 679 { .name = "OSLSR_EL1", .state = ARM_CP_STATE_BOTH, 680 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 4, 681 .access = PL1_R, .resetvalue = 10, 682 .accessfn = access_tdosa, 683 .fieldoffset = offsetof(CPUARMState, cp15.oslsr_el1) }, 684 /* Dummy OSDLR_EL1: 32-bit Linux will read this */ 685 { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH, 686 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4, 687 .access = PL1_RW, .accessfn = access_tdosa, 688 .writefn = osdlr_write, 689 .fieldoffset = offsetof(CPUARMState, cp15.osdlr_el1) }, 690 /* 691 * Dummy DBGVCR: Linux wants to clear this on startup, but we don't 692 * implement vector catch debug events yet. 693 */ 694 { .name = "DBGVCR", 695 .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, 696 .access = PL1_RW, .accessfn = access_tda, 697 .type = ARM_CP_NOP }, 698 /* 699 * Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor 700 * to save and restore a 32-bit guest's DBGVCR) 701 */ 702 { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64, 703 .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0, 704 .access = PL2_RW, .accessfn = access_tda, 705 .type = ARM_CP_NOP | ARM_CP_EL3_NO_EL2_KEEP }, 706 /* 707 * Dummy MDCCINT_EL1, since we don't implement the Debug Communications 708 * Channel but Linux may try to access this register. The 32-bit 709 * alias is DBGDCCINT. 710 */ 711 { .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH, 712 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, 713 .access = PL1_RW, .accessfn = access_tda, 714 .type = ARM_CP_NOP }, 715 }; 716 717 static const ARMCPRegInfo debug_lpae_cp_reginfo[] = { 718 /* 64 bit access versions of the (dummy) debug registers */ 719 { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0, 720 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 721 { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0, 722 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 723 }; 724 725 void hw_watchpoint_update(ARMCPU *cpu, int n) 726 { 727 CPUARMState *env = &cpu->env; 728 vaddr len = 0; 729 vaddr wvr = env->cp15.dbgwvr[n]; 730 uint64_t wcr = env->cp15.dbgwcr[n]; 731 int mask; 732 int flags = BP_CPU | BP_STOP_BEFORE_ACCESS; 733 734 if (env->cpu_watchpoint[n]) { 735 cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]); 736 env->cpu_watchpoint[n] = NULL; 737 } 738 739 if (!FIELD_EX64(wcr, DBGWCR, E)) { 740 /* E bit clear : watchpoint disabled */ 741 return; 742 } 743 744 switch (FIELD_EX64(wcr, DBGWCR, LSC)) { 745 case 0: 746 /* LSC 00 is reserved and must behave as if the wp is disabled */ 747 return; 748 case 1: 749 flags |= BP_MEM_READ; 750 break; 751 case 2: 752 flags |= BP_MEM_WRITE; 753 break; 754 case 3: 755 flags |= BP_MEM_ACCESS; 756 break; 757 } 758 759 /* 760 * Attempts to use both MASK and BAS fields simultaneously are 761 * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case, 762 * thus generating a watchpoint for every byte in the masked region. 763 */ 764 mask = FIELD_EX64(wcr, DBGWCR, MASK); 765 if (mask == 1 || mask == 2) { 766 /* 767 * Reserved values of MASK; we must act as if the mask value was 768 * some non-reserved value, or as if the watchpoint were disabled. 769 * We choose the latter. 770 */ 771 return; 772 } else if (mask) { 773 /* Watchpoint covers an aligned area up to 2GB in size */ 774 len = 1ULL << mask; 775 /* 776 * If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE 777 * whether the watchpoint fires when the unmasked bits match; we opt 778 * to generate the exceptions. 779 */ 780 wvr &= ~(len - 1); 781 } else { 782 /* Watchpoint covers bytes defined by the byte address select bits */ 783 int bas = FIELD_EX64(wcr, DBGWCR, BAS); 784 int basstart; 785 786 if (extract64(wvr, 2, 1)) { 787 /* 788 * Deprecated case of an only 4-aligned address. BAS[7:4] are 789 * ignored, and BAS[3:0] define which bytes to watch. 790 */ 791 bas &= 0xf; 792 } 793 794 if (bas == 0) { 795 /* This must act as if the watchpoint is disabled */ 796 return; 797 } 798 799 /* 800 * The BAS bits are supposed to be programmed to indicate a contiguous 801 * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether 802 * we fire for each byte in the word/doubleword addressed by the WVR. 803 * We choose to ignore any non-zero bits after the first range of 1s. 804 */ 805 basstart = ctz32(bas); 806 len = cto32(bas >> basstart); 807 wvr += basstart; 808 } 809 810 cpu_watchpoint_insert(CPU(cpu), wvr, len, flags, 811 &env->cpu_watchpoint[n]); 812 } 813 814 void hw_watchpoint_update_all(ARMCPU *cpu) 815 { 816 int i; 817 CPUARMState *env = &cpu->env; 818 819 /* 820 * Completely clear out existing QEMU watchpoints and our array, to 821 * avoid possible stale entries following migration load. 822 */ 823 cpu_watchpoint_remove_all(CPU(cpu), BP_CPU); 824 memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint)); 825 826 for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) { 827 hw_watchpoint_update(cpu, i); 828 } 829 } 830 831 static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri, 832 uint64_t value) 833 { 834 ARMCPU *cpu = env_archcpu(env); 835 int i = ri->crm; 836 837 /* 838 * Bits [1:0] are RES0. 839 * 840 * It is IMPLEMENTATION DEFINED whether [63:49] ([63:53] with FEAT_LVA) 841 * are hardwired to the value of bit [48] ([52] with FEAT_LVA), or if 842 * they contain the value written. It is CONSTRAINED UNPREDICTABLE 843 * whether the RESS bits are ignored when comparing an address. 844 * 845 * Therefore we are allowed to compare the entire register, which lets 846 * us avoid considering whether or not FEAT_LVA is actually enabled. 847 */ 848 value &= ~3ULL; 849 850 raw_write(env, ri, value); 851 hw_watchpoint_update(cpu, i); 852 } 853 854 static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri, 855 uint64_t value) 856 { 857 ARMCPU *cpu = env_archcpu(env); 858 int i = ri->crm; 859 860 raw_write(env, ri, value); 861 hw_watchpoint_update(cpu, i); 862 } 863 864 void hw_breakpoint_update(ARMCPU *cpu, int n) 865 { 866 CPUARMState *env = &cpu->env; 867 uint64_t bvr = env->cp15.dbgbvr[n]; 868 uint64_t bcr = env->cp15.dbgbcr[n]; 869 vaddr addr; 870 int bt; 871 int flags = BP_CPU; 872 873 if (env->cpu_breakpoint[n]) { 874 cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]); 875 env->cpu_breakpoint[n] = NULL; 876 } 877 878 if (!extract64(bcr, 0, 1)) { 879 /* E bit clear : watchpoint disabled */ 880 return; 881 } 882 883 bt = extract64(bcr, 20, 4); 884 885 switch (bt) { 886 case 4: /* unlinked address mismatch (reserved if AArch64) */ 887 case 5: /* linked address mismatch (reserved if AArch64) */ 888 qemu_log_mask(LOG_UNIMP, 889 "arm: address mismatch breakpoint types not implemented\n"); 890 return; 891 case 0: /* unlinked address match */ 892 case 1: /* linked address match */ 893 { 894 /* 895 * Bits [1:0] are RES0. 896 * 897 * It is IMPLEMENTATION DEFINED whether bits [63:49] 898 * ([63:53] for FEAT_LVA) are hardwired to a copy of the sign bit 899 * of the VA field ([48] or [52] for FEAT_LVA), or whether the 900 * value is read as written. It is CONSTRAINED UNPREDICTABLE 901 * whether the RESS bits are ignored when comparing an address. 902 * Therefore we are allowed to compare the entire register, which 903 * lets us avoid considering whether FEAT_LVA is actually enabled. 904 * 905 * The BAS field is used to allow setting breakpoints on 16-bit 906 * wide instructions; it is CONSTRAINED UNPREDICTABLE whether 907 * a bp will fire if the addresses covered by the bp and the addresses 908 * covered by the insn overlap but the insn doesn't start at the 909 * start of the bp address range. We choose to require the insn and 910 * the bp to have the same address. The constraints on writing to 911 * BAS enforced in dbgbcr_write mean we have only four cases: 912 * 0b0000 => no breakpoint 913 * 0b0011 => breakpoint on addr 914 * 0b1100 => breakpoint on addr + 2 915 * 0b1111 => breakpoint on addr 916 * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c). 917 */ 918 int bas = extract64(bcr, 5, 4); 919 addr = bvr & ~3ULL; 920 if (bas == 0) { 921 return; 922 } 923 if (bas == 0xc) { 924 addr += 2; 925 } 926 break; 927 } 928 case 2: /* unlinked context ID match */ 929 case 8: /* unlinked VMID match (reserved if no EL2) */ 930 case 10: /* unlinked context ID and VMID match (reserved if no EL2) */ 931 qemu_log_mask(LOG_UNIMP, 932 "arm: unlinked context breakpoint types not implemented\n"); 933 return; 934 case 9: /* linked VMID match (reserved if no EL2) */ 935 case 11: /* linked context ID and VMID match (reserved if no EL2) */ 936 case 3: /* linked context ID match */ 937 default: 938 /* 939 * We must generate no events for Linked context matches (unless 940 * they are linked to by some other bp/wp, which is handled in 941 * updates for the linking bp/wp). We choose to also generate no events 942 * for reserved values. 943 */ 944 return; 945 } 946 947 cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]); 948 } 949 950 void hw_breakpoint_update_all(ARMCPU *cpu) 951 { 952 int i; 953 CPUARMState *env = &cpu->env; 954 955 /* 956 * Completely clear out existing QEMU breakpoints and our array, to 957 * avoid possible stale entries following migration load. 958 */ 959 cpu_breakpoint_remove_all(CPU(cpu), BP_CPU); 960 memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint)); 961 962 for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) { 963 hw_breakpoint_update(cpu, i); 964 } 965 } 966 967 static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri, 968 uint64_t value) 969 { 970 ARMCPU *cpu = env_archcpu(env); 971 int i = ri->crm; 972 973 raw_write(env, ri, value); 974 hw_breakpoint_update(cpu, i); 975 } 976 977 static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, 978 uint64_t value) 979 { 980 ARMCPU *cpu = env_archcpu(env); 981 int i = ri->crm; 982 983 /* 984 * BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only 985 * copy of BAS[0]. 986 */ 987 value = deposit64(value, 6, 1, extract64(value, 5, 1)); 988 value = deposit64(value, 8, 1, extract64(value, 7, 1)); 989 990 raw_write(env, ri, value); 991 hw_breakpoint_update(cpu, i); 992 } 993 994 void define_debug_regs(ARMCPU *cpu) 995 { 996 /* 997 * Define v7 and v8 architectural debug registers. 998 * These are just dummy implementations for now. 999 */ 1000 int i; 1001 int wrps, brps, ctx_cmps; 1002 1003 /* 1004 * The Arm ARM says DBGDIDR is optional and deprecated if EL1 cannot 1005 * use AArch32. Given that bit 15 is RES1, if the value is 0 then 1006 * the register must not exist for this cpu. 1007 */ 1008 if (cpu->isar.dbgdidr != 0) { 1009 ARMCPRegInfo dbgdidr = { 1010 .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, 1011 .opc1 = 0, .opc2 = 0, 1012 .access = PL0_R, .accessfn = access_tda, 1013 .type = ARM_CP_CONST, .resetvalue = cpu->isar.dbgdidr, 1014 }; 1015 define_one_arm_cp_reg(cpu, &dbgdidr); 1016 } 1017 1018 /* 1019 * DBGDEVID is present in the v7 debug architecture if 1020 * DBGDIDR.DEVID_imp is 1 (bit 15); from v7.1 and on it is 1021 * mandatory (and bit 15 is RES1). DBGDEVID1 and DBGDEVID2 exist 1022 * from v7.1 of the debug architecture. Because no fields have yet 1023 * been defined in DBGDEVID2 (and quite possibly none will ever 1024 * be) we don't define an ARMISARegisters field for it. 1025 * These registers exist only if EL1 can use AArch32, but that 1026 * happens naturally because they are only PL1 accessible anyway. 1027 */ 1028 if (extract32(cpu->isar.dbgdidr, 15, 1)) { 1029 ARMCPRegInfo dbgdevid = { 1030 .name = "DBGDEVID", 1031 .cp = 14, .opc1 = 0, .crn = 7, .opc2 = 2, .crn = 7, 1032 .access = PL1_R, .accessfn = access_tda, 1033 .type = ARM_CP_CONST, .resetvalue = cpu->isar.dbgdevid, 1034 }; 1035 define_one_arm_cp_reg(cpu, &dbgdevid); 1036 } 1037 if (cpu_isar_feature(aa32_debugv7p1, cpu)) { 1038 ARMCPRegInfo dbgdevid12[] = { 1039 { 1040 .name = "DBGDEVID1", 1041 .cp = 14, .opc1 = 0, .crn = 7, .opc2 = 1, .crn = 7, 1042 .access = PL1_R, .accessfn = access_tda, 1043 .type = ARM_CP_CONST, .resetvalue = cpu->isar.dbgdevid1, 1044 }, { 1045 .name = "DBGDEVID2", 1046 .cp = 14, .opc1 = 0, .crn = 7, .opc2 = 0, .crn = 7, 1047 .access = PL1_R, .accessfn = access_tda, 1048 .type = ARM_CP_CONST, .resetvalue = 0, 1049 }, 1050 }; 1051 define_arm_cp_regs(cpu, dbgdevid12); 1052 } 1053 1054 brps = arm_num_brps(cpu); 1055 wrps = arm_num_wrps(cpu); 1056 ctx_cmps = arm_num_ctx_cmps(cpu); 1057 1058 assert(ctx_cmps <= brps); 1059 1060 define_arm_cp_regs(cpu, debug_cp_reginfo); 1061 1062 if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) { 1063 define_arm_cp_regs(cpu, debug_lpae_cp_reginfo); 1064 } 1065 1066 for (i = 0; i < brps; i++) { 1067 char *dbgbvr_el1_name = g_strdup_printf("DBGBVR%d_EL1", i); 1068 char *dbgbcr_el1_name = g_strdup_printf("DBGBCR%d_EL1", i); 1069 ARMCPRegInfo dbgregs[] = { 1070 { .name = dbgbvr_el1_name, .state = ARM_CP_STATE_BOTH, 1071 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4, 1072 .access = PL1_RW, .accessfn = access_tda, 1073 .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]), 1074 .writefn = dbgbvr_write, .raw_writefn = raw_write 1075 }, 1076 { .name = dbgbcr_el1_name, .state = ARM_CP_STATE_BOTH, 1077 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5, 1078 .access = PL1_RW, .accessfn = access_tda, 1079 .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]), 1080 .writefn = dbgbcr_write, .raw_writefn = raw_write 1081 }, 1082 }; 1083 define_arm_cp_regs(cpu, dbgregs); 1084 g_free(dbgbvr_el1_name); 1085 g_free(dbgbcr_el1_name); 1086 } 1087 1088 for (i = 0; i < wrps; i++) { 1089 char *dbgwvr_el1_name = g_strdup_printf("DBGWVR%d_EL1", i); 1090 char *dbgwcr_el1_name = g_strdup_printf("DBGWCR%d_EL1", i); 1091 ARMCPRegInfo dbgregs[] = { 1092 { .name = dbgwvr_el1_name, .state = ARM_CP_STATE_BOTH, 1093 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6, 1094 .access = PL1_RW, .accessfn = access_tda, 1095 .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]), 1096 .writefn = dbgwvr_write, .raw_writefn = raw_write 1097 }, 1098 { .name = dbgwcr_el1_name, .state = ARM_CP_STATE_BOTH, 1099 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7, 1100 .access = PL1_RW, .accessfn = access_tda, 1101 .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]), 1102 .writefn = dbgwcr_write, .raw_writefn = raw_write 1103 }, 1104 }; 1105 define_arm_cp_regs(cpu, dbgregs); 1106 g_free(dbgwvr_el1_name); 1107 g_free(dbgwcr_el1_name); 1108 } 1109 } 1110 1111 #if !defined(CONFIG_USER_ONLY) 1112 1113 vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len) 1114 { 1115 ARMCPU *cpu = ARM_CPU(cs); 1116 CPUARMState *env = &cpu->env; 1117 1118 /* 1119 * In BE32 system mode, target memory is stored byteswapped (on a 1120 * little-endian host system), and by the time we reach here (via an 1121 * opcode helper) the addresses of subword accesses have been adjusted 1122 * to account for that, which means that watchpoints will not match. 1123 * Undo the adjustment here. 1124 */ 1125 if (arm_sctlr_b(env)) { 1126 if (len == 1) { 1127 addr ^= 3; 1128 } else if (len == 2) { 1129 addr ^= 2; 1130 } 1131 } 1132 1133 return addr; 1134 } 1135 1136 #endif 1137